JP2009188790A - Output buffer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an output buffer circuit in which the number of circuit components is reduced by constituting a pull-up/pull-down resistor while sharing one resistive element and electrostatic destruction resistance of internal circuits is ensured by the shared resistive element. <P>SOLUTION: As a transistor for driving a load, there are provided a first transistor connected between a first power supply line and an output terminal and a second transistor connected between a second power supply line and the output terminal and further, a resistive element to the output terminal of which one terminal is connected and to the polarity switching section of which another terminal is connected, is provided. The polarity switching section connects herein the other terminal of the resistive element to any one of the first and second power supply lines. When the polarity switching section selects the first power supply line, the first transistor is maintained in a non-conducted state and the second transistor is then subjected to conduction control. When the polarity switching section selects the second power supply line, the second transistor is maintained in a non-conducted state and the first transistor is then subjected to conduction control. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an open drain type output buffer circuit. In particular, the present invention relates to an open drain type output buffer circuit incorporating a pull-up / pull-down resistor.

  As shown in FIG. 5, the signal output device of Patent Document 1 includes a buffer circuit A, an open drain selection circuit B, and a pull-up / pull-down resistance circuit C.

  In the open drain selection circuit B, a low level selection signal is input to the selection signal input terminals 1B and 1C. At this time, the N-channel transistor 130 is turned off (on), the P-channel transistor 120 is turned on (off), and the P (N) channel transistor 110 (140) becomes a pseudo open drain.

The N channel transistor 150 is turned off by the low (high) level selection signal input to the selection signal input terminal 1C. Further, the low (high) level selection signal input to the selection signal input terminal 1B is inverted by the inverter 170, whereby the N-channel transistor 160 is turned on (off). As a result, the N-channel transistor 160 (150) functions as a pull-down resistor.
JP 2000-165225 A

  In the signal output device of Patent Document 1, the pull-down or pull-up resistor is configured by the on-resistance of a MOS transistor. Here, it is well known that the on-resistance of the MOS transistor is in principle proportional to channel width (W) / channel length (L).

  However, there are the following problems in configuring a pull-down or pull-up resistor having a sufficient resistance value (several tens of kilohms) by a MOS transistor having an adjusted W / L ratio. In this case, a certain resistance value must be realized using a MOS transistor. For this purpose, it is necessary to shorten the channel width (W), lengthen the channel length (L), or both. By shortening the channel width (W), a nonlinear effect called a so-called narrow effect becomes remarkable. This is a problem because the controllability of the current value flowing through the MOS transistor may deteriorate. Further, when the channel length (L) is increased, so-called variation in the impurity concentration of the channel region appears remarkably. In this case, the controllability of the current value flowing through the MOS transistor may be deteriorated, which is a problem. In a practical process technology, there is a problem that variation in resistance value due to a manufactured MOS transistor becomes large.

  Further, in the circuit configuration of Patent Document 1, the transistor configuring the buffer circuit A and the transistor configuring the open drain selection circuit B are connected in series to form a two-stage configuration. In order to ensure the same drive capability (predetermined output drive current standard value IOH / IOL or predetermined output voltage standard value VOH / VOL), it is composed of a single-stage transistor in consideration of the on-resistance of the transistor. Compared to the case, the transistor size must be doubled. The occupied area on the layout becomes large, which is a problem.

  Further, the N-channel transistors 150 and 160 constituting the pull-up / pull-down resistor circuit C have a small transistor size for the purpose, and have a small parasitic capacitance component associated with the drain of each transistor. Therefore, in order to ensure the electrostatic breakdown tolerance which is an overcurrent model of these elements, it is necessary to include a resistance element between the output terminal and each drain. The same applies to the P-channel transistor 120 and the N-channel transistor 130, and these four resistance elements are redundant with respect to an overcurrent that does not know where to flow.

  The present invention has been proposed in view of the above-described problems, and by configuring the pull-up resistor and the pull-down resistor in common with one resistive element, the number of parts on the circuit configuration can be reduced and the circuit arrangement can be reduced. An object of the present invention is to provide an output buffer circuit capable of securing an electrostatic breakdown resistance of an internal circuit by using a shared resistance element while suppressing an occupied area.

  An output buffer circuit according to the present invention is an open drain type output buffer circuit provided between a first power supply line and a second power supply line, and serves as a transistor for driving a load between a first power supply line and an output terminal. And a second transistor connected between the second power supply line and the output terminal, one terminal connected to the output terminal, and the other terminal connected to the polarity switching unit. The resistance element is provided. Here, the polarity switching unit connects the other terminal of the resistance element to one of the first and second power supply lines. When the polarity switching unit selects the first power supply line, the second transistor is controlled to be conductive after the first transistor is kept non-conductive, and when the polarity switching unit selects the second power supply line, The first transistor is controlled to be conductive while the second transistor is kept nonconductive.

  Thereby, the other terminal of the resistance element can be connected to either the first power supply line or the second power supply line. Depending on the connection destination of the other terminal of the resistance element, either the first transistor or the second transistor is kept non-conductive, and the other is controlled to be conductive as a load driving transistor.

  Specifically, when the other terminal of the resistance element is connected to the first power supply line, the first transistor is turned off and the second transistor is turned on. In addition, when the other terminal of the resistance element is connected to the second power supply line, the second transistor is turned off and the first transistor is turned on. An output buffer circuit having an open drain configuration that can be connected to either the first power supply line or the second power supply line by one resistance element can be configured. That is, one resistance element can be used for both the pull-up resistor and the pull-down resistor.

  In an output buffer circuit that can be switched between an open drain configuration with a pull-up resistor and an open drain configuration with a pull-down resistor, the pull-up resistor and pull-down resistor can be shared, reducing the number of parts in the circuit configuration. An increase in the occupied area on the circuit arrangement can be suppressed.

  In addition, since the resistance element is connected between the output terminal and the polarity switching unit, it is possible to receive an abnormal voltage such as static electricity applied to the output terminal by the resistance element and to prevent propagation to the polarity switching unit. can do. The resistance element can also serve as at least a part of the electrostatic breakdown protection circuit of the polarity switching unit.

  According to the output buffer circuit of the present invention, the pull-up resistor and the pull-down resistor are configured by sharing one resistive element, thereby reducing the number of parts on the circuit configuration and suppressing the occupied area on the circuit arrangement. it can. Furthermore, the shared resistance element can also serve as an electrostatic breakdown protection circuit, and the electrostatic breakdown resistance of internal circuits such as the polarity switching unit can be ensured.

  FIG. 1 is a principle circuit diagram for explaining the principle of the present invention. The drain of the PMOS transistor 1 and the drain of the NMOS transistor 2 are connected to the output terminal 10. Further, the source of the PMOS transistor 1 and the source of the NMOS transistor 2 are connected to the power supply voltage line VDD and the ground voltage line GND, respectively. Further, signals SP and SN are input to the gate of the PMOS transistor 1 and the gate of the NMOS transistor 2, respectively.

  Further, one terminal of the resistance element 3 is connected to the output terminal 10. The other terminal of the resistance element 3 is connected to a polarity switching unit that determines the voltage polarity of the open drain. The polarity switching unit 4 is connected to the power line pressure line VDD and the ground voltage line GND, and is controlled by a polarity switching control signal CP.

  In the open drain type output buffer circuit, one of the PMOS transistor 1 and the NMOS transistor 2 is controlled as an output driver according to the signal level of either the signal SP or the signal SN. At this time, either the PMOS transistor 1 or the NMOS transistor 2 is kept non-conductive when the signal SP is at a high level or the signal SN is at a low level. At the same time, according to the signal level of the control signal CP, the polarity switching unit 4 connects the other terminal of the resistance element 3 to the power supply voltage line VDD or the ground voltage line GND.

  Specifically, when the PMOS transistor 1 is controlled to be conductive by the signal SP as an output driver, the signal SN is maintained at a low level and the NMOS transistor 2 is maintained nonconductive. At the same time, the polarity switching unit 4 connects the other terminal of the resistance element 3 to the ground voltage line GND. Thereby, if the signal SP is at a low level, the PMOS transistor 1 becomes conductive. A signal path PDP from the power supply voltage line VDD to the ground voltage line GND through the PMOS transistor 1, the resistance element 3, and the polarity switching unit 4 is conducted. One terminal of the resistance element 3 has a high voltage level, and an output signal OUT having a high voltage level is output from the output terminal 10. If the signal SP is at a high level, the PMOS transistor 1 is turned off and the signal path PDP is turned off. Since the other terminal of the resistive element 3 is connected to the ground voltage line GND, one terminal of the resistive element 3 is at a low voltage level. An output signal OUT having a low voltage level is output from the output terminal 10. As a result, the resistive element 3 functions as a pull-down resistive element, and an open drain type output buffer circuit that inverts and outputs the signal level of the signal SP is configured.

  When the NMOS transistor 2 is controlled to be turned on by the signal SN as an output driver, the signal SP is kept at a high level and the PMOS transistor 1 is kept non-conductive. At the same time, the polarity switching unit 4 connects the other terminal of the resistance element 3 to the power supply voltage line VDD. Thereby, if the signal SN is at a high level, the NMOS transistor 2 becomes conductive. A signal path PUP from the power supply voltage line VDD to the ground voltage line GND through the polarity switching unit 4, the resistance element 3, and the NMOS transistor 2 is conducted. One terminal of the resistance element 3 has a low voltage level, and an output signal OUT having a low voltage level is output from the output terminal 10. On the other hand, if the signal SN is at a low level, the NMOS transistor 2 is turned off and the signal path PUP is turned off. Since the other terminal of the resistance element 3 is connected to the power supply voltage line VDD, one terminal of the resistance element 3 is at a high voltage level. An output signal OUT having a high voltage level is output from the output terminal 10. Thereby, the resistive element 3 functions as a pull-up resistive element, and an open drain type output buffer circuit that inverts and outputs the signal level of the signal SN is configured.

  FIG. 2 is a circuit diagram of the first embodiment. 1 is a configuration in which the polarity switching unit 4A is embodied and a HiZ switching unit 5A is newly added to the principle circuit diagram of FIG. Further, resistance elements 11 and 12 for an electrostatic breakdown protection circuit are provided between the PMOS transistor 1 and the NMOS transistor 2 and the output terminal 10. About another structure, it is the same as that of a principle circuit diagram (FIG. 1), and attaches | subjects the same code | symbol. The description of the same configuration as the principle explanatory diagram is omitted.

  The polarity switching unit 4A includes PMOS and NMOS transistors 41 and 42 whose drains are connected to the other terminal of the resistance element. Each gate receives a control signal CP connected in common. The sources of the PMOS and NMOS transistors 41 and 42 are connected to the drains of the PMOS and NMOS transistors 51 and 52, respectively. The sources of the PMOS and NMOS transistors 51 and 52 are connected to the power supply voltage line VDD and the ground voltage line GND, respectively. A control signal / HZ for controlling the high impedance state is input to the gate of the PMOS transistor 51 via the inverter 53 and directly to the gate of the NMOS transistor 52.

  The polarity switching unit 4A has a function of switching the connection destination of the other terminal of the resistance element 3 in accordance with the control signal CP. That is, when the control signal CP is at a low level, the PMOS transistor 41 is turned on and the NMOS transistor 42 is turned off. On the condition that the PMOS transistor 51 is in a conductive state, the other terminal of the resistance element 3 is connected to the power supply voltage line VDD. When the control signal CP is at a high level, the PMOS transistor 41 is turned off and the NMOS transistor 42 is turned on. On the condition that the NMOS transistor 52 is in a conductive state, the other terminal of the resistance element 3 is connected to the ground voltage line GND.

Here, the PMOS transistor 51, the NMOS transistor 52, and the inverter 53 constitute a HiZ switching unit 5A. The HiZ switching unit 5A has a function of opening and closing the drains of the PMOS or NMOS transistors 1 and 2 serving as open drains, and the ground voltage line GND or the power supply voltage line VDD. That is, it is controlled whether a pull-down resistor or a pull-up resistor is connected to the open drain. When the control signal / HZ is at a low level, both the PMOS and NMOS transistors 51 and 52 are non-conductive. As a result, the drains of the PMOS or NMOS transistors 1 and 2 are disconnected from the ground voltage line GND or the power supply voltage line VDD and opened. This is a so-called open drain. When the control signal / HZ is at a high level, both the PMOS and NMOS transistors 51 and 52 are turned on. Thereby, the drains of the PMOS or NMOS transistors 1 and 2 are connected to the ground voltage line GND or the power supply voltage line VDD. The open drain is connected to either the ground voltage line GND or the power supply voltage line VDD via a pull-down or pull-up resistor shared by the polarity switching unit 4A and one resistance element.

  The resistance elements 11 and 12 for the electrostatic breakdown protection circuit are resistance elements for protecting the PMOS and NMOS transistors 1 and 2 (particularly the drain) from electrostatic breakdown. The PMOS and NMOS transistors 1 and 2 are output driver transistors, and have a transistor size (on-resistance <10−Ohm) with a large driving current capability. Since the parasitic capacitance component associated with the drain becomes large, it is generally sufficient that the resistance elements 11 and 12 that cause the drain voltage lowering action accompanying overvoltage discharge (overcurrent model) have a small resistance value (<50−Ohm). Is. Further, even when the source and drain of a transistor have a metal source / drain structure, it is common to add a resistance element having a constant resistance value per predetermined channel width. When a large channel width is configured like the output driver transistor, a plurality of transistors having a predetermined channel length are arranged in parallel between the source and drain. Therefore, the resistance elements 11 and 12 which are equivalent resistances of the ESD protection resistance elements added to the respective drains have a small resistance value.

  Also, protection from electrostatic breakdown must be taken into account for PMOS and NMOS transistors 41 and 42 as well. This is because the drains of the PMOS and NMOS transistors 41 and 42 are connected to the output terminal 10. Here, the PMOS transistor 41 and the NMOS transistor 42 are provided for causing the resistance element 3 to function as a pull-up / pull-down resistor. This is a transistor having a role of connecting the resistance element 3 to the power supply voltage line VDD and the ground voltage line GND. As a pull-up / pull-down resistor, a relatively large resistance value (10K-Ohm) is generally allowed. Therefore, the on-resistance values of the PMOS transistor 41 and the NMOS transistor 42 have a wide allowable range, The magnitude of the resistance value is not a problem. Accordingly, the PMOS transistor 41 and the NMOS transistor 42 may have a small size limited as a transistor size.

  Therefore, although the parasitic capacitance component associated with the drains of the PMOS transistor 41 and the NMOS transistor 42 is limited, the resistance element 3 connected between the drains of the PMOS transistor 41 and the NMOS transistor 42 and the output terminal 10 is relatively Has a large resistance value. For this reason, the resistance element 3 which is also used as a pull-up / pull-down resistance is also used as a resistance element for electrostatic breakdown protection, and ensures an electrostatic breakdown tolerance which is an overcurrent model. The resistance element 3 can also realize sufficient protection from electrostatic breakdown for the PMOS transistor 41 and the NMOS transistor 42.

  FIG. 3 is a circuit diagram of the second embodiment. In contrast to the first embodiment (FIG. 2), a HiZ switching unit 5B is provided instead of the HiZ switching unit 5A. About another structure, it is the same as that of 1st Embodiment (FIG. 2), and attaches | subjects the same code | symbol. The description of the same configuration as that of the first embodiment (FIG. 2) is omitted.

  The HiZ switching unit 5B connects between the other terminal of the resistance element 3 and the polarity switching unit 4A. An inverter 53 is added to the transmission gate 54 to configure the HiZ switching unit 5B. A control signal / HZ for controlling the high impedance state is input to the gate of the PMOS transistor of the transmission gate 54 via the inverter 53 and directly to the gate of the NMOS transistor of the transmission gate 54.

  The operational effects of the HiZ switching unit 5B are the same as the operational effects of the HiZ switching unit 5A. The description here is omitted.

  FIG. 4 is a circuit diagram of the third embodiment. Instead of the HiZ switching units 5A and 5B in the first and second embodiments (FIGS. 2 and 3), a HiZ control unit 6A is provided. About another structure, it is the same as that of 1st, 2nd embodiment (FIG. 2, FIG. 3), and attaches | subjects the same code | symbol. The description of the same configuration as the principle explanatory diagram is omitted.

  The HiZ control unit 6A also serves as voltage polarity control in addition to voltage application to the open drain. A NAND circuit 61 is connected to the gate of the PMOS transistor 41 of the polarity switching unit 4A. A NOR circuit 62 is connected to the gate of the NMOS transistor 42 of the polarity switching unit 4A.

  A control signal CP is input to the NAND circuit 61 via the control signal / HZ and the inverter 64. The NOR circuit 62 is supplied with a control signal / HZ via an inverter 63 and a control signal CP via an inverter 64.

  When the control circuit / HZ is at a low level, the output signal of the NAND circuit 61 is fixed at a high level regardless of the control signal CP. The output signal of the NOR circuit 62 is fixed at a low level. As a result, both the PMOS and NMOS transistors 41 and 42 are kept non-conductive, and the drains of the PMOS or NMOS transistors 1 and 2 are in an open drain state.

  When the control circuit / HZ is at a high level, both the NAND circuit 61 and the NOR circuit 62 function as inverters. The control signal CP inverted by the inverter 64 is re-inverted and input to the PMOS and NMOS transistors 41 and 42. When a signal having the same phase as the control signal CP is input, one of the PMOS or NMOS transistors 41 and 42 is turned on and the other is turned off. The other terminal of resistance element 3 is connected to power supply voltage line VDD or ground voltage line GND. A pull-up resistor or a pull-down resistor is connected.

  Here, the PMOS transistor 1 is an example of a first transistor, and the NMOS transistor 2 is an example of a second transistor. The power supply voltage line VDD is an example of a first power supply line, and the ground voltage line GND is an example of a second power supply line. The PMOS transistor 41 is an example of a third transistor, and the NMOS transistor 42 is an example of a fourth transistor. The PMOS transistor 51 is an example of a fifth transistor, and the NMOS transistor 52 is an example of a sixth transistor.

  As described above in detail, according to the embodiment of the present invention, the other terminal of the resistance element 3 can be connected to either the power supply voltage line VDD or the ground voltage line GND. When the resistance element 3 is connected to the power supply voltage line VDD, the PMOS transistor 1 is turned off by the signal SP, and the NMOS transistor 2 is controlled to be turned on by the signal SN. When the resistance element 3 is connected to the ground voltage line GND, the NMOS transistor 2 is turned off by the signal SN, and the PMOS transistor 1 is controlled to be turned on by the signal SP. An output buffer circuit having an open drain configuration in which one resistance element 3 can be connected to both the power supply voltage line VDD and the ground voltage line GND can be configured. The resistance element 3 can be used for either a pull-up resistor or a pull-down resistor.

  In an output buffer circuit that can be switched between an open drain configuration with a pull-up resistor and an open drain configuration with a pull-down resistor, the pull-up resistor and pull-down resistor can be shared, reducing the number of parts in the circuit configuration. An increase in the occupied area on the circuit arrangement can be suppressed.

  In addition, since the resistance element 3 is connected between the output terminal 10 and the polarity switching unit 4A or the HiZ switching unit 5B, the resistance element 3 can serve as a resistance element for electrostatic breakdown protection. .

  The special actions and effects of the present application are shown below. In Patent Document 1, a buffer circuit A (110, 140) that is an output transistor and an open drain selection circuit B (120, 130) that is a polarity inverting element are combined in series, and are combined in parallel with a pull-up / pull-down resistor circuit C. Yes. On the other hand, in the present application, the output transistor (1, 2) connected to the output terminal 10 side and the pull-up resistor and pull-down resistor combined in one resistor element are combined in parallel. The polarity switching part (41, 42) which is an inverting element is combined in series. Output transistor (1,2) and polarity switching part (41,42) are combined in parallel. As a result, the ability of the signal paths PDP and PUP from the power supply voltage line VDD to the ground voltage line GND can be adjusted with one resistance element 3 while keeping the output impedance viewed from the output terminal 10 side low. This means that the polarity switching unit 4 can be set separately from the output transistors (1, 2). As a result, the polarity switching unit 4 can be made small and simple. In addition, one resistive element 3 prevents the deterioration of the electrostatic breakdown withstand characteristics as a negative effect of making the polarity switching part 4 small.

Needless to say, the present invention is not limited to the above-described embodiment, and various improvements and modifications can be made without departing from the spirit of the present invention.
For example, in the present embodiment, the configuration of the polarity switching unit 4A has been exemplified, but the present invention is not limited to this. Any configuration can be used as long as the connection between the other terminal of the resistance element 3 and the power supply voltage line VDD and the ground voltage line GND can be switched.
In the first embodiment, the polarity switching unit 4A and the HiZ switching unit 5A connected in series between the power supply and the other terminal of the resistance element 3 can be switched in order.

It is a principle circuit diagram explaining the principle of this invention. It is a circuit diagram of a 1st embodiment. It is a circuit diagram of a 2nd embodiment. It is a circuit diagram of a 3rd embodiment. FIG. 6 is a circuit diagram disclosed in Patent Document 1.

Explanation of symbols

1, 41, 51 PMOS transistor 2, 42, 52 NMOS transistor 3 Resistance element 4, 4A Polarity switching unit 5A, 5B HiZ switching unit 6A HiZ control unit 10 Output terminal 53 Inverter 54 Transmission gate

Claims (5)

An open drain type output buffer circuit provided between the first and second power supply lines,
A first transistor connected between the first power supply line and the output terminal and driving a load;
A second transistor connected between the second power supply line and the output terminal and driving a load;
A resistance element having one terminal connected to the output terminal;
A polarity switching part for connecting the other terminal of the resistance element to either one of the first or second power supply line,
When the polarity switching unit selects the first power supply line, the second transistor is controlled to be conductive while the first transistor is maintained nonconductive, and the polarity switching unit is connected to the second power supply line. When selecting, the output buffer circuit is characterized in that the second transistor is maintained nonconductive and the first transistor is controlled to be conductive.   A HiZ switching unit is provided in a path between the other terminal of the resistance element and the first or second power supply line connected by the polarity switching unit, and controls conduction of the path. Item 4. The output buffer circuit according to Item 1. The polarity switching unit controls conduction between the other terminal of the resistance element and the first power supply line, and controls the conduction between the other terminal of the resistance element and the second power supply line. And a fourth transistor that
The output buffer circuit according to claim 2, wherein the HiZ switching unit includes a fifth transistor connected in series to the third transistor and a sixth transistor connected in series to the fourth transistor.   The output buffer circuit according to claim 2, wherein the HiZ switching unit is a transmission gate provided between the other terminal of the resistance element and the polarity switching unit.   The output buffer circuit according to claim 1, further comprising a HiZ control unit that performs switching control of the polarity switching unit.

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