JP2009177247A - Comparator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a comparator capable of achieving the driving with low power supply voltage, low current consumption and high-speed operation. <P>SOLUTION: A current mirror circuit of the comparator consists of two pairs of circuits consisting of two transistors connected in series, and of the two transistors connected in series, the transistor connected to a power supply side or a ground side has a gate length longer than the gate length of the other transistor out of the two transistors connected in series. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a comparator, and more particularly to a comparator having a current mirror circuit.

  In recent years, a comparator having three characteristics of low power supply voltage driving, low current consumption, and high-speed operation is desired.

  A conventional comparator will be described below with reference to the drawings. FIG. 2 is a circuit diagram showing an example of the configuration of a conventional comparator. 2 includes a comparison circuit 11, a current mirror circuit 12 serving as a current source of the comparison circuit 11, and a current mirror circuit 13 connected to the output of the comparison circuit 11.

  The comparison circuit 11 includes transistors M1 and M2. The current mirror circuit 12 includes transistors M3 and M4 connected to a constant current source. The current mirror circuit 13 includes transistors M5 and M6. The transistors M1 to M4 are n-channel MOS transistors, and the transistors M5 and M6 are p-channel MOS transistors.

  The gates of the transistor M3 and the transistor M4 are connected and connected to the drain of the transistor M3. The drain of the transistor M3 is connected to a constant current source. The sources of the transistors M3 and M4 are grounded. The drain of the transistor M4 is connected to the sources of the transistors M1 and M2.

  Input signals are respectively applied to the gates of the transistors M1 and M2. The drain of the transistor M1 is connected to the drain of the transistor M5, and the drain of the transistor M2 is connected to the drain of the transistor M6. The sources of the transistors M5 and M6 are connected to the power supply voltage VDD, and the gates of the transistors M5 and M6 are connected and connected to the drain of the transistor M6. The comparator 10 outputs the voltage at the connection point between the drain of the transistor M1 and the drain of the transistor M5 as the output of the comparator 10.

  In the comparator 10, when the voltage of the input signal + IN applied to the gate of the transistor M1 is higher than the voltage of the input signal −IN applied to the gate of the transistor M2, the output becomes L level. Further, when the voltage of the input signal + IN is lower than the voltage of the input signal -IN, the output becomes H level.

  In the comparator 10, for example, the threshold voltages of the transistors M5 and M6 may be shifted due to manufacturing variations of the transistors M5 and M6 constituting the current mirror circuit 13. In this case, a deviation occurs between the drain current of the transistor M5 and the drain current of the transistor M6, and an accurate mirror ratio cannot be obtained and an offset occurs. Further, even when the drain-source voltages of the transistors M5 and M6 vary due to the fluctuation of the power supply voltage VDD, an accurate mirror ratio cannot be obtained and an offset occurs. Further, in order to perform high-speed operation in the comparator 10, it is necessary to increase the voltage gain.

  FIG. 3 shows an improved version of the comparator 10 shown in FIG. FIG. 3 is a circuit diagram showing another example of the configuration of a conventional comparator. The comparator 10A shown in FIG. 3 uses a cascode connection for the current mirror circuit 13 of the comparator 10 shown in FIG.

  In the current mirror circuit 13A of the comparator 10A, transistors M7 and M8 are provided between the sources of the transistors M5 and M6 and the power supply voltage VDD. Transistors M7 and M8 are p-channel MOS transistors.

  The sources of the transistors M7 and M8 are connected to the power supply voltage VDD. The gates of the transistors M7 and M8 are connected to each other, and are connected to the drain of the transistor M7. The drain of the transistor M7 is connected to the source of the transistor M5. The drain of the transistor M8 is connected to the source of the transistor M6.

  In the comparator 10A shown in FIG. 3, the transistor M7 and the transistor M8 can reduce the influence of the manufacturing variations of the transistors M5 and M6 and the fluctuation of the power supply voltage VDD, and can take an accurate mirror ratio. Further, when the current mirror circuit 13A is considered as an active load in the comparator 10A, the active load can be increased and the voltage gain can be increased. In addition, since the voltage gain can be increased, current consumption can be reduced.

Patent Document 1 describes a differential amplifier circuit with a reduced power supply current that is less affected by fluctuations in the power supply voltage or transistor threshold voltage when the power supply voltage is low.
JP 7-154164 A

  However, the conventional comparator 10A shown in FIG. 3 is configured such that the comparator 10 shown in FIG. 2 connects three transistors between the ground and the power supply voltage VDD. The configuration is such that four transistors are connected between them. Therefore, for example, when the drain-source voltage required for operating the transistor in the saturation region is about 0.3 V, the power supply voltage required for the comparator 10 is 0.9 V, whereas in the comparator 10A, the power supply voltage is 1.2V is required. Therefore, the low power supply voltage drive cannot be realized with the comparator 10A.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a comparator capable of realizing low power supply voltage driving, low current consumption, and high-speed operation. .

  The present invention employs the following configuration in order to achieve the above object.

The comparator of the present invention includes a current source (160) of the comparison circuit (110),
A first current mirror circuit (130) connected to one output of the comparison circuit (110);
A second current mirror circuit (140) connected to the other output of the comparison circuit (110);
A third current mirror circuit (150) for controlling an output current following the current output from one of the comparison circuits (110) in the first current mirror circuit (130),
The output on the side that follows in the output of the second current mirror circuit (140) and the output on the side that follows in the third current mirror circuit (150) are connected,
With the configuration in which the voltage at the connection point is output, low power supply voltage driving, low current consumption, and high-speed operation can be realized.

In the comparator of the present invention, the first to third current mirror circuits (130, 140, 150) have two sets of circuits composed of two transistors connected in series,
In the first current mirror circuit (130) and the second current mirror circuit (140),
Of the two transistors connected in series, the gate length of the transistors (M16, M18, M20, M22) connected to the power supply side is the same as that of the transistors (M17, M19, M21, M23) connected to the ground side. Longer than the gate length,
In the third current mirror circuit (150),
Of the two transistors connected in series, the gate length of the transistors (M25, M27) connected to the ground side may be longer than the gate length of the transistors (M24, M26) connected to the power supply side. .

In the comparator of the present invention, the current source (160)
A constant current source (105) and a current mirror circuit (120) may be used.

In the comparator of the present invention, the current mirror circuit (120) constituting the current source (160)
Having two sets of circuits composed of two transistors connected in series;
Of the two transistors connected in series, the gate length of the transistors (M13, M15) connected to the ground side may be longer than the gate length of the transistors (M12, M14) connected to the power supply side. .

  Note that the reference numerals in the parentheses are given for ease of understanding, are merely examples, and are not limited to the illustrated modes.

  According to the present invention, low power supply voltage driving, low current consumption, and high-speed operation can be realized.

In the present invention, the current mirror circuit of the comparator is composed of two sets of circuits composed of two transistors connected in series, and the two transistors connected in series are connected to the power supply side or the ground side. By setting the gate length of the transistor longer than the gate length of the other of the two transistors connected in series, low power supply voltage driving, low current consumption, and high speed operation are realized.
(Embodiment)
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a comparator of the present invention.

  The comparator 100 of the present invention includes a comparison circuit 110, current mirror circuits 130, 140, 150, and a current source 160.

  The comparison circuit 110 is supplied with a current from a current source 160 including a constant current source 105 and a current mirror circuit 120, and receives an input signal + IN and an input signal -IN. The current mirror circuit 130 is connected to one output of the comparison circuit 110, and the current mirror circuit 140 is connected to the other output of the comparison circuit 110. The current mirror circuit 150 is connected to the output on the tracking side of the current mirror circuit 130. The output on the tracking side of the current mirror circuit 150 is connected to the output on the tracking side of the current mirror circuit 140, and the voltage at this connection point becomes the output OUT of the comparator 100.

  In the comparator 100 of the present embodiment, when the voltage of the input signal + IN is higher than the voltage of the input signal −IN, the output OUT becomes the H level. Further, when the voltage of the input signal + IN is lower than the voltage of the input signal −IN, the output OUT becomes L level.

  Hereinafter, each circuit constituting the comparator 100 of the present embodiment will be described.

  The comparison circuit 110 includes a transistor M10 and a transistor M11. The transistors M10 and M11 are n-channel MOS transistors. An input signal + IN is applied to the gate of the transistor M10. An input signal -IN is applied to the gate of the transistor M11. The drain of the transistor M10 is connected to the drain of the transistor M23 included in the current mirror circuit 140. The drain of the transistor M11 is connected to the drain of the transistor M17 included in the current mirror circuit 130. The sources of the transistors M10 and M11 are connected to each other, and are connected to the drain of the transistor M12 included in the current mirror circuit 120.

  The current mirror circuit 120 includes a transistor M12, a transistor M13, a transistor M14, and a transistor M15. Transistors M12 to M15 are n-channel MOS transistors.

  The source of the transistor M12 and the drain of the transistor M13 are connected, and the source of the transistor M13 is grounded. The gates of the transistors M12, M13, M14, and M15 are connected to the drain of the transistor M14. The drain of the transistor M14 is connected to the constant current source 105, and the source of the transistor M14 is connected to the drain of the transistor M15. The source of the transistor M15 is grounded.

  The current mirror circuit 130 includes a transistor M16, a transistor M17, a transistor M18, and a transistor M19. Transistors M16 to M19 are p-channel MOS transistors. The gates of the transistors M16 to M19 are connected to the drain of the transistor M17.

  The source of the transistor M16 is connected to the power supply voltage VDD, and the drain of the transistor M16 is connected to the source of the transistor M17. The drain of the transistor M17 is connected to the drain of the transistor M11 included in the comparison circuit 110. The source of the transistor M18 is connected to the power supply voltage VDD, and the drain of the transistor M18 is connected to the source of the transistor M19. The drain of the transistor M19 is connected to the drain of the transistor M24 included in the current mirror circuit 150.

  The current mirror circuit 140 includes a transistor M20, a transistor M21, a transistor M22, and a transistor M23. Transistors M20 to M23 are p-channel MOS transistors. The gates of the transistors M20 to M23 are connected to the drain of the transistor M23.

  The source of the transistor M22 is connected to the power supply voltage VDD, and the drain of the transistor M22 is connected to the source of the transistor M23. The drain of the transistor M23 is connected to the drain of the transistor M10 included in the comparison circuit 110. The source of the transistor M20 is connected to the power supply voltage VDD, and the drain of the transistor M20 is connected to the source of the transistor M21. The drain of the transistor M21 is connected to the drain of the transistor M26 included in the current mirror circuit 150.

  The current mirror circuit 150 includes a transistor M24, a transistor M25, a transistor M26, and a transistor M27. Transistors M24 to M27 are n-channel MOS transistors. The gates of the transistors M24 to M27 are connected to the drain of the transistor M24.

  The drain of the transistor M24 is connected to the drain of the transistor M19, and the source of the transistor M24 is connected to the drain of the transistor M25. The source of the transistor M25 is grounded. The drain of the transistor M26 is connected to the drain of the transistor M21, and the source of the transistor M26 is connected to the drain of the transistor M27. The source of the transistor M27 is grounded.

  In the current mirror circuit 100 of the present invention, in the current mirror circuits 130 and 140, the gate lengths of the transistors M16, M18, M20, and M22 connected to the power supply voltage VDD side are set to the transistor M17 connected to the ground side. The gate lengths of the transistors M19, M21, and M23 are longer. Specifically, the gate length of the transistor connected to the power supply voltage VDD side in the current mirror circuits 130 and 140 is about three times the gate length of the transistor connected to the ground side when the gate width is the same. It was made to become.

  In the current mirror circuit 150, the gate lengths of the transistors M25 and M27 connected to the ground side are made longer than the gate lengths of the transistors M24 and M26 grounded to the power supply side. Specifically, the gate length of the transistor connected to the ground side is set to be about three times the gate length of the transistor grounded to the power source side when the gate width is the same.

  Further, in the comparator 100, similarly to the configuration of the current mirror circuit 150 in the current mirror circuit 120, the gate lengths of the transistors M13 and M15, which are transistors on the ground side, are the same when the gate width is the same. The gate length is about 3 times longer.

  As described above, in the comparator 100 of this embodiment, in the current mirror circuit 130 and the current mirror circuit 140, a transistor having a long gate length is provided on the power supply voltage VDD side, and in the current mirror circuit 150, a transistor having a long gate length is provided on the ground side. The configuration realizes low power supply voltage drive, low current consumption, and high-speed operation.

  First, realization of low power supply voltage driving in the current mirror circuit 100 of the present embodiment will be described.

  For example, in the current mirror circuit 130, the gate length of the transistor M16 provided on the power supply voltage VDD side is about three times the gate length of the transistor M17 when the gate width is the same. Then, the pinch-off voltage of the transistor M16 becomes smaller than the pinch-off voltage of the transistor M17, and the transistor M16 starts the operation in the saturation region first. Therefore, the drain current Id16 of the transistor M16 becomes a saturation current.

  In the current mirror circuit 130, the sum of the drain current Id16 of the transistor M16 and the drain current Id17 of the transistor M17 is determined by the current Iref output from the comparison circuit 110. Therefore, when the drain current Id16 of the transistor M16 becomes a saturation current, the drain current Id17 of the transistor M17 inevitably decreases. For this reason, the transistor M17 operates in a non-saturated region, and the drain-source voltage of the transistor M17 decreases.

  Therefore, in the current mirror circuit 130, the sum of the drain-source voltage of the transistor M16 and the drain-source voltage of the transistor M17 can be set to substantially the same value as the pinch-off voltage of the transistor M16. In this embodiment, the pinch-off voltage of the transistor M16 is about 0.2V. Therefore, in this embodiment, the voltage between the source of the transistor M16 and the drain of the transistor M17 can be about 0.2V.

  The relationship between the transistor M18 and the transistor M19 is the same as the relationship between the transistor M16 and the transistor M17. That is, the sum of the voltage between the drain and source of the transistor M18 and the voltage between the drain and source of the transistor M19 can be set to substantially the same value as the pinch-off voltage of the transistor M18.

  The current mirror circuit 140 is the same as the current mirror circuit 130. That is, the sum of the drain-source voltage of the transistor M20 and the drain-source voltage of the transistor M21, the sum of the drain-source voltage of the transistor M22 and the drain-source voltage of the transistor M22, the pinch-off voltage of the transistor M20, and the transistor M22 The same value as the pinch-off voltage.

  In the embodiment, the gate lengths of the transistors M16, M18, M20, and M22 are the same, and the pinch-off voltages are also the same.

  The current mirror circuits 120 and 150 of this embodiment are the same as the current mirror circuits 130 and 140. In the current mirror circuit 120, the gate lengths of the transistors M13 and M15 are longer than the gate lengths of the transistors M12 and M14. Specifically, the gate lengths of the transistors M13 and M15 are determined so that the pinch-off voltages of the transistors M13 and M15 are about 0.2V.

  In the current mirror circuit 150, the gate lengths of the transistors M25 and M27 are longer than the gate lengths of the transistors M24 and M26. Specifically, the gate lengths of the transistors M25 and M27 are determined so that the pinch-off voltages of the transistors M25 and M27 are about 0.2V.

  Therefore, in the comparator 100 of the present embodiment, if the current mirror circuits 120, 130, 140, and 150 each supply a voltage of about 0.2 V, the transistor connected to the power supply voltage VDD side or the transistor connected to the ground side Can be operated in the saturation region. Therefore, the comparator 100 of the present embodiment can be driven even when the power supply voltage VDD is 0.9 V or less, and low power supply voltage driving can be realized.

  In the present embodiment, since the transistors having a long gate length are provided on the power supply voltage VDD side of the current mirror circuits 130 and 140 and the ground side of the current mirror circuits 120 and 150, fluctuations in the power supply voltage VDD can be absorbed. In this embodiment, the drain currents of the transistor M16, the transistor M18, the transistor M20, the transistor M22, the transistor M25, and the transistor M27 do not depend on the power supply voltage VDD, so that the drain current fluctuation can be suppressed. Therefore, an accurate mirror ratio can be realized in the current mirror circuits 130, 140, and 150, and the offset can be reduced.

  Next, realization of high-speed operation in this embodiment will be described.

  In this embodiment, the transistors M16, M18, M20, and M22 are provided in the current mirror circuits 130 and 140, and the transistors M25 and M27 are provided in the current mirror circuit 150, thereby enabling high-speed operation.

  The transistor M16, the transistor M18, the transistor M20, the transistor M22, the transistor M25, and the transistor M27 can be regarded as resistors having higher resistance values than the other transistors that constitute each current mirror circuit. Therefore, in this embodiment, the voltage gain can be increased as compared with the conventional comparator. For this reason, according to the comparator 100 of the present embodiment, high-speed operation can be realized.

  Next, realization of low current consumption in this embodiment will be described.

  In the current mirror circuit 100 of the present embodiment, the voltage gain can be increased as described above. Therefore, in the current mirror circuit 100 of this embodiment, it is possible to obtain a sufficient voltage fluctuation with a low current, so that a low current consumption can be realized.

  As described above, according to the comparator 100 of the present embodiment, low power supply voltage driving, low current consumption, and high-speed operation can be realized.

  As described above, the present invention has been described based on the embodiment, but the present invention is not limited to the requirements shown in the embodiment. With respect to these points, the gist of the present invention can be changed without departing from the scope of the present invention, and can be appropriately determined according to the application form.

It is a circuit diagram which shows the comparator of this invention. It is a circuit diagram which shows an example of a structure of the conventional comparator. It is a circuit diagram which shows another example of a structure of the conventional comparator.

Explanation of symbols

100 Comparator 105 Constant Current Source 110 Comparison Circuit 120, 130, 140, 150 Current Mirror Circuit 160 Current Source

Claims (4)

A current source of the comparison circuit;
A first current mirror circuit connected to one output of the comparison circuit;
A second current mirror circuit connected to the other output of the comparison circuit;
A third current mirror circuit that controls an output current that follows a current output from one of the comparison circuits in the first current mirror circuit;
The output on the side that follows in the output of the second current mirror circuit and the output on the side that follows in the third current mirror circuit are connected,
A comparator characterized in that the voltage at the connection point is output. The first to third current mirror circuits have two sets of circuits composed of two transistors connected in series,
In the first current mirror circuit and the second current mirror circuit,
Of the two transistors connected in series, the gate length of the transistor connected to the power supply side is longer than the gate length of the transistor connected to the ground side,
In the third current mirror circuit,
2. The comparator according to claim 1, wherein, of the two transistors connected in series, a gate length of a transistor connected to the ground side is longer than a gate length of a transistor connected to the power source side.   3. The comparator according to claim 1, wherein the current source includes a constant current source and a current mirror circuit. The current mirror circuit constituting the current source is:
Having two sets of circuits composed of two transistors connected in series;
4. The comparator according to claim 3, wherein, of the two transistors connected in series, a gate length of a transistor connected to the ground side is longer than a gate length of a transistor connected to the power supply side.

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