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JP2009152253A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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Publication number
JP2009152253A
JP2009152253A JP2007326622A JP2007326622A JP2009152253A JP 2009152253 A JP2009152253 A JP 2009152253A JP 2007326622 A JP2007326622 A JP 2007326622A JP 2007326622 A JP2007326622 A JP 2007326622A JP 2009152253 A JP2009152253 A JP 2009152253A
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JP
Japan
Prior art keywords
semiconductor device
protruding electrode
wiring board
protruding
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2007326622A
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Japanese (ja)
Inventor
Yuichiro Yamada
雄一郎 山田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Priority to JP2007326622A priority Critical patent/JP2009152253A/en
Priority to US12/331,467 priority patent/US8390117B2/en
Publication of JP2009152253A publication Critical patent/JP2009152253A/en
Priority to US13/777,670 priority patent/US8841772B2/en
Pending legal-status Critical Current

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
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    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H01L2924/1533—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate
    • H01L2924/15331—Connection portion the connection portion being formed on the die mounting surface of the substrate the connection portion being formed both on the die mounting surface of the substrate and outside the die mounting surface of the substrate being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L2924/181—Encapsulation
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Abstract

【課題】高信頼性の３次元実装が実現できる突起電極を備えた半導体装置およびその製造方法を提供する。
【解決手段】一方の面の素子実装領域に複数の接続端子6を有し、その外周側の領域に前記複数の接続端子6に各々接続した複数のランド8およびその上に形成された突起電極9を有し、他方の面に複数の裏面ランド11を有する配線基板5と、前記配線基板5の素子実装領域に搭載され電気的に接続された半導体素子1と、前記半導体素子1を包埋するように前記配線基板5の一方の面に形成された封止樹脂部10とを備えた半導体装置において、前記突起電極9は、前記封止樹脂部10の上面から端部が突出し、その突出部の先端が平担面13であり、かつ、前記突出部よりも断面が大きい部分が前記封止樹脂部10内に位置するものとする。
【選択図】図１A semiconductor device including a protruding electrode capable of realizing highly reliable three-dimensional mounting and a method of manufacturing the same are provided.
SOLUTION: A plurality of connection terminals 6 are provided in an element mounting region on one surface, a plurality of lands 8 connected to the plurality of connection terminals 6 in a region on the outer peripheral side, and a protruding electrode formed thereon Wiring board 5 having a plurality of backside lands 11 on the other surface, semiconductor element 1 mounted in and electrically connected to an element mounting region of wiring board 5, and embedding semiconductor element 1 In the semiconductor device including the sealing resin portion 10 formed on one surface of the wiring board 5 as described above, the protruding electrode 9 has an end protruding from the upper surface of the sealing resin portion 10, and the protrusion It is assumed that the tip of the part is the flat bearing surface 13 and a part having a larger cross section than the protruding part is located in the sealing resin part 10.
[Selection] Figure 1

Description

本発明は、３次元実装に使用される半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device used for three-dimensional mounting and a manufacturing method thereof.

従来、携帯電話、デジタルカメラ、および携帯用パソコン等に、Package on Package 型（以下「ＰｏＰ型」と記す）半導体装置が使用されており、かかる３次元実装に有利な半導体装置として、積層のための突起電極の上部を露出させた各種の薄型小型の半導体装置が提案されている。   Conventionally, package on package type (hereinafter referred to as “PoP type”) semiconductor devices have been used for mobile phones, digital cameras, portable personal computers, and the like, and as a semiconductor device advantageous for such three-dimensional mounting, for stacking. Various thin and small semiconductor devices in which the upper portions of the protruding electrodes are exposed have been proposed.

例えば、特許文献１では、可撓性配線基板の表面に半導体素子を搭載し、この半導体素子を越えて突出する突起電極を形成するとともに、突起電極位置の基板裏面に裏面電極を形成し、前記半導体素子および突起電極を樹脂封止する際に、シリコンゴム等の弾性体を成形面に配設した樹脂封止金型を用いて、樹脂成形時の圧縮力によって、突起電極の両端部位置の弾性体を変形させる状態で成形している。このようにすると、突起電極の基板表面側の端部は弾性体に密着状態となって、樹脂が付着することなく封止樹脂面から突出して露出する一方で、配線基板自体も裏面電極が突出するように変形する。つまり、樹脂封止する工程で、突起電極の一方の端部を突出させて露出させると同時に、裏面電極も突出させることができるのであり、従来のようにはんだの裏面突起電極をリフローで配線基板の貫通孔に流し込む手間は不要であり、信頼性の高い電気接続構造を容易に形成可能である。   For example, in Patent Document 1, a semiconductor element is mounted on the surface of a flexible wiring board, a protruding electrode protruding beyond the semiconductor element is formed, and a back electrode is formed on the back surface of the substrate at the protruding electrode position. When resin-sealing the semiconductor element and the protruding electrode, a resin-sealed mold having an elastic body such as silicon rubber disposed on the molding surface is used to compress the both ends of the protruding electrode by the compressive force during resin molding. The elastic body is molded in a deformed state. In this way, the end portion of the protruding electrode on the substrate surface side is in close contact with the elastic body and protrudes from the sealing resin surface without being attached to the resin, while the back surface electrode also protrudes from the wiring substrate itself. Deform to That is, in the resin sealing step, one end of the protruding electrode is protruded and exposed, and at the same time, the back electrode can be protruded. This eliminates the need to pour into the through-hole, and can easily form a highly reliable electrical connection structure.

また特許文献２では、剥離性フィルムを密着させた上下金型内に、半導体素子を配線基板にボンディングワイヤーもしくはバンプで電気的に接続したものをセットし、封止用シリコーンゴム組成物もしくは液状熱硬化性エポキシ樹脂組成物を供給して圧縮成形することにより、成形品たる半導体装置の反りを抑制するとともに、ワイヤーボンドしている場合は圧縮成形時のワイヤーの変形や断線を防止し、ウェハーレベルＣＳＰの場合にはウェハー主面のバンプの一部を封止樹脂面から露出させるようにしている。   In Patent Document 2, a semiconductor element is electrically connected to a wiring board with bonding wires or bumps in an upper and lower mold having a peelable film adhered thereto, and a sealing silicone rubber composition or liquid heat By supplying a curable epoxy resin composition and compression molding, it suppresses warping of the semiconductor device that is the molded product, and when wire bonding is performed, prevents deformation and disconnection of the wire during compression molding at the wafer level. In the case of CSP, a part of bumps on the wafer main surface is exposed from the sealing resin surface.

特許文献３では、半導体素子が接合された配線基板上に外部電極形成用の突起電極を形成し、樹脂封止する際に、前記突起電極を樹脂封止用金型で圧縮して５％以上押し潰すことにより、突起電極の先端面を樹脂封止用金型に密着状態として樹脂成形を行い、樹脂の付着のない先端面を樹脂表面から露出させるとともに、樹脂成形前の突起電極の高さにバラツキがある場合も緩和するようにしている。
特開２００３−１７４０４８号公報 特開２００４−２９６５５５号公報 特開２００３−１７４１２４号公報 In Patent Document 3, when a protruding electrode for forming an external electrode is formed on a wiring substrate to which a semiconductor element is bonded, and the resin sealing is performed, the protruding electrode is compressed by a resin sealing mold to be 5% or more. By crushing, the tip surface of the protruding electrode is in close contact with the mold for resin sealing, resin molding is performed, the tip surface without adhesion of the resin is exposed from the resin surface, and the height of the protruding electrode before resin molding Even if there is a variation in the range, it is alleviated.
Japanese Patent Laid-Open No. 2003-174048 JP 2004-296555 A JP 2003-174124 A

しかしながら、上述した従来の各技術には次のような問題がある。まず特許文献１の技術では、突起電極としてスタッド棒を配線基板に取り付けているのであるが、スタッド棒の先端は平坦面であるため、その平坦面と樹脂封止金型の弾性体との間に樹脂が入り込み、結果的に突起電極に樹脂残りが生じることがある。またスタッド棒は円柱状であるため、製品となった半導体装置の実装後に突起電極に縦方向の応力が発生したときに、その側面と封止樹脂との界面で剥離が起きやすく、更に強い応力が発生したときには、配線基板への取り付け部でも剥離が起きて抜け出てしまう。配線基板への取り付けから樹脂封止までの間にスタッド棒の傾きや脱落が生じて、封止樹脂面でのスタッド棒先端部の位置がずれたり、スタッド棒が欠落することもある。   However, the conventional techniques described above have the following problems. First, in the technique of Patent Document 1, a stud rod is attached to a wiring board as a protruding electrode. Since the tip end of the stud rod is a flat surface, the flat surface and the elastic body of the resin-sealed mold are interposed. As a result, resin may enter the bump electrode, resulting in residual resin on the bump electrode. In addition, since the stud rod is cylindrical, when vertical stress is generated on the protruding electrode after mounting the semiconductor device that is the product, peeling is likely to occur at the interface between the side surface and the sealing resin. When this occurs, peeling occurs even at the attachment portion to the wiring board, and it comes out. In some cases, the stud rod is tilted or dropped between the mounting on the wiring board and the resin sealing, and the position of the tip end portion of the stud rod on the sealing resin surface may be shifted or the stud rod may be missing.

さらに、このスタッド棒を取り付ける際に、配線基板の貫通孔にスタッド棒の小径部を挿入して配線パターンとの導通を得る接合部を形成すると同時に、その接合のために貫通孔に注入するはんだペーストで裏面電極部を形成しているのであるが、樹脂封止の際に上述のようにスタッド棒によって配線基板を裏面電極が突出するように変形させるため、配線基板の貫通孔周辺に外側に向かって大きな張力が作用する。そして、この樹脂封止時に発生する配線基板の貫通孔周辺での張力により、樹脂封止後に、スタッド棒直下の裏面電極部がスタッド棒や配線パターンと断線を生じ易くなる。またこの樹脂封止時に発生する配線基板の貫通孔周辺での張力が半導体素子のバンプとの接合領域にまで伝播して、接合部のクラックや応力集中を生じ、電気特性に影響を及ぼす。   Furthermore, when attaching the stud rod, a small-diameter portion of the stud rod is inserted into the through hole of the wiring board to form a joint for obtaining electrical connection with the wiring pattern, and at the same time, the solder injected into the through hole for the joint The back electrode part is formed with paste, but the resin substrate is deformed so that the back electrode protrudes by the stud rod as described above during resin sealing. A large tension acts toward it. Then, due to the tension around the through hole of the wiring board generated at the time of resin sealing, the back electrode portion directly below the stud bar is likely to be disconnected from the stud bar and the wiring pattern after resin sealing. In addition, the tension around the through hole of the wiring board generated at the time of resin sealing propagates to the bonding region with the bump of the semiconductor element, causing cracks and stress concentration at the bonding portion, affecting the electrical characteristics.

特許文献２の技術では、上述のようにウェハー主面のバンプの一部を封止樹脂面から露出させるようにしているのであるが、封止樹脂面から露出したバンプの一部をランドとして、その上に別の半導体装置の先端球面の裏面突起電極を接合する場合、この裏面突起電極の球面がバンプ先端（球面）に垂直方向に押し付けられるため、水平方向にずれ、水平方向の搭載位置のバラツキが発生し、接合部の信頼性が低下してしまう。   In the technique of Patent Document 2, as described above, a part of the bump on the wafer main surface is exposed from the sealing resin surface, but a part of the bump exposed from the sealing resin surface is used as a land. When the back surface protruding electrode of the tip spherical surface of another semiconductor device is bonded to the top, the spherical surface of the back surface protruding electrode is pressed in the vertical direction against the bump tip (spherical surface). Variations occur and the reliability of the joint is reduced.

特許文献３の技術では、上述のように配線基板上に形成した突起電極を樹脂封止金型で押し潰して先端面を露出させているので、樹脂封止面と突起電極の先端面とが同一面になる。そのため、ＰｏＰ型半導体装置を構成するべくこの半導体装置の突起電極面に他の半導体装置の裏面電極をはんだ接合した場合には、この接合部の突起電極面と裏面電極との界面で断面形状に急激な変化を生じ、この接合部が応力集中点となり、外力や温度の繰り返し変化により断線しやすくなる。さらにこの突起電極は、配線基板上にスタッドバンプを重ねることで形成しているもので、かかる積層構造の突起電極を樹脂封止金型で押圧しても、弓状に曲がって先端に所定の圧力がかからず、平面が得られない。   In the technique of Patent Document 3, since the protruding electrode formed on the wiring board as described above is crushed with a resin-sealing mold to expose the tip surface, the resin sealing surface and the tip surface of the protruding electrode are It becomes the same side. Therefore, when the back electrode of another semiconductor device is solder-bonded to the protruding electrode surface of this semiconductor device so as to form a PoP type semiconductor device, the cross-sectional shape is formed at the interface between the protruding electrode surface and the back electrode of this bonded portion. An abrupt change occurs, and this joint becomes a stress concentration point, and breaks easily due to repeated changes in external force and temperature. Further, this protruding electrode is formed by stacking stud bumps on the wiring board. Even when the protruding electrode having such a laminated structure is pressed with a resin-sealed mold, it is bent in a bow shape and has a predetermined tip at the tip. No pressure is applied and a flat surface cannot be obtained.

本発明は上記問題を解決するもので、高信頼性の３次元実装が実現できる突起電極を備えた半導体装置およびその製造方法を提供することを目的とする。   SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, and to provide a semiconductor device including a protruding electrode that can realize highly reliable three-dimensional mounting and a method for manufacturing the same.

上記課題を解決するために、本発明の半導体装置は、一方の面の素子実装領域に複数の接続端子を有し、その外周側の領域に前記複数の接続端子に各々接続した複数のランドおよびその上に形成された突起電極を有し、他方の面に複数の裏面ランドを有する配線基板と、前記配線基板の素子実装領域に搭載され電気的に接続された半導体素子と、前記半導体素子を包埋するように前記配線基板の一方の面に形成された封止樹脂部とを備え、前記突起電極は、前記封止樹脂部の上面から端部が突出し、その突出部の先端が平担面であり、かつ、前記突出部よりも断面が大きい部分が前記封止樹脂部内に位置することを特徴とする。   In order to solve the above problems, a semiconductor device of the present invention has a plurality of connection terminals in an element mounting region on one surface, and a plurality of lands connected to the plurality of connection terminals in a region on the outer peripheral side thereof, and A wiring board having a protruding electrode formed thereon and having a plurality of backside lands on the other surface; a semiconductor element mounted on and electrically connected to an element mounting region of the wiring board; and the semiconductor element A sealing resin portion formed on one surface of the wiring board so as to be embedded, and the protruding electrode has an end protruding from the upper surface of the sealing resin portion, and the tip of the protruding portion is flat. A portion that is a surface and has a larger cross section than the protruding portion is located in the sealing resin portion.

上記構成によれば、突起電極の端部が封止樹脂部の上面から突出しており、且つその突出部の先端が平坦面であるため、ＰｏＰ型半導体装置を構成する際に、この半導体装置の突起電極の平坦面に対して、上段に積層する他の半導体装置の裏面電極を安定して接合可能である。また突起電極はその突出部よりも断面が大きい部分が封止樹脂部内にあるため、半導体装置の実装後に突起電極に縦方向の応力が発生しても、突起電極の側面と封止樹脂とは剥離し難く、配線基板への取り付け部も剥離し難く、突起電極の傾きや抜けは発生し難い。これらのことにより、高信頼性化を実現できる。   According to the above configuration, since the end portion of the protruding electrode protrudes from the upper surface of the sealing resin portion, and the tip of the protruding portion is a flat surface, when configuring the PoP type semiconductor device, The back surface electrode of another semiconductor device stacked in the upper stage can be stably bonded to the flat surface of the protruding electrode. In addition, since the protruding electrode has a portion whose cross section is larger than the protruding portion in the sealing resin portion, the side surface of the protruding electrode and the sealing resin are not affected even if longitudinal stress is generated in the protruding electrode after mounting the semiconductor device. It is difficult to peel off, and it is difficult to peel off the attachment portion to the wiring board, and the protruding electrode is unlikely to be tilted or pulled out. As a result, high reliability can be realized.

突起電極は、基板面に沿う方向の断面が円形であるのが好ましい。このような形状であると、応力の集中箇所がなく、応力が分散されるため、突起電極の側面と封止樹脂との剥離、配線基板への取り付け部の剥離、突起電極の傾きや抜けを防止する効果を高めることができる。   The protruding electrode preferably has a circular cross section in the direction along the substrate surface. With such a shape, there is no stress concentration point and the stress is dispersed. Therefore, peeling of the side surface of the protruding electrode from the sealing resin, peeling of the mounting portion to the wiring board, inclination and disconnection of the protruding electrode are prevented. The effect to prevent can be heightened.

突起電極ははんだで構成されていることが好ましい。はんだという柔らかい材料であると平坦面が容易に形成されるからである。
半導体素子は、ワイヤーボンドしてもよいし、主面に複数のバンプを備えるものを用いてフリップチップ接続してもよい。フリップチップ接続する場合は、配線基板には、半導体素子が搭載される領域に接続端子を設ければよいので、言い換えると半導体素子搭載領域の外周側に接続端子を設ける必要がないので、さらに言い換えると半導体素子搭載領域が実質上の素子実装領域となるので、配線基板の小型化を図ることができる。このことにより、半導体装置は、投影平面が小さいものとなり、実装基板などに対して２次元に高密度に実装可能となる。 The protruding electrode is preferably made of solder. This is because a flat surface is easily formed with a soft material such as solder.
The semiconductor element may be wire-bonded or may be flip-chip connected using a main surface provided with a plurality of bumps. In the case of flip-chip connection, it is only necessary to provide connection terminals in the region where the semiconductor element is mounted on the wiring board. In other words, it is not necessary to provide connection terminals on the outer peripheral side of the semiconductor element mounting region. Since the semiconductor element mounting area becomes a substantial element mounting area, the wiring board can be miniaturized. Thus, the semiconductor device has a small projection plane, and can be mounted two-dimensionally and densely on a mounting substrate or the like.

また主面中央部に接続用電極を備えた半導体素子の上に他の半導体素子をフリップチップ接続するなどして、配線基板上に複数の半導体素子を３次元に積層実装してもよい。このことにより、２次元実装の半導体装置と比較して高密度実装に適した半導体装置が実現できる。   Alternatively, a plurality of semiconductor elements may be three-dimensionally stacked on the wiring substrate by flip-chip connecting other semiconductor elements on the semiconductor element having the connection electrode in the central portion of the main surface. Thus, a semiconductor device suitable for high-density mounting can be realized as compared with a two-dimensional mounting semiconductor device.

本発明の半導体装置の製造方法は、一方の面の素子実装領域に複数の接続端子を有し、その外周側の領域に前記複数の接続端子に各々接続した複数のランドを有し、他方の面に複数の裏面ランドを有する配線基板を準備する工程と、前記配線基板の素子実装領域に半導体素子を搭載し電気的に接続する工程と、前記配線基板の一方の面のランド上に端部が次第に狭まった突起電極を接続する工程と、前記半導体素子および突起電極が接続された配線基板を、封止樹脂に対して剥離性を有するリリースシートを成形面に密着させた封止金型に設置し、前記突起電極の端部をリリースシートに押圧する圧縮成形法で前記配線基板の一方の面を前記半導体素子を包埋するように樹脂封止する工程と、前記封止金型より樹脂封止された成形体を取り出す工程とを含むことを特徴とする。   The method for manufacturing a semiconductor device of the present invention has a plurality of connection terminals in an element mounting region on one surface, a plurality of lands connected to the plurality of connection terminals in a region on the outer periphery side, and the other A step of preparing a wiring board having a plurality of backside lands on the surface; a step of mounting and electrically connecting a semiconductor element to an element mounting region of the wiring board; and an end portion on a land on one side of the wiring board The step of connecting the projecting electrode gradually narrowed and the wiring substrate to which the semiconductor element and the projecting electrode are connected to a sealing mold in which a release sheet having a peelability to the sealing resin is adhered to the molding surface Installing and sealing the one side of the wiring board by a compression molding method in which an end of the protruding electrode is pressed against a release sheet so as to embed the semiconductor element; and resin from the sealing mold Take out the sealed molded body Characterized in that it comprises a step.

上記構成によれば、突起電極の端部をリリースシートに押圧する圧縮成形法を採るため、当該突起電極の端部が封止樹脂面から突出し、かつ、その突出部の先端が押し潰されて平坦面になる。また端部が次第に狭まった形状の突起電極を用いるため、リリースシートとの間に樹脂が入り込むことはなく、樹脂封止工程後に樹脂バリ取りや洗浄を行う必要はない。   According to the above configuration, in order to adopt a compression molding method in which the end of the protruding electrode is pressed against the release sheet, the end of the protruding electrode protrudes from the sealing resin surface, and the tip of the protruding portion is crushed. It becomes a flat surface. In addition, since the protruding electrode having a gradually narrowed end portion is used, the resin does not enter between the release sheet and the resin deburring or cleaning is not required after the resin sealing step.

リリースシートは、可撓性かつ弾性の層と高硬度性の層との積層構造を有することが好ましい。突起電極の端部は可撓性かつ弾性の層を押し潰し、その押し潰した可撓性かつ弾性の層を介して高硬度性の層に押し当てられるため、より一層平坦な面が得られるからである。   The release sheet preferably has a laminated structure of a flexible and elastic layer and a high hardness layer. The ends of the protruding electrodes crush the flexible and elastic layer, and are pressed against the high-hardness layer through the crushed flexible and elastic layer, so that a flatter surface can be obtained. Because.

本発明による半導体装置は、突起電極の端部が樹脂封止面から突出し、かつその突出部の先端が平坦面となるため、３次元実装のための下段半導体装置として用いて、上段半導体装置の水平方向の搭載位置のバラツキを抑制することができる。つまり、電極の先端形状が球面である上段半導体装置を搭載する場合であっても、その裏面突起電極が本発明の半導体装置の突起電極の平坦面上に搭載による押圧で垂直方向に押し付けられるときに、水平方向にずれることはなく、上段半導体装置の水平方向の搭載位置のバラツキを抑制することができる。このため、接合部の信頼性を向上させることができる。   The semiconductor device according to the present invention is used as a lower semiconductor device for three-dimensional mounting because the end of the protruding electrode protrudes from the resin sealing surface and the tip of the protruding portion is a flat surface. Variations in the horizontal mounting position can be suppressed. That is, even when an upper semiconductor device having a spherical tip shape is mounted, the rear surface protruding electrode is pressed vertically on the flat surface of the protruding electrode of the semiconductor device of the present invention by mounting pressure. In addition, there is no deviation in the horizontal direction, and variations in the horizontal mounting position of the upper semiconductor device can be suppressed. For this reason, the reliability of a junction part can be improved.

また突起電極の先端の平坦面に樹脂残りが発生することがないため、樹脂封止工程後に樹脂バリ取りや洗浄を行う必要はなく、製造期間の短縮化、製造工程の削減、それによるコスト削減も実現できる。   In addition, since no resin residue is generated on the flat surface at the tip of the bump electrode, there is no need to perform resin deburring or cleaning after the resin sealing process, shortening the manufacturing period, reducing the manufacturing process, and thereby reducing costs. Can also be realized.

以下、本発明の実施の形態について図面を参照しながら説明する。各図においては、図示を簡単にするために各部材の厚みや長さや電極数等は実際とは異なるものとしている。
図１（ａ）は本発明の実施の形態１の半導体装置を一部切り欠いて示す斜視図、図１（ｂ）は同半導体装置の図１（ａ）におけるＡ−Ａ線に沿った断面図である。 Hereinafter, embodiments of the present invention will be described with reference to the drawings. In each of the drawings, the thickness, length, number of electrodes, and the like of each member are different from actual ones in order to simplify the illustration.
FIG. 1A is a perspective view of the semiconductor device according to the first embodiment of the present invention, partly cut away, and FIG. 1B is a cross-sectional view of the semiconductor device along the line AA in FIG. FIG.

図１（ａ）（ｂ）において、半導体装置５０は、配線基板５と、配線基板５の素子実装領域に搭載され金属細線４により電気的に接続された半導体素子１と、半導体素子１および金属細線４を包埋するように配線基板５の一方の面に形成された封止樹脂部１０とを備えている。   1A and 1B, a semiconductor device 50 includes a wiring board 5, a semiconductor element 1 mounted in an element mounting region of the wiring board 5 and electrically connected by a thin metal wire 4, a semiconductor element 1 and a metal. And a sealing resin portion 10 formed on one surface of the wiring substrate 5 so as to embed the fine wire 4.

配線基板５は、一方の面（以下、表面という）の素子実装領域にダイパターン３および複数の接続端子６を有し、その外周側の領域に複数の接続端子６に各々接続した複数の積層ランド８を有し、他方の面（以下、裏面という）に、積層ランド８に各々接続した複数の裏面ランド１１を有している。   The wiring substrate 5 has a die pattern 3 and a plurality of connection terminals 6 in an element mounting region on one surface (hereinafter referred to as a surface), and a plurality of laminated layers respectively connected to the plurality of connection terminals 6 in an outer peripheral region. It has a land 8, and has a plurality of back surface lands 11 connected to the laminated land 8 on the other surface (hereinafter referred to as a back surface).

積層ランド８上には、他の半導体装置と電気的に接続するための突起電極９が設けられており、裏面ランド１１上には、実装基板に電気的に接続するための裏面突起電極１２が設けられている。突起電極９は、封止樹脂部１０の上面から端部が突出し、その突出部の先端が平担面１３であり、かつ、突出部よりも断面が大きい部分が封止樹脂部１０内にある。なお積層ランド８とは、ＰｏＰ型半導体装置を構成するときに、この半導体装置５０の上に積層する他の半導体装置の裏面電極と突起電極９を介して電気的に接続することを目的として配線基板５上に形成したランドを指す。   A protruding electrode 9 for electrically connecting to another semiconductor device is provided on the laminated land 8, and a back surface protruding electrode 12 for electrically connecting to the mounting substrate is provided on the back surface land 11. Is provided. The protruding electrode 9 has an end protruding from the upper surface of the sealing resin portion 10, the tip of the protruding portion is the flat surface 13, and a portion having a larger cross section than the protruding portion is in the sealing resin portion 10. . Note that the laminated land 8 is a wiring for the purpose of electrically connecting to the back electrode of another semiconductor device laminated on the semiconductor device 50 via the protruding electrode 9 when constituting the PoP type semiconductor device. A land formed on the substrate 5 is indicated.

詳述する。半導体素子１は、主面上の中央部に内部回路が形成され、内部回路と接続した複数の電極端子２が周辺部に配置されている。半導体素子１はシリコンを基材とするが、例えばゲルマニウムやグラファイトのような単元素材料であってもよく、砒化ガリウムや、テルル化亜鉛のような化合物材料であってもよい。半導体素子１の厚みは、例えば５０μｍ〜２００μｍの範囲、好ましくは１００μｍ程度である。   Detailed description. In the semiconductor element 1, an internal circuit is formed in the central part on the main surface, and a plurality of electrode terminals 2 connected to the internal circuit are arranged in the peripheral part. The semiconductor element 1 is based on silicon, but may be a single element material such as germanium or graphite, or may be a compound material such as gallium arsenide or zinc telluride. The thickness of the semiconductor element 1 is, for example, in the range of 50 μm to 200 μm, preferably about 100 μm.

かかる半導体素子１が、配線基板５のダイパターン３上に接着剤７で固着され、接続端子６に対して金属細線４で電気的に接続されている。接着剤７は、エポキシ系樹脂、ポリイミド系樹脂、アクリル系樹脂から選択された少なくとも１つを含んでいてよく、はんだまたは金−シリコン共晶のいずれかであってもよい。また接着剤７は導電性または絶縁性のいずれであってもよく、光開始剤が配合された紫外線硬化性であってもよい。例えば銀フィラーを添加したエポキシ系の導電性接着剤を使用できる。ペーストであっても半硬化状のシートであってもよい。金属細線４は金線とするが、例えば銅線、アルミニウム線、銀線であってよい。金属細線４のループの頂点の高さは、配線基板５の表面から例えば４０μｍ〜２５０μｍの範囲、好ましくは１３０μｍ程度である。   The semiconductor element 1 is fixed on the die pattern 3 of the wiring board 5 with an adhesive 7 and is electrically connected to the connection terminal 6 with a fine metal wire 4. The adhesive 7 may include at least one selected from an epoxy resin, a polyimide resin, and an acrylic resin, and may be either solder or gold-silicon eutectic. The adhesive 7 may be either conductive or insulating, and may be UV curable with a photoinitiator. For example, an epoxy-based conductive adhesive added with a silver filler can be used. It may be a paste or a semi-cured sheet. The metal thin wire 4 is a gold wire, but may be, for example, a copper wire, an aluminum wire, or a silver wire. The height of the apex of the loop of the fine metal wire 4 is, for example, in the range of 40 μm to 250 μm from the surface of the wiring board 5, preferably about 130 μm.

配線基板５は、基板およびその両面に導電性膜で形成された配線パターンと、両面の配線パターン間を直接もしくは中間配線層を介して電気的に接続するビア１４などの導電体（導電性膜や導電性充填物により形成される）とを有している。配線基板５の表面の中央部に上述のダイパターン３が形成され、ダイパターン３よりも外周の領域に、複数の接続端子６とそれらに各々接続した複数の積層ランド８とがダイパターン３の中心に対して放射方向となるように配置されている。配線基板５の裏面に、積層ランド８とビア１４などを介して接続する裏面ランド１１が配置されている。   The wiring board 5 includes a wiring pattern formed of a conductive film on both sides of the board and a conductor (conductive film) such as a via 14 that electrically connects the wiring patterns on both sides directly or via an intermediate wiring layer. And formed of a conductive filler. The above-described die pattern 3 is formed at the center of the surface of the wiring substrate 5, and a plurality of connection terminals 6 and a plurality of laminated lands 8 connected to each of them are formed in the outer periphery of the die pattern 3. It arrange | positions so that it may become a radial direction with respect to the center. On the back surface of the wiring board 5, a back surface land 11 connected to the laminated land 8 via the via 14 or the like is disposed.

基板としては、ガラス繊維やケプラー等の有機物からなる繊維にエポキシ樹脂、フェノール樹脂、ポリイミド樹脂等を含浸して硬化させたものや、ＢＴレジン、液晶ポリマを用いたもの等、種々の樹脂基板を用いることができる。樹脂基板は単層基板であってもよいし、多層基板であってもよい。他に、酸化アルミニウム、窒化アルミニウム、ガラスまたは石英のいずれか１つで構成された単層もしくは積層のセラミック基板を用いてもよい。配線基板５の厚みは、例えば１００μｍから６００μｍの範囲、好ましくは２１０μｍ程度である。   As the substrate, various resin substrates such as those obtained by impregnating and curing epoxy resin, phenol resin, polyimide resin, etc. with fibers made of organic materials such as glass fiber and Kepler, and those using BT resin, liquid crystal polymer, etc. Can be used. The resin substrate may be a single layer substrate or a multilayer substrate. In addition, a single-layer or multi-layer ceramic substrate made of any one of aluminum oxide, aluminum nitride, glass, and quartz may be used. The thickness of the wiring board 5 is, for example, in the range of 100 μm to 600 μm, preferably about 210 μm.

導電性膜は銅箔とするが、銅箔上に金属層を形成してもよい。金属層は、例えばニッケル、はんだ、金、銀およびパラジウム等から選択された少なくとも１つを含んでいてよい。基板が酸化アルミニウムや窒化アルミニウムのような焼結材料よりなるときは、タングステン、マンガン、モリブデン、タンタルのうちのいずれかの高融点金属で形成された導電性膜上を、金、銀、銅、パラジウムのうちのいずれかの導電性材料で覆った構成とする。基板がガラスや石英のような透明材料よりなるときは、例えば塩化錫のような透明な導電性材料で導電性膜を構成してもよい。   The conductive film is a copper foil, but a metal layer may be formed on the copper foil. The metal layer may include at least one selected from, for example, nickel, solder, gold, silver, palladium, and the like. When the substrate is made of a sintered material such as aluminum oxide or aluminum nitride, gold, silver, copper, a conductive film formed of a refractory metal of any one of tungsten, manganese, molybdenum, and tantalum is used. The structure is covered with any conductive material of palladium. When the substrate is made of a transparent material such as glass or quartz, the conductive film may be made of a transparent conductive material such as tin chloride.

封止樹脂部１０は、半導体素子１、金属細線４、突起電極９（先端部を除く）を包埋するように配線基板５の表面全体に形成されている。この封止樹脂部１０の材料は、熱硬化性のエポキシ系樹脂とするが、例えばビフェニル系樹脂、フェノール系樹脂またはシリコーン系樹脂、シアネートエステルのうちのいずれか、例えばビスフェノールＡ型、ビスフェノールＦ型、ビフェニル型、ナフタレン型から選択された少なくとも１つを含んでいてよい。封止樹脂部１０の厚み、つまり基板面から樹脂上面までの寸法は、例えば１２０μｍから４００μｍの範囲、好ましくは２００μｍ程度である。   The sealing resin portion 10 is formed on the entire surface of the wiring substrate 5 so as to embed the semiconductor element 1, the fine metal wire 4, and the protruding electrode 9 (except for the tip portion). The material of the sealing resin portion 10 is a thermosetting epoxy resin. For example, any of biphenyl resin, phenol resin or silicone resin, and cyanate ester, for example, bisphenol A type, bisphenol F type , At least one selected from a biphenyl type and a naphthalene type. The thickness of the sealing resin portion 10, that is, the dimension from the substrate surface to the resin upper surface is, for example, in the range of 120 μm to 400 μm, preferably about 200 μm.

突起電極９は、基板面に沿う方向の断面が円形であって、封止樹脂部１０上面からの突出部よりも断面が大きい部分（以下、大径部という）が封止樹脂部１０内にある。ここでは突起電極９は軸方向の中央部の径が最も大きい樽型である。突出部の高さは、例えば５μｍから６０μｍの範囲、好ましくは２０μｍ程度とし、大径部の径は１００μｍから３００μｍ程度とする。平坦面１３の径は４０μmから２５０μｍ程度とする。   The protruding electrode 9 has a circular cross section in the direction along the substrate surface, and a portion having a larger cross section than the protruding portion from the upper surface of the sealing resin portion 10 (hereinafter referred to as a large diameter portion) is in the sealing resin portion 10. is there. Here, the protruding electrode 9 has a barrel shape in which the diameter of the central portion in the axial direction is the largest. The height of the protrusion is, for example, in the range of 5 μm to 60 μm, preferably about 20 μm, and the diameter of the large diameter portion is about 100 μm to 300 μm. The diameter of the flat surface 13 is about 40 μm to 250 μm.

この突起電極９は、例えば亜鉛系合金、錫系合金、ビスマス系合金、または銀系合金で構成することができる。具体的には、Ｓｎ−Ａｇ−Ｃｕ系、Ｓｎ−Ｐｂ系、Ｓｎ−Ａｇ−Ｂｉ−Ｉｎ系、およびＳｎ−Ｚｎ−Ｂｉ系の内のいずれかのはんだ材料を用いることができる。   The protruding electrode 9 can be made of, for example, a zinc alloy, a tin alloy, a bismuth alloy, or a silver alloy. Specifically, any one of Sn—Ag—Cu, Sn—Pb, Sn—Ag—Bi—In, and Sn—Zn—Bi solder materials can be used.

裏面突起電極１２も、Ｓｎ−Ａｇ−Ｃｕ系、Ｓｎ−Ｐｂ系、Ｓｎ−Ａｇ−Ｂｉ−Ｉｎ系、およびＳｎ−Ｚｎ−Ｂｉ系などのはんだ材料を用いることができる。銅またはニッケルからなる芯部の上層部または表面全体にはんだ層が形成されたものであってもよい。   The back surface protruding electrode 12 can also be made of a solder material such as Sn—Ag—Cu, Sn—Pb, Sn—Ag—Bi—In, and Sn—Zn—Bi. A solder layer may be formed on the upper layer portion or the entire surface of the core portion made of copper or nickel.

上記半導体装置の製造方法を図２および図３を参照して説明する。
図２（ａ）に示すように、上述の配線基板５を準備する。表面の中央部にダイパターン３が形成され、ダイパターン３よりも外周の領域に複数の接続端子６および積層ランド８が形成され、各積層ランド８とビア１４などの導電体を介して接続する複数の裏面ランド１１が裏面に形成されている配線基板５である。 A method for manufacturing the semiconductor device will be described with reference to FIGS.
As shown in FIG. 2A, the above-described wiring board 5 is prepared. A die pattern 3 is formed at the center of the surface, and a plurality of connection terminals 6 and laminated lands 8 are formed in a region on the outer periphery of the die pattern 3 and connected to each laminated land 8 via a conductor such as a via 14. A wiring substrate 5 having a plurality of backside lands 11 formed on the backside.

配線基板５の作製法を簡単に説明すると、両面に導電性膜を形成した基板において、一方の面の導電性膜をフォトリソグラフィ法により所定の形状に加工して配線パターン、接続端子６、積層ランド８を形成し、他方の面の導電性膜も同じくフォトリソグラフィ法により所定の形状に加工して配線パターン、裏面ランド１１を形成し、両面の配線パターン間をビア１４などで電気的に接続する。その後に、接続端子６、積層ランド８、裏面ランド１１の接続部を除く基板両面にソルダーレジスト等の絶縁膜を形成する。基板両面の導電性膜の間に１層以上からなる中間配線層を設けてもよい。   The manufacturing method of the wiring substrate 5 will be briefly described. In a substrate having a conductive film formed on both surfaces, the conductive film on one surface is processed into a predetermined shape by a photolithography method to form a wiring pattern, connection terminals 6, and a laminated layer. The land 8 is formed, and the conductive film on the other side is also processed into a predetermined shape by photolithography to form a wiring pattern and a back surface land 11, and the wiring patterns on both sides are electrically connected by vias 14 or the like. To do. Thereafter, an insulating film such as a solder resist is formed on both surfaces of the substrate excluding the connection portions of the connection terminals 6, the stacked lands 8, and the back surface lands 11. An intermediate wiring layer composed of one or more layers may be provided between the conductive films on both sides of the substrate.

次に、図２（ｂ）に示すように、配線基板５の複数の積層ランド８上にボール状の突起電極９を接合する。ここでは断面が楕円形の突起電極９を用いている。突起電極９が上述のはんだ材料であれば、複数の積層ランド８上に印刷法ではんだペーストを供給する一方で、複数の積層ランド８の各々に対応する複数箇所に吸着孔を有する吸着装置（図示せず）で突起電極９を吸着して、各突起電極９が積層ランド８に一致する位置まで搬送し、上述のはんだペースト上に載置した後に、不活性ガス雰囲気中でリフローすることにより、積層ランド８上に突起電極９を接合する。このときの突起電極９は、基板表面から電極先端部までの高さが例えば１３５μｍから４６０μｍの範囲、好ましくは２７０μm程度とする。   Next, as shown in FIG. 2B, ball-shaped protruding electrodes 9 are bonded onto the plurality of laminated lands 8 of the wiring substrate 5. Here, the protruding electrode 9 having an elliptical cross section is used. If the protruding electrode 9 is the above-described solder material, a solder paste is supplied onto the plurality of laminated lands 8 by a printing method, while an adsorption device having adsorption holes at a plurality of locations corresponding to each of the plurality of laminated lands 8 ( (Not shown) by adsorbing the protruding electrodes 9, transporting each protruding electrode 9 to a position corresponding to the laminated land 8, placing on the solder paste, and then reflowing in an inert gas atmosphere. Then, the protruding electrode 9 is joined on the laminated land 8. In this case, the protruding electrode 9 has a height from the substrate surface to the electrode tip, for example, in the range of 135 μm to 460 μm, preferably about 270 μm.

図２（ｃ）に示すように、半導体素子１を配線基板５のダイパターン３上に接着する。そのためにまず、ダイパターン３上に接着剤７を供給する。接着剤７がペースト状であれば、例えばスクリーン印刷で適正な厚みに印刷塗布してもよいし、マルチノズルディスペンサーで適量を多点塗布してもよい。接着剤７が半硬化状のシートであれば適当サイズのものを載置する。そして接着剤７上の所定の位置に半導体素子１を載置し、不活性ガス中もしくは減圧中で加熱して接着剤７を硬化させる。その後に、半導体素子１の電極端子２と配線基板５上の対応する接続端子６との間を、直径が例えば１０μｍから４０μｍの範囲、好ましくは１８μｍ程度の金属細線４を用いて、ワイヤーボンディング法によって接続する。   As shown in FIG. 2C, the semiconductor element 1 is bonded on the die pattern 3 of the wiring board 5. For this purpose, first, an adhesive 7 is supplied onto the die pattern 3. If the adhesive 7 is a paste, it may be applied by printing to an appropriate thickness by screen printing, for example, or an appropriate amount may be applied by a multi-nozzle dispenser. If the adhesive 7 is a semi-cured sheet, an appropriate size is placed. Then, the semiconductor element 1 is placed at a predetermined position on the adhesive 7 and heated in an inert gas or reduced pressure to cure the adhesive 7. Thereafter, a wire bonding method is used between the electrode terminal 2 of the semiconductor element 1 and the corresponding connection terminal 6 on the wiring substrate 5 by using a thin metal wire 4 having a diameter in the range of 10 μm to 40 μm, preferably about 18 μm. Connect by.

図２（ｄ）に示すように、樹脂封止用圧縮成形機の上金型２９・下金型３０に半導体素子１および突起電極９が接合された配線基板５をセットし、封止樹脂材料１０ａを供給する。つまり、上金型２９・下金型３０を所定の樹脂溶融温度に設定し、下金型３０にその成形面および上金型２９への対向面の全面を覆うリリースシート３３を吸引によって密着させ、配線基板５を上金型２９に吸引によって保持するとともに、樹脂封止に要する量の顆粒状の封止樹脂材料１０ａをキャビティ領域のリリースシート３３上に供給する。封止樹脂材料１０ａは、顆粒状のほか、液状、ミニタブレット状、あるいはシート状であっても構わない。   As shown in FIG. 2 (d), the wiring substrate 5 in which the semiconductor element 1 and the protruding electrode 9 are bonded is set in the upper mold 29 and the lower mold 30 of the resin-sealing compression molding machine, and the sealing resin material 10a is supplied. That is, the upper mold 29 and the lower mold 30 are set to a predetermined resin melting temperature, and the release sheet 33 that covers the entire molding surface and the entire surface facing the upper mold 29 is brought into close contact with the lower mold 30 by suction. The wiring substrate 5 is held in the upper mold 29 by suction, and an amount of granular sealing resin material 10a required for resin sealing is supplied onto the release sheet 33 in the cavity region. The sealing resin material 10a may be in the form of granules, liquid, mini-tablets, or sheets.

ここで、リリースシート３３は、封止樹脂材料１０ａ（およびその成形品）に対して剥離性を有するものである。例えばポリテトラフルオロエチレン樹脂（ＰＴＦＥ）、エチレン−テトラフルオロエチレン共重合樹脂（ＥＴＦＥ）、テトラフルオロエチレン−ペルフルオロプロピレン共重合樹脂（ＦＥＰ）、ポリビニリデンフルオライド樹脂（ＰＢＤＦ）、ポリエチレンテレフタレート樹脂（ＰＥＴ）、ポリプロピレン樹脂（ＰＰ）、またはシリコーンゴム（ＳＲ）からなる単層型であってもよいし、積層型としてもよい。図２（ｅ）に示すような、可撓性かつ弾性の第１の層３４と高硬度性の第２の層３５との積層構造を有することが好ましい。第１の層３４は上記の各樹脂あるいはゴムのいずれかであってよく、第２の層３５は、例えばニッケル、鉄ニッケル合金、または銅などの金属膜を用いることができる。積層型のリリースシート３３を用いる場合は、第２の層３５が下金型３０に接するように配置する。このようにするとリリースシート３３の強度が大きくなり、圧縮成形工程で生じる破損等を回避することができる。リリースシート３３の厚みは３０μｍから１００μｍの範囲、好ましくは５０μｍ程度である。   Here, the release sheet 33 has releasability from the sealing resin material 10a (and its molded product). For example, polytetrafluoroethylene resin (PTFE), ethylene-tetrafluoroethylene copolymer resin (ETFE), tetrafluoroethylene-perfluoropropylene copolymer resin (FEP), polyvinylidene fluoride resin (PBDF), polyethylene terephthalate resin (PET) , A single layer type made of polypropylene resin (PP) or silicone rubber (SR), or a laminated type. It is preferable to have a laminated structure of a flexible and elastic first layer 34 and a high hardness second layer 35 as shown in FIG. The first layer 34 may be any of the above resins or rubbers, and the second layer 35 may be a metal film such as nickel, iron-nickel alloy, or copper. When the laminated release sheet 33 is used, the second layer 35 is disposed in contact with the lower mold 30. If it does in this way, the intensity | strength of the release sheet 33 will become large and the breakage etc. which arise in a compression molding process can be avoided. The thickness of the release sheet 33 is in the range of 30 μm to 100 μm, preferably about 50 μm.

次に、図３（ａ）（ｂ）に示すように、上金型２９・下金型３０による圧縮成形を行って、半導体素子１、金属細線４、突起電極９を樹脂封止する。そのために、上金型２９・下金型３０間を図示しない排気手段によって減圧にしながら、溶融した封止樹脂材料１０ａを保持した下金型３０を所定の位置まで上昇させる。この下金型３０の位置は、リリースシート３３が上金型２９に向けて押圧され、かつ、上金型２９との間に所定の樹脂成形厚みに対応するキャビティが形成される位置とする。このときに突起電極９の先端部が平坦面１３にされながらリリースシート３３の内部に侵入していくので、この侵入深さが所定量になるように、リリースシート３３の材質や厚みを予め適正に選択しておく。この侵入深さは、例えば５μｍから６０μｍの範囲、好ましくは２０μｍ程度とする。封止樹脂材料１０ａが硬化するまでこの状態を保持し、硬化後に成形品を取り出す。   Next, as shown in FIGS. 3A and 3B, compression molding is performed by the upper mold 29 and the lower mold 30 to seal the semiconductor element 1, the fine metal wires 4, and the protruding electrodes 9 with resin. For this purpose, the lower mold 30 holding the molten sealing resin material 10a is raised to a predetermined position while the pressure between the upper mold 29 and the lower mold 30 is reduced by an exhaust means (not shown). The position of the lower mold 30 is a position where the release sheet 33 is pressed toward the upper mold 29 and a cavity corresponding to a predetermined resin molding thickness is formed between the release mold 33 and the upper mold 29. At this time, the tip portion of the protruding electrode 9 enters the inside of the release sheet 33 with the flat surface 13 being made, so that the material and thickness of the release sheet 33 are appropriately set in advance so that the penetration depth becomes a predetermined amount. Select it. The penetration depth is, for example, in the range of 5 μm to 60 μm, preferably about 20 μm. This state is maintained until the sealing resin material 10a is cured, and the molded product is taken out after the curing.

その後に、図３（ｃ）に示すように、配線基板５の裏面ランド１１上に裏面突起電極１２を接合する。裏面突起電極１２は、例えばはんだボール等を搭載するボールセット法を用いて接合しても構わないし、裏面ランド１１上にはんだペーストを供給しリフローすることで突起状とする印刷法を用いても構わない。   Thereafter, as shown in FIG. 3C, the back surface protruding electrode 12 is bonded onto the back surface land 11 of the wiring substrate 5. The back surface protruding electrode 12 may be joined using, for example, a ball setting method in which a solder ball or the like is mounted, or may be printed using a printing method in which a solder paste is supplied onto the back surface land 11 and reflowed to form a protruding shape. I do not care.

以上の製造方法によれば、半導体素子１、金属細線４、突起電極９を包埋するように配線基板５の表面全体を覆う封止樹脂部１０が形成され、その圧縮成形の工程で、リリースシート３３に向けて押圧されて侵入する突起電極９の端部が封止樹脂部１０上面から突出し、その突出部の先端が平担面１３となる。リリースシート３３が上述の可撓性かつ弾性の第１の層３４と高硬度性の第２の層３５との積層構造を有する場合は、突起電極９の端部は第１の層３４を押し潰し、その押し潰した第１の層３４を介して第２の層３５に押し当てられるため、より一層平坦な平担面１３が得られる。   According to the above manufacturing method, the sealing resin portion 10 that covers the entire surface of the wiring substrate 5 is formed so as to embed the semiconductor element 1, the fine metal wires 4, and the protruding electrodes 9, and is released in the compression molding process. The end of the protruding electrode 9 that is pressed toward the sheet 33 protrudes from the upper surface of the sealing resin portion 10, and the tip of the protruding portion becomes the flat surface 13. When the release sheet 33 has a laminated structure of the above-described flexible and elastic first layer 34 and the high-hardness second layer 35, the end of the protruding electrode 9 pushes the first layer 34. Since it is crushed and pressed against the second layer 35 through the crushed first layer 34, a flatter flat surface 13 is obtained.

しかも突起電極９は樹脂封止前はボール状であるため、つまり端部が次第に狭まった形状であるため、リリースシート３３との間に封止樹脂材料１０ａが入り込むことはなく、樹脂封止工程後に樹脂バリ取りや洗浄を行う必要はない。また突出部よりも断面が大きい大径部が封止樹脂部１０内に位置することとなるため、樹脂や積層ランド８との剥離は起こり難く、突起電極９の接合部での断線、封止樹脂部１０上面からの突出部（特に平担面１３）の位置ずれ、突起電極９の欠落は防止される。   In addition, since the protruding electrode 9 is ball-shaped before resin sealing, that is, the end portion is gradually narrowed, the sealing resin material 10a does not enter between the release sheet 33 and the resin sealing step. There is no need to deburr or wash the resin later. In addition, since the large-diameter portion having a larger cross section than the protruding portion is located in the sealing resin portion 10, separation from the resin or the laminated land 8 hardly occurs, and disconnection or sealing at the joint portion of the protruding electrode 9 occurs. Misalignment of the protruding portion (especially the flat surface 13) from the upper surface of the resin portion 10 and loss of the protruding electrode 9 are prevented.

またその成形の過程においては、十分に溶融した低粘度の封止樹脂材料１０ａの中に金属細線４が低速で浸漬されるため、金属細線４の変形も防止される。
得られる半導体装置５０は、三次元実装のＰｏＰ型半導体装置を構成する際に、下段半導体装置として用いて、突起電極９の平坦面１３に上段半導体装置の裏面電極をはんだで接合するときに、両者の２次元的位置関係におけるバラツキを抑制することができる。つまり、電極の先端形状が球面である上段半導体装置を搭載する場合であっても、その裏面突起電極が半導体装置５０の突起電極９の平坦面１３上に搭載による押圧で垂直方向に押し付けられるときに、水平方向にずれることはなく、上段半導体装置の水平方向の搭載位置のバラツキを抑制することができる。よって、上段半導体装置を安定に接合することができ、接合部の信頼性が高くなる。ＰｏＰ型半導体装置の作製も容易かつ安価となる。 Further, in the molding process, the fine metal wires 4 are immersed at a low speed in the sufficiently melted low-viscosity sealing resin material 10a, so that deformation of the fine metal wires 4 is also prevented.
The obtained semiconductor device 50 is used as a lower semiconductor device when a three-dimensionally mounted PoP type semiconductor device is configured, and when the back electrode of the upper semiconductor device is joined to the flat surface 13 of the protruding electrode 9 with solder. Variations in the two-dimensional positional relationship between the two can be suppressed. That is, even when an upper semiconductor device having a spherical tip shape is mounted, the rear surface protruding electrode is pressed vertically on the flat surface 13 of the protruding electrode 9 of the semiconductor device 50 by mounting pressure. In addition, there is no deviation in the horizontal direction, and variations in the horizontal mounting position of the upper semiconductor device can be suppressed. Therefore, the upper semiconductor device can be stably bonded, and the reliability of the bonded portion is increased. The production of the PoP type semiconductor device is easy and inexpensive.

この実施の形態では、圧縮成形の際に、リリースシート３３を下金型３０の表面に配置するとして説明したが、上金型２９の表面にも配置してもよい。このように配置すると、上金型２９に配線基板５が接することがないので、裏面ランド１１の損傷等を防止することができる。   In this embodiment, it has been described that the release sheet 33 is disposed on the surface of the lower mold 30 during compression molding. However, the release sheet 33 may also be disposed on the surface of the upper mold 29. With such an arrangement, the wiring substrate 5 does not contact the upper mold 29, so that damage to the back surface land 11 can be prevented.

突起電極９の材料がはんだであれば容易に平担面１３とされる。また、リリースシート３３として、薄い弾性の層と高硬度性の層とが積層された積層構造のものを用いれば、突起電極９の端部は弾性の層を突き破って高硬度性の層に当接するため、より一層平坦な面が得られる。   If the material of the protruding electrode 9 is solder, the flat surface 13 can be easily formed. If the release sheet 33 has a laminated structure in which a thin elastic layer and a high-hardness layer are laminated, the end of the protruding electrode 9 breaks through the elastic layer and hits the high-hardness layer. Because of contact, a flatter surface can be obtained.

なお実際には、上述の半導体装置５０を１個ずつ製造するのでなく、他面取りの配線基板を用いて複数個一括して製造し、裏面ランド１１上に裏面突起電極１２を形成した後に、あるいは裏面突起電極１２の形成前に、ダイサーやレーザーによって個片化する手法がとられる。   In practice, the semiconductor devices 50 are not manufactured one by one, but a plurality of other chamfered wiring boards are manufactured in a lump and the back surface protruding electrode 12 is formed on the back surface land 11, or Before the back surface protruding electrode 12 is formed, a method of dividing into pieces by a dicer or a laser is used.

図４は本発明の実施の形態２にかかる半導体装置の構成を示す断面図である。この実施の形態２の半導体装置５２では、半導体素子６１は配線基板５５に対してフリップチップ法で実装されている。半導体素子６１は主面の所定位置に内部回路と接続された複数のバンプ４２が形成されている。配線基板５５は、実施の形態１で説明したダイパターンや接続端子を持たず、表面中央部に半導体素子６１のバンプ４２と対応した配置で半導体素子用ランド４３が形成されており、各半導体素子用ランド４３に積層ランド８や裏面ランド１１が接続されている。このほかは実施の形態１の半導体装置と同様である。   FIG. 4 is a cross-sectional view showing the configuration of the semiconductor device according to the second embodiment of the present invention. In the semiconductor device 52 of the second embodiment, the semiconductor element 61 is mounted on the wiring board 55 by the flip chip method. The semiconductor element 61 has a plurality of bumps 42 connected to the internal circuit at predetermined positions on the main surface. The wiring board 55 does not have the die pattern and the connection terminal described in the first embodiment, and the semiconductor element land 43 is formed at the center of the surface so as to correspond to the bumps 42 of the semiconductor element 61. The laminated land 8 and the back surface land 11 are connected to the land 43 for use. The rest is the same as the semiconductor device of the first embodiment.

この半導体装置でも、実施の形態１の半導体装置と同様の突起電極９を有することから、３次元実装のＰｏＰ型半導体装置を構成する際の接合が安定して得られ、高信頼性化が実現できる。一方、この半導体装置は、実施の形態１の半導体装置に較べて、配線基板５５の素子搭載領域内に半導体素子用ランド４３を配置すればよいので、言い換えるとワイヤーボンディングのように素子搭載領域外に接続端子を配置する必要がないため、同じ面積のチップ実装領域において、ワイヤーボンドの場合より大きいサイズのチップが搭載可能となる。   Since this semiconductor device also has the protruding electrodes 9 similar to those of the semiconductor device of the first embodiment, the junction can be stably obtained when constructing the three-dimensional mounting PoP type semiconductor device, and high reliability is realized. it can. On the other hand, in this semiconductor device, as compared with the semiconductor device of the first embodiment, the semiconductor element land 43 may be arranged in the element mounting region of the wiring board 55. In other words, the semiconductor device land is out of the element mounting region like wire bonding. Therefore, it is possible to mount a chip having a size larger than that in the case of wire bonding in a chip mounting region having the same area.

半導体素子６１のバンプ４２は、例えば亜鉛系合金、錫系合金、ビスマス系合金または銀系合金で形成されたものであってもよいし、電解／無電解めっきで形成された銅またはニッケルからなる芯部の上層部または表面全体にはんだ層が形成されたものであってもよい。   The bumps 42 of the semiconductor element 61 may be formed of, for example, a zinc-based alloy, a tin-based alloy, a bismuth-based alloy, or a silver-based alloy, or made of copper or nickel formed by electrolytic / electroless plating. A solder layer may be formed on the upper layer part or the entire surface of the core part.

図５は、本発明の実施の形態３にかかる半導体装置の構成を示す断面図である。この実施の形態３の半導体装置５３では、半導体素子６２と半導体素子６３とが積層されている。ダイパターン３上に接着された半導体素子６３は主面中央部に複数の接続用電極６５が形形成されており、この半導体素子６３の上に、半導体素子６３よりも投影面積が小さい半導体素子６２がバンプ６４によりフリップチップ法で接続されている。バンプ６４は、実施の形態２と同様の材料で形成される。このほかは実施の形態１の半導体装置と同様である。   FIG. 5 is a cross-sectional view showing the configuration of the semiconductor device according to the third embodiment of the present invention. In the semiconductor device 53 of the third embodiment, the semiconductor element 62 and the semiconductor element 63 are stacked. The semiconductor element 63 bonded onto the die pattern 3 has a plurality of connection electrodes 65 formed at the center of the main surface. A semiconductor element 62 having a projected area smaller than that of the semiconductor element 63 is formed on the semiconductor element 63. Are connected to each other by the bump 64 by a flip chip method. Bump 64 is formed of the same material as in the second embodiment. The rest is the same as the semiconductor device of the first embodiment.

この半導体装置でも、実施の形態１の半導体装置と同様の突起電極９を有することから、３次元実装のＰｏＰ型半導体装置を構成する際の接合が安定して得られ、高信頼性化が実現できる。一方、この半導体装置は、実施の形態１の半導体装置に較べて、複数の半導体素子６２，６３が積層されることで３次元に高密度化されているもので、より高密度なＰｏＰ型半導体装置が可能となる。   Since this semiconductor device also has the protruding electrodes 9 similar to those of the semiconductor device of the first embodiment, the junction can be stably obtained when constructing the three-dimensional mounting PoP type semiconductor device, and high reliability is realized. it can. On the other hand, this semiconductor device is three-dimensionally densified by stacking a plurality of semiconductor elements 62 and 63 as compared with the semiconductor device of the first embodiment. The device becomes possible.

図６は、ＰｏＰ型半導体装置の断面図である。実施の形態１の半導体装置５０の上に、ＢＧＡ型（Ball Grid Array 型）半導体装置８０が３次元実装されている。
ＢＧＡ型半導体装置８０は、半導体素子８１が配線基板８３の表面に搭載され、接続用電極８２と接続端子８６とが金属細線８４で電気的に接続され、封止樹脂８５（圧縮成形法あるいはトランスファー成形法）で封止され、配線基板８３の裏面の裏面ランド８７上に裏面突起電極８８が接合されている。裏面ランド８７および裏面突起電極８８は、半導体装置５０の突起電極９に対応する配置とされていて、各裏面突起電極８８が突起電極９の先端の平坦面１３上にはんだで接合されている。 FIG. 6 is a cross-sectional view of a PoP type semiconductor device. A BGA type (Ball Grid Array type) semiconductor device 80 is three-dimensionally mounted on the semiconductor device 50 of the first embodiment.
In the BGA type semiconductor device 80, the semiconductor element 81 is mounted on the surface of the wiring board 83, the connection electrode 82 and the connection terminal 86 are electrically connected by the thin metal wire 84, and the sealing resin 85 (compression molding method or transfer) is used. The back surface protruding electrode 88 is bonded onto the back surface land 87 on the back surface of the wiring substrate 83. The back surface land 87 and the back surface protruding electrode 88 are arranged corresponding to the protruding electrode 9 of the semiconductor device 50, and each back surface protruding electrode 88 is joined to the flat surface 13 at the tip of the protruding electrode 9 with solder.

このＰｏＰ型半導体装置は、半導体装置５０の突起電極９による接合安定性、高信頼性が得られるほか、ＰｏＰによって３次元に高密度化されていることにより、高性能、薄型小型ともなる。よって、このＰｏＰ型半導体装置を用いることにより、携帯端末や家庭電化製品の超小型化が実現できる。   This PoP type semiconductor device can obtain bonding stability and high reliability due to the protruding electrodes 9 of the semiconductor device 50, and also has high performance and a small size because it is three-dimensionally densified by PoP. Therefore, by using this PoP type semiconductor device, it is possible to realize miniaturization of portable terminals and home appliances.

図７は、他のＰｏＰ型半導体装置の断面図である。実施の形態１の半導体装置５０の上に、ＬＧＡ型（Land Grid Array 型）半導体装置９０が３次元実装されている。
ＬＧＡ型半導体装置９０は、図６に示したＢＧＡ型半導体装置８０に較べて、裏面ランド８７上に裏面突起電極が設けられていない点のみ異なっており、裏面ランド８７が直接に突起電極９の先端の平坦面１３上にはんだで接合されている。 FIG. 7 is a cross-sectional view of another PoP type semiconductor device. On the semiconductor device 50 of the first embodiment, an LGA type (Land Grid Array type) semiconductor device 90 is three-dimensionally mounted.
The LGA type semiconductor device 90 is different from the BGA type semiconductor device 80 shown in FIG. 6 only in that the back surface protruding electrode is not provided on the back surface land 87. It joins on the flat surface 13 of the front-end | tip with solder.

このＰｏＰ型半導体装置も、半導体装置５０の突起電極９による接合安定性、高信頼性が得られるほか、ＰｏＰによって３次元に高密度化されており、かつ図６のＰｏＰ型半導体装置に較べて裏面突起電極が存在しない分だけより一層薄型化されていることにより、高性能、より薄型小型ともなる。よって、このＰｏＰ型半導体装置を用いることにより、携帯端末や家庭電化製品の超小型化が実現できる。   This PoP type semiconductor device also obtains the junction stability and high reliability by the protruding electrode 9 of the semiconductor device 50, and is three-dimensionally densified by PoP, and compared with the PoP type semiconductor device of FIG. Since the thickness is further reduced by the absence of the back-surface protruding electrode, high performance and thinner and smaller size can be achieved. Therefore, by using this PoP type semiconductor device, it is possible to realize miniaturization of portable terminals and home appliances.

なお、半導体装置５０、ＢＧＡ型半導体装置８０、ＬＧＡ型半導体装置９０のそれぞれに搭載されている半導体素子１、半導体素子８１は、図示したようにフェースアップで配線基板５，８３に搭載され金属細線４，８４で接続されるのでなく、フリップチップ接続されても構わない。   The semiconductor element 1 and the semiconductor element 81 mounted on the semiconductor device 50, the BGA type semiconductor device 80, and the LGA type semiconductor device 90, respectively, are mounted on the wiring boards 5 and 83 face up as shown in the figure. Instead of being connected at 4,84, flip-chip connection may be used.

本発明にかかる半導体装置は、他の半導体装置を上に積層してはんだで接合する場合の接合信頼性が高いもので、ＰｏＰ型半導体装置を容易に、高信頼性、かつ安価に構成することができ、種々の電子機器、特に携帯用電子機器に有用である。   The semiconductor device according to the present invention has high bonding reliability when another semiconductor device is stacked on top and joined with solder, and the PoP type semiconductor device can be configured easily, with high reliability, and at low cost. It is useful for various electronic devices, particularly portable electronic devices.

本発明の実施の形態１の半導体装置の構成図Configuration diagram of the semiconductor device according to the first embodiment of the present invention. 図１の半導体装置を製造する前半工程を説明する断面図Sectional drawing explaining the first half process of manufacturing the semiconductor device of FIG. 図１の半導体装置を製造する後半工程を説明する断面図Sectional drawing explaining the latter half process of manufacturing the semiconductor device of FIG. 本発明の実施の形態２の半導体装置の断面図Sectional drawing of the semiconductor device of Embodiment 2 of this invention 本発明の実施の形態３の半導体装置の断面図Sectional drawing of the semiconductor device of Embodiment 3 of this invention 図１の半導体装置を用いたＰｏＰ型半導体装置の断面図Sectional drawing of the PoP type semiconductor device using the semiconductor device of FIG. 図１の半導体装置を用いた他のＰｏＰ型半導体装置の断面図Sectional drawing of the other PoP type semiconductor device using the semiconductor device of FIG.

符号の説明Explanation of symbols

１ 半導体素子
２ 電極端子
３ ダイパターン
４ 金属細線
５ 配線基板
６ 接続端子
７ 接着剤
８ 積層ランド
９ 突起電極
10 封止樹脂部
11 裏面ランド
12 裏面突起電極
13 平坦面
29 上金型
30 下金型
33 リリースシート
34 第１の層
35 第２の層
50 半導体装置
51，52，53 半導体装置
61，62，63，81 半導体素子
80 ＢＧＡ型半導体装置
90 ＬＧＡ型半導体装置 DESCRIPTION OF SYMBOLS 1 Semiconductor element 2 Electrode terminal 3 Die pattern 4 Metal fine wire 5 Wiring board 6 Connection terminal 7 Adhesive 8 Laminated land 9 Projection electrode
10 Sealing resin part
11 Backside land
12 Back bump electrode
13 Flat surface
29 Upper mold
30 Lower mold
33 Release sheet
34 First layer
35 Second layer
50 Semiconductor devices
51, 52, 53 Semiconductor devices
61, 62, 63, 81 Semiconductor element
80 BGA type semiconductor device
90 LGA type semiconductor device

Claims (5)

一方の面の素子実装領域に複数の接続端子を有し、その外周側の領域に前記複数の接続端子に各々接続した複数のランドおよびその上に形成された突起電極を有し、他方の面に複数の裏面ランドを有する配線基板と、前記配線基板の素子実装領域に搭載され電気的に接続された半導体素子と、前記半導体素子を包埋するように前記配線基板の一方の面に形成された封止樹脂部とを備え、前記突起電極は、前記封止樹脂部の上面から端部が突出し、その突出部の先端が平担面であり、かつ、前記突出部よりも断面が大きい部分が前記封止樹脂部内に位置することを特徴とする半導体装置。   It has a plurality of connection terminals in the element mounting region on one surface, a plurality of lands connected to the plurality of connection terminals in the region on the outer peripheral side, and a protruding electrode formed thereon, and the other surface A wiring board having a plurality of backside lands, a semiconductor element mounted and electrically connected to an element mounting region of the wiring board, and formed on one surface of the wiring board so as to embed the semiconductor element. The protruding electrode has an end protruding from an upper surface of the sealing resin portion, a tip of the protruding portion is a flat surface, and a section having a larger cross section than the protruding portion. Is located in the sealing resin portion. 突起電極は、基板面に沿う方向の断面が円形であることを特徴とする請求項１記載の半導体装置。   The semiconductor device according to claim 1, wherein the protruding electrode has a circular cross section in the direction along the substrate surface. 突起電極ははんだで構成されていることを特徴とする請求項１記載の半導体装置。   2. The semiconductor device according to claim 1, wherein the protruding electrode is made of solder. 一方の面の素子実装領域に複数の接続端子を有し、その外周側の領域に前記複数の接続端子に各々接続した複数のランドを有し、他方の面に複数の裏面ランドを有する配線基板を準備する工程と、前記配線基板の素子実装領域に半導体素子を搭載し電気的に接続する工程と、前記配線基板の一方の面のランド上に端部が次第に狭まった突起電極を接続する工程と、前記半導体素子および突起電極が接続された配線基板を、リリースシートを成形面に密着させた封止金型に設置し、前記突起電極の端部をリリースシートに押圧する圧縮成形法で前記配線基板の一方の面を前記半導体素子を包埋するように樹脂封止する工程と、前記封止金型より樹脂封止された成形体を取り出す工程とを含むことを特徴とする半導体装置の製造方法。   A wiring board having a plurality of connection terminals in an element mounting region on one side, a plurality of lands connected to the plurality of connection terminals in a region on the outer peripheral side, and a plurality of backside lands on the other side A step of mounting a semiconductor element in an element mounting region of the wiring substrate and electrically connecting the semiconductor element, and a step of connecting a protruding electrode whose end portion is gradually narrowed on a land on one surface of the wiring substrate And the wiring board to which the semiconductor element and the protruding electrode are connected is placed in a sealing mold in which a release sheet is closely attached to a molding surface, and the end of the protruding electrode is pressed against the release sheet by the compression molding method. A semiconductor device comprising: a step of resin-sealing one surface of a wiring board so as to embed the semiconductor element; and a step of taking out a molded body resin-sealed from the sealing mold. Production method. リリースシートは、可撓性かつ弾性の層と高硬度性の層との積層構造を有することを特徴とする請求項４記載の半導体装置の製造方法。   5. The method of manufacturing a semiconductor device according to claim 4, wherein the release sheet has a laminated structure of a flexible and elastic layer and a high hardness layer.
JP2007326622A 2007-12-11 2007-12-19 Semiconductor device and manufacturing method thereof Pending JP2009152253A (en)

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JP2011086766A (en) * 2009-10-15 2011-04-28 Renesas Electronics Corp Method for manufacturing semiconductor device and semiconductor device
WO2011102096A1 (en) * 2010-02-19 2011-08-25 パナソニック株式会社 High frequency module manufacturing method
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US8928132B2 (en) 2011-02-17 2015-01-06 Samsung Electronics Co., Ltd. Semiconductor package having through silicon via (TSV) interposer and method of manufacturing the semiconductor package
US8710642B2 (en) 2011-03-25 2014-04-29 Fujitsu Semiconductor Limited Semiconductor device, method of manufacturing semiconductor device, and electronic apparatus
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