JP2009124099A - Semiconductor chip electrode structure - Google Patents

Abstract

[Problem] To prevent a solder bump of an adjacent electrode pad from being electrically short-circuited, and to suppress the progress of a crack caused by a bump stress concentrated at a lower portion of an edge position of a barrier metal, thereby reliability of bump connection in the electrode pad Provided is an electrode structure of a semiconductor chip that improves the performance.
In an electrode pad 100, a dummy metal 111 is arranged in an uppermost layer portion of silicon 101 so that an edge portion does not coincide with a lower edge portion 109 of a barrier metal 107 between a pad wiring metal 102 and a wiring metal 103. To do. By forming many interfaces between the dummy metal 111 and the interlayer film 140, the progress of cracks generated by bump stress concentrated on the lower edge portion 109 of the barrier metal 107 between the pad wiring metal 102 and the wiring metal 103. Suppress.
[Selection] Figure 1

Description

  The present invention relates to an electrode structure of a semiconductor chip, and more particularly to an electrode structure of a semiconductor chip constituting a flip chip connection that suppresses the progress of cracks.

  An electrode pad structure in flip chip connection of a conventional semiconductor device will be described with reference to the drawings. FIG. 11A is a diagram showing a general flip-chip connection configuration. In FIG. 11A, the semiconductor chip 1101 and the interposer substrate 1102 are connected via solder bumps. 11B is a cross-sectional view of the flip-chip connection configuration shown in FIG. 11A as viewed from the A-A ′ plane. In FIG. 11B, the semiconductor chip 1101 and the interposer substrate 1102 are connected via solder bumps 1103, and the periphery of the connection portion of the solder bumps 1103 is covered with an underfill resin 1104. As described above, the circuit formed inside the semiconductor chip 1101 is connected to the back surface of the interposer substrate 1102 via the solder bump 1103, so that the mounting area is small and the electrical characteristics are short because the wiring is short. good. Further, the connection reliability of the connection portion of the solder bump 1103 is improved by hardening the periphery of the connection portion of the solder bump 1103 with the underfill resin 1104.

  Examples of the flip chip connection pad formed inside the semiconductor chip 1101 include an area pad and a peripheral pad. FIG. 12A is a diagram showing a layout pattern of area pads in which electrode pads 1201 are arranged on the entire surface of the semiconductor chip 1101. FIG. 12B is a diagram showing a layout pattern of peripheral pads in which electrode pads 1202 are arranged on the periphery of the semiconductor chip 1101. The flip chip connection pads are often formed with a uniform pattern of electrode pads on the surface of the semiconductor chip 1101.

  FIG. 13 is a cross-sectional view of a conventional electrode pad structure formed on the semiconductor chip 1101 shown in FIGS. 11A to 12B. In FIG. 13, the electrode pad 1300 in the prior art has a pad wiring metal 1302 disposed on the uppermost layer portion of silicon 1301, and a wiring metal 1303 disposed on the same layer as the pad wiring metal 1302. A pad connection metal 1304 is disposed on the pad wiring metal 1302. The upper surfaces of the silicon 1301 and the pad connection metal 1304 are covered with a nitride protective film 1305 mainly made of a nitride film so as to protect the pad connection metal 1304 and further a resin material protective film 1306 made of a resin material such as polyimide. It has been broken. However, a part of the upper surface of the pad connection metal 1304 has an opening 1308 that is not covered with either the nitride protective film 1305 or the resin material protective film 1306. The pad connection metal 1304 is electrically connected to the solder bump 1103 formed on the top of the barrier metal 1307 when the opening 1308 is in contact with the barrier metal 1307.

  In the electrode pad 1300 according to the prior art, a portion of the upper surface of the pad connection metal 1304 that is not covered by either the nitride protective film 1305 or the resin material protective film 1306, that is, an opening where the pad connection metal 1304 is in contact with the barrier metal 1307. The position of the portion 1308 is determined by the range in which the resin material protective film 1306 is formed. Further, since the resin material protective film 1306 is also present at the lower edge position 1309 of the barrier metal 1307, the bump stress concentrated on the lower edge position 1309 of the barrier metal 1307 can be relieved. The bump stress applied to the lower edge position 1309 of the barrier metal 1307 refers to the stress applied to the barrier metal when the solder bump is formed, the stress applied to the solder bump when the semiconductor chip is mounted on the interposer substrate, and the like.

  However, in the configuration of the electrode pad 1300 in the prior art shown in FIG. 13, when the plating method, which is the mainstream technique for forming solder bumps, is used, there is a tendency that the solder bumps of the electrode pads adjacent to each other are electrically short-circuited. There was a problem. FIG. 14 is a diagram showing a state in which the solder bumps 1103 of the electrode pads 1300 shown in FIG. 13 adjacent to each other are electrically short-circuited. In FIG. 14, the conductive component α adheres to the resin material protective film 1306, and the solder bumps 1103 adjacent to each other are electrically short-circuited through the barrier metal 1307. This is because the conductive component α often adheres to the resin material protective film 1306 during the plating process when the solder bump 1103 is formed using the plating method.

  In order to solve such a problem of the electrode pad 1300 in the prior art, there are electrode pads in other prior art as described below. FIG. 15 is a cross-sectional view of an electrode pad 1500 according to another prior art for solving the problem of the electrode pad 1300 according to the prior art. In FIG. 15, an electrode pad 1500 according to another prior art has a structure in which the resin material protective film 1506 is laminated on the upper surface of the nitride protective film 1305 and does not contact the barrier metal 1507. Therefore, the portion of the upper surface of the pad connection metal 1304 that is not covered with the nitride protection film 1305, that is, the position of the opening 1508 where the pad connection metal 1304 contacts the barrier metal 1507 depends on the range where the nitride protection film 1305 is formed. It is decided.

As described above, according to the configuration of the electrode pad 1500 according to another prior art, when the plating method which is the mainstream technology for forming the solder bump is used, there is a problem that the solder bump of the electrode pad adjacent to each other is electrically short-circuited. It becomes difficult. 16 is a diagram showing a case where the conductive component α is attached to the resin material protective film 1506 of the electrode pad 1500 shown in FIG. 15 adjacent to each other. In FIG. 16, even if the conductive component α is attached to the resin material protective film 1506, the resin material protective film 1506 and the barrier metal 1507 are not in contact with each other, so that the solder bumps 1103 of the electrode pads 1500 adjacent to each other are electrically connected. Do not short-circuit.
Japanese Patent Laid-Open No. 1-114055 JP 2006-19550 A

  However, the electrode pad 1500 in another prior art shown in FIG. 15 has the following problems. FIG. 17 is a diagram showing an uppermost layer portion of silicon 1301 in which pad wiring metal 1302 and wiring metal 1303 of electrode pad 1500 according to another prior art shown in FIG. 15 are arranged. The edge of the barrier metal 1507 is located above the area 1700 between the pad wiring metal 1302 and the wiring metal 1303 (indicated by a broken line 1507a in FIG. 17). The electrode pad 1500 according to another prior art shown in FIG. 15 does not have the resin material protective film 1506 at the edge position lower portion 1509 of the barrier metal 1507, and therefore the barrier metal as in the electrode pad 1300 shown in FIG. The bump stress concentrated on the lower edge 1509 of the edge position 1507 cannot be relaxed.

  Therefore, there is a problem that a crack is generated in the nitrided protective film 1305 due to the bump stress concentrated on the lower edge position 1509 of the barrier metal 1507. 18 is an enlarged view of the B1 portion of the electrode pad 1500 shown in FIG. In FIG. 18, a crack 1800 is generated in the nitride protective film 1305 due to bump stress concentrated on the edge position lower portion 1509 of the barrier metal 1507.

  Therefore, an object of the present invention is to suppress the progress of cracks caused by bump stress concentrated at the lower edge position of the barrier metal while preventing the solder bump of the adjacent electrode pad from being electrically short-circuited. It is an object to provide an electrode structure of a semiconductor chip that improves the reliability of bump connection in a pad.

In order to achieve the above object, an electrode structure of a first semiconductor chip of the present invention is formed on a semiconductor substrate having a pad metal and a wiring metal having a different potential from the pad metal in the uppermost layer, and the semiconductor substrate. An electrode pad, a resin protective film covering the semiconductor substrate and having an opening so as to expose the electrode pad, a barrier metal formed on the electrode pad in the opening of the resin protective film, A semiconductor chip electrode structure consisting of bumps formed on the barrier metal, which has a dummy pattern having no potential between the pad metal and the wiring metal, and the dummy pattern has the edge position of the barrier metal vertically It is characterized by being formed in a region including a portion extending in the direction.
The upper surface of a region where a preferable dummy pattern is formed has a region not covered with a resin protective film.

Further, in order to achieve the above object, the electrode structure of the second semiconductor chip of the present invention is formed on a semiconductor substrate having a pad metal and a wiring metal for forming an electrode pad on the uppermost layer, and on the electrode pad. An electrode structure of a semiconductor chip consisting of a barrier metal and a bump formed on the barrier metal, and a metal pattern is provided between the electrode pad and the wiring metal, and the metal pattern has a vertical edge position of the barrier metal. It is characterized by being formed in a region including a portion extending in the direction.
Preferably, the semiconductor substrate further includes a resin protective film covering a region where the barrier metal is not formed, and an upper surface of the region where the metal pattern is formed has a region not covered with the resin protective film.

Furthermore, a preferable metal pattern is composed of one metal, and the edge of the metal does not coincide with the edge of the barrier metal in the vertical direction, or the metal pattern is composed of a plurality of metals, Among the metals, the specific metal is arranged in the vertical direction of the edge position of the barrier metal, and the edge of the specific metal does not coincide with the edge of the barrier metal in the vertical direction.
Furthermore, a preferable metal pattern is formed by a plurality of metals arranged at equal intervals and an interlayer film formed between adjacent metals.

Another preferred metal pattern is characterized in that it is formed on a continuous surface by a plurality of metals.
Furthermore, a preferable continuous surface is formed of a plurality of regular hexagonal metals.

  Another preferable metal pattern is formed of metal arranged in a radial direction from the center of the semiconductor chip.

Another preferable metal pattern includes a pattern for suppressing the occurrence of cracks.
Another preferable metal pattern includes a pattern for preventing a generated crack from proceeding.
Furthermore, another preferable pattern for preventing cracks from proceeding is formed of a plurality of discontinuous metals.

  A preferable metal pattern is a dummy pattern having no potential or the same potential as the electrode pad.

  In order to achieve the above object, the semiconductor chip of the present invention is a semiconductor chip having a plurality of electrodes on the upper surface, and the above-described electrode structure is provided only around the four corners of the semiconductor chip farthest from the center of the semiconductor chip. It is characterized by having.

  As described above, according to the electrode structure of the semiconductor chip of the present invention, it is generated by the bump stress concentrated at the lower part of the edge position of the barrier metal while preventing the solder bump of the adjacent electrode pad from being electrically short-circuited. It is possible to realize an electrode structure of a semiconductor chip that suppresses the progress of cracks and improves the reliability of bump connection in the electrode pad. In addition, according to the electrode structure of the semiconductor chip of the present invention, it is difficult to induce the generation of cracks due to bump stress concentrated at the lower edge position of the barrier metal, and there is an effect of suppressing the generation of cracks.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
FIG. 1 is a diagram showing an electrode pad 100 of a semiconductor device according to the first embodiment of the present invention. In FIG. 1, the electrode pad 100 includes a pad wiring metal 102 disposed on the uppermost layer portion of silicon 101, and a pad wiring metal 102 and a wiring metal 103 disposed thereon. A pad connection metal 104 is disposed on the pad wiring metal 102. The upper surfaces of the silicon 101 and the pad connection metal 104 are covered with a nitride protective film 105 mainly composed of a nitride film so as to protect the pad connection metal 104. However, a part of the upper surface of the pad connection metal 104 has an opening 108 that is not covered with the nitride protective film 105. The pad connection metal 104 is electrically connected to the solder bump 110 formed on the upper portion of the barrier metal 107 when the opening 108 is in contact with the barrier metal 107. The resin material protective film 106 is laminated on the upper surface of the nitride protective film 105 so as not to contact the barrier metal 107. The portion of the upper surface of the pad connection metal 104 that is not covered with the nitride protection film 105, that is, the position of the opening 108 where the pad connection metal 104 contacts the barrier metal 107 is determined by the area where the nitride protection film 105 is formed. . The structure of the electrode pad 100 described so far is not different from the structure of the electrode pad 1500 in the prior art shown in FIG.

  In this embodiment, the nitride protective film 105 is used as the silicon surface protective layer. However, this protective film is not limited to nitride, and for example, an oxide film or the like may be used. The barrier metal 107 is made of a material having a relatively large Young's modulus, such as titanium, tungsten, or nickel.

  Next, differences between the electrode pad 100 according to the first embodiment of the present invention and the electrode pad 1500 in the prior art will be described. The electrode pad 100 is different from the electrode pad 1500 in the prior art in that a dummy metal 111 is provided. Further, the dummy metal 111 is characterized in that it is disposed between the pad wiring metal 102 and the wiring metal 103 in the uppermost layer portion of the silicon 101. FIG. 2 is an enlarged view of a portion B2 in the electrode pad 100 shown in FIG. The dummy metal 111 is composed of a first dummy metal 111a and a second dummy metal 111b.

  The arrangement of the first dummy metal 111a and the second dummy metal 111b will be described in more detail. The first dummy metal 111 a is arranged so that the edge of the first dummy metal 111 a does not coincide with the edge of the barrier metal 107. This is because, in the case where the edge of the first dummy metal 111 a coincides with the edge of the barrier metal 107, the generation of cracks due to bump stress concentrated on the lower edge position 109 of the barrier metal 107 is induced. As described above, by arranging the first dummy metal 111a in the region including the portion where the edge position of the barrier metal 107 extends in the vertical direction, the bump metal is generated in the vertical direction from the edge position of the barrier metal 107 where the bump stress is most concentrated. The progress of the crack 120 to be suppressed can be suppressed.

  As described above, the second dummy metal 111b is arranged at a constant interval from the first dummy metal 111a in a region other than the first dummy metal 111a. By arranging the first dummy metal 111a as described above, an oblique crack from the edge position of the barrier metal 107 toward the edge position of the first dummy metal 111a is formed at the lower edge position 109 of the barrier metal 107. It is thought that it occurs. FIG. 3 is an enlarged view of a portion B2 of the electrode pad 100 where the oblique crack 130 is generated in the nitride protective film 105. FIG. The second dummy metal 111b is not disposed in a portion extending in the vertical direction from the edge position of the barrier metal 107, but in order to suppress the progress of the oblique crack 130 generated in the nitride protective film 105, the dummy metal 111a is arranged at a constant interval. In this manner, by arranging the dummy metal 111b, it is possible to suppress the progress of cracks generated over a wide range of the nitride protective film 105.

  Next, the dummy pattern composed of the dummy metal 111 will be described in detail. FIG. 4 is a diagram showing the uppermost layer portion of the silicon 101 on which the pad wiring metal 102 and the wiring metal 103 of the electrode pad 100 according to the first embodiment are arranged. In FIG. 4, a dot pattern is formed by arranging a plurality of dummy metals 111 at equal intervals between the pad wiring metal 102 and the wiring metal 103. Between each dummy metal 111, an interlayer film 140 made of tetraethoxysilane or the like exists. Note that the edge of the barrier metal 107 is located above the area where the dot pattern is formed (indicated by a broken line 107a in FIG. 4).

  Thus, by forming a large number of interfaces with the plurality of dummy metals 111 and the interlayer film 140, cracks generated by bump stress concentrated on the lower edge position 109 of the barrier metal 107 come into contact with the interfaces, Progress can be suppressed.

  As described above, according to the electrode structure of the semiconductor chip according to the first embodiment of the present invention, the crack generated by the bump stress concentrated at the lower part of the edge position of the barrier metal is vertically downward from the edge position of the barrier metal. In addition to suppressing the progress of cracks that occur, the progress of cracks that occur over a wide range can be suppressed, and the reliability of bump connection in the electrode pad can be improved.

  In the present embodiment, a dot pattern in which two dummy metals 111 are arranged between the pad wiring metal 102 and the wiring metal 103 as shown in FIG. 4 is shown as a dummy pattern. However, the present invention is not limited to this. is not. For example, three or more dummy metals smaller than the dummy metal 111 may be disposed between the pad wiring metal 102 and the wiring metal 103 to form a dot pattern finer than the dot pattern shown in FIG.

(Second Embodiment)
The electrode structure of the semiconductor chip according to the second embodiment of the present invention is different from the electrode structure of the semiconductor chip according to the first embodiment described above in the dummy pattern made of a dummy metal. FIG. 5 is a diagram showing an electrode pad 500 of a semiconductor device according to the second embodiment of the present invention. In FIG. 5, the same components as those shown in FIG. The electrode pad 500 forms a dummy metal 150 between the pad wiring metal 102 and the wiring metal 103 in the uppermost layer portion of the silicon 101.

  The electrode pad dummy pattern according to the second embodiment will be described in detail below. FIG. 6 is a diagram showing a dummy pattern of the electrode pad according to the second embodiment. In FIG. 6, a line pattern is formed between a pad wiring metal 102 and a wiring metal 103 by arranging a dummy metal 150 as a continuous surface over a wide range.

  In this way, by forming a continuous surface with the dummy metal 150 over a wide range, cracks caused by bump stress concentrated on the lower edge portion 109 of the edge of the barrier metal 107 between the pad wiring metal 102 and the wiring metal 103 are generated. Can be suppressed. In general, the bump stress is difficult to concentrate if there is no metal interface. Therefore, the configuration of the line pattern according to the second embodiment is further improved compared to the configuration of the dot pattern according to the first embodiment described above, and cracks due to bump stress concentrated on the lower edge portion 109 of the barrier metal 107 are further reduced. It is difficult to induce the occurrence and the effect of suppressing the occurrence of cracks can be expected.

  As described above, according to the electrode structure of the semiconductor chip according to the second embodiment of the present invention, the progress of cracks generated over a wide range due to the bump stress concentrated at the lower edge position of the barrier metal is suppressed, and the electrode pad The reliability of bump connection can be improved. Furthermore, it is difficult to induce the occurrence of cracks due to the bump stress concentrated at the lower part of the edge position of the barrier metal, and the generation of cracks can be suppressed.

(Third embodiment)
The electrode structure of the semiconductor chip according to the third embodiment of the present invention is different from the electrode structure of the semiconductor chip according to the second embodiment described above in the dummy pattern made of a dummy metal. The dummy pattern of the electrode pad according to the third embodiment will be described below. FIG. 7 is a diagram showing a dummy pattern of the electrode pad according to the third embodiment. Although the dummy pattern shown in FIG. 6 in the second embodiment has a continuous surface formed by the dummy metal 150, the dummy pattern shown in FIG. 7 has a plurality of dummy metals 170 having a regular hexagon as one unit. Are continuously arranged to form a honeycomb pattern.

  In this way, by forming a continuous surface with a plurality of dummy metals 170 each having a regular hexagon as a unit, it is concentrated on the lower edge portion 109 of the edge of the barrier metal 107 between the pad wiring metal 102 and the wiring metal 103. It is possible to suppress the progress of cracks generated by the bump stress. In addition, since the configuration of the honeycomb pattern according to the third embodiment is configured by a continuous surface as in the second embodiment described above, it is caused by bump stress concentrated on the lower edge portion 109 of the barrier metal 107. It can be said that the structure is less likely to induce the generation of cracks.

  As described above, according to the electrode structure of the semiconductor chip according to the third embodiment of the present invention, the progress of cracks generated over a wide range due to the bump stress concentrated at the lower edge position of the barrier metal is suppressed, and the electrode pad The reliability of bump connection can be improved.

  In addition, although the dummy pattern of the electrode pad which concerns on 3rd Embodiment comprised the honeycomb pattern by the several dummy metal 170 which makes a regular hexagon a unit, it is not limited to this. The same effect can be obtained as long as a pattern or the like forms a continuous surface by a plurality of dummy metals each having a uniform polygon as a unit.

(Fourth embodiment)
The electrode structure of the semiconductor chip according to the fourth embodiment of the present invention is different from the electrode structure of the semiconductor chip according to the first to third embodiments described above in the dummy pattern made of a dummy metal. The dummy pattern of the electrode pad according to the fourth embodiment will be described below. 8, the same components as those shown in FIGS. 4 to 7 are denoted by the same reference numerals, and the description thereof is omitted. FIG. 8 is a view showing a dummy pattern of the electrode pad according to the fourth embodiment. In FIG. 8, a diagonal line pattern is formed between the pad wiring metal 102 and the wiring metal 103 by arranging a plurality of dummy metals 180 diagonally.

  Next, the direction in which the plurality of dummy metals 180 constituting the oblique line pattern are arranged will be described in detail. When solder bumps are formed and when a semiconductor chip is mounted on an interposer substrate, the direction of bump stress applied to the electrode pads varies depending on the position of each electrode pad disposed on the semiconductor chip. In general, the direction of the bump stress applied to each electrode pad is a radial direction from the center of the semiconductor chip. Therefore, the direction in which the plurality of dummy metals 180 constituting the oblique line pattern is arranged is determined by the position of the electrode pad on the semiconductor chip.

  FIG. 9 is a diagram showing a semiconductor chip 900 in which electrode pads are arranged on the entire surface of the semiconductor chip. The electrode pads having the oblique line pattern shown in FIG. 8 are electrode pads 901 to 904 arranged in the direction from the center point O of the semiconductor chip 900 toward the point P at the upper left corner of the semiconductor chip 900, and the semiconductor chip 900 It is assumed that the present invention is applied to electrode pads 905 to 908 arranged in the direction from the center point O toward the point Q at the lower right corner of the semiconductor chip 900. In this case, the plurality of dummy metals 180 constituting the oblique line pattern of the electrode pad are arranged in a direction along the direction from the center of the semiconductor chip toward the electrode pad. Similarly, the electrode pads arranged at other positions also need to be arranged in a direction along the direction from the center point of the semiconductor chip toward the electrode pads.

  In this way, by forming the dummy metal in the direction from the center of the semiconductor chip toward the electrode pad, the barrier metal applied between the pad wiring metal 102 and the wiring metal 103 is the same as in the first embodiment described above. The progress of cracks caused by the bump stress concentrated on the lower edge 109 of the edge 107 can be suppressed. Note that the configuration of the oblique line pattern according to the direction of the bump stress applied to each electrode pad can be said to be a configuration that hardly induces the generation of cracks due to the bump stress concentrated on the lower edge portion 109 of the barrier metal 107.

  As described above, according to the electrode structure of the semiconductor chip according to the fourth embodiment of the present invention, it is possible to suppress the progress of cracks caused by the bump stress concentrated at the lower part of the edge position of the barrier metal, and to connect the bump in the electrode pad. Reliability can be improved.

  In the electrode pads according to the first to fourth embodiments described above, the pad wiring metal and the wiring metal are configured in the uppermost layer portion of the semiconductor substrate. However, the wiring metal has a different potential from the pad wiring metal. It doesn't matter.

  In the electrode pads according to the first to fourth embodiments described above, the region where the barrier metal is not formed on the semiconductor substrate is covered with the resin protective film. However, the present invention is not limited to this.

  In addition, the dummy pattern in the electrode structure of the semiconductor chip of the present invention is not limited to the one described in the first to fourth embodiments, and the pattern for suppressing the generation of cracks or the generated cracks are not advanced. Any pattern can be used. Furthermore, there may be one or more dummy metals constituting the pattern.

  Further, in the electrode pads according to the first to fourth embodiments described above, a dummy pattern having no potential between the pad wiring metal and the wiring metal is configured in the uppermost layer portion of the semiconductor substrate. It is not limited. Instead of the dummy pattern having no potential, a configuration including a metal pattern having the same potential as the electrode pad may be used. For example, while the metal pattern is composed of wired metal, the same effect as the dummy pattern in the first to fourth embodiments described above can be obtained.

(Fifth embodiment)
In the fifth embodiment of the present invention, the arrangement of the electrode pads according to the above-described first to fourth embodiments in a semiconductor chip will be described. FIG. 10A is a diagram showing a layout pattern of area pads in which electrode pads are arranged on the entire surface of the semiconductor chip 1010. FIG. 10B is a diagram showing a layout pattern of peripheral pads in which electrode pads are arranged on the periphery of the semiconductor chip 1020.

  In the semiconductor chip 1010 shown in FIG. 10A, the electrodes according to the first to fourth embodiments described above are provided only on the electrode pads 1011 to 1014 at positions farthest from the center point O of the semiconductor chip 1010 (four corner positions of the semiconductor chip). Apply the pad. In the semiconductor chip 1020 shown in FIG. 10B as well, the electrode pads according to the first to fourth embodiments described above are similarly applied only to the electrode pads 1021 to 1028 located farthest from the center point O of the semiconductor chip 1020. .

  Generally, in the flip chip connection configuration, the position where the largest bump stress is likely to be applied is the lower part of the barrier metal edge position of the electrode pad formed at the position farthest from the center of the semiconductor chip. This is because the semiconductor chip is made of silicon and the interposer substrate is made of resin, and the bump distortion is most generated due to the mismatch of thermal expansion coefficients.

  Thus, by applying the electrode pad according to the first to fourth embodiments described above only to the electrode pad farthest from the center of the semiconductor chip, the pad wiring metal in the electrode pad that is most susceptible to bump stress. It is possible to suppress the progress of cracks caused by the bump stress concentrated on the lower edge portion 109 of the barrier metal 107 between the wire 102 and the wiring metal 103.

  As described above, according to the electrode structure of the semiconductor chip according to the fifth embodiment of the present invention, the electrode pads near the four corners of the semiconductor chip arranged away from the center of the semiconductor chip are below the edge position of the barrier metal. The progress of cracks caused by concentrated bump stress can be suppressed, and the reliability of bump connection in the electrode pad can be improved.

  When the electrode pad according to the first to fourth embodiments described above is applied to the electrode pad farthest from the center of the semiconductor chip, the other electrode pads arranged are the first to fourth embodiments described above. You may arrange | position the electrode pad which concerns on a form.

  The semiconductor device to which the electrode structure of the semiconductor chip of the present invention is applied can suppress the progress of cracks caused by the bump stress and improve the connection reliability of the solder bumps. A narrow pad pitch can be achieved, which is useful for increasing the density of semiconductor devices.

The figure which shows the electrode pad of the semiconductor device which concerns on the 1st Embodiment of this invention. Enlarged view of part B2 in FIG. 1 when a vertical crack occurs Enlarged view of part B2 in FIG. 1 when an oblique crack occurs The figure which shows the dummy pattern of the electrode pad which concerns on the 1st Embodiment of this invention The figure which shows the electrode pad of the semiconductor device which concerns on the 2nd Embodiment of this invention. The figure which shows the dummy pattern of the electrode pad which concerns on the 2nd Embodiment of this invention The figure which shows the dummy pattern of the electrode pad which concerns on the 3rd Embodiment of this invention The figure which shows the dummy pattern of the electrode pad which concerns on the 4th Embodiment of this invention The figure which shows the semiconductor chip which concerns on the 4th Embodiment of this invention. The figure which shows the area pad of the semiconductor chip concerning the 5th Embodiment of this invention. The figure which shows the peripheral pad of the semiconductor chip which concerns on the 5th Embodiment of this invention. The figure which shows the flip-chip connection structure of the semiconductor device in a prior art Sectional drawing which shows the flip-chip connection structure of the semiconductor device in a prior art The figure which shows the area pad of the semiconductor chip in a prior art The figure which shows the peripheral pad of the semiconductor chip in a prior art The figure which shows the electrode pad of the semiconductor device in a prior art The figure which shows the adjacent electrode pad of the semiconductor device in a prior art The figure which shows the electrode pad of the semiconductor device in another prior art The figure which shows the adjacent electrode pad of the semiconductor device in another prior art The figure which shows the uppermost layer part of the electrode structure of the semiconductor chip in a prior art Enlarged view of part B1 in FIG.

Explanation of symbols

100, 500, 901-908, 1011-1014, 1021-1028, 1201, 1202, 1300, 1500 Electrode pad 101, 1301 Silicon 102, 1302 Pad wiring metal 103, 1303 Wiring metal 104, 1304 Pad connection metal 105, 1305 Nitride Protective film 106, 1306, 1506 Resin material protective film 107, 1307, 1507 Barrier metal 107a, 1507a Barrier metal edge 108, 1308, 1508 Opening 109, 1309, 1509 Edge position lower part 110, 1103 Solder bump 111, 111a, 111b , 160, 170, 180 Dummy metal 120, 130, 1800 Crack 140 Interlayer film 900, 1010, 1020, 1101 Semiconductor chip 1102 Inter Area A-A 'cross section B1, B2 portion of the electrode pads O semiconductor chip center P of the corner points α conductive component of Q semiconductor chip between the over The substrate 1104 underfill resin 1700 pad wiring metal and the wiring metal

Claims (23)

A semiconductor substrate having a pad metal and a wiring metal having a different potential from the pad metal in the uppermost layer;
An electrode pad formed on the semiconductor substrate;
A resin protective film covering the semiconductor substrate and having an opening so as to expose the electrode pad;
A barrier metal formed on the electrode pad in the opening of the resin protective film;
An electrode structure of a semiconductor chip comprising bumps formed on the barrier metal,
A dummy pattern having no potential between the pad metal and the wiring metal;
The electrode structure of a semiconductor chip, wherein the dummy pattern is formed in a region including a portion in which an edge position of the barrier metal extends in a vertical direction.   2. The electrode structure of a semiconductor chip according to claim 1, wherein an upper surface of a region where the dummy pattern is formed has a region not covered with the resin protective film. The dummy pattern is composed of one dummy metal,
The semiconductor chip electrode structure according to claim 1, wherein an edge of the dummy metal does not coincide with an edge of the barrier metal in a vertical direction. The dummy pattern is composed of a plurality of dummy metals,
Among the plurality of dummy metals, a specific dummy metal is arranged in the vertical direction of the edge position of the barrier metal,
3. The semiconductor chip electrode structure according to claim 1, wherein the edge of the specific dummy metal does not coincide with the edge of the barrier metal in the vertical direction.   5. The electrode structure of a semiconductor chip according to claim 4, wherein the dummy pattern is formed of a plurality of dummy metals arranged at equal intervals and an interlayer film formed between adjacent dummy metals. .   5. The semiconductor chip electrode structure according to claim 4, wherein the dummy pattern is formed in a continuous surface by a plurality of dummy metals.   7. The semiconductor chip electrode structure according to claim 6, wherein the continuous surface is formed of a plurality of regular hexagonal dummy metals.   5. The semiconductor chip electrode structure according to claim 4, wherein the dummy pattern is formed of the dummy metal disposed in a radial direction from the center of the semiconductor chip. A semiconductor chip having a plurality of electrodes on the upper surface,
2. The semiconductor chip having the electrode structure according to claim 1 only around four corners of the semiconductor chip farthest from the center of the semiconductor chip. A semiconductor substrate having a pad metal and a wiring metal for forming an electrode pad on the uppermost layer;
A barrier metal formed on the electrode pad;
An electrode structure of a semiconductor chip comprising bumps formed on the barrier metal,
A metal pattern is provided between the electrode pad and the wiring metal,
The electrode structure of a semiconductor chip, wherein the metal pattern is formed in a region including a portion where an edge position of the barrier metal extends in a vertical direction. A resin protective film covering a region where the barrier metal is not formed on the semiconductor substrate;
11. The electrode structure of a semiconductor chip according to claim 10, wherein an upper surface of a region where the metal pattern is formed has a region not covered with the resin protective film. The metal pattern is composed of one metal,
12. The electrode structure of a semiconductor chip according to claim 10, wherein the edge of the metal does not coincide with the edge of the barrier metal in a vertical direction. The metal pattern is composed of a plurality of metals,
Among the plurality of metals, a specific metal is arranged in the vertical direction of the edge position of the barrier metal,
12. The semiconductor chip electrode structure according to claim 10, wherein the edge of the specific metal does not coincide with the edge of the barrier metal in the vertical direction.   14. The electrode structure of a semiconductor chip according to claim 13, wherein the metal pattern is formed of a plurality of metals arranged at equal intervals and an interlayer film formed between adjacent metals.   The electrode structure of a semiconductor chip according to claim 13, wherein the metal pattern is formed of a plurality of metals on a continuous surface.   The semiconductor chip electrode structure according to claim 15, wherein the continuous surface is formed of a plurality of regular hexagonal metals.   14. The semiconductor chip electrode structure according to claim 13, wherein the metal pattern is formed of the metal disposed in a radial direction from the center of the semiconductor chip. A semiconductor chip having a plurality of electrodes on the upper surface,
The semiconductor chip having the electrode structure according to claim 10 only around four corners of the semiconductor chip farthest from the center of the semiconductor chip.   The electrode structure of a semiconductor chip according to claim 10, wherein the metal pattern includes a pattern for suppressing generation of cracks.   The electrode structure of a semiconductor chip according to claim 10, wherein the metal pattern includes a pattern for preventing the generated crack from proceeding.   21. The electrode structure of a semiconductor chip according to claim 20, wherein the pattern for preventing the crack from proceeding is made of a plurality of discontinuous metals.   11. The semiconductor chip electrode structure according to claim 10, wherein the metal pattern is a dummy pattern having no potential.   The electrode structure of a semiconductor chip according to claim 10, wherein the metal pattern has the same potential as the electrode pad.

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