JP2009111065A - Optical semiconductor equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the property of a multiple beam laser diode element. <P>SOLUTION: A stress relaxation layer 30 comprising an Au-plated layer is formed on a p-type electrode 21 of a GaAs chip 4. The same stress relaxation layer 42 is provided on an element fixing portion 40 formed on a chip mounting surface of a sub-mount 9. Since the Young's modulus of Au constituting the stress relaxation layers 30 and 42 is lower than the Young's modulus of GaAs, residual stress resulting from the difference of linear expansion coefficients between the GaAs chip 4 and the sub-mount 9 is absorbed and eased by these stress relaxation layers 30 and 42. Since the residual stress of the GaAs chip 4 is reduced, the property change of a laser diode element is controlled. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to an optical semiconductor device, and more particularly to a technique effective when applied to an optical semiconductor device having a semiconductor laser diode (LD) element.

  Laser diode elements that are frequently used as light sources for optical communication systems and information processing equipment have a structure in which a multilayer semiconductor layer made of AlGaInP, GaInP, GaAs, etc. is epitaxially grown on the main surface of a compound semiconductor substrate made of GaAs or the like. It has become.

  An active layer is provided in the middle layer of the multilayer semiconductor layer, and one of the layers sandwiching the active layer is a first conductivity type semiconductor layer and the other is a second conductivity type semiconductor layer, whereby a pn junction is formed. (Pn junction) is formed. Various structures such as a ridge structure are employed to form a resonator (optical waveguide) for causing laser oscillation.

  The compound semiconductor substrate (chip) on which the laser diode element is formed is fixed by solder to a support substrate made of a material having good thermal conductivity (eg, AlN, SiC, etc.) called a submount disposed in the package. Have been used. Further, in order to efficiently dissipate heat generated when the laser diode element emits light, it is possible to adopt a junction down method in which a pn junction (junction) serving as a heat generation source is fixed in the state of being close to the support substrate. Many.

The above-described submount materials such as AlN and SiC are sufficient for the function of dissipating heat generated during light emission of the laser diode element, but the linear expansion coefficient of GaAs is 5.9 × 10 ⁻⁶ / ° C. located in contrast, the linear expansion coefficient of AlN and SiC, respectively 4.6 × ^{10 -6} /℃,4.0×10 ^-6 / ℃ and small. Therefore, after the semiconductor substrate is solder-bonded to the support substrate, strain stress remains in the semiconductor substrate due to the above-described difference in linear expansion coefficient between the semiconductor substrate and the support substrate, which causes fluctuations in the characteristics of the laser diode element.

An optical semiconductor device described in Japanese Patent Application Laid-Open No. 2006-278694 (Patent Document 1) is provided by providing a stress relaxation layer made of a thick Au plating layer on an electrode of a semiconductor substrate (an electrode connected to a support substrate). Discloses a technique for reducing the residual strain stress described above.
JP 2006-278694 A

  Conventionally, when mounting a semiconductor substrate on which a laser diode element is formed on a submount, Pb-Sn solder has been widely used. The Pb—Sn solder can be bonded at a relatively low temperature (about 200 ° C.), and stress relaxation can be achieved by the creep deformation of the solder after mounting.

  However, since Pb-Sn solder cannot be used due to recent environmental measures (Pb-free), the field of optical semiconductor devices is also being converted to Pb-free solder such as Au-Sn solder. ing. However, since the mounting temperature of Au—Sn solder is as high as 300 ° C. to 350 ° C., it is difficult to reduce the strain stress remaining on the semiconductor substrate after mounting by the technique described in Patent Document 1. ing.

  For this reason, in particular, in a multi-beam laser diode element in which a plurality of resonators are formed on a semiconductor substrate, there is a problem that the wavelength and polarization characteristics differ from beam to beam due to the influence of the residual distortion. In the case of a single beam, there is no problem as a characteristic within the single beam, but when viewed in lot units, the polarization characteristic varies, causing a decrease in reliability and yield.

  An object of the present invention is to provide a technique for solving the problem that in an optical semiconductor device, distortion stress remains in a semiconductor substrate due to a difference in linear expansion coefficient between the semiconductor substrate and a support substrate, and the characteristics of the laser diode element fluctuate. There is to do.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  An optical semiconductor device according to the present invention is formed on a semiconductor substrate, a multilayer semiconductor layer formed on a first surface of the semiconductor substrate and having a resonator for laser oscillation, and the multilayer semiconductor layer. A laser diode element having a first electrode in which conductor layers are stacked in multiple layers, and a second electrode formed on a second surface opposite to the first surface of the semiconductor substrate; A support substrate having an element fixing portion made of a conductor layer for fixing the first electrode of the laser diode element on the surface of the laser diode element, and the laser is interposed between the element fixing portion of the support substrate and a bonding material. An optical semiconductor device to which the first electrode of a diode element is connected, wherein the element fixing portion of the support substrate has a difference in thermal expansion coefficient between the semiconductor substrate and the support substrate. Relax and absorb stress applied to the substrate First stress relieving layer to is one that is provided.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By providing the stress relaxation layer in the element fixing portion of the support substrate, the stress applied to the semiconductor substrate due to the difference in thermal expansion coefficient between the semiconductor substrate and the support substrate can be relaxed and absorbed.

  As a result, the strain stress remaining on the semiconductor substrate due to the difference in linear expansion coefficient between the semiconductor substrate and the support substrate can be reduced, so that the characteristic variation of the laser diode element can be reduced.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted.

(Embodiment 1)
FIG. 1 is a fragmentary perspective view showing an optical semiconductor device of the present embodiment. The optical semiconductor device 1 has a package (sealing container) including a disc-shaped stem 2 and a cap 3 that covers the upper surface of the stem 2, and a GaAs chip 4 is sealed inside the cap 3. Has been. The stem 2 is made of an Fe alloy having a diameter of about 5.6 mm and a thickness of about 1.2 mm. The flange portion 5 provided on the outer periphery of the bottom portion of the cap 3 is fixed to the upper surface of the stem 2 by a bonding material (not shown). A round hole 7 to which a transparent glass plate 6 is joined is provided in the central portion of the upper surface of the cap 3.

  Near the center of the upper surface of the stem 2, a heat sink 8 made of a metal having good thermal conductivity such as Cu is mounted. The heat sink 8 is joined to the upper surface of the stem 2 via a brazing material (not shown). A submount (support substrate) 9 is fixed to one side of the heat sink 8 via solder (not shown), and a GaAs chip 4 on which a semiconductor laser element is formed is formed on one side of the submount 9. Has been implemented.

The submount 9 serves as a support substrate for the GaAs chip 4 and is made of a material having good thermal conductivity and a thermal expansion coefficient close to that of the GaAs chip 4, such as AlN (aluminum nitride), SiC (silicon carbide). Become. The linear expansion coefficient of the GaAs chip 4 is 5.9 × 10 ⁻⁶ / ° C. The linear expansion coefficient of AlN and SiC are each ^{4.6 × 10 -6 /℃,4.0×10 -6 / ℃} .

  An electrode (n-type electrode) not shown in FIG. 1 is formed on the surface of the GaAs chip 4, and this electrode and the heat sink 8 are electrically connected by an Au wire 10. As will be described later, the GaAs chip 4 is mounted on the surface of the submount 9 by a junction down system in which a main surface serving as a light emitting portion is opposed to the submount 9.

  The GaAs chip 4 emits laser light from its both ends (upper end and lower end in FIG. 1). Therefore, the submount 9 that supports the GaAs chip 4 is fixed to the heat sink 8 so that the chip mounting surface faces a direction perpendicular to the upper surface of the stem 2. Laser light emitted from the upper end of the GaAs chip 4 is emitted to the outside through the circular hole 7 of the cap 3.

  Three leads 12a, 12b, and 12c are attached to the lower surface of the stem 2. Among them, the two leads 12 a and 12 b are fixed to the stem 2 through the insulator 13 in a penetrating manner. The upper end portion of the lead 12 a protruding to the upper surface side of the stem 2 and the heat sink 8 are electrically connected by the Au wire 11. Although not shown in the drawing, the Au wire 11 is electrically connected to the electrode (p-type electrode) of the GaAs chip 4 via the heat sink 8. On the other hand, the lead 12 c is fixed to the lower surface of the stem 2 and is in an electrically equipotential state with the stem 2.

  FIG. 2 is an enlarged cross-sectional view showing a joint portion between the GaAs chip 4 and the submount 9. Here, a GaAs chip 4 having a two-beam structure is shown as an example of a multi-beam laser diode element.

  The GaAs chip 4 has a multilayer semiconductor layer made of a compound semiconductor formed on the surface of an n-type GaAs substrate 4a, and an n-type electrode 20 formed on the back surface of the GaAs substrate 4a. The n-type electrode 20 that is a common electrode has a structure in which, for example, an AuGeNi layer, a Cr layer, and an Au layer are sequentially stacked from the side close to the GaAs substrate 4a. The thickness of the GaAs substrate 4a is about 100 μm.

  The semiconductor layer has a structure in which, for example, an n-type buffer layer 23, an n-type cladding layer 24, an active layer 25, a p-type cladding layer 26, and a p-type etch stop layer 27 are sequentially stacked from the side close to the GaAs substrate 4a. In the upper part of the p-type etch stop layer 27, two convex ridges 28 are formed at a predetermined interval. A resonator that performs laser oscillation is formed in the middle layer of the multilayer semiconductor device.

  Of the multilayer semiconductor layers, the n-type buffer layer 23 is formed of a GaAs layer having a thickness of 0.5 μm, and the n-type cladding layer 24 is formed of AlGaInP having a thickness of 2.0 μm. The active layer 25 is formed of a barrier layer made of an AlGaInP layer having a thickness of 5 nm and a well layer made of a GaInP layer having a thickness of 6 nm. This well layer has a three-layer multiple quantum well structure. The p-type cladding layer 26 is formed of an AlGaInP layer having a thickness of 0.3 μm, and the p-type etch stop layer 27 is formed of a GaInP layer having a thickness of 5 nm. The convex ridge portion 28 is formed of an AlGaInP layer having a thickness of 1.2 μm and a p-type contact layer made of a GaAs layer having a thickness of 0.4 μm.

  A stress relaxation layer 30 is formed on the ridge portion 28 via an adhesion layer 29. An Au layer 32 is formed on the upper part of the stress relaxation layer 30, that is, on the outermost surface of the GaAs chip 4 with a barrier layer 31 interposed therebetween. The adhesion layer 29, the stress relaxation layer 30, the barrier layer 31, and the Au layer 32 constitute the p-type electrode 21 of the GaAs chip 4, and are each formed by a known vapor deposition technique.

  The stress relaxation layer 30 is provided to absorb and relieve stress generated due to the difference in linear expansion coefficient between the GaAs chip 4 and the submount 9. In this embodiment, for example, the thickness is 3 μm or more. The Au plating layer. The adhesion layer 29 is provided in order to prevent the semiconductor layer and the stress relaxation layer 30 from peeling off, and is formed of, for example, a three-layer film of Ti / Pt / Au. The barrier layer 31 is formed of, for example, a two-layer film of Ti / Pt, and is provided to prevent mutual diffusion between the Au plating layer and the Au layer 32 constituting the stress relaxation layer 30.

  On the other hand, an element fixing portion 40 to which the GaAs chip 4 is fixed is formed on the chip mounting surface of the submount 9. The element fixing portion 40 is formed of a three-layer film formed by vapor deposition in the order of the adhesion layer 41, the stress relaxation layer 42 and the barrier layer 43 from the side close to the submount 9. Similar to the stress relaxation layer 30 provided on the GaAs chip 4, the stress relaxation layer 42 is provided to absorb and relax the stress generated due to the difference in linear expansion coefficient between the GaAs chip 4 and the submount 9. In this embodiment, for example, it is formed of an Au plating layer having a thickness of 3 μm or more. The adhesion layer 41 is provided to prevent the submount 9 and the stress relaxation layer 42 from being peeled off. When the stress relaxation layer 42 is made of Au, it is formed of, for example, a three-layer film of Ti / Pt / Au. The barrier layer 43 is formed of, for example, a Pt film.

  In order to mount the GaAs chip 4 on the surface of the submount 9, AuSn solder 34 is interposed between the p-type electrode 21 of the GaAs chip 4 and the element fixing portion 40 of the submount 9, and a temperature of 300 ° C. to 350 ° C. Then, the AuSn solder 34 is melted. As a result, the Au layer 32 on the surface of the p-type electrode 21 and the molten AuSn solder 34 are interdiffused and eutectic, whereby the GaAs chip 4 and the submount 9 are joined.

  Although not shown in FIG. 2, the Au wire 10 shown in FIG. 1 is bonded to the n-type electrode 20 of the GaAs chip 4. Further, the Au wire 11 shown in FIG. 1 is bonded to the surface of the submount 9 electrically connected to the p-type electrode 21 of the GaAs chip 4. Then, by applying a predetermined voltage between the n-type electrode 20 and the p-type electrode 21 through the Au wires 10 and 11, laser light is emitted from both end faces of the GaAs chip 4 orthogonal to the extending direction of the ridge portion 28. Is done.

  Thus, in this embodiment, the stress relaxation layer 30 is provided on the p-type electrode 21 of the GaAs chip 4, and the stress relaxation layer 42 is provided on the element fixing portion 40 formed on the chip mounting surface of the submount 9. . Here, the Young's modulus of Au constituting the stress relaxation layers 30 and 42 is 81 GPa, which is lower than that of GaAs (= 85.5 GPa). Therefore, the residual stress resulting from the difference in linear expansion coefficient between the GaAs chip 4 and the submount 9 is absorbed and relaxed by these stress relaxation layers 30 and 42. As a result, the residual stress of the GaAs chip 4 is reduced, so that a two-beam laser diode with uniform wavelength characteristics, FFP characteristics, polarization characteristics, etc. between the two beams can be obtained.

  In this embodiment, since the stress relaxation layer 30 of the GaAs chip 4 is formed of an Au plating layer having a thickness of 3 μm or more, the outermost Au layer 32 can be formed extremely thin. Thereby, when the GaAs chip 4 is mounted on the submount 9, excessive interdiffusion between the molten AuSn solder 34 and the Au layer 32 is suppressed, so that the reliability of the joint due to segregation or dispersion of the diffusion state is suppressed. Reduction is suppressed.

  The p-type electrode 21 of the GaAs chip 4 has a structure in which the Au layer 32 is provided on the outermost surface in the same manner as in the past. The structure is provided. Therefore, by providing the stress relaxation layers 30 and 42, the bonding strength between the GaAs chip 4 and the submount 9 does not decrease, and the wire bonding property does not decrease.

(Embodiment 2)
In the first embodiment, the stress relaxation layer 42 of the element fixing portion 40 is formed of an Au plating layer. In this embodiment, the stress relaxation layer 42 is formed of a solder material having a Young's modulus lower than that of Au. ing. As a solder material having a Young's modulus lower than that of Au, Bi-Sn solder (Young's modulus: 33 GPa) used as a low melting point solder (melting point: 139 ° C.) can be exemplified. In addition, Sn—Ag solder, Sn—Ag—Cu solder, or the like can be used as a solder material having a low Young's modulus other than Bi—Sn solder.

  According to the present embodiment, the residual stress caused by the difference in linear expansion coefficient between the GaAs chip 4 and the submount 9 can be absorbed and relaxed by the stress relaxation layers 30 and 42, so that the same as in the first embodiment. An effect can be obtained.

(Embodiment 3)
In the first embodiment, the stress relaxation layer 42 of the element fixing portion 40 is formed of an Au plating layer. However, in this embodiment, the stress relaxation layer 42 is formed of a polyimide resin having a Young's modulus lower than that of Au (Young's modulus). : 7 GPa). Although the polyimide resin is an organic material, its melting temperature is higher than the melting temperature of the AuSn solder 34, so that it can withstand high temperatures when the GaAs chip 4 is mounted on the submount 9. Since polyimide resin is an insulating material, it is desirable to reduce the film thickness in order to ensure electrical continuity between the GaAs chip 4 and the submount 9.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  In the above embodiment, the stress relaxation layer 30 is provided on the p-type electrode 21 of the GaAs chip 4 and the stress relaxation layer 42 is provided on the element fixing portion 40 of the submount 9, but only on the element fixing portion 40 of the submount 9. Only the stress relaxation layer 42 may be provided, and the stress relaxation layer 30 of the p-type electrode 21 is not necessarily required.

  In the above-described embodiment, an example in which the present invention is applied to a laser diode element having a two-beam structure has been described, but it is needless to say that the present invention can be applied to a multi-beam laser diode element having a three-beam structure or more. Further, the stress relaxation layer 42 is not limited to an Au plating layer, solder, or polyimide resin as long as the same effect can be obtained.

  The present invention can be applied not only to a multi-beam laser diode element but also to a single beam laser diode element. In this case, variation in polarization characteristics between lots can be suppressed.

  The present invention can be applied to an optical semiconductor device having a laser diode element.

It is a principal part fracture perspective view showing an optical semiconductor device which is one embodiment of the present invention. It is a principal part expanded sectional view of the optical semiconductor device which is one embodiment of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Optical semiconductor device 2 Stem 3 Cap 4 GaAs chip 4a GaAs substrate 5 Flange part 6 Glass plate 7 Round hole 8 Heat sink 9 Submount 10, 11 Au wire 12a, 12b, 12c Lead 13 Insulator 20 N-type electrode 20a AuGeNi layer 20b Cr layer 20c Au layer 21 p-type electrode 23 n-type buffer layer 24 n-type cladding layer 25 active layer 26 p-type cladding layer 27 p-type etch stop layer 28 ridge portion 29 adhesion layer 30 stress relaxation layer 31 barrier layer 32 Au layer 34 AuSn solder 40 Element fixing part 41 Adhesion layer 42 Stress relaxation layer 43 Barrier layer

Claims (8)

A semiconductor substrate;
A multi-layered semiconductor layer formed on the first surface of the semiconductor substrate and formed with a laser that oscillates;
A first electrode in which a conductor layer formed on the multilayer semiconductor layer is laminated in multiple layers;
A laser diode element having a second electrode formed on a second surface opposite to the first surface of the semiconductor substrate;
A support substrate having an element fixing portion made of a conductor layer for fixing the first electrode of the laser diode element on the first surface;
An optical semiconductor device in which the first electrode of the laser diode element is connected to the element fixing portion of the support substrate via a bonding material,
The element fixing portion of the support substrate is provided with a first stress relaxation layer for relaxing and absorbing stress applied to the semiconductor substrate due to a difference in thermal expansion coefficient between the semiconductor substrate and the support substrate. An optical semiconductor device.   The first electrode of the laser diode element has a second stress relaxation layer for relaxing and absorbing stress applied to the semiconductor substrate due to a difference in thermal expansion coefficient between the semiconductor substrate and the support substrate. The optical semiconductor device according to claim 1, wherein the optical semiconductor device is provided.   2. The optical semiconductor device according to claim 1, wherein a plurality of the resonators are formed on the first surface of the semiconductor substrate.   The optical semiconductor device according to claim 1, wherein the first stress relaxation layer is made of an Au layer.   2. The optical semiconductor device according to claim 1, wherein the first stress relaxation layer comprises a solder layer having a Young's modulus smaller than that of the semiconductor substrate.   6. The optical semiconductor device according to claim 5, wherein the solder layer is Bi-Sn solder.   The optical semiconductor device according to claim 1, wherein the first stress relaxation layer is made of a polyimide resin.   The optical semiconductor device according to claim 2, wherein the second stress relaxation layer is made of an Au layer.

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