JP2009053594A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display device capable of suppressing an increase in power consumption of the device is provided.
The liquid crystal display device 100 includes a pixel 40 including a liquid crystal 46. The pixel 40 includes a plurality of transistors 41a to 41c, and signal storage capacitors 42a to 42c connected to the plurality of transistors 41a to 41c. A plurality of transistors 43a to 43c connected to the signal storage capacitors 42a to 42c, a signal storage capacitor 44a to 44c connected to each of the plurality of transistors 43a to 43c, and a plurality of transistors connected to the signal storage capacitors 44a to 44c Transistors 45a to 45c and a display pixel capacitor 47 connected to the plurality of transistors 45a to 45c are included.
[Selection] Figure 2

Description

  The present invention relates to a liquid crystal display device.

  Conventionally, various liquid crystal display devices are known (see, for example, Patent Document 1). In Patent Document 1, one frame forming one color image is composed of three consecutive subframes displaying three unit color images of red (R), green (G), and blue (B). A liquid crystal display device that performs configured field sequential driving is disclosed. In a field sequential liquid crystal display device, in each subframe, writing of unit color image data to pixels and light emission of a light source corresponding to the unit color are sequentially performed, so that red, green, and blue When the unit color images appear to overlap, a color image can be displayed.

JP 2002-211702 A

  However, in the liquid crystal display device described in Patent Document 1, it is necessary to switch subframes at high speed in order to display a color image in which red, green, and blue unit color images appear to overlap. For this reason, there is a problem that the power consumption of the liquid crystal display device increases.

  The present invention has been made to solve the above-described problems, and one object of the present invention is to provide a liquid crystal display device capable of suppressing an increase in power consumption of the device. It is.

Means for Solving the Problems and Effects of the Invention

  A liquid crystal display device according to an aspect of the present invention includes a plurality of signal lines, a first gate line, a second gate line, and a plurality of third gate lines intersecting with the plurality of signal lines, a plurality of signal lines, and a first signal line. And a pixel including a liquid crystal arranged corresponding to a position where the gate line, the second gate line, and the third gate line cross each other, and the pixel has one of a source and a drain connected to the signal line, A plurality of first transistors whose gates are connected to one gate line; a first signal storage capacitor having one electrode connected to the other of the source and drain of each of the plurality of first transistors; and one of the first signal storage capacitors A plurality of second transistors having one of a source and a drain connected to the electrode and a gate connected to the second gate line; A second signal storage capacitor having one electrode connected to the other of each source and drain; one of the source and drain connected to one electrode of the second signal storage capacitor; and a plurality of third gate lines A plurality of third transistors whose gates are connected to each other, and a display pixel capacitor connected to the other of the sources and drains of the plurality of third transistors.

  In the liquid crystal display device according to this aspect, as described above, the pixel has a first signal storage capacitor connected to each of the plurality of first transistors and a second signal connected to each of the plurality of second transistors. By including the storage capacity and the display pixel capacity, for example, RGB image signals of the currently displayed subframes are simultaneously stored in the plurality of second signal storage capacities, respectively, and the RGB image signals are sequentially displayed. Therefore, field sequential driving can be performed without converting RGB parallel signals to RGB serial signals. Thereby, unlike the conventional field sequential drive, it is not necessary to increase the frequency (Hz) of the signal. As a result, increase in power consumption can be suppressed. Further, since it is not necessary to convert the RGB parallel signal to the RGB serial signal, a driver used in conventional driving including an RGB color filter can be used. In addition, while sequentially writing and displaying RGB image signals to the display pixel capacity, the RGB image signals of the next subframe to be displayed can be written to the first signal storage capacity in parallel, so that one subframe can be written. This period can be shortened.

  In the liquid crystal display device according to the above aspect, preferably, the plurality of signal lines include three signal lines corresponding to RGB, and the plurality of first transistors, the plurality of second transistors, and the plurality of third transistors are: Each of the third gate lines includes three first transistors corresponding to red, green, and blue, three second transistors, and three third transistors. The plurality of third gate lines correspond to three third transistors corresponding to red, green, and blue. Includes gate lines. If comprised in this way, while simultaneously writing the image signal corresponding to RGB to the 1st signal storage capacity connected to three 1st transistors, it is moved to the 2nd signal storage capacity, and it writes in a display pixel capacity one by one, and displays Therefore, the field sequential drive can be easily performed without converting the RGB parallel signal into the RGB serial signal.

  In this case, preferably, the first signal is turned on by writing the charge corresponding to RGB to the first signal storage capacitor of the pixel by turning on the first transistor and then turning on the second transistor. The charge written in the storage capacity is moved to the second signal storage capacity. According to this configuration, after the charge corresponding to the image signal written in the first signal storage capacity is moved to the second signal storage capacity, the image signal of the next subframe to be displayed can be easily stored in the first signal storage. Can write to capacity.

  In the liquid crystal display device including the three first transistors, the three second transistors, and the three third transistors corresponding to RGB, preferably, the second signal is obtained by sequentially turning on the three third transistors. Charges corresponding to RGB written in the storage capacitor are sequentially moved to the display pixel capacitor for each color. With this configuration, field sequential driving can be easily performed by sequentially turning on the three third transistors without converting the RGB parallel signal to the RGB serial signal. As a result, the power consumption of the liquid crystal display device is smaller because the third transistor is driven by turning it on / off sequentially than when the RGB parallel signal is converted to the RGB serial signal and the field sequential drive is performed. It is possible to suppress the increase.

  In the liquid crystal display device according to the above aspect, preferably, a gate is connected to the fourth gate line intersecting with the plurality of signal lines, and one of the source and the drain is connected to the display pixel capacitor. And a reset transistor for initializing a display pixel capacitor in which the other of the source and the drain is connected to a predetermined potential. With this configuration, since the display pixel capacitance is initialized by the reset transistor, it is possible to suppress the influence of the image signal of the subframe immediately before being stored in the display pixel capacitance on the image signal of the immediately subsequent subframe. be able to.

  The liquid crystal display device according to the above aspect preferably further includes a backlight as a light source, and the backlight is kept constant while the liquid crystal contained in the pixel responds due to the charge accumulated in the display pixel capacitor and after the response of the liquid crystal. The charge corresponding to the image signal is written in the first signal storage capacity while the light is on for a period of time. With this configuration, the writing and display of the image signal of the subframe displayed immediately before to the display pixel capacity and the writing of the image signal of the subframe displayed immediately after to the first signal storage capacity are performed in parallel. Since it can be performed, the period of one subframe can be easily shortened.

  In this case, preferably, the backlight is configured by light emitting diode elements composed of red, green, and blue, and the backlight is configured to be controlled by field sequential driving that is sequentially turned on for each color. With this configuration, pixels corresponding to each of RGB are not necessary, and the number of pixels can be reduced to 1/3.

  In the liquid crystal display device according to the above aspect, the voltage applied to each of the plurality of signal lines is preferably corrected based on the voltage of the image signal of the immediately preceding subframe applied to the display pixel capacitor. It is configured. With this configuration, even when the voltage of the image signal in the subframe immediately before being applied to the display pixel capacitor affects the voltage of the image signal in the subframe to be displayed immediately afterward, the voltage applied to the signal line Therefore, an appropriate image can be displayed.

  In the liquid crystal display device according to the above aspect, it is preferable that the capacity value of the first signal storage capacity is larger than the capacity value of the second signal storage capacity. With this configuration, for example, by setting the capacity value of the first signal storage capacity to be twice the capacity value of the second signal storage capacity, the image displayed immediately before being stored in the second signal storage capacity is displayed. Since it is possible to suppress an increase in the influence of the signal, an increase in the amount of correction of the voltage applied to the signal line can be suppressed.

  In the liquid crystal display device according to the above aspect, the liquid crystal included in the pixel preferably has a bend alignment in which constituent molecules are arranged in a bow shape after applying a phase transition voltage. With this configuration, the change in the orientation of the liquid crystal molecules is accelerated by the bending of the bow, so that a liquid crystal display device with a high response speed can be configured.

  In the liquid crystal display device according to the above aspect, the other electrode of the first signal storage capacitor and the other electrode of the second signal storage capacitor and the other electrode of the display pixel capacitor are preferably configured to have the same potential. Yes. With this configuration, when the charge accumulated in the first signal storage capacitor is moved to the second signal storage capacitor, and when the charge accumulated in the second signal storage capacitor is moved to the display pixel capacitor In addition, since the potential before the movement and the potential after the movement can be made the same, the change in the image signal due to the movement of the charges can be suppressed.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a block diagram showing the overall configuration of the liquid crystal display device according to the first embodiment of the present invention. FIG. 2 is a diagram illustrating a configuration of a pixel according to the first embodiment of the present invention. First, the configuration of the liquid crystal display device 100 according to the first embodiment will be described with reference to FIGS. 1 and 2. In the first embodiment, a case where the present invention is applied to a field sequential liquid crystal display device 100 which is an example of a liquid crystal display device will be described.

  As shown in FIG. 1, the field sequential liquid crystal display device 100 according to the first embodiment includes a driver IC 1 and a liquid crystal module 2. This will be described in detail below.

As shown in FIG. 1, the driver IC 1 includes a field memory 11, a first latch (memory) 12, a second latch (memory) 13, a digital analog converter (DAC) 14, a timing controller (TC) 15, and a DC / DC converter. (DC / DC) 16, V _COM driver 17 and DSD (drain storage data) driver 18.

  The field memory 11 is configured to receive RGB parallel signals. Here, in the first embodiment, the field memory 11 has a function of correcting the voltage of an image signal applied to signal lines 31 to 33 described later. The field memory 11 is connected to the first latch 12, and RGB parallel signals output from the field memory 11 pass through the first latch 12, the second latch 13, and the digital / analog converter 14 to be described later. It is configured to be input to the switch 24.

The timing controller 15 is configured to receive a vertical synchronization signal V _SYNC , a horizontal synchronization signal H _SYNC and a clock signal D _CLK . The timing controller 15 is connected to a signal line switch 22, a V driver 23, and an H shift register 25, which will be described later.

Further, the DC / DC converter 16, + with 5V supply is connected, and is configured to output a positive potential _{V DD} of the lower voltage _{V BB} and + 6.5V for -4 V. The DC / DC converter 16 is connected to a V _COM driver 17 and a DSD driver 18. The V _COM driver 17 has a function of generating a potential of the common electrode V _COM . The DSD driver 18 has a function of generating a DSD (drain storage data) signal and is connected to the signal line switch 22.

  As shown in FIG. 1, the liquid crystal module 2 includes a liquid crystal panel 21, a signal line switch 22, a V driver 23, an H switch 24, an H shift register 25, and a backlight 26.

Signal line switch 22 is connected to the liquid crystal panel 21 has a function of precharging the signal lines 31 to 33 to be described later, it has a function of shorting the common electrode _{V COM} and the signal lines 31 to 33. The signal line switch 22 is connected to the timing controller 15 and is configured to receive the drain storage gate signal DSG from the timing controller 15.

  The V driver 23 is connected to the liquid crystal panel 21. The V driver 23 is connected to the timing controller 15 and is configured to receive the start signal STV and the clock signal CKV from the timing controller 15.

  The H switch 24 is connected to the liquid crystal panel 21 and is connected to signal lines 31 to 33 described later. The H switch 24 is connected to the digital / analog converter 14.

  The H shift register 25 is connected to the H switch 24 and to the timing controller 15, and is configured to receive the start signal STH and the clock signal CKH from the timing controller 15.

  Here, in the first embodiment, the backlight 26 is configured by three light emitting diode elements corresponding to RGB.

  As shown in FIG. 2, the liquid crystal panel 21 includes a signal line 31 corresponding to red (R), a signal line 32 corresponding to green (G), and a signal line 33 corresponding to blue (B). ing. A gate line 34 and a gate line 35 are provided so as to cross the signal lines 31 to 33. The gate lines 34 and 35 are examples of the “first gate line” and the “second gate line” in the present invention, respectively.

  Further, the liquid crystal panel 21 includes gate lines 36 to 38 that are connected to the gates of transistors 45a to 45c, which will be described later, and correspond to RGB. The gate lines 36 to 38 are examples of the “third gate line” in the present invention. Further, a gate line 39 connected to the gate of a reset transistor 48 described later is provided. The gate line 39 is an example of the “fourth gate line” in the present invention. A pixel 40 including a liquid crystal 46 described later is provided at a position where the signal lines 31 to 33 and the gate lines 34 to 39 intersect.

  Here, in the first embodiment, the pixel 40 includes a transistor 41 a (41 b, 41 c) that is connected to one of the source and drain of the signal line 31 (32, 33) and whose gate is connected to the gate line 34. Contains. The transistor 41a (41b, 41c) is an example of the “first transistor” in the present invention.

  Further, the pixel 40 includes a signal storage capacitor 42a (42b, 42c) in which one electrode 421a (421b, 421c) is connected to the other of the source and drain of the transistor 41a (41b, 41c). The signal storage capacity 42a (42b, 42c) is an example of the “first signal storage capacity” in the present invention.

  The pixel 40 includes a transistor 43a (43b, 43b) having one of a source and a drain connected to one electrode 421a (421b, 421c) of the signal storage capacitor 42a (42b, 42c) and a gate connected to the gate line 35. 43c). The transistor 43a (43b, 43c) is an example of the “second transistor” in the present invention.

  The pixel 40 includes a signal storage capacitor 44a (44b, 44c) in which one electrode 441a (441b, 441c) is connected to the other of the source and drain of the transistor 43a (43b, 43c). 44a (44b, 44c) is an example of the “second signal storage capacity” in the present invention. Here, in the first embodiment, the capacity of the signal storage capacities 42a to 42c is configured to be 2 to 5 times the capacity of the signal storage capacities 44a to 44c.

  In the pixel 40, one of the source and the drain is connected to one electrode 441a (441b, 441c) of the signal storage capacitor 44a (44b, 44c), and the gate is connected to the gate line 36 (37, 38). Transistors 45a (45b, 45c) are included. The transistor 45a (45b, 45c) is an example of the “third transistor” in the present invention.

  The transistors 41a to 41c, 43a to 43c, and 45a to 45c are composed of low-temperature polysilicon TFTs (Thin Film Transistors) formed at a relatively low temperature of about 600 ° C. or less.

  One electrode 47a of the display pixel capacitor 47 included in the liquid crystal 46 is connected to the other of the sources and drains of the transistors 45a to 45c.

  Here, in the first embodiment, the liquid crystal 46 has a bend alignment in which constituent molecules are arranged in a bow shape after applying a phase transition voltage. The liquid crystal 46 has a thickness (cell gap) of about 3.8 μm, and the liquid crystal 46 has a refractive index anisotropy of about 0.2. The rubbing direction is parallel rubbing in which the rubbing direction is the same between the upper and lower substrates. The liquid crystal 46 is in a normally white mode in which the display is white when no voltage is applied. The minimum transmittance voltage is set to about 6V.

  The response speed of the liquid crystal 46 is about 0.1 msec when changing from white to black, and is also about 0.1 msec when changing from white to a gradation other than white. Further, the change from black to white is about 1 msec, which is the slowest response time between gradations. The writing time of the image signal to the liquid crystal 46 is about 2 msec.

Here, in the first embodiment, the other electrode 422a (422b, 422c) of the signal storage capacitor 42a (42b, 42c), the other electrode 442a (442b, 442c) of the signal storage capacitor 44a (44b, 44c), and the display the other electrode 47b of the pixel capacitor 47 is connected to the common electrode _{V COM.}

In the first embodiment, the gate is connected to the gate line 39, one of the source and the drain is connected to the one electrode 47a of the display pixel capacitor 47, and the other of the source and the drain is connected to the common electrode _VCOM. A reset transistor 48 is provided.

  FIG. 3 is a diagram for explaining the operation of the liquid crystal display device according to the first embodiment of the present invention. Next, the operation of the liquid crystal display device 100 according to the first embodiment of the present invention will be described with reference to FIGS.

  First, as shown in FIG. 1, RGB parallel signals are input to the field memory 11. Next, the RGB parallel signals output from the field memory 11 are input to the H switch 24 via the first latch 12, the second latch 13 and the digital / analog converter 14.

Further, the timing controller 15 receives the vertical synchronization signal V _SYNC , the horizontal synchronization signal H _SYNC and the clock signal D _CLK . The timing controller 15 outputs a start signal STH and a clock signal CKH to the H shift register 25 and outputs a start signal STV and a clock signal CKV to the V driver 23. Further, the timing controller 15 outputs the drain storage gate signal DSG to the signal line switch 22.

Further, the DC / DC converter 16 is applied with a voltage of +5 V from the power supply, and generates a negative potential V _{BB of} −4 V and a positive potential V _DD of +6.5 V.

The V _COM driver 17 generates the potential of the common electrode V _COM from the voltage supplied from the DC / DC converter 16, and the DSD driver 18 generates a DSD signal. The DSD signal is supplied to the signal line switch 22. Signal line switch 22, based on the DSD signal and DSG signal, the signal lines 31 to 33 (see FIG. 2) as well as the pre-charge, shorting the common electrode _{V COM} and the signal lines 31 to 33.

  Next, when the pixel 40 is selected by the V driver 23 and the H shift register 25, the gate line 34 is scanned and the transistors 41a to 41c are turned on as shown in FIG. Thus, charges corresponding to red (R), green (G), and blue (B) image signals are simultaneously written into the signal storage capacitors 42a to 42c from the signal lines 31 to 33, respectively. Note that the operation of writing charges corresponding to image signals to the signal storage capacitors 42a to 42c is the same as the driving of a conventional liquid crystal display device provided with RGB color filters. That is, in the conventional field sequential drive, RGB parallel signals are converted into RGB serial signals, and charges corresponding to the RGB image signals are sequentially written to the pixels 40. In the first embodiment, however, field sequential drive is used. However, RGB parallel signals are simultaneously written in parallel to the pixels 40. As shown in FIG. 3, one frame of field sequential driving is driven at 60 Hz, and one frame includes two 120 Hz RGB display cycles. As a result, when the line of sight is moved or when the image moves at high speed, a color breakup phenomenon in which a display color different from the original image is recognized due to a time difference in the display of each RGB image. It becomes possible to suppress.

  Here, in the first embodiment, after charges corresponding to RGB image signals are written in all the pixels 40, the gate line 35 is scanned, and the transistors 43a to 43c are turned on, whereby the signals The charges written in the storage capacitors 42a to 42c are moved all at once to the signal storage capacitors 44a to 44c. The time required for this movement is about 0.1 msec.

  Next, the gate line 36 is scanned and the transistor 45 a is turned on, whereby the charge written in the signal storage capacitor 44 a is moved to the display pixel capacitor 47. The time required for this movement is about 0.1 msec. Thereafter, after about 0.6 msec of response time of the liquid crystal 46, the red (R) backlight 26 is turned on for about 2.2 msec.

Next, the gate line 39 is scanned and the reset transistor 48 is turned on, whereby the charge written in the display pixel capacitor 47 is discharged to the common electrode _VCOM .

  Next, the gate line 37 is scanned and the transistor 45 b is turned on, whereby the charge written in the signal storage capacitor 44 b is moved to the display pixel capacitor 47. The time required for this movement is about 0.1 msec. Thereafter, after about 0.6 msec of response time of the liquid crystal 46, the green (G) backlight 26 is turned on for about 2.2 msec.

Next, the gate line 39 is scanned and the reset transistor 48 is turned on, whereby the charge written in the display pixel capacitor 47 is discharged to the common electrode _VCOM .

  Next, the gate line 38 is scanned and the transistor 45 c is turned on, whereby the charge written in the signal storage capacitor 44 c is moved to the display pixel capacitor 47. The time required for this movement is about 0.1 msec. Thereafter, after about 0.6 msec of response time of the liquid crystal 46, the blue (B) backlight 26 is turned on for about 2.2 msec.

  Thus, in the first embodiment, by sequentially turning on the transistors 45a to 45c, the charges corresponding to RGB written in the signal storage capacitors 44a to 44c are sequentially moved to the display pixel capacitor 47.

Next, the gate line 39 is scanned and the reset transistor 48 is turned on, whereby the charge written in the display pixel capacitor 47 is discharged to the common electrode _VCOM . It is to be noted that a reset transistor 48 that discharges charges accumulated in the display pixel capacitor 47 and a reset transistor that discharges charges accumulated in the signal storage capacitors 44a to 44c, although not shown, provide the immediately preceding subframe. Therefore, it is possible to suppress the influence of the image signal of the immediately preceding subframe on the image signal of the immediately following subframe. Thereby, it is not necessary to correct the voltage of the image signal of the subframe immediately after being applied to the signal lines 31 to 33.

  Here, in the first embodiment, in parallel with the writing of the RGB image signal to the display pixel capacitor 47 and the light emission of the backlight 26, the RGB image signal of the next frame is the signal storage capacity. 42a to 42c are written. Thereby, field sequential driving is performed.

  In the first embodiment, as described above, the pixel 40 includes the signal storage capacitors 42a to 42c connected to the transistors 41a to 41c and the signal storage capacitors 44a to 44c connected to the transistors 43a to 43c, respectively. And the display pixel capacitor 47, the RGB image signals of the sub-frames currently displayed are simultaneously stored in the signal storage capacitors 44a to 44c, respectively, and the RGB image signals are sequentially stored in the display pixel capacitor 47. Since writing and display can be performed, field sequential driving can be performed without converting RGB parallel signals to RGB serial signals. Thereby, unlike the conventional field sequential drive, it is not necessary to increase the frequency (Hz) of the signal. As a result, increase in power consumption can be suppressed. Further, since it is not necessary to convert the RGB parallel signal to the RGB serial signal, a driver used in conventional driving including an RGB color filter can be used. In addition, while sequentially writing and displaying RGB image signals in the display pixel capacitor 47, the RGB image signals of the next subframe to be displayed can be written in the signal storage capacitors 42a to 42c in parallel. The period of the subframe can be shortened.

  In the first embodiment, as described above, the signal lines 31 to 33 corresponding to RGB, the transistors 41a to 41c, the transistors 43a to 43c and the transistors 45a to 45c corresponding to RGB, and the gate lines corresponding to RGB. 36 to 38, image signals corresponding to RGB are simultaneously written in the signal storage capacitors 42a to 42c connected to the transistors 41a to 41c, and moved to the signal storage capacitors 44a to 44c to be sequentially displayed in the display pixel capacitor 47. Since writing and display can be performed, field sequential driving can be easily performed without converting RGB parallel signals to RGB serial signals.

  In the first embodiment, as described above, the transistors 41a to 41c are turned on to write the charges corresponding to RGB to the signal storage capacitors 42a to 42c of the pixel 40, and then the transistors 43a to 43c. Is turned on to move the electric charges written in the signal storage capacitors 42a to 42c to the signal storage capacitors 44a to 44c, thereby corresponding to the image signals written in the signal storage capacitors 42a to 42c. After the charge is moved to the signal storage capacitors 44a to 44c, the image signal of the next subframe to be displayed can be easily written to the signal storage capacitors 42a to 42c.

  In the first embodiment, as described above, by sequentially turning on the three transistors 45a to 45c, the charges corresponding to RGB written in the signal storage capacitors 44a to 44c are sequentially displayed for each color. By being configured to move to the pixel capacitor 47, field sequential driving can be easily performed by sequentially turning on the three transistors 45a to 45c without converting the RGB parallel signal to the RGB serial signal. be able to. As a result, the power consumption of the liquid crystal display device 100 is smaller when driving by turning on / off the transistors 45a to 45c than when converting RGB parallel signals to RGB serial signals and performing field sequential driving. It is possible to suppress the increase.

  In the first embodiment, as described above, the gate line 39 intersecting with the signal lines 31 to 33 and the gate line 39 are connected to the gate, and one of the source and the drain is connected to the display pixel capacitor 47. By providing the reset transistor 48 for initializing the display pixel capacitor 47 in which the other of the source and the drain is connected to a predetermined potential, the display pixel capacitor 47 can be initialized by the reset transistor 48. It is possible to suppress the influence of the image signal of the immediately preceding subframe stored in the pixel capacitor 47 on the image signal of the immediately following subframe.

  In the first embodiment, as described above, the backlight 26 as the light source is provided, and the liquid crystal 46 included in the pixel 40 responds by the charge accumulated in the display pixel capacitor 47 and after the response of the liquid crystal 46. By configuring the signal storage capacitors 42a to 42c to store charges corresponding to the image signal while the backlight 26 is lit for a certain period of time, the display pixel of the image signal of the subframe displayed immediately before is displayed. Since the writing and display to the capacitor 47 and the writing of the image signal of the sub-frame displayed immediately after to the signal storage capacitors 42a to 42c can be performed in parallel, the period of one sub-frame can be easily shortened. be able to.

  Moreover, in 1st Embodiment, as mentioned above, the backlight 26 is comprised by the light emitting diode element which consists of RGB, and the backlight 26 is controlled by the field sequential drive which lights in order for every color, Since the pixels 40 corresponding to each of RGB are not necessary, the number of pixels can be reduced to 1/3.

  In the first embodiment, as described above, the signal storage capacities 42a to 42c are configured such that the capacity values of the signal storage capacities 42a to 42c are larger than the capacity values of the signal storage capacities 44a to 44c. Is made twice the capacity value of the signal storage capacities 44a to 44c, thereby suppressing an increase in the influence of the signal of the image displayed immediately before being stored in the signal storage capacities 44a to 44c. Therefore, for example, even when the voltage applied to the signal lines 31 to 33 is corrected, an increase in the amount of correction can be suppressed.

  In the first embodiment, as described above, the liquid crystal 46 included in the pixel 40 has a bend alignment in which constituent molecules are arranged in a bow shape in a state where a voltage is applied. Since the change in molecular orientation is accelerated, the liquid crystal display device 100 having a high response speed can be configured.

In the first embodiment, as described above, the other electrodes 422a to 422c of the signal storage capacitors 42a to 42c, the other electrodes 442a to 442c of the signal storage capacitors 44a to 44c, and the other electrode 47b of the display pixel capacitor 47 and by connecting the common electrode _{V COM,} when moving the charges accumulated in the signal storage capacitance 42a~42c the signal storage capacitance 44a-44c, and the charge stored in the signal storage capacitance 44a-44c When the display pixel capacitor 47 is moved, the potential before the movement and the potential after the movement can be made the same, so that the change of the image signal due to the movement of the charges can be suppressed.

(Second Embodiment)
FIG. 4 is a diagram illustrating a configuration of a pixel according to the second embodiment of the present invention. Next, with reference to FIG. 4, in the second embodiment, a liquid crystal display device 101 in which the voltage applied to the signal lines 31 to 33 is corrected will be described, unlike the first embodiment.

  As shown in FIG. 4, unlike the pixel 40 of the first embodiment, the pixel 40a is not provided with the gate line 39 and the reset transistor 48. Thereby, the voltage of the image signal of the immediately preceding subframe accumulated in the display pixel capacitor 47 affects the voltage of the image signal of the immediately following subframe. For this reason, it is necessary to correct the voltage applied to the signal lines 31 to 33.

  In addition, the other structure of 2nd Embodiment is the same as that of the said 1st Embodiment. The operation of the second embodiment is the same as that of the first embodiment except for the image signal correction operation required in the second embodiment.

  Next, an image signal correction operation according to the second embodiment of the present invention will be described with reference to FIG.

  The capacity of the signal storage capacities 44a to 44c shown in FIG. 4 is expressed by the following formula (1).

C _R2 = C _G2 = C _B2 = C ₂ (1)
Next, when the transistor 45a is in the OFF state, the voltage V _1R corresponding to red (R) before correction applied to the signal storage capacitor 44a, the corrected voltage V _1R2, and the display pixel capacitor 47 are applied. The voltage V _2B corresponding to blue (B) in the immediately preceding subframe is expressed as the following equation (2) using the capacitance C ₂ of the signal storage capacitor 44 a and the capacitance C _LC of the display pixel capacitor 47. Is done.

V _1R = (C ₂ V _{1R 2} + C _LC V _2B ) / (C ₂ + C _LC ) (2)
Similarly, the voltage V _1G corresponding to green (G) before correction applied to the signal storage capacitor 44b and the voltage V _1B corresponding to blue (B) before correction applied to the signal storage capacitor 44c are: It is expressed as the following formula (3) and formula (4).

_{V 1G = (C 2 V 1G2} + C LC V 1R) / (C 2 + C LC) ····· (3)
_{V 1B = (C 2 V 1B2} + C LC V 1G) / (C 2 + C LC) ····· (4)
Further, voltages V _2R , V _2G and V _2B applied to the signal storage capacitors 44a to 44c after the transistors 45a to 45c are turned on are expressed by the following equations (5) to (7). It is expressed in

V _2R = (C ₂ V _1R + C _LC V _1B ) / (C ₂ + C _LC ) (5)
V _2G = (C ₂ V _1G + C _LC V _2R ) / (C ₂ + C _LC ) (6)
V _2B = (C ₂ V _1B + C _LC V _2G ) / (C ₂ + C _LC ) (7)
Next, Expression (8) is derived from Expression (2) and Expression (5). However, it is assumed that V _1R = V _2R = V _R and V _1B = V _2B .

_{V 1R2 = (2V R (C} 2 + C LC) -C 2 V 1R -2C LC V 1B) / C 2 ····· (8)
Similarly, the following expressions (9) and (10) are derived from the above expressions (3) and (6), and expressions (4) and (7), respectively.

_{V 1G2 = (2V G (C} 2 + C LC) -C 2 V 1G -2C LC V 1R) / C 2 ····· (9)
_{V 1B2 = (2V B (C} 2 + C LC) -C 2 V 1B -2C LC V 1G) / C 2 ····· (10)
Next, the following formulas (11) to (13) are obtained by solving the above formulas (2) to (10).

V _1R2 = f ₁ (V _R , V _G , V _B , C ₂ , C _LC ) (11)
V _1G2 = f ₂ (V _R , V _G , V _B , C ₂ , C _LC ) (12)
V _1B2 = f ₃ (V _R , V _G , V _B , C ₂ , C _LC ) (13)
Here, f ₁ , f _2, and f ₃ represent functions having V _R , V _G , V _B , C _2, and C _LC as variables.

  Moreover, the capacity | capacitance of the signal storage capacity 42a-42c shown in FIG. 4 is represented by following Formula (14).

C _R1 = C _G1 = C _B1 = C ₁ (14)
Further, as shown in FIG. 4, the relationship between the voltages applied to the signal storage capacitors 42a to 42c and the signal storage capacitors 44a to 44c when the transistors 43a to 43c are in an off state is expressed by the following equation (15 ) To (17).

V _1R1 = V _1R2 (15)
V _1G1 = V _1G2 (16)
V _1B1 = V _1B2 (17)
When the on-resistances of the transistors 41a to 41c are sufficiently small, corrected voltages VR _R and VR _G corresponding to red (R), green (G), and blue (B) applied to the signal lines 31 to 33 are provided. And VR _B are represented by Formula (18) to Formula (20), respectively.

VR _R = V _1R1 = V _1R2 (18)
VR _G = V _1G1 = V _1G2 (19)
VR _B = V _1B1 = V _1B2 (20)
Further, the formula (11) and to (13), equation (18) by a to (20), the voltage _VR R corrected, VR _G and VR _B, respectively, formula (21) to (23) It is represented by

VR _R = f ₁ (V _R , V _G , V _B , C ₂ , C _LC ) (21)
VR _G = f ₂ (V _R , V _G , V _B , C ₂ , C _LC ) (22)
VR _B = f ₃ (V _R , V _G , V _B , C ₂ , C _LC ) (23)
A voltage corrected based on the equations (21) to (23) is applied to the signal lines 31 to 33.

  In the second embodiment, as described above, the voltage applied to each of the signal lines 31 to 33 is corrected based on the voltage of the image signal of the immediately preceding subframe applied to the display pixel capacitor 47. By configuring, even when the voltage of the image signal of the subframe immediately before being applied to the display pixel capacitor 47 affects the voltage of the image signal of the subframe to be displayed immediately thereafter, the voltage is applied to the signal lines 31 to 33. Therefore, an appropriate image can be displayed.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is shown not by the above description of the embodiments but by the scope of claims for patent, and further includes all modifications within the meaning and scope equivalent to the scope of claims for patent.

  For example, in the first embodiment and the second embodiment, the example in which the light emitting diode element (LED) is used as the light source for the backlight is shown. However, the present invention is not limited to this, and the light source for the backlight other than the LED is used. May be used.

In the first and second embodiments, the other electrodes 422a to 422c of the signal storage capacitors 42a to 42c, the other electrodes 442a to 442c of the signal storage capacitors 44a to 44c, and the other electrode 47b of the display pixel capacitor 47 are used. Is connected to the common electrode V _COM . However, the present invention is not limited to this, and the other electrodes 422a to 422c of the signal storage capacitors 42a to 42c and the signal storage capacitors 44a to 44c may be used as long as the potential is the same. and the other electrode 442a~442c of, may be connected to the other electrode 47b and the electrode other than the common electrode _{V COM} of the display pixel capacitor 47.

  In the first and second embodiments, an example in which one frame of field sequential driving is driven at 60 Hz is shown. However, the present invention is not limited to this, and one frame may be driven at 30 Hz. Thereby, the power consumption of the liquid crystal display device can be reduced. In this case, the display of the RGB image is set to 60 Hz by the transistors 45a to 45c.

1 is a block diagram illustrating an overall configuration of a liquid crystal display device according to a first embodiment of the present invention. It is a figure which shows the structure of the pixel by 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the liquid crystal display device by 1st Embodiment of this invention. It is a figure which shows the structure of the pixel by 2nd Embodiment of this invention.

Explanation of symbols

26 Backlight 31-33 Signal line 34 Gate line (first gate line)
35 Gate line (second gate line)
36-38 gate line (third gate line)
39 Gate line (4th gate line)
40, 40a Pixel 41a-41c Transistor (first transistor)
42a to 42c Signal storage capacity (first signal storage capacity)
43a to 43c transistor (second transistor)
44a to 44c Signal storage capacity (second signal storage capacity)
45a to 45c transistor (third transistor)
46 Liquid crystal 47 Display pixel capacitance 47a One electrode 47b The other electrode 48 Reset transistor 421a to 421c One electrode 422a to 422c The other electrode 441a to 441c One electrode 442a to 442c The other electrode

Claims (11)

Multiple signal lines,
A first gate line, a second gate line and a plurality of third gate lines intersecting with the plurality of signal lines;
A pixel including a liquid crystal disposed corresponding to a position where the plurality of signal lines intersect the first gate line, the second gate line, and the third gate line;
The pixel includes a plurality of first transistors having one of a source and a drain connected to the signal line and a gate connected to the first gate line, and a source and a drain of each of the plurality of first transistors. A first signal storage capacitor having one electrode connected to the other; a plurality of first signal storage capacitors connected to one electrode of the first signal storage capacitor and having a gate connected to the second gate line; Two transistors, a second signal storage capacitor having one electrode connected to the other of the source and drain of each of the plurality of second transistors, and one source or drain connected to one electrode of the second signal storage capacitor. A plurality of third transistors each having a gate connected to each of the plurality of third gate lines; And a display pixel capacitance connected to the other of the source and the drain of the third transistor, a liquid crystal display device.   The plurality of signal lines include three signal lines corresponding to red, green, and blue, and the plurality of first transistors, the plurality of second transistors, and the plurality of third transistors are red, green, respectively. 2. And three first transistors corresponding to blue, three second transistors, and three third transistors, and the plurality of third gate lines includes three third gate lines corresponding to RGB. A liquid crystal display device according to 1.   By turning on the first transistor, an electric charge corresponding to RGB is written in the first signal storage capacitor of the pixel, and then turning on the second transistor to turn on the first signal storage. The liquid crystal display device according to claim 2, wherein the liquid crystal display device is configured to move the electric charge written in the capacitor to the second signal storage capacitor.   By sequentially turning on the three third transistors, the charges corresponding to RGB written in the second signal storage capacitor are moved to the display pixel capacitor in order for each color. The liquid crystal display device according to claim 2 or 3. A fourth gate line intersecting the plurality of signal lines;
A gate is connected to the fourth gate line, one of a source and a drain is connected to the display pixel capacitor, and the other of the source and the drain is connected to a predetermined potential for initializing the display pixel capacitor The liquid crystal display device according to claim 1, further comprising a reset transistor. Further equipped with a backlight as a light source,
An image is stored in the first signal storage capacitor while the liquid crystal contained in the pixel responds by the electric charge accumulated in the display pixel capacitor and during the time when the backlight is lit for a certain time after the response of the liquid crystal. The liquid crystal display device according to claim 1, wherein a charge corresponding to a signal is written.   The said backlight is comprised by the light emitting diode element which consists of red, green, and blue, The said backlight is comprised so that it may be controlled by the field sequential drive which lights in order for every color. The liquid crystal display device described.   The voltage applied to each of the plurality of signal lines is corrected based on the voltage of the image signal of the immediately preceding subframe applied to the display pixel capacitor. The liquid crystal display device according to any one of the above.   The liquid crystal display device according to claim 1, wherein a capacity value of the first signal storage capacity is configured to be larger than a capacity value of the second signal storage capacity.   The liquid crystal display device according to claim 1, wherein the liquid crystal included in the pixel has a bend alignment in which constituent molecules are arranged in a bow shape after applying a phase transition voltage.   The other electrode of the first signal storage capacitor, the other electrode of the second signal storage capacitor, and the other electrode of the display pixel capacitor are configured to have the same potential. 2. A liquid crystal display device according to item 1.

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