JP2009016568A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device which can reprogram to an identical bit, and can improve convenience. <P>SOLUTION: The semiconductor integrated circuit device includes a first fuse circuit 11, a second fuse circuit 12, and a control signal generating circuit 13. The control signal generating circuit transmits a first control signal 1st/PE, and programs so that a resistance value of the first fuse circuit 11 may become larger than a resistance value of the second fuse circuit 12, while the control signal generating circuit transmits a second control signal 2nd/PE, and reprograms so that the resistance value of the second fuse circuit 12 may become larger than the resistance value of the first fuse circuit 11. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor integrated circuit device, and is applied to, for example, an SRAM provided with a fuse box.

  2. Description of the Related Art Conventionally, for example, there is a semiconductor integrated circuit device that uses a fusing type fuse element such as an e-fuse and causes a current to flow through the fuse element to destroy the fuse element and program data (see, for example, Patent Documents 1 to 3). . For example, by fusing the fuse element, the resistance value of the fuse element after programming is increased by an order of magnitude compared to the fuse element before programming.

  However, when the fusing type fuse element is used, the fuse element is destroyed once programmed, so that the bit cannot be rewritten. Therefore, when rewriting is necessary, it is necessary to separately prepare a fuse element having a different bit and write to the different fuse element.

As described above, the conventional semiconductor integrated circuit device has a problem in that convenience cannot be reduced because the same bit cannot be reprogrammed.
JP-A-9-7385 JP 2003-318275 A JP 2001-118996 A

  The present invention provides a semiconductor integrated circuit device capable of reprogramming the same bit and improving convenience.

  According to one aspect of the present invention, a first fuse circuit comprising a first fuse element and a first write transistor having one end of a current path connected to one end of the first fuse element, a second fuse element, And a second write transistor connected to one end of the second fuse element, and the resistance value of the second fuse element is larger than the resistance value of the first fuse element. A second fuse circuit having a resistance value larger than that of the fuse circuit, and a first control signal is transmitted to the control terminal of the first writing transistor, so that the resistance value of the first fuse circuit is greater than the resistance value of the second fuse circuit. And a second control signal is transmitted to the control terminal of the second write transistor so that the resistance value of the second fuse circuit is the first fuse. Possible to provide a semiconductor integrated circuit device and a control signal generating circuit for re-programmed to be greater than the resistance value of's circuit.

  According to one aspect of the present invention, a first fuse circuit comprising a first fuse element and a first read transistor having one end of a current path connected to one end of the first fuse element, a second fuse element, A second read transistor connected to one end of the second fuse element, and an on-resistance of the second read transistor is larger than an on-resistance of the first read transistor. A second fuse circuit having a resistance value larger than that of the first fuse circuit; and a first control signal is transmitted to the first fuse circuit so that the resistance value of the first fuse circuit is larger than the resistance value of the second fuse circuit. And a second control signal is transmitted to the second fuse circuit so that the resistance value of the second fuse circuit is the resistance value of the first fuse circuit. Ri may also provide a semiconductor integrated circuit device and a control signal generating circuit for reprogramming to be larger.

  According to the present invention, a semiconductor integrated circuit device that can be reprogrammed with respect to the same bit and can improve convenience is obtained.

  Embodiments of the present invention will be described below with reference to the drawings. In this description, common parts are denoted by common reference symbols throughout the drawings.

[First embodiment (an example in which the resistance value of the fuse element has a magnitude relationship)]
First, the configuration of the semiconductor integrated circuit device according to the first embodiment of the present invention will be described with reference to FIGS. This embodiment relates to an example in which there is a magnitude relationship between the resistance values of two fuse elements. In this example, an e-fuse (eFuse) that can be electrically programmed by fusing the fuse element will be described as an example of the fuse element.

<1. Configuration example>
As shown in the figure, the e-fuse 10 according to this example includes a first fuse circuit 11, a second fuse circuit 12, a sense amplifier 15, and a control signal generation circuit 13.

  The first fuse circuit 11 includes a first fuse element R1, a first write transistor N1, and a first read transistor N3. One end of the first fuse element R1 is connected to the program voltage node VBP. The source of the first write transistor N1 is connected to the internal power supply voltage VSS, the drain is connected to the other end of the first fuse element R1, and the first control signal 1st / PE is input to the gate. The source of the first read transistor N3 is connected to the internal power supply voltage VSS, the drain is connected to the other end of the first fuse element R1, and the read control signal / RE is input to the gate.

  The second fuse circuit 12 includes a second fuse element R2, a second write transistor N2, and a second read transistor N4. One end of the second fuse element R2 is connected to the program voltage node VBP. The source of the second write transistor N2 is connected to the internal power supply voltage VSS, the drain is connected to the other end of the second fuse element R2, and the second control signal 2nd / PE is input to the gate. The source of the second read transistor N4 is connected to the internal power supply voltage VSS, the drain is connected to the other end of the second fuse element R2, and the read control signal / RE is input to the gate.

  In the case of this example, the length of the second fuse element R2 is provided to be longer than the length of the first fuse element R1. On the other hand, the W size (gate width size) ratio of the read transistors N3 and N4 is approximately the same (W size ratio = 1: 1). Therefore, in the initial state, since the resistance value of the second fuse element R2 is larger than the resistance value of the first fuse element R1 (resistance value in the initial state: R1> R2), the resistance value of the second fuse circuit 12 is It is larger than the resistance value of the first fuse circuit 11. The first and second fuse elements R1 and R2 are blown fuse elements that can be blown and programmed by applying a high voltage to both ends thereof. For example, polysilicon, copper (Cu), It is made of a metal such as aluminum (Al).

  The sense amplifier 15 has a first input (positive + side input) connected to the other end of the first fuse element R1, and a second input (negative − side input) connected to the other end of the second fuse element R2 for control. The terminal is connected to the internal power supply voltage VCC and outputs output data Dout of “0” or “1” data. With the above circuit configuration, the sense amplifier 15 reads the voltage difference between the fuse elements R1 and R2 and determines “1” or “0”.

  The control signal generation circuit 13 is configured to generate first and second control signals 1st / PE, 2nd / PE, a read control signal / RE, and a sense amplifier read control signal / RE (S / A). Yes. In this example, the first and second control signals are the program enable signal / PE (“/” means negative), and the read control signal is the read enable signal / RE.

  As will be described later, the control signal generation circuit 13 transmits the first control signal 1st / PE to the gate of the first write transistor N1, and melts the first fuse element R1, thereby causing the resistance value of the first fuse circuit 11 to be blown. Is controlled so as to be larger than the resistance value of the second fuse circuit 12. Further, the control signal generation circuit 13 transmits the second control signal 2nd / PE to the gate of the second write transistor N2, so that the second fuse R2 is blown, and the resistance value of the second fuse circuit 12 is the first fuse. Control is performed so that re-programming is performed so that the resistance value of the circuit 11 becomes larger.

  Therefore, as shown in FIG. 2, even after the first fuse element R1 is programmed (1st program), the second fuse element R2 is reprogrammed by reapplying the program voltage to the second fuse element R2. (2nd program). Therefore, the output data Dout is re-inverted (“0” → “1”, “1” → “0”) by inverting the magnitude relationship between the resistance values of the first and second fuse circuits 11 and 12 twice. be able to. In other words, two electrically programmable first and second fuse elements R1 and R2 are used, and the program mode (medium resistance (1st program), high resistance (2nd program)) is selectively used, and data is stored up to two times. Can write. Thus, according to the above configuration, reprogramming can be performed on the e-fuse 10 that is the same bit.

<2. Read operation (initial state)>
Next, the read operation of the e-fuse 10 in the initial state according to this example will be described with reference to FIG. As illustrated, in the initial state, the resistance value of the second fuse element R2 is set to be larger than the resistance value of the first fuse element R1 (resistance value: R2> R1). For example, in the initial state, the resistance value of the first fuse element R1 is about 100Ω, and the resistance value of the second fuse element R2 is about 200Ω. On the other hand, the W size ratio of the read transistors N3 and N4 is approximately the same (W size ratio = 1: 1). Therefore, in the initial state, the resistance value of the second fuse circuit 12 is larger than the resistance value of the first fuse circuit 11.

  First, the control signal generation circuit 13 outputs the read control signal / RE to the gates of the read transistors N3 and N4, and turns on the read transistors N3 and N4.

  Subsequently, read currents IR1 and IR2 are supplied to both ends of the first and second fuse elements R1 and R2, and the read currents IR1 and IR2 are input to the sense amplifier 15.

  Subsequently, the sense amplifier 15 reads the voltage difference between the fuse elements R1 and R2 from the input read currents IR1 and IR2, and outputs, for example, output data Dout of “0” data.

<3. Program operation>
Next, the program operation of the efuse 10 in the initial state according to this example will be described with reference to FIGS.

<3-1. First program (1st program) operation>
First, the first program (1st program) operation will be described with reference to FIG.
As shown in the figure, first, the control signal generation circuit 13 transmits the first control signal 1st / PE to the gate of the first write transistor N1, and turns on the first write transistor N1.

  Subsequently, the program voltage is applied to the program voltage node VBP, the program voltage is applied to both ends of the first fuse element R1, and the program current Ipgm1 is caused to flow, thereby blowing the first fuse element R1. Therefore, at the time of this 1st programming, the resistance value of the second fuse element R2 is smaller than the resistance value of the first fuse element R1 (resistance value: R2 <R1). For example, in the 1st programming, the resistance value of the programmed first fuse element R1 is about several kΩ. As described above, the control circuit 13 is programmed so that the resistance value of the first fuse circuit 11 is larger than the resistance value of the second fuse circuit 12 in the 1st programming.

  Subsequently, the sense amplifier 15 reads the voltage difference between the fuse elements R1 and R2 from the read currents IR1 and IR2 and outputs the output data Dout of “1” data inverted from the initial state, similarly to the read operation. .

<3-2. Second program (2nd program) operation>
Next, the second program (2nd program) operation will be described with reference to FIG.
As shown in the figure, first, the control signal generation circuit 13 transmits the second control signal 2nd / PE to the gate of the second write transistor N2, and turns on the second write transistor N2.

  Subsequently, the program voltage is applied to the program voltage node VBP, the program voltage is applied to both ends of the second fuse element R2, and the program current Ipgm2 is supplied to blow the second fuse element R2. Therefore, during the 2nd programming, the resistance value of the second fuse element R2 becomes larger again than the resistance value of the first fuse element R1 (resistance value: R2> R1). For example, in the 2nd programming, the resistance value of the programmed second fuse element R2 is about several tens of kΩ. In this way, the control circuit 13 can be reprogrammed so that the resistance value of the second fuse circuit 12 is larger than the resistance value of the first fuse circuit 11 during the second programming.

  Subsequently, the sense amplifier 15 reads the voltage difference between the fuse elements R1 and R2 from the read currents IR1 and IR2 and outputs the output data Dout of “0” data inverted from the time of the 1st program, as in the above read operation. To do.

<4. Effects according to this embodiment>
According to the semiconductor integrated circuit device of this embodiment, at least the following effects (1) to (2) can be obtained.
(1) The same bit can be reprogrammed, and convenience can be improved.
As described above, the control signal generation circuit 13 transmits the first control signal 1st / PE to the gate of the first write transistor N1, blows the first fuse element R1, and the resistance value of the first fuse circuit 11 Is controlled so as to be larger than the resistance value of the second fuse circuit 12. Further, the control signal generation circuit 13 transmits the second control signal 2nd / PE to the gate of the second write transistor N2, so that the second fuse R2 is blown, and the resistance value of the second fuse circuit 12 is the first fuse. It can be controlled to reprogram the circuit 11 so that it is larger than the resistance value.

  Therefore, as shown in FIG. 2, even after the first fuse element R1 is programmed (1st program), the program voltage is applied to the second fuse element R2 to reprogram the second fuse element R2 (2nd Program). Therefore, the output data Dout is re-inverted (“0” → “1”, “1” → “0”) by inverting the magnitude relationship between the resistance values of the first and second fuse elements R1, R2 twice. be able to. In other words, two electrically programmable first and second fuse elements R1 and R2 are used, and the program mode (medium resistance (1st program), high resistance (2nd program)) is selectively used, and data is stored up to two times. Can write.

  Thus, according to the above configuration, reprogramming can be performed for the e-fuse 10 that is the same bit, and convenience can be improved.

  For example, it is assumed that the efuse 10 according to this example is applied as a redundant memory of an SRAM (Static Random Access Memory) as in a third embodiment to be described later. In this case, even if the redundancy is performed once in the wafer test (the program is performed once for the e-fuse 10), redundancy is performed again on the defective cell found in the final test (the same e Since the fuse 10 (the same bit) can be reprogrammed), the yield of the SRAM can be improved.

  (2) It is advantageous for reducing the manufacturing cost.

  As described above, the first and second fuse circuits 11 and 12 have mirror surfaces in the connection between the program voltage node VBP and the node to which the read control signal / RE is input, except for the lengths of the fuse elements R1 and R2. The target structure. Therefore, the number of photomasks when manufacturing the transistors N1 to N4 can be reduced, and the manufacturing cost of the first and second fuse circuits 11 and 12 can be reduced. Thus, according to this example, it is advantageous for reducing the manufacturing cost.

[Second Embodiment (an example in which the on-resistance value of the reading transistor has a magnitude relationship)]
Next, a semiconductor memory device according to the second embodiment will be described with reference to FIGS. This embodiment relates to an example in the case where there is a magnitude relationship between the on-resistance values of the read transistors N3 and N4. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Configuration example>
The configuration of this example will be described with reference to FIGS. As illustrated, the efuse 10 according to this example is different from the first embodiment in the following points.

  First, in the case of this example, the read transistors N3 and N4 are provided so that the W size ratio is 2: 1 (W size ratio). Therefore, the on-resistance of the second read transistor N4 is provided to be larger than the on-resistance of the first read transistor N3. On the other hand, since the lengths of the first and second fuse elements R1 and R2 are substantially the same, the resistance values of the fuse elements R1 and R2 in the initial state are substantially equal (resistance values: R1 to R2).

  Therefore, in the initial state, the on-resistance of the second read transistor N4 is larger than the on-resistance of the first read transistor N3, so that the resistance value of the second fuse circuit 12 is larger than the resistance value of the first fuse circuit 11. It is provided to become.

  Thus, in the configuration of this example, the fuse sizes of the first and second fuse elements R1 and R2 are approximately the same size, but the dimensions (W size ratio) of the read transistors N3 and N4 are unbalanced. Is different from the first embodiment in that a voltage difference input to the sense amplifier 15 is generated.

<Read operation (initial state)>
Next, the read operation of the efuse 10 in the initial state according to this example will be described with reference to FIG. As shown in the drawing, the W size ratio of the read transistors N3 and N4 is set to 2: 1 (W size ratio) in the initial state. On the other hand, since the lengths of the first and second fuse elements R1 and R2 are substantially the same, the resistance values of the fuse elements R1 and R2 in the initial state are substantially equal (resistance values: R1 to R2). Therefore, in the initial state, the resistance value of the second fuse circuit 12 is larger than the resistance value of the first fuse circuit 11.

  First, the control signal generation circuit 13 outputs the read control signal / RE to the gates of the read transistors N3 and N4, and turns on the read transistors N3 and N4.

  Subsequently, read currents IR1 and IR2 are supplied to both ends of the first and second fuse elements R1 and R2, and the read currents IR1 and IR2 are input to the sense amplifier 15.

  Subsequently, the sense amplifier 15 reads the voltage difference between the first and second fuse circuits 11 and 12 from the input read currents IR1 and IR2, and outputs, for example, output data Dout of “1” data.

<Program operation>
Next, the program operation of the eFuse 10 in the initial state according to this example will be described with reference to FIGS.

<First program (1st program) operation>
First, the first program (1st program) operation will be described with reference to FIG.
As shown in the figure, first, the control signal generation circuit 13 transmits the first control signal 1st / PE to the gate of the first write transistor N1, and turns on the first write transistor N1.

  Subsequently, a program voltage is applied to the program voltage node VBP, a program voltage is applied to both ends of the first fuse element R1, a program current Ipgm1 is passed, and the first fuse element R1 is blown. Therefore, at the time of this 1st programming, the resistance value of the second fuse element R2 is smaller than the resistance value of the first fuse element R1 (resistance value: R2 <R1). For example, in the 1st programming, the resistance value of the programmed first fuse element R1 is about several kΩ. On the other hand, the W size ratio of the read transistors N3 and N4 is 2: 1 as in the initial state. Therefore, the control circuit 13 can be programmed so that the resistance value of the first fuse circuit 11 is larger than the resistance value of the second fuse circuit 12 in the 1st programming.

  Subsequently, in the same manner as described above, the sense amplifier 15 reads the voltage difference between the fuse elements R1 and R2 from the read currents IR1 and IR2, and outputs the output data Dout of “0” data inverted from the initial state.

<Second program (2nd program) operation>
Next, the second program (2nd program) operation will be described with reference to FIG.
As shown in the figure, first, the control signal generation circuit 13 transmits the second control signal 2nd / PE to the gate of the second write transistor N2, and turns on the second write transistor N2.

  Subsequently, a program voltage is applied to the program voltage node VBP, a program voltage is applied to both ends of the second fuse element R2, a program current Ipgm2 is passed, and the second fuse element R2 is blown. Therefore, during the 2nd programming, the resistance value of the second fuse element R2 becomes larger again than the resistance value of the first fuse element R1 (resistance value: R2> R1). For example, in the 2nd programming, the resistance value of the programmed second fuse element R2 is about several tens of kΩ. On the other hand, the W size ratio of the read transistors N3 and N4 is 2: 1 as in the initial state. Therefore, the control circuit 13 can be reprogrammed so that the resistance value of the second fuse circuit 12 is larger than the resistance value of the first fuse circuit 11 in the second programming.

  Subsequently, the sense amplifier 15 reads the voltage difference between the first and second fuse circuits 11 and 12 from the read currents IR1 and IR2 in the same manner as the above read operation, and the “1” data inverted from the 1st program time is read. Output data Dout is output.

<Effects according to this embodiment>
According to the semiconductor integrated circuit device of this embodiment, at least the effects (1) to (2) can be obtained. Furthermore, the configuration as in this example can be applied as necessary.

[Third Embodiment (an example applied to a redundant memory of SRAM)]
Next, a semiconductor memory device according to the third embodiment will be described with reference to FIGS. This embodiment relates to an example in which the eFuse 10 described in the first embodiment is applied to a redundant memory of an SRAM (Static Random Access Memory) and configured as a redundancy system. In this description, detailed description of the same parts as those in the first embodiment is omitted.

<Overall configuration example of redundancy system>
An example of the entire configuration of the redundancy system will be described with reference to FIG. As shown in the figure, the SRAM according to this example includes a memory cell array 27, a fuse box 21, a fuse data expansion circuit 22, and a row decoder 25.

  The memory cell array 27 includes a plurality of SRAM cells 1 to SRAM cells n arranged in a matrix.

  The fuse box 21 includes a plurality of efuses <1> to efuses <n> as redundant memories. As shown in FIG. 12, in this example, each of the e-fuse <1> to e-fuse <n> is the e-fuse 10 described in the first embodiment.

  Each of the e-fuse <1> to e-fuse <n> holds “0” or “1” as a defective address of the SRAM cell 1 to the SRAM cell n. The held data (Dout) is output to the Fuse data expansion circuit 22 as output serial data SO of the fuse box 21.

  The Fuse data expansion circuit 22 performs predetermined data expansion on the input serial data SO of the fuse box, and outputs the data serially to the row decoder 25. The predetermined data expansion means the following. That is, the Fuse data expansion circuit 22 outputs “0” data to the 4-bit (“0000”) row decoder 25 when the input serial data SO is “0” data. For example, a case where “0” data held in the e-fuse <1> is input to the Fuse data expansion circuit 22 as serial data SO is taken as an example. In this case, since the input serial data SO is “0” data, the Fuse data expansion circuit 22 outputs “0” data to the 4-bit (“0000”) row decoder 25.

  On the other hand, if the input serial data SO is “1” data, the Fuse data expansion circuit 22 outputs the 4 bits of the fuse box at the address after the “1” data to the row decoder 25. For example, a case where “1” data held in the e-fuse <3> is input to the Fuse data expansion circuit 22 as serial data SO is taken as an example. In this case, since the input serial data SO is “1” data, the Fuse data expansion circuit 22 outputs 4 bits (“1001”) of the fuse box after this “1” data to the row decoder 25.

  The row decoder 25 stores the output of the Fuse data expansion circuit 22 in predetermined R / D shift addresses <1> to R / D shift addresses <n> having a 4-bit configuration. R / D shift address <1> to R / D shift address <n> correspond to the R / D shift addresses of SRAM cell 1 to SRAM cell n.

  Here, SRAM cells that are all “0” (“0000”) in the 4-bit R / D shift address <1> to R / D shift address <n> are determined as normal cells. For example, the SRAM cell n in which all of the R / D shift addresses <n> are “0” (“0000”) is determined as a normal cell. On the other hand, an SRAM cell in which at least one of the 4-bit R / D shift address <1> to R / D shift address <n> is “1” is determined as a defective cell. For example, the SRAM cell 3 which is “1001” of the R / D shift address <3> is determined as a defective cell.

<Redundancy operation>
Next, the redundancy operation of the semiconductor integrated circuit device according to this example will be described. In this description, the following description will be made in accordance with the flowchart of FIG.

(Step ST1 (wafer test 1))
First, a wafer test is performed to determine whether or not the SRAM cells 1 to n of the SRAM manufactured on the silicon wafer function normally. In this wafer test, an SRAM cell determined not to function normally is determined as a defective cell. In the case of this example, a case where the SRAM cell 3 at the R / D shift address <3> is determined as a defective cell in this test is taken as an example.

(Step ST2 (Redundancy 1))
Subsequently, redundancy is performed in which defective cells found during the wafer test 1 are replaced with redundant cells in the SRAM (not shown). For example, in the case of this example, the redundancy of the SRAM cell 3 of the R / D shift address <3>, which is a defective cell found in the above test, is performed.

  Therefore, as shown in FIG. 14, for example, a program operation is performed to invert the output data of the efuse <3> corresponding to the R / D shift address <3> in the fuse box 21 from “0” to “1”. . More specifically, as described in the first embodiment, the program voltage is applied to the program voltage node VBP of the e-fuse <3>, and the program voltage is applied to both ends of the first fuse element R1. The first fuse element R1 is blown. Therefore, the resistance value of the second fuse element R2 is smaller than the resistance value of the first fuse element R1 (resistance value: R2 <R1). As a result, the control circuit 13 performs programming so that the resistance value of the first fuse circuit 11 is larger than the resistance value of the second fuse circuit 12 at the time of step ST2 (1st program).

  Subsequently, in order to identify the SRAM cell 3 as a defective cell, a program (1st program) similar to the above by predetermined data inversion is performed for the 4-bit e-fuse at the address after the e-fuse <3>. For example, the same program operation is performed on the output data of eFuse <4> and eFuse <7> corresponding to R / D shift address <4> and R / D shift address <7> in fuse box 21, Inverted from “0” to “1”.

(Step ST3 (wafer test 2))
Subsequently, the same wafer test as in step ST1 is performed on the SRAM cells 1 to n of the SRAM.

(Step ST4 (assembly))
Subsequently, the SRAM after the test is separated from the silicon wafer by dicing. Subsequently, the separated SRAM is mounted on the board.

(Step ST5 (final test 1))
Subsequently, a final test is performed on whether or not the SRAM cells 1 to n of the mounted SRAM function normally. In this final test, an SRAM cell that is determined not to function normally is determined to be a defective cell. For example, in this example, it is assumed that the SRAM cell 1 at the R / D shift address <1> is determined as a defective cell in this test.

  As described above, although the wafer test is finished, defective cells are generated after mounting because some trouble occurs in the mounting process in step ST4 and a malfunction may occur. It is. For example, an operation failure due to a connection failure of a signal bonding wire or the like can be considered.

(Step ST6 (Redundancy 2))
Subsequently, redundancy of defective cells found during the final test 1 is performed. For example, in the case of this example, the redundancy of the SRAM cell 1 of the R / D shift address <1>, which is a defective cell found in the above test, is performed.

  Therefore, as shown in FIG. 15, for example, the output data of the e-fuse <3> corresponding to the R / D shift address <1> in the fuse box 21 is inverted from “0” to “1”. Do the program.

  Further, in order to identify the SRAM cell 1 as a defective cell, a program by data inversion (1st program) or a reprogram by data reinversion (2nd program) for the 4-bit efuse at the address after efuse <1>. I do. For example, a reprogram operation is performed to invert the eFuse <3> output data corresponding to the R / D shift address <3> in the fuse box 21 from “1” to “0”.

  More specifically, the program voltage is applied to the program voltage node VBP, the program voltage is applied to both ends of the second fuse element R2, and the second fuse element R2 is blown. Therefore, in this step ST6 (2nd program), the resistance value of the second fuse element R2 becomes larger again than the resistance value of the first fuse element R1 (resistance value: R2> R1). As described above, the control circuit 13 re-programs the resistance value of the second fuse circuit 12 to be larger than the resistance value of the first fuse circuit 11 at the time of step ST6.

  Thereafter, based on the result of the final test 1 (ST5), the same program or reprogram is performed on the e-fuse in the fuse box 21.

(Step ST7 (final test 2))
Subsequently, a final test is performed on whether or not the SRAM cell 1 to the SRAM cell n of the SRAM further function normally.

<Effects according to this embodiment>
According to the semiconductor integrated circuit device of this embodiment, at least the effects (1) and (2) can be obtained. Furthermore, according to this example, at least the following effect (3) can be obtained.

(3) Yield can be improved.
As described above, according to the configuration and operation according to the present example, even after the redundancy is detected once for the defective cell found in the wafer test 1 (after ST2), it is found in the final test 1. Redundancy (ST6) can be performed again on the defective cells that have been made (reprogramming can be performed on the same e-fuse 10 (the same bit)).

  For example, as shown in FIG. 15, in order to identify the SRAM cell 1 as a defective cell, e fuse <3> output data corresponding to the R / D shift address <3> of the address after e fuse <1> is used. A reprogramming operation that inverts from “1” to “0” is performed. More specifically, the program voltage is applied to the program voltage node VBP, the program voltage is applied to both ends of the second fuse element R2, and the second fuse element R2 is blown. Therefore, in this step ST6 (2nd program), the resistance value of the second fuse element R2 becomes larger again than the resistance value of the first fuse element R1 (resistance value: R2> R1). As described above, the control circuit 13 re-programs the resistance value of the second fuse circuit 12 to be larger than the resistance value of the first fuse circuit 11 at the time of step ST6.

  Here, despite the completion of the wafer test, defective cells are generated after mounting in the mounting process at step ST4, for example, due to some problem due to poor connection of signal bonding wires. This is because an operation failure may occur.

  Thus, according to this example, even when a defective cell occurs after mounting, the defective cell can be remedied, which is further advantageous in that the yield of the SRAM can be improved. .

  The present invention has been described above using the first to third embodiments. However, the present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention in the implementation stage. Is possible. Each of the above embodiments includes inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in each embodiment, at least one of the problems described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When at least one of the effects is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.

1 is a circuit diagram showing a semiconductor integrated circuit device according to a first embodiment of the present invention. FIG. 3 is a view for explaining output data of the semiconductor integrated circuit device according to the first embodiment. FIG. 3 is a view showing a read operation in an initial state of the semiconductor integrated circuit device according to the first embodiment. FIG. 6 is a diagram for explaining a first programming time of the semiconductor integrated circuit device according to the first embodiment. FIG. 6 is a diagram for explaining a second programming time of the semiconductor integrated circuit device according to the first embodiment. A circuit diagram showing a semiconductor integrated circuit device concerning a 2nd embodiment of this invention. The figure for demonstrating the output data of the semiconductor integrated circuit device which concerns on 2nd Embodiment. FIG. 10 is a view showing a read operation in an initial state of the semiconductor integrated circuit device according to the second embodiment. The figure for demonstrating the time of the 1st program of the semiconductor integrated circuit device which concerns on 2nd Embodiment. The figure for demonstrating the time of the 2nd program of the semiconductor integrated circuit device which concerns on 2nd Embodiment. A circuit diagram showing a semiconductor integrated circuit device concerning a 3rd embodiment of this invention. A circuit diagram for explaining a fuse box of a semiconductor integrated circuit device concerning a 3rd embodiment. FIG. 10 is a flowchart showing a redundancy operation of the semiconductor integrated circuit device according to the third embodiment. FIG. 10 is a circuit diagram for explaining one step (ST2) of a redundancy operation of the semiconductor integrated circuit device according to the third embodiment. The circuit diagram for demonstrating one step (ST6) of the redundancy operation | movement of the semiconductor integrated circuit device which concerns on 3rd Embodiment.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 ... e fuse, 11 ... 1st fuse circuit, 12 ... 2nd fuse circuit, 13 ... Control signal generation circuit, R1, R2 ... 1st, 2nd fuse element, N1, N2 ... 1st, 2nd writing transistor , N3, N4... First and second read transistors, 15... Sense amplifier, VBP... Voltage node for programming, 1st / PE... First control signal, 2nd / PE. , / RE (S / A): sense amplifier read control signal, Dout: output data.

Claims (5)

A first fuse circuit comprising a first fuse element and a first write transistor having one end of a current path connected to one end of the first fuse element;
A second write element connected to one end of the second fuse element; and a resistance value of the second fuse element is larger than a resistance value of the first fuse element. A second fuse circuit having a resistance value larger than that of the first fuse circuit,
Transmitting a first control signal to a control terminal of the first write transistor to program a resistance value of the first fuse circuit to be larger than a resistance value of the second fuse circuit; And a control signal generating circuit that transmits a second control signal to a control terminal of the first fuse circuit and reprograms the second fuse circuit so that a resistance value of the second fuse circuit is larger than a resistance value of the first fuse circuit. A semiconductor integrated circuit device. The first fuse circuit further includes a first read transistor in which one end of a current path is connected to one end of the first fuse element,
The second fuse circuit further includes a second read transistor having one end of a current path connected to one end of the second fuse element and a control terminal connected to a control terminal of the first read transistor,
The semiconductor integrated circuit device according to claim 1, wherein the control signal generation circuit transmits a read control signal to a control terminal of the first and second read transistors. A first fuse circuit comprising a first fuse element and a first read transistor having one end of a current path connected to one end of the first fuse element;
And a second read transistor having one end of a current path connected to one end of the second fuse element, and the on-resistance of the second read transistor is greater than the on-resistance of the first read transistor. A second fuse circuit having a resistance value larger than that of the first fuse circuit,
A first control signal is transmitted to the first fuse circuit to program a resistance value of the first fuse circuit to be larger than a resistance value of the second fuse circuit, and a second control signal is transmitted to the second fuse circuit. And a control signal generation circuit that re-programs the second fuse circuit so that the resistance value of the second fuse circuit is larger than the resistance value of the first fuse circuit. The first fuse circuit further includes a first write transistor having one end of a current path connected to one end of the first fuse element,
The second fuse circuit further includes a second write transistor having one end of a current path connected to one end of the second fuse element,
The control signal generation circuit includes:
Transmitting the first control signal to a control terminal of the first writing transistor to conduct a current path, applying a program voltage to the first fuse element, and performing the program;
The reprogramming is performed by transmitting the second control signal to a control terminal of the second writing transistor to make a current path conductive, and applying a program voltage to the second fuse element. 4. The semiconductor integrated circuit device according to 3. 5. The semiconductor integrated circuit according to claim 1, wherein the first and second fuse elements are fusing fuse elements, and are formed to include polysilicon or metal. 6. apparatus.

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