JP2009004879A - Video image circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an adverse effect caused by the operation of a charge pump circuit on a video signal even if element characteristics have variations. <P>SOLUTION: A charge pump circuit 20 starts charging of a negative voltage to an output capacitor C3 on the basis of a rise timing of an output signal S22 of a synchronous signal detection circuit 30, and finishes the charging of the negative voltage to the output capacitor C3 after a predetermined time elapses from a finish timing tb of the output signal S22. The predetermined time is determined on the basis of a time from start of constant current charging of a second time constant circuit 45 with a finish timing tb of the output signal S22 of the synchronous signal detecting circuit 30 set to 0V up to a threshold Vth3. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a video circuit including a video processing circuit and a charge pump circuit that supplies a negative voltage to the video processing circuit.

  FIG. 3 shows a configuration of a conventional video circuit that generates a negative voltage by a charge pump circuit and supplies the negative voltage to the video processing circuit. The video processing circuit 10 is a clamp circuit 11 that clamps the sync chip and pedestal level of an RGB input video signal including a synchronization signal, and performs various image processing (hue adjustment, contrast on the video signal output from the clamp circuit 11). A video signal processing circuit 12 that performs adjustment, enlargement, reduction, edge enhancement, and other processing), and an output drive circuit 13 that amplifies the output signal of the video signal processing circuit 12 to a video drive signal and supplies it to a load of, for example, 75Ω Have. The output drive circuit 13 is supplied with a positive power supply voltage + V and a negative power supply voltage −V as power supplies in order to expand the dynamic range. C1 is a capacitor for DC cut. The positive power supply voltage + V and the ground voltage GND are applied to the clamp circuit 11 and the video signal processing circuit 12.

  Reference numeral 50 denotes a free-run oscillator that generates pulses having a frequency of around 100 kHz. A charge pump circuit 20 includes a drive control circuit 21 that inputs a free-run signal S51 output from the free-run oscillator 50, and an output circuit 22 that is driven and controlled by the drive control circuit 21. The negative voltage −V is supplied to the output drive circuit 13 of the video processing circuit 10 as a negative power supply voltage.

  As shown in FIG. 4, the output circuit 22 includes a charging capacitor C2, an output capacitor C3, and switches SW1 to SW4. When the free-run signal S51 is at the L level, the switches SW1 and SW2 are turned on and the switches SW3 and SW4 are turned on. When the signal is at the H level, the switches SW1 and SW2 are turned off, and the switches SW3 and SW4 are turned on. By repeating the H level and L level of the signal S51, the capacitors C2 and C3 are charged with the charges of the polarity shown in the figure. And a negative voltage −V is generated.

  On the other hand, using the free-run oscillator 50, a synchronization signal is extracted from the input video signal, a continuous pulse is generated based on the synchronization signal, and this continuous pulse is input to the charge pump circuit to generate a negative voltage. There is an amplifier described in Patent Document 1 in which this negative voltage is supplied to a main amplifier (corresponding to the output drive circuit 13 in FIG. 3).

  FIG. 5 shows another conventional video circuit. This video circuit includes a synchronization signal detection circuit 30, a detection time constant circuit 60, and a comparison circuit 70 instead of the free-run oscillator 50 in the video circuit of FIG. The synchronization signal detection circuit 30 detects and outputs the synchronization signal S22 from the output signal of the clamp circuit 11. As shown in FIG. 6, the detection time constant circuit 60 receives the synchronization signal S22, and outputs a signal S61 that rises in synchronization with the rising edge and decreases with a predetermined time constant in synchronization with the falling edge. As shown in FIG. 6, the comparison circuit 70 outputs a signal S62 that rises in synchronization with the rise of the signal S61 and falls when the signal S61 falls below the threshold value Vth4. The output circuit 22 (FIG. 4) of the charge pump circuit 20 turns on the switches SW1 and SW2 and turns off the switches SW3 and SW4 when the signal S62 output from the comparison circuit 70 is at the L level. At the level, the switches SW1 and SW2 are turned off and the switches SW3 and SW4 are turned on.

According to the video circuit shown in FIG. 3 and the video circuit shown in FIG. 5, the negative power supply voltage −V is applied to the output drive circuit 13 of the video processing circuit 10 in addition to the positive power supply voltage + V. Expansion can be achieved. The same applies to the amplifier disclosed in Patent Document 1.
JP 2005-151468 A

  However, in the conventional video circuit shown in FIG. 3 and the amplifier described in Patent Document 1, the charge pump circuit 20 is continuously driven by a continuous signal, and the charge pump circuit 20 is operated even during the video signal period. The video signal is affected by the fluctuation of the positive voltage + V due to the switching of the switches SW1 to SW4 of the charge pump circuit 20 and the ripple component of the generated negative voltage, and a pattern such as beat noise appears in the actual video. Occurs.

  In the other conventional video circuit shown in FIG. 5, the charging end timing ta of the capacitor C3 is determined when the output signal S61 of the detection time constant circuit 60 drops to the threshold value Vth4. The voltage at the timing tb is the peak value of the signal S61, and the peak value is easily affected by variations in element characteristics. For this reason, variation occurs in the charging end timing ta of the capacitor C3. For example, when the charging end timing ta enters the video period, a defect such as a beat noise pattern appears in the actual video as described above. Occurs. In order to avoid this, if the threshold value Vth4 is set higher, the charging period becomes shorter and the charging efficiency becomes worse. In addition, when a negative voltage is generated using an equalization pulse of a video signal, there is a problem similar to the above.

  An object of the present invention is to prevent the operation of the charge pump circuit from adversely affecting the video signal even when the device characteristics vary when the negative voltage is generated using the synchronization signal or the equalization pulse. It is to provide an image circuit that is made up of.

To achieve the above object, the video circuit according to the first aspect of the present invention clamps a sync chip or pedestal of a video signal including a synchronization signal or an equalization pulse by a clamp circuit, processes the video, and outputs it as a video drive signal. A video processing circuit that performs charging, a charge pump circuit that charges an output capacitor with a negative voltage supplied to the video processing circuit, a synchronization signal detection circuit that detects a synchronization signal or equalization pulse from the output signal of the clamp circuit, and the synchronization Starting the negative voltage to the output capacitor of the charge pump circuit based on the start timing of the synchronization signal or the equalization pulse output from the signal detection circuit, the synchronization signal output from the synchronization signal detection circuit or Charge of the negative voltage to the output capacitor after a lapse of a predetermined time from the end timing of the equalization pulse And a charge pump drive circuit that terminates, and the predetermined time is set to 0 V as the end timing of the synchronization signal or the equalization pulse, from which constant current charging of the second time constant circuit is started and the third threshold value is reached. It is characterized by being determined by the time to reach.
According to a second aspect of the present invention, in the video circuit according to the first aspect, the second time constant circuit is configured so that at least a pulse width of the equalization pulse has elapsed from the start timing of the synchronization signal or the equalization pulse. It is characterized in that it is cleared by a signal output from the second signal generation circuit that is generated and disappears at the end timing of the synchronization signal or the equalization pulse.
According to a third aspect of the present invention, in the video circuit according to the first or second aspect, the start timing of charging the negative voltage to the output capacitor is set to 0 V as the start timing of the synchronization signal or the equalization pulse. The first time constant circuit is charged at a constant current and reaches a first threshold value.

  According to the present invention, since the influence of variations in element characteristics is small, the charging end timing of the capacitor by the charge pump circuit can be brought closer to the end of the pedestal period, and the charging efficiency can be increased. The equalization pulse can be charged in the same manner as in the case of the synchronization signal, so that the overall charging efficiency can be increased.

  FIG. 1 is a block diagram showing a configuration of a video circuit according to one embodiment of the present invention, and FIG. 2 is an operation waveform diagram thereof. The video processing circuit 10, the charge pump circuit 20, and the synchronization signal detection circuit 30 are the same as those described with reference to FIG. Reference numeral 40 denotes a charge pump drive circuit, which includes a noise filter 41, a first time constant circuit 42, a first signal generation circuit 43, a second signal generation circuit 44, a second time constant circuit 45, a third signal generation circuit 46, and a drive. A signal generation circuit 47 is provided.

  The noise filter 41 is a circuit that removes noise included in the output signal S22 of the synchronization signal detection circuit 30, but allows the equalization pulse to pass therethrough. That is, a signal having a shorter pulse width than the equalization pulse is blocked by the noise filter 41.

  The first time constant circuit 42 starts constant current charging from 0V with a time constant Ta in synchronization with the rising edge of the output signal S22 of the noise filter 41, and after reaching the saturation value, the signal S22 is synchronized with the falling edge. Then, an output signal S24 having a waveform that is reset (discharged at once) is output. The time constant Ta is set to a time larger than the pulse width of the equalization pulse.

  The first signal generating circuit 43 generates a signal S25 having a waveform that rises when the output signal S24 of the first time constant circuit 42 reaches the threshold value Vth1 and falls when the signal S24 is reset (discharged at once).

  The second signal generation circuit 44 generates a signal S26 having a waveform that rises when the output signal S24 of the first time constant circuit 42 reaches the threshold value Vth2 (> Vth1) and falls when the signal S24 is reset (discharged at once). To do. The threshold value Vth2 is set to a level at which time T1 has elapsed from the start of charging of the output signal S24 of the first time constant circuit 42. This time is slightly shorter than the pulse width of the equalization pulse.

  The second time constant circuit 45 is reset (discharged once) in synchronization with the rise of the output signal S26 of the second signal generation circuit 44, and the time constant Tb (> Ta) from 0 V in synchronization with the fall of the signal S26. To output a signal S27 having a waveform for starting constant current charging.

  The third signal generation circuit 46 outputs a signal S28 having a waveform that rises in synchronization with the reset (discharge at once) of the output signal S27 of the second time constant circuit 45 and falls when the signal S27 reaches the threshold value Vth3.

  The drive signal generation circuit 47 outputs a signal S29 having a waveform that rises in synchronization with the rise of the output signal S25 of the first signal generation circuit 43 and falls in synchronization with the fall of the output signal S28 of the third signal generation circuit 47. To do. The drive signal generation circuit 47 is configured to take a logical sum of the input signal S25 and the signal S28, and there is no problem even if the signals S25 and S28 partially overlap.

  When the video signal S21 is input to the video signal input terminal, the DC component of the video signal is removed by the external capacitor C1, and the sync chip and pedestal of the video signal are set to a predetermined voltage by the clamp circuit 11 of the video processing circuit 10. The image signal processing circuit 12 performs various image processing (hue adjustment, contrast adjustment, enlargement, reduction, edge enhancement, and other processing), and the output drive circuit 13 supplies a positive power supply voltage + V and a negative power supply voltage −. A video drive signal having a wide dynamic range is amplified by V and supplied to a load of 75Ω, for example.

  Here, when the output signal S22 of the synchronization signal detection circuit 30 is a horizontal synchronization signal, the signals S22 to S28 have waveforms as shown in FIG. 2, and the rise of the output signal S25 of the first signal generation circuit 43 is the drive signal. The rise timing t1 of the output signal S29 of the generation circuit 47 is determined, and the fall of the output signal S28 of the third signal generation circuit 46 determines the fall timing t2 of the output signal S29 of the drive signal generation circuit 47.

  At this time, since the output signal S28 of the third signal generation circuit 46 falls when the level of the output signal S27 of the second time constant circuit 45 reaches the threshold value Vth3, the variation in the fall timing t2 is very small. That is, the output signal S27 of the second time constant circuit 45 rises from the stable 0V (= GND) with the time constant Tb at the synchronization signal end timing tb, so that the timing t2 reaching the threshold Vth3 has high accuracy. . On the other hand, the output signal S61 of the detection time constant circuit 60 shown in FIG. 6 decreases from the unstable peak value (significantly influenced by variations in element characteristics) at the end timing tb of the synchronization signal, and the threshold value Vth4. Since the timing ta is detected by the comparison circuit 70 when the value reaches, the detection accuracy is low. Therefore, according to the present embodiment, since the influence of variations in element characteristics is small, the charging end timing t2 can be made as close as possible to the start end of the video signal in the pedestal section, and the charging period can be extended. .

  Further, when the output signal S22 of the synchronization signal detection circuit 30 is an equalization pulse in the vertical period, the pulse width is about half of the horizontal synchronization signal (time T1 or more), so the output of the first time constant circuit 42 Since the signal S24 rises at least to the threshold value Vth2, the output signal S26 of the second signal generation circuit 44 rises, and thereby the output signal S27 of the second time constant circuit 45 is also generated, so the output of the third signal generation circuit 46 A signal S28 is also generated. Therefore, the output signal S29 of the drive signal generation circuit 47 is also generated, and a negative voltage is generated by the charge pump circuit 20.

  Further, the pulse width of the output signal S22 of the synchronization signal detection circuit 30 is short (normally blocked by the noise filter 41 but not blocked), and the output signal S24 of the first time constant generation circuit 43 becomes the threshold value Vth2. When the output signal S26 of the second signal generation circuit 44 does not rise, the output signal S27 of the second time constant circuit 45 remains at the high level. Does not stand up. At this time, the pulse width of the output signal S25 of the first signal generation circuit 43 is narrowed, and the output signal S29 of the drive generation circuit 47 is output according to this pulse width.

  Further, the pulse width of the output signal S22 of the synchronization signal detection circuit 30 is short (usually blocked by the noise filter 41 but not blocked), and the output signal S24 of the first time constant generation circuit 43 becomes the threshold value Vth1. Output signal S25 from the first signal generation circuit 43 does not rise, and the output signal S26 from the second signal generation circuit 44 does not rise, so the output signal S29 from the drive signal generation circuit 47 does not rise. . The threshold value Vth1 is effective in preventing the influence of noise having a short pulse width as described above. However, the higher the level is, the later the timing t1 of the output signal S29 of the drive signal generation circuit 47 is delayed. The charging period will be shorter. Therefore, the level of the threshold value Vth1 is a trade-off with the performance of the noise filter 41.

It is a block diagram which shows the structure of the video circuit of one Example of this invention. FIG. 2 is an operation waveform diagram of the video circuit in FIG. 1. It is a block diagram which shows the structure of the conventional video circuit. It is a circuit diagram of the output circuit of a charge pump circuit. It is a block diagram which shows the structure of another conventional video circuit. FIG. 6 is an operation waveform diagram of the video circuit in FIG. 5.

Explanation of symbols

10: Video processing circuit, 11: Clamp circuit, 12: Video signal processing circuit, 13: Output drive circuit, 20: Charge pump circuit, 21: Drive control circuit, 22: Output circuit, 30: Sync signal detection circuit, 40: Charge pump drive Circuit 41: noise filter 42: first time constant circuit 43: first signal generation circuit 44: second signal generation circuit 45: second time constant circuit 46: second signal generation circuit 47: drive Signal generation circuit 50: Free-run oscillator 60: Detection time constant circuit 70: Comparison circuit

Claims (3)

A video processing circuit that clamps a sync chip or a pedestal of a video signal including a synchronization signal or an equalization pulse by a clamp circuit, performs video processing, and outputs as a video driving signal;
A charge pump circuit that charges an output capacitor with a negative voltage supplied to the video processing circuit;
A synchronization signal detection circuit for detecting a synchronization signal or an equalization pulse from the output signal of the clamp circuit;
The synchronization signal output from the synchronization signal detection circuit starts the negative voltage charging to the output capacitor of the charge pump circuit based on the start timing of the synchronization signal or the equalization pulse, and outputs from the synchronization signal detection circuit A charge pump drive circuit that terminates charging of the negative voltage to the output capacitor after elapse of a predetermined time from the end timing of the signal or the equalization pulse,
In addition, the predetermined time is determined by the time from the start of constant current charging of the second time constant circuit to the arrival of the third threshold value, with the end timing of the synchronization signal or the equalization pulse set to 0V. A video circuit characterized by The video circuit according to claim 1,
The second time constant circuit is generated after at least the pulse width of the equalization pulse has elapsed from the start timing of the synchronization signal or the equalization pulse and disappears at the end timing of the synchronization signal or the equalization pulse. A video circuit which is cleared by a signal output from a signal generation circuit. The video circuit according to claim 1 or 2,
The negative voltage charging start timing of the output capacitor is a timing at which the start timing of the synchronization signal or the equalization pulse is set to 0 V, and then the first time constant circuit is constant-current charged to reach the first threshold value. A video circuit characterized by that.

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