JP5739850B2 - Switching power supply - Google Patents

Description

  The present invention relates to a switching power supply apparatus that performs pulse width control by comparing an error amplification voltage and a ramp wave voltage.

  Conventionally, for example, as shown in FIG. 10, there has been a switching power supply device 10 that performs pulse width control of an input voltage feedforward system. The switching power supply device 10 includes a converter circuit 14 that intermittently switches the input voltage Vi when the main switching element 12 is turned on, converts the input voltage Vi into a DC output voltage Vo, and outputs the converted voltage. Here, it is a single-ended forward type converter circuit, and the rectifying element on the secondary side of the main transformer is formed of a diode. In addition, a switching control circuit 16 that controls on / off of the main switching element 12 is provided so that the output voltage Vo approaches a predetermined voltage.

  The switching control circuit 16 includes an error amplification circuit 18, a ramp wave generation circuit 20, and a PWM comparator 22. The error amplification circuit 18 is, for example, an analog inverting amplification circuit, and amplifies the difference between the output voltage signal Vo1 output from the output voltage detection circuit 18a and a predetermined reference voltage Vref, and outputs an error amplification voltage Ver.

  The ramp wave generation circuit 20 includes a series circuit of an integration resistor 24 and an integration capacitor 26 to which a DC input voltage Vi is input, and further includes an integration circuit in which a bias resistor 28 is inserted in series with the integration capacitor 26. In addition, the switching element 30 is an N-channel MOS type FET that is connected so that both ends of the integrating capacitor 26 can be short-circuited, and a switch driving circuit 32 that outputs a reset pulse Vre for driving the switching element 30. The reset pulse Vre is at a high level for a short time with a constant period tsw, and the switch element 30 can be turned on only during the high level period. The ramp wave generation circuit 20 outputs a ramp wave voltage Vram from both ends of the series circuit of the integrating capacitor 26 and the bias resistor 28. The ramp voltage Vram is a waveform obtained by adding a direct current voltage substantially proportional to the input voltage Vi to a sawtooth waveform that rises with a gentle slope and instantaneously decreases. The slope at which the ramp wave voltage Vram rises varies depending on the input voltage Vi.

  The PWM comparator 22 is a so-called comparator element, and has a non-inverting input terminal to which the error amplification voltage Ver is input and an inverting input terminal to which the ramp wave voltage Vram is input, and compares the voltages of the input terminals. To perform pulse width modulation. Then, a main drive pulse Vg is output in which the voltage at the non-inverting input terminal is at a high level during a period higher than the voltage at the inverting input terminal and is at a low level during other periods, thereby driving the main switching element 12. The main switching element 12 is turned on when the main drive pulse Vg is at a high level and turned off when it is at a low level.

  The switching power supply device 10 is similar in configuration to the switching power supply device disclosed in Patent Document 1. The switching power supply device of Patent Document 1 differs from the switching power supply device 10 in that the configuration of the converter circuit is different in that a synchronous rectifier circuit is provided on the secondary side of the main transformer, but the configuration of the switching control circuit is the same. is there.

  The conventional switching power supply device 10 and the switching power supply device disclosed in Patent Document 1 increase the stability of the output voltage Vo against a sudden change in the input voltage Vi by adjusting the value of the bias resistance of the ramp wave generation circuit 20 described above. There is an advantage that you can.

JP 2008-131721 A

  In the case of the conventional switching power supply device 10, for example, when the output current supplied to the load 34 is small, the time ratio of turning on the main switching element 12 (hereinafter referred to as the “on-time ratio”) is made extremely small. The voltage Vo is controlled to be constant. However, the switching control circuit 16 has a problem that it is difficult to stabilize the on-time ratio in a small state due to the influence of the operation delay of the PWM comparator 22. Hereinafter, an operation when the switching power supply device 10 is controlled to have a small ON-time ratio will be described with reference to FIG.

  The periods α and β in FIG. 11 are each a switching cycle, and the lengths of the periods α and β are a fixed time tsw. In addition, the error amplification voltage Ver gradually increases with time, and the period β is slightly higher than the period α.

  The period β starts when the switch drive circuit 32 outputs a high-level reset pulse Vre and the switch element 30 is turned on. When the switch element 30 is turned on, the voltage of the integrating capacitor 26 is instantaneously discharged, and the ramp wave voltage Vram is lowered to a DC voltage generated in the bias resistor 28, and becomes lower than the error amplification voltage Ver. Then, the PWM comparator 22 inverts the main drive pulse Vg to a high level at the timing when the time t1 has elapsed since the ramp wave voltage Vram crossed the error amplification voltage Ver. Hereinafter, this time t1 is referred to as a first delay time t1.

  Thereafter, the reset pulse Vre is inverted to a low level, the switch element 30 is turned off, the ramp wave voltage Vram starts to rise, rises with a predetermined gentle slope, and crosses the error amplification voltage Ver. The PWM comparator 22 inverts the main drive pulse Vg to the low level at the timing when the time t2 has elapsed since the ramp wave voltage Vram crossed the error amplification voltage Ver. Hereinafter, this time t2 is referred to as a second delay time t2.

  Here, the first and second delay times t1 and t2 become a problem. The PWM comparator 22 is a general comparator element. As shown in FIG. 12, when the overdrive voltage ΔV (the difference between the voltages Vx and Vy input to each input terminal) is smaller than a predetermined voltage value Vk, The delay time t1 has a very long characteristic. That is, when the overdrive voltage ΔV is smaller than the voltage value Vk, the first delay time t1 becomes a very long time such as ta. On the other hand, if the overdrive voltage ΔV is larger than the voltage value Vk, the first delay time t1 is as short as tb, and an operation close to ideal is performed. In addition, the relationship between the second delay time t2 and the overdrive voltage is almost the same as that in FIG.

  Returning to the period β in FIG. 11, looking at the operation in which the main drive pulse Vg is inverted to a high level, the voltage Vram (ramp wave voltage Vram) of the inverting input terminal of the PWM comparator 22 is the voltage Ver ( Since the voltage difference (overdrive voltage ΔV) of each input terminal is smaller than the voltage value Vk for a while after crossing the error amplification voltage Ver), the first delay time t1 is very long. ta.

  As for the operation in which the main drive pulse Vg is inverted to a low level, the ramp wave voltage Vram continuously rises after the voltage Vram at the inverting input terminal of the PWM comparator 22 crosses the voltage Ver at the non-inverting input terminal. To do. Then, the voltage difference (overdrive voltage ΔV) between the input terminals quickly increases and exceeds the voltage value Vk, and the second delay time t2 becomes a short time tb. As described above, since the first delay time t1 becomes very long in period β, ideal pulse width modulation cannot be performed, and the time ta has a property of being easily fluctuated, so that the control becomes unstable. Become.

  The period α is more severe than the period β. In the period α, since the difference between the ramp wave voltage Vram and the error amplification voltage Ver is smaller than the period β, the first delay time t1 becomes longer than the above time ta, and as a result, the main drive pulse Vg has no missing pulse. It has occurred. As described above, the conventional switching power supply 10 has a problem that control tends to become unstable when the main switching element 12 is operated at a small on-time ratio.

  The problem of the delay time of the PWM comparator 22 may occur even when the on-time ratio is large. For example, if the error amplification voltage Ver rises to the right, and the difference between the slope of the rise and the slope of the ramp wave voltage Vram rises at a small timing, it becomes equivalent to the overdrive voltage ΔV being small. The second delay period t2 becomes very long, causing a problem that the control becomes unstable. This is a problem that may occur even in the switching power supply device of Patent Document 1.

  The present invention has been made in view of the above-described background art, and can perform ideal pulse width modulation while minimizing the influence of delay of the PWM comparator and stably control on / off of the main switching element. It aims at providing a switching power supply device.

According to the present invention, an input voltage is intermittently switched by turning on and off the main switching element, converted to a DC output voltage and output, and on / off of the main switching element is controlled so that the output voltage approaches a predetermined voltage. A switching power supply device comprising a switching control circuit,
The switching control circuit amplifies a difference between an output voltage signal obtained by detecting the output voltage and a predetermined reference voltage, and outputs an error amplification voltage, and a ramp voltage that rises and falls in a sawtooth manner. An output ramp wave generation circuit; a PWM auxiliary circuit that generates a pulsed drive voltage and superimposes the drive voltage on the error amplification voltage; and the error amplification voltage and the ramp wave voltage on which the drive voltage is superimposed. A PWM comparator that has a pair of input terminals that are respectively input, compares the voltage of each input terminal to perform pulse width modulation, and outputs a rectangular main drive pulse that drives the main switching element;
The switching power supply device in which the voltage relationship between the pair of input terminals is instantaneously reversed by the drive voltage at the timing when the difference in voltage between the pair of input terminals of the PWM comparator becomes small.

  The PWM auxiliary circuit may be a circuit that stops the operation of superimposing the drive voltage on the error amplification voltage when the difference in the slope of the voltage between the pair of input terminals is larger than a certain value. The ramp wave generating circuit is composed of a series circuit of an integrating resistor and an integrating capacitor to which a DC voltage is input, and an integrating circuit that outputs the ramp wave voltage from both ends of the integrating capacitor and both ends of the integrating capacitor are short-circuited. A switch element connected in a releasable manner, and a switch driving circuit that outputs a short width reset pulse for driving the switch element at a constant period and turns on the switch element for the short width period, and the PWM auxiliary circuit The circuit includes a voltage dividing circuit that divides the reset pulse or an inversion pulse obtained by inverting the reset pulse by a series circuit of a plurality of resistors or capacitors, and outputs the drive voltage from a middle point thereof, The drive voltage is superimposed on the error amplification voltage by connecting the output terminal of the circuit to the output terminal of the error amplification circuit. It may be a circuit.

According to the present invention, an input voltage is intermittently switched by turning on and off the main switching element, converted to a DC output voltage and output, and on / off of the main switching element is controlled so that the output voltage approaches a predetermined voltage. A switching power supply device comprising a switching control circuit,
The switching control circuit amplifies a difference between an output voltage signal obtained by detecting the output voltage and a predetermined reference voltage, and outputs an error amplification voltage, and a ramp voltage that rises and falls in a sawtooth manner. An output ramp wave generation circuit; a PWM auxiliary circuit that generates a pulsed drive voltage and superimposes the drive voltage on the ramp wave voltage; and the ramp wave voltage and the error amplification voltage on which the drive voltage is superimposed. A PWM comparator that has a pair of input terminals that are respectively input, compares the voltages of the pair of input terminals, performs pulse width modulation, and outputs a rectangular main drive pulse for driving the main switching element And
At the timing when the voltage difference between the pair of input terminals of the PWM comparator becomes small, the voltage relationship between the pair of input terminals is instantaneously reversed by the drive voltage.

  The PWM auxiliary circuit may be a circuit that stops the operation of superimposing the drive voltage on the ramp wave voltage when the difference in the slope of the voltage between the pair of input terminals is larger than a certain value. The ramp wave generating circuit is composed of a series circuit of an integrating resistor and an integrating capacitor to which a DC voltage is input, and an integrating circuit that outputs the ramp wave voltage from both ends of the integrating capacitor and both ends of the integrating capacitor are short-circuited. A switch element connected in a releasable manner, and a switch driving circuit that outputs a short width reset pulse for driving the switch element at a constant period and turns on the switch element for the short width period, and the PWM auxiliary circuit The circuit includes a voltage dividing circuit that divides the reset pulse or an inversion pulse obtained by inverting the reset pulse by a series circuit of a plurality of resistors or capacitors, and outputs the drive voltage from a middle point thereof, The drive voltage is superimposed on the ramp wave voltage by connecting the output end of the circuit to the output end of the ramp wave generating circuit. It may be a circuit that.

  The integrating circuit of the ramp wave generating circuit receives a DC voltage proportional to an input voltage, and a bias resistor is inserted in a position in series with the integrating capacitor, and both ends of the series circuit of the integrating capacitor and the bias resistor. To output the ramp voltage. Alternatively, the integration circuit of the ramp wave generation circuit receives a stable DC voltage, a bias resistor is inserted in a position in series with the integration capacitor, and the ramp from both ends of the series circuit of the integration capacitor and the bias resistor. Output wave voltage.

  This switching power supply device compares the voltage level of each input terminal with the switching cycle by the drive voltage output from the PWM auxiliary circuit at the timing when the voltage difference between the input terminals of the PWM comparator becomes small. A sufficient overdrive voltage can be quickly ensured when the voltages at the respective input terminals cross each other in an instant, which is a sufficiently short period. Therefore, the first and second delay times t1 and t2 described in the background art can be kept short, ideal pulse width modulation can be performed regardless of the on-time ratio, and the on / off operation of the main switching element can be stabilized. Can be controlled.

1 is a circuit diagram showing a first embodiment of a switching power supply device of the present invention. It is a time chart which shows operation | movement of the switching power supply device of 1st embodiment. It is a circuit diagram which shows 2nd embodiment of the switching power supply device of this invention. It is a time chart which shows operation | movement of the switching power supply device of 2nd embodiment. It is a circuit diagram which shows 3rd embodiment of the switching power supply device of this invention. It is a time chart which shows operation | movement of the switching power supply device of 3rd embodiment. It is a circuit diagram which shows 4th embodiment of the switching power supply device of this invention. It is a circuit diagram which shows the internal structure of the PWM auxiliary circuit of FIG. It is a time chart which shows operation | movement of the switching power supply device of 4th embodiment. It is a circuit diagram which shows the conventional switching power supply device. It is a time chart which shows operation | movement of the conventional switching power supply device. It is the graph (a) which measured the relationship between the delay time of a PWM comparator, and an overdrive voltage, a measurement circuit (b), and the waveform (c) at the time of a measurement.

  Hereinafter, a first embodiment of the switching power supply device of the present invention will be described with reference to FIGS. Here, the same components as those of the conventional switching power supply device 10 are described with the same reference numerals. As shown in FIG. 1, the switching power supply device 36 of the first embodiment includes a converter circuit 14 that intermittently inputs an input voltage Vi when the main switching element 12 is turned on and off, converts the input voltage Vi into a DC output voltage Vo, and outputs the output voltage Vo. . Here, a single-ended forward type converter circuit is illustrated, but a flyback type, bridge type, chopper type, or other type of converter circuit may be used.

  In addition, a switching control circuit 38 that controls on / off of the main switching element 12 so that the output voltage Vo approaches a predetermined voltage is provided. The switching control circuit 38 includes an error amplification circuit 40, a ramp wave generation circuit 42, and a PWM auxiliary circuit 44. , And the same PWM comparator 22 as described above.

  The error amplifier circuit 40 is, for example, an analog inverting amplifier circuit, and amplifies the difference between the output voltage signal Vo1 output from the output voltage detection circuit 18a and a predetermined reference voltage Vref, and the error is transmitted through the signal insulating photocoupler 40a. Outputs amplified voltage Ver. Here, the responsiveness of the error amplification circuit 40 is limited to a relatively low frequency band, and the gradient at which the error amplification voltage Ver changes is very slow.

  The ramp wave generation circuit 42 includes a series circuit of an integration resistor 24 and an integration capacitor 26 to which a stable DC voltage is input from a DC power supply 42a, and further includes an integration circuit in which a bias resistor 28 is inserted in series with the integration capacitor 26. ing. In addition, the switching element 30 is an N-channel MOS type FET that is connected so that both ends of the integrating capacitor 26 can be short-circuited, and a switch driving circuit 32 that outputs a reset pulse Vre for driving the switching element 30. The reset pulse Vre becomes high level for a short time with a constant period tsw, and the switch element 30 can be turned on only during a high level period. The ramp wave generation circuit 42 outputs the ramp wave voltage Vram from both ends of the series circuit of the integrating capacitor 26 and the bias resistor 28. The ramp wave voltage Vram is a waveform obtained by adding a constant DC voltage to a sawtooth waveform that rises with a gentle slope and instantaneously drops. The ramp wave generation circuit 42 differs from the ramp wave generation circuit 20 in that the ramp wave voltage Vram rises with a constant slope regardless of the input voltage Vi, and feedforward control based on the input voltage Vi. Do not do.

  The PWM comparator 22 is a so-called comparator element, and has a non-inverting input terminal to which the error amplification voltage Ver superimposed with the drive voltage Vdr is input and an inverting input terminal to which the ramp wave voltage Vram is input. Are compared to perform pulse width modulation. Then, a main drive pulse Vg that is at a high level when the voltage at the inverting input terminal is higher than the voltage at the inverting input terminal and is at a low level during other periods is output to drive the main switching element 12. The main switching element 12 is turned on when the main drive pulse Vg is at a high level and turned off when it is at a low level.

  The PWM auxiliary circuit 44 is a voltage dividing circuit that divides the reset pulse Vre output from the switch driving circuit 32 by a series circuit of capacitors 44a and 44b and outputs a drive voltage Vdr from both ends of the ground side capacitor 44b. In this voltage dividing circuit, the voltage dividing ratio is set so that the amplitude of the drive voltage Vdr is larger than the voltage value Vk of the PWM comparator 22 described in FIG. Then, the middle point of the voltage dividing circuit is connected to the output terminal of the error amplification circuit 40, and an operation of superimposing the drive voltage Vdr on the error amplification voltage Ver is performed. The capacitor 44b can also be used as a soft-start capacitor that gradually increases the on-time ratio at the start-up when the input voltage Vi is applied.

  Next, the operation when the switching power supply device 36 is controlled to have a small on-time ratio will be described with reference to FIG. The periods α and β in FIG. 2 are each one switching cycle, and the lengths of the periods α and β are a fixed time tsw. Further, the error amplification voltage Ver is constant over the periods α and β, which is the same as the error amplification voltage Ver in the period α of FIG.

  The period β starts when the switch drive circuit 32 outputs a high-level reset pulse Vre and the switch element 30 is turned on. When the switch element 30 is turned on, the voltage of the integrating capacitor 26 is instantaneously discharged, and the voltage Vram (ramp wave voltage Vram) at the inverting input terminal of the PWM comparator 22 is reduced to a DC voltage generated in the bias resistor 28, thereby amplifying the error. It becomes lower than the voltage Ver. Further, almost simultaneously with the decrease of the voltage Vram at the inverting input terminal, the drive voltage Vdr output from the PWM auxiliary circuit 44 is inverted to a high level, and the voltage at the non-inverting input terminal rises sharply from Ver to (Vdr + Ver). . Then, the PWM comparator 22 inverts the main drive pulse Vg to a high level at the timing when the first delay time t1 has elapsed since the voltage at the inverting input terminal crossed the voltage Ver at the non-inverting input terminal.

  Thereafter, at the timing when the reset pulse Vre is inverted to the low level, the switch element 30 is turned off, the integration capacitor 26 is charged via the integration resistor 24, and the voltage Vram of the inverting input terminal starts to rise with a gentle slope. Further, the drive voltage Vdr output from the PWM auxiliary circuit 44 is inverted to a low level, and the voltage at the non-inverting input terminal is instantaneously lowered to Ver.

  The PWM comparator 22 inverts the main drive pulse Vg to a low level at the timing when the second delay time t2 has elapsed after the voltage Vram at the inverting input terminal rises and crosses the voltage Ver at the non-inverting input terminal.

  Here, the first and second delay times t1 and t2 will be described. First, looking at the operation in which the main drive pulse Vg is inverted to a high level, as shown in FIG. 2, the voltage Vram of the inverting input terminal of the PWM comparator 22 sharply decreases and crosses the voltage Ver of the non-inverting input terminal. At almost the same time, the voltage at the non-inverting input terminal increases to (Vdr + Ver). That is, the drive voltage Vdr of the PWM auxiliary circuit 44 is inverted to a high level at a timing when the voltage difference between the input terminals becomes sufficiently small as compared with the maximum value of the ramp voltage Vram. The voltage relationship between the input terminals is instantaneously reversed, which is a sufficiently short period compared to the switching period. Since the voltage difference (overdrive voltage) between the input terminals is larger than the voltage value Vk, the first delay time t1 is a short time tb.

  Further, regarding the operation in which the main drive pulse Vg is inverted to the low level, the ramp wave voltage Vram continues to rise after the voltage Vram of the inverting input terminal of the PWM comparator 22 crosses the voltage Ver of the non-inverting input terminal. . Then, the voltage difference (overdrive voltage) between the input terminals quickly increases and exceeds the voltage value Vk, and the second delay time t2 becomes a short time tb. Thus, since both the first and second delay times t1 and t2 are short times tb, ideal pulse width modulation can be controlled stably.

  Here, the function of the bias resistor 28 will be described. Depending on the type of comparator element used, the PWM comparator 22 may have long and unstable first and second delay times t1 and t2 when the two input voltages are close to zero volts. Therefore, the switching power supply device 36 avoids the problem by providing a bias resistor 28 in the ramp wave generation circuit 42 and superimposing a constant DC voltage on the ramp wave voltage Vram.

  As described above, the switching power supply device 36 has the PWM auxiliary timing at the timing when the voltage difference between the input terminals of the PWM comparator 22 becomes relatively small compared to the maximum value of the ramp wave voltage Vram. By superimposing the drive voltage Vdr of the circuit 44 on the error amplification voltage Ver, the level relationship of the voltage at each input terminal is reversed in an instant sufficiently shorter than the switching period, and after the voltages cross each other, sufficient The overdrive voltage can be secured quickly. Therefore, the first and second delay times t1 and t2 can be kept short, ideal pulse width modulation can be performed even when the on-time ratio is very small, and the on / off of the main switching element 12 can be stably controlled. Can do.

  In addition, since the ramp wave generation circuit 42 and the PWM auxiliary circuit 44 have a simple configuration with a small number of parts, they do not take a mounting space and have a low cost burden. In particular, in the case of the switching power supply device 36, the response of the error amplifier circuit 40 is limited to a relatively low frequency band, and the gradient of the ramp voltage Vram is substantially low because the gradient at which the error amplification voltage Ver changes is very slow. It is known that the difference between the slope of the error amplification voltage Ver and the slope of the ramp wave voltage Vram is large during a period other than a short time when the reset pulse Vre is at a high level and the switch element 30 is turned on. . Therefore, in the switching power supply 36, the predetermined drive voltage Vdr has only to be generated within a short time when the difference in slope is small, so that the delay time of the PWM comparator 22 can be reduced by a very simple PWM auxiliary circuit 44. The problem has been solved.

  Next, a second embodiment of the switching power supply device of the present invention will be described with reference to FIGS. Here, the same configurations as those of the switching power supply device 36 of the first embodiment are denoted by the same reference numerals and description thereof is omitted. As shown in FIG. 3, the switching power supply 46 according to the second embodiment includes a converter circuit 14 that intermittently converts the input voltage Vi by turning on and off the main switching element 12, converts the input voltage Vi into a DC output voltage Vo, and outputs the output voltage Vo. And a switching control circuit 38 that controls on / off of the main switching element 12 so that Vo approaches a predetermined voltage.

  The switching control circuit 38 includes an error amplification circuit 40, a ramp wave generation circuit 42 and a PWM comparator 22 similar to those described above, and a PWM auxiliary circuit 48 having a novel configuration.

  The PWM auxiliary circuit 48 inverts the reset pulse Vre output from the switch drive circuit 32 through the inverter 50, divides the inverted pulse by the series circuit of the resistors 48a and 48b, and drives the drive voltage Vdr from both ends of the ground-side resistor 48b. Is a voltage dividing circuit that outputs. In this voltage dividing circuit, the voltage dividing ratio is set so that the amplitude of the drive voltage Vdr is larger than the voltage value Vk of the PWM comparator 22 described in FIG. Then, the middle point of the voltage dividing circuit is connected to the output terminal of the ramp wave generating circuit 42, and the drive voltage Vdr is superimposed on the ramp wave voltage Vram.

  Next, an operation when the switching power supply device 46 is controlled to have a small on-time ratio will be described with reference to FIG. Here, the periods α and β in FIG. 4 are each one cycle of switching, and the lengths of the periods α and β are a fixed time tsw. Further, the error amplification voltage Ver is constant over the periods α and β, which is the same as the error amplification voltage Ver in the period α of FIG.

  The period β starts when the switch drive circuit 32 outputs a high-level reset pulse Vre and the switch element 30 is turned on. When the switch element 30 is turned on, the voltage of the integrating capacitor 26 is instantaneously discharged, and the voltage (Vdr + Vram) at the inverting input terminal is sharply reduced to be lower than the error amplification voltage Ver. Further, almost simultaneously with the decrease of the ramp wave voltage Vram, the drive voltage Vdr output from the PWM auxiliary circuit 48 is inverted to a low level. As a result, the voltage at the inverting input terminal becomes Vram, which is a DC voltage generated in the bias resistor 28. Then, the PWM comparator 22 inverts the main drive pulse Vg to a high level at the timing when the first delay time t1 has elapsed since the voltage at the inverting input terminal crossed the voltage Ver at the non-inverting input terminal.

  Thereafter, the drive voltage Vdr output from the PWM auxiliary circuit 48 is inverted to high level at the timing when the reset pulse Vre is inverted to low level. Further, the switch element 30 is turned off, the integration capacitor 26 is charged via the integration resistor 24, and the ramp wave voltage Vram starts to rise with a gentle slope. Therefore, the voltage at the inverting input terminal of the PWM comparator 22 increases from Vram to (Vdr + Vram) instantaneously sufficiently short compared with the switching period, and then increases with a gentle slope.

  The PWM comparator 22 inverts the main drive pulse Vg to a low level at the timing when the second delay time t2 has elapsed after the voltage (Vdr + Vram) at the inverting input terminal rises and crosses the voltage Ver at the non-inverting input terminal.

  Here, the first and second delay times t1 and t2 will be described. First, looking at the operation in which the main drive pulse Vg is inverted to a high level, as shown in FIG. 4, the operation in which the integrating capacitor 26 is discharged by the switch element 30 and the operation in which the drive voltage Vdr is inverted to a low level The voltage at the non-inverting input terminal of the PWM comparator 22 decreases to Vram almost simultaneously with the voltage Ver across the non-inverting input terminal. That is, the drive voltage Vdr of the PWM auxiliary circuit 48 is inverted to a low level at a timing when the voltage difference between the input terminals becomes relatively small compared to the maximum value of the ramp voltage Vram. The voltage relationship of each input terminal reverses instantaneously sufficiently shorter than the switching period. Since the voltage difference (overdrive voltage) between the input terminals is larger than the voltage value Vk, the first delay time t1 is a short time tb.

  Further, regarding the operation in which the main drive pulse Vg is inverted to a low level, the ramp wave voltage Vram increases after the voltage (Vdr + Vram) of the inverting input terminal of the PWM comparator 22 crosses the voltage Ver of the non-inverting input terminal. continue. Then, the voltage difference (overdrive voltage) between the input terminals quickly increases and exceeds the voltage value Vk, and the second delay time t2 becomes a short time tb.

  The operation during the period α is the same as the operation during the period β. Thus, since both the first and second delay times t1 and t2 are short times tb, ideal pulse width modulation can be controlled stably.

  As described above, the switching power supply 46 is configured so that the voltage difference between the input terminals of the PWM comparator 22 is relatively low compared to the maximum value of the ramp wave voltage Vram. By superimposing the drive voltage Vdr output from the circuit 48 on the ramp wave voltage Vram, the level relationship of the voltages at each input terminal reverses instantaneously sufficiently short compared to the switching period, and after the voltage crosses, A sufficient overdrive voltage can be secured quickly. Accordingly, like the switching power supply 36 described above, the first and second delay times t1 and t2 are kept short, and ideal pulse width modulation can be performed even when the on-time ratio is very small. The on / off operation of the element 12 can be stably controlled.

  Next, a third embodiment of the switching power supply device of the present invention will be described with reference to FIGS. Here, the same configurations as those of the switching power supply devices 36 and 46 of the first and second embodiments are denoted by the same reference numerals, and description thereof is omitted. As shown in FIG. 5, the switching power supply 52 of the third embodiment includes a converter circuit 14 that intermittently converts the input voltage Vi by turning on and off the main switching element 12, converts the input voltage Vi to a DC output voltage Vo, and outputs the output voltage Vo. And a switching control circuit 38 that controls on / off of the main switching element 12 so that Vo approaches a predetermined voltage.

  The switching control circuit 38 includes an error amplification circuit 40, a ramp wave generation circuit 42, a PWM comparator 22 similar to the above, and a PWM auxiliary circuit 54 having a new configuration.

  The PWM auxiliary circuit 54 detects the error amplification voltage Ver and the ramp wave voltage Vram, and outputs a predetermined drive voltage Vdr when the difference between the respective voltage values is small and the difference between the slopes at which each voltage changes is small. It is a circuit block. The output terminal of the PWM auxiliary circuit 54 is connected to the output terminal of the error amplifier circuit 40, and the drive voltage Vdr is superimposed on the error amplification voltage Ver. The drive voltage Vdr is set to have an amplitude larger than the voltage value Vk of the PWM comparator 22, and the subsequent operation will be described in detail in the description.

  Here, the error amplification circuit 40 is set to a constant value so that it can respond to a relatively high frequency. For example, when the input voltage Vi changes suddenly, the difference between the slope of the error amplification voltage Ver and the slope of the ramp wave voltage Vram. Is considered to be small.

  Next, the operation of the switching power supply device 52 will be described with reference to FIG. Here, the periods α and β in FIG. 2 are each one cycle of switching, and the lengths of the periods α and β are a constant time tsw. Further, the period α is controlled to have a small ON-time ratio, similarly to the period α in FIG. On the other hand, during the period β, the error amplification voltage Ver rises with a predetermined slope in order to increase the on-time ratio because the input voltage Vi is changed in the decreasing direction.

  The period α starts when the switch drive circuit 32 outputs a high level reset pulse Vre and the switch element 30 is turned on. When the switch element 30 is turned on, the voltage of the integrating capacitor 26 is instantaneously discharged, and the ramp wave voltage Vram rapidly decreases to a certain DC voltage generated in the bias resistor 28 and becomes lower than the error amplification voltage Ver. The PWM auxiliary circuit 54 detects that the ramp voltage Vram has crossed the error amplification voltage Ver and that the difference in slope immediately after that is small, switches the drive voltage Vdr to a positive voltage, and non-inverts the PWM comparator 22. The voltage at the input terminal rises from Ver to (Vdr + Ver) in an instant that is sufficiently short compared to the switching period. Then, the PWM comparator 22 inverts the main drive pulse Vg to the high level at the timing when the first delay time t1 has elapsed after the voltage Vram of the inverting input terminal crosses the voltage (Vdr + Ver) of the non-inverting input terminal. Thereafter, the PWM auxiliary circuit 54 quickly switches the drive voltage Vdr to zero.

  Thereafter, at the timing when the reset pulse Vre is inverted to the low level, the switch element 30 is turned off, the integration capacitor 26 is charged via the integration resistor 24, and the ramp voltage Vram starts to rise with a gentle slope. Further, the drive voltage Vdr output from the PWM auxiliary circuit 54 is inverted to a low level, and the voltage at the non-inverting input terminal of the PWM comparator 22 is instantaneously reduced to Ver.

  At the timing when the second delay time t2 has elapsed after the ramp wave voltage Vram rises and the voltage Vram at the inverting input terminal crosses the voltage Ver at the non-inverting input terminal, the PWM comparator 22 sets the main drive pulse Vg to the low level. Invert. Thereafter, in order to increase the ON ratio of the next period β, the error amplification voltage Ver gradually increases.

  Accordingly, the period α is substantially the same as the operation of the switching power supply device 36 shown in FIG. 2, and both the first and second delay times t1 and t2 become the short time tb as in the switching power supply device 36.

  The period β starts when the switch drive circuit 32 outputs a reset pulse Vre that is inverted to a high level and the switch element 30 is turned on. When the switch element 30 is turned on, the voltage of the integrating capacitor 26 is instantaneously discharged, and the ramp wave voltage Vram is instantaneously lowered to a certain DC voltage generated in the bias resistor 28 and becomes lower than the error amplification voltage Ver. At this time, the PWM auxiliary circuit 54 detects that the ramp voltage Vram and the error amplification voltage Ver have crossed, but the drive voltage Vdr maintains zero because the difference in slope immediately after crossing is large. Then, the PWM comparator 22 inverts the main drive pulse Vg to the high level at the timing when the first delay time t1 has elapsed after the voltage Vram of the inverting input terminal crosses the voltage Ver of the non-inverting input terminal.

  Thereafter, at the timing when the reset pulse Vre is inverted to the low level, the switch element 30 is turned off, the integration capacitor 26 is charged via the integration resistor 24, and the ramp wave voltage Vram rises. When the ramp wave voltage Vram crosses the error amplification voltage Ver, the PWM auxiliary circuit 54 has a small difference between the ramp voltage Vram and the error amplification voltage Ver and the slope of each voltage immediately after that. Is detected, the drive voltage Vdr is switched to a negative voltage, and the voltage at the non-inverting input terminal of the PWM comparator 22 instantaneously decreases from Ver to (Vdr + Ver). Then, the PWM comparator 22 inverts the main drive pulse Vg to the low level at the timing when the second delay time t2 has elapsed after the voltage Vram of the inverting input terminal crosses the voltage Ver of the non-inverting input terminal. Thereafter, the PWM auxiliary circuit 54 quickly switches the drive voltage Vdr to zero.

  Here, the first and second delay times t1 and t2 in the period β will be described. First, looking at the operation in which the main drive pulse Vg is inverted to a high level, as shown in FIG. 6, the voltage Vram of the inverting input terminal of the PWM comparator 22 sharply decreases and crosses the voltage Ver of the non-inverting input terminal. After that, the error amplification voltage Ver continues to rise. Then, the voltage difference (overdrive voltage) between the input terminals quickly increases and exceeds the voltage value Vk, and the first delay time t1 becomes a short time tb.

  Further, regarding the operation in which the main drive pulse Vg is inverted to the low level, the voltage at the non-inverting input terminal of the PWM comparator 22 is almost the same as the voltage Vram at the inverting input terminal crosses the voltage Ver at the non-inverting input terminal. Decreases to (Vdr + Ver). That is, the drive voltage Vdr of the PWM auxiliary circuit 54 is switched to a negative voltage at a timing when the voltage difference between the input terminals becomes relatively small compared to the maximum value of the ramp wave voltage Vram. The voltage relationship between the input terminals is reversed instantaneously, which is sufficiently shorter than the switching period. Since the voltage difference (overdrive voltage) between the input terminals is larger than the voltage value Vk, the second delay time t2 is a short time tb.

  As described above, the switching power supply 52 also has the PWM auxiliary timing at the timing when the voltage difference between the input terminals of the PWM comparator 22 becomes sufficiently smaller than the maximum value of the ramp wave voltage Vram. By superimposing the drive voltage Vdr output from the circuit 54 on the error amplification voltage Ver, the level relationship of the voltage at each input terminal reverses instantaneously sufficiently short compared to the switching period, and after the voltage crosses, A sufficient overdrive voltage can be secured quickly. Therefore, both the period α with a small on-time ratio and the period β with a large on-time ratio have both the first and second delay times t1, t2 being a short time tb, and ideal pulse width modulation can be controlled. it can.

  Next, 4th embodiment of the switching power supply device of this invention is described based on FIGS. Here, the same configurations as those of the switching power supply devices 36, 46, 52 of the above embodiment are denoted by the same reference numerals, and the description thereof is omitted. As shown in FIG. 7, the switching power supply device 56 of the fourth embodiment includes a converter circuit 14 that intermittently converts the input voltage Vi by turning on and off the main switching element 12, converts the output voltage into a DC output voltage Vo, and outputs the output voltage Vo. And a switching control circuit 38 that controls on / off of the main switching element 12 so that Vo approaches a predetermined voltage.

  The switching control circuit 38 includes an error amplification circuit 40, a ramp wave generation circuit 42, a PWM comparator 22 similar to the above, and a PWM auxiliary circuit 58 having a new configuration.

  The PWM auxiliary circuit 58 is a circuit block that detects the voltage of each input terminal of the PWM comparator 22 and outputs a predetermined drive voltage Vdr when the difference between the respective voltage values becomes small. As shown in FIG. 8, the internal configuration of the PWM auxiliary circuit 58 includes NPN-type first and second transistors 60a and 60b in which the emitters are connected to each other. A first collector resistor 64a is provided between the DC power source 62 and the collector of the first transistor 60a, and a second collector resistor 64b is provided between the DC power source 62 and the collector of the second transistor 60b. A resistor 66 is provided between the transistors 60a and 60b and the ground. The resistance values of the first and second collector resistors 64a and 64b are the same, and the resistor 66 is set so that a substantially constant current always flows. Further, a first capacitor 68a is provided between the collector of the first transistor 60a and the base of the second transistor 60b, and a second capacitor 68b is provided between the collector of the second transistor 60b and the base of the first transistor 60a. It has been. The base of the first transistor 60a that is the first output terminal of the PWM auxiliary circuit 58 is connected to the output terminal of the ramp wave generating circuit 42, and the base of the second transistor 60b that is the second output terminal is the error amplifier circuit. It is connected to 40 output terminals.

  The PWM auxiliary circuit 58 detects the voltage of each input terminal of the PWM comparator 22, and when the two voltages cross and the non-inverting input terminal becomes higher, for example, the first transistor 60a is in a non-conductive state. The second transistor 60b is switched from the non-conductive state to the conductive state. Then, the collector voltage of the first transistor 60a instantaneously rises as much as no voltage is generated in the first collector resistor 64a, and the drive voltage Vdr, which is the rise, is supplied through the first capacitor 68a as the error amplification voltage. Superposed (added) on Ver. At the same time, the voltage at the collector of the second transistor 60b is instantaneously reduced by the amount of voltage generated at the second collector resistor 64a, and the drive voltage Vdr, which is the reduction, is amplified through the first capacitor 68a. Superposed (subtracted) on the voltage Ver. The amplitude of the drive voltage Vdr is set to be larger than ½ of the voltage value Vk of the PWM comparator 22 described with reference to FIG. 12, and the subsequent operation will be described in detail in the description.

  Here, the error amplification circuit 40 is set to a constant value so that it can respond to a relatively high frequency. For example, when the input voltage Vi changes suddenly, the difference between the slope of the error amplification voltage Ver and the slope of the ramp wave voltage Vram. Is considered to be small.

  Next, the operation of the switching power supply device 56 will be described with reference to FIG. Here, the periods α and β in FIG. 9 are each one cycle of switching, and the lengths of the periods α and β are a fixed time tsw. In addition, the period α is controlled to have a relatively small on-time ratio, and the period β has a relationship in which the input voltage Vi decreases in order to increase the on-time ratio. Therefore, the error amplification voltage Ver is a predetermined value. It is rising with an inclination.

  The period α starts when the switch drive circuit 32 outputs a high level reset pulse Vre and the switch element 30 is turned on. When the switch element 30 is turned on, the voltage of the integrating capacitor 26 is instantaneously discharged, the voltage Vram (ramp wave voltage Vram) of the inverting input terminal of the PWM comparator 22 sharply decreases, and the voltage Ver (error) of the non-inverting input terminal. Amplified voltage Ver). The PWM auxiliary circuit 58 detects that the voltage Vram of the inverting input terminal has decreased across the voltage Ver of the non-inverting terminal, and the voltage of the inverting input terminal is changed from Vram to −Vdr + Vram by the operation of the first transistor 60a. Decreases instantaneously. Further, the operation of the second transistor 60b instantaneously increases the voltage at the non-inverting input terminal from Ver to (Vdr + Ver). Then, the PWM comparator 22 inverts the main drive pulse Vg to the high level at the timing when the first delay time t1 has elapsed after the voltage Vram of the inverting input terminal crosses the voltage Ver of the non-inverting input terminal.

  Thereafter, at the timing when the reset pulse Vre is inverted to the low level, the switch element 30 is turned off, the integration capacitor 26 is charged via the integration resistor 24, and the ramp wave voltage Vram starts to rise with a gentle slope. The inverting input terminal voltage Vram crosses the non-inverting input terminal voltage (Vdr + Ver). The PWM auxiliary circuit 58 detects that the voltages at the input terminals have crossed each other, and the voltage at the inverting input terminal instantaneously increases from (−Vdr + Vram) to Vram by the operation of the first transistor 60a. Further, the voltage of the non-inverting input terminal is instantaneously decreased from (Vdr + Ver) to Ver by the operation of the second transistor 60b. Then, the PWM comparator 22 inverts the main drive pulse Vg to the low level at the timing when the second delay time t2 has elapsed after the voltage Vram of the inverting input terminal crosses the voltage (Vdr + Ver) of the non-inverting input terminal. Thereafter, in order to increase the ON ratio of the next period β, the error amplification voltage Ver gradually increases.

  Although the on-time ratio is relatively large in the period β, the operation is the same as that in the period α, and thus the description is omitted. Here, the first and second delay times t1 and t2 in the periods α and β will be described. First, looking at the operation in which the main drive pulse Vg is inverted to a high level, as shown in FIG. 9, the voltage Vram at the inverting input terminal of the PWM comparator 22 sharply decreases due to the switching element 30 being turned on. After crossing the terminal voltage Ver, a predetermined drive voltage Vdr is superimposed, so that the voltage difference (overdrive voltage) at each input terminal is reversed instantaneously sufficiently shorter than the switching period. Since the voltage difference (overdrive voltage) between the input terminals is larger than the voltage value Vk, the first delay time t1 is a short time tb. In addition, regarding the operation in which the main drive pulse Vg is inverted to the low level, the voltage (−Vdr + Vram) of the inverting input terminal of the PWM comparator 22 rises and crosses the voltage (Vdr + Ver) of the non-inverting input terminal almost at the same time. When the predetermined drive voltage Vdr is superimposed, the voltage level relationship of each input terminal is reversed instantaneously sufficiently shorter than the switching period. Since the voltage difference (overdrive voltage) between the input terminals is larger than the voltage value Vk, the second delay time t2 is a short time tb.

  As described above, in the switching power supply 56, the first and second delay times t1, t2 are the same as the switching power supply 52 in the period α where the on-time ratio is small and the period β where the on-time ratio is large. Both of them become a short time tb, and ideal pulse width modulation can be controlled.

  Here, the amplitude of the drive voltage Vdr can be made larger than the voltage value Vk of the PWM comparator 22 by adjusting the resistance value of the resistance element in the PWM auxiliary circuit 58 and the voltage of the DC power supply 62. For example, either the first capacitor 68a or the second capacitor 68b can be omitted. For example, when the second capacitor 68b is omitted, the drive voltage Vdr is not superimposed on the voltage of the inverting input terminal of the PWM comparator 22, and always becomes the ramp wave voltage Vram. However, the drive voltage Vdr superimposed on the voltage at the non-inverting input terminal secures an overdrive voltage equal to or higher than the voltage value Vk, and the first and second delay times t1 and t2 can be set to a short time tb.

  The present invention is not limited to the above embodiment. For example, in the ramp wave generation circuit 42, a stable DC voltage of the DC power supply 42a is input to the input terminal of the integration circuit. However, like the conventional switching power supply device 10 shown in FIG. The voltage Vi (or a voltage proportional to the input voltage Vi) may be input to perform input voltage feedforward pulse width control. The ramp wave generation circuit may be any circuit that generates a ramp wave voltage that rises and falls in a sawtooth manner. For example, the switching power supply devices 52 and 56 in FIGS. When it is not necessary to synchronize between the “operation for generating the voltage Vram” and the “operation for generating the drive voltage Vdr by the PWM auxiliary circuit”, the circuit can be changed to a known circuit other than the ramp wave generation circuit 42. .

  Further, even if the connection between the inverting input terminal and the non-inverting input terminal of the PWM comparator is reversed, the same effect as described above can be obtained. For example, when a logic inverting buffer circuit is added between the output of the PWM comparator 22 and the main switching element 12, an error amplification signal is input to the inverting input terminal side and a ramp is input to the non-inverting input terminal side. A wave voltage should be input.

  The error amplification circuit may be any circuit that amplifies the difference between the output voltage signal and a predetermined reference value and outputs an analog error amplification voltage. For example, in the case of the error amplification circuit 40 described above, since the insulating converter circuit 14 is provided, a signal insulating photocoupler 40a is provided in accordance therewith, but in the case of a non-insulating converter circuit, etc. The photocoupler 40a can be omitted.

  The PWM auxiliary circuit outputs a predetermined drive voltage at a timing when the voltage of each input terminal of the PWM comparator becomes relatively small compared to the maximum value of the ramp voltage Vram, The timing may be immediately before, simultaneously or immediately after the crossing of the voltages. In particular, if the drive voltage is output immediately before each voltage crosses, there is an advantage that the overdrive voltage is surely secured when crossing and the delay time of the PWM comparator can be shortened reliably. As a method of outputting the drive voltage immediately before each voltage crosses, for example, the timing at which each input terminal voltage crosses is predicted based on the difference in voltage between the input terminals being equal to or less than a reference value. A configuration in which a drive voltage is output to the output is conceivable. Further, in the case of the switching power supply circuit 36 of the first embodiment, a signal delay element (for example, a resistance element) is added between the output terminal of the switch drive circuit 32 and the drive terminal of the switch element 30, thereby The drive voltage Vdr may be output before the element 30 is turned on and the ramp wave voltage Vram decreases.

10, 36, 46, 52, 56 Switching power supply device 12 Main switching element 14 Converter circuit 16, 38 Switching control circuit 18, 40 Error amplification circuit 20, 42 Ramp wave generation circuit 22 PWM comparator 24 Integration resistor 26 Integration capacitor 28 Bias Resistor 30 Switch element 32 Switch drive circuit 44, 48, 54, 58 PWM auxiliary circuit
Vdr drive voltage
Ver Error amplification voltage
Vg Main drive pulse
Vi input voltage
Vo output voltage
Vo1 output voltage signal
Vram ramp wave voltage
Vre reset pulse
Vref reference voltage

Claims (8)

A converter circuit that intermittently switches an input voltage according to on / off of the main switching element, converts the input voltage into a DC output voltage, and outputs, and a switching control circuit that controls on / off of the main switching element so that the output voltage approaches a predetermined voltage; In a switching power supply device comprising:
The switching control circuit amplifies a difference between an output voltage signal obtained by detecting the output voltage and a predetermined reference voltage, and outputs an error amplification voltage, and a ramp voltage that rises and falls in a sawtooth manner. An output ramp wave generation circuit; a PWM auxiliary circuit that generates a pulsed drive voltage and superimposes the drive voltage on the error amplification voltage; and the error amplification voltage and the ramp wave voltage on which the drive voltage is superimposed. A PWM comparator that has a pair of input terminals that are respectively input, compares the voltage of each input terminal to perform pulse width modulation, and outputs a rectangular main drive pulse that drives the main switching element;
At the timing when the voltage difference between the pair of input terminals of the PWM comparator is relatively small compared to the maximum value of the ramp wave voltage, the voltage of the pair of input terminals is driven by the drive voltage. The switching power supply device is characterized in that the height relationship is reversed instantaneously sufficiently shorter than the switching period.   2. The switching power supply device according to claim 1, wherein the PWM auxiliary circuit stops the operation of superimposing the drive voltage on the error amplification voltage when a difference in slope of the voltage between the pair of input terminals is larger than a certain value. . The ramp wave generation circuit is composed of a series circuit of an integration resistor and an integration capacitor to which a DC voltage is input. The integration circuit that outputs the ramp wave voltage from both ends of the integration capacitor and both ends of the integration capacitor can be short-circuited open. And a switch drive circuit that outputs a short-width reset pulse for driving the switch element at a constant cycle and turns on the switch element for the short-width period,
The PWM auxiliary circuit has a voltage dividing circuit that divides the reset pulse or an inverted pulse obtained by inverting the reset pulse with a series circuit of a plurality of resistors or a plurality of capacitors, and outputs the drive voltage from the middle point thereof, 3. The switching power supply device according to claim 1, wherein the drive voltage is superimposed on the error amplification voltage by connecting an output terminal of the voltage dividing circuit to an output terminal of the error amplification circuit. A converter circuit that intermittently switches an input voltage according to on / off of the main switching element, converts the input voltage into a DC output voltage, and outputs, and a switching control circuit that controls on / off of the main switching element so that the output voltage approaches a predetermined voltage; In a switching power supply device comprising:
The switching control circuit amplifies a difference between an output voltage signal obtained by detecting the output voltage and a predetermined reference voltage, and outputs an error amplification voltage, and a ramp voltage that rises and falls in a sawtooth manner. An output ramp wave generation circuit; a PWM auxiliary circuit that generates a pulsed drive voltage and superimposes the drive voltage on the ramp wave voltage; and the ramp wave voltage and the error amplification voltage on which the drive voltage is superimposed. A PWM comparator that has a pair of input terminals that are respectively input, compares the voltages of the pair of input terminals, performs pulse width modulation, and outputs a rectangular main drive pulse for driving the main switching element And
At the timing when the voltage difference between the pair of input terminals of the PWM comparator becomes relatively small as compared with the maximum value of the ramp wave voltage, the voltage of the pair of input terminals is reduced by the drive voltage. A switching power supply device characterized in that the height relationship reverses instantaneously sufficiently shorter than the switching period.   5. The switching power supply device according to claim 4, wherein the PWM auxiliary circuit stops the operation of superimposing the drive voltage on the ramp wave voltage when a difference in slope of the voltage between the pair of input terminals is larger than a certain value. . The ramp wave generation circuit is composed of a series circuit of an integration resistor and an integration capacitor to which a DC voltage is input. The integration circuit that outputs the ramp wave voltage from both ends of the integration capacitor and both ends of the integration capacitor can be short-circuited open. And a switch drive circuit that outputs a short-width reset pulse for driving the switch element at a constant cycle and turns on the switch element for the short-width period,
The PWM auxiliary circuit has a voltage dividing circuit that divides the reset pulse or an inverted pulse obtained by inverting the reset pulse with a series circuit of a plurality of resistors or a plurality of capacitors, and outputs the drive voltage from the middle point thereof, 6. The switching power supply device according to claim 4, wherein the drive voltage is superimposed on the ramp wave voltage by connecting an output end of the voltage dividing circuit to an output end of the ramp wave generating circuit.   The integration circuit of the ramp wave generation circuit receives a DC voltage proportional to an input voltage, a bias resistor is inserted in a position in series with the integration capacitor, and the both ends of the series circuit of the integration capacitor and the bias resistor are connected to the integration circuit. The switching power supply device according to claim 3 or 6, which outputs a ramp wave voltage. The integration circuit of the ramp wave generation circuit receives a stable DC voltage, a bias resistor is inserted in a position in series with the integration capacitor, and the ramp wave voltage from both ends of the series circuit of the integration capacitor and the bias resistor. The switching power supply device according to claim 3 or 6, wherein:

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