JP2008305451A - State detection method of flash memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a new state detection method of a flash memory by which natural writing accuracy of the flash memory can be individually estimated to contribute to its quality control in a manufacturer shipment step and the whole writing accuracy of the flash memory and secular change (degradation) of a stored value can be known in a user usage step. <P>SOLUTION: Writing and erasing errors to a data written block and data erased block, respectively, are detected in a bit unit in order of the physical block number by using firmware and the errors are totaled to calculate a BER (Bit Error Rate) of the flash memory. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to a flash memory state detection method suitable for use in quality control at the time of factory shipment of a semiconductor flash memory and / or prediction of arrival of a lifetime after use by a user.

A flash memory is known as one of semiconductor memory devices. Before the factory shipment of the flash memory, a defective block having a physical defect in a cell is inspected, and a group of good blocks excluding the defective block is repeatedly written with data to load an electrical stress, A reliability test is performed by inspecting the electrical resistance. However, this method is only a reliability test that is performed from the viewpoint of defects in the physical structure of the cell and electrical durability, and is estimated by an increase in the frequency of data write errors peculiar to flash memory. This is not from the viewpoint of monitoring the overall and aged deterioration of the flash memory (Patent Documents 1 to 3).

A flash memory is a kind of non-volatile memory, but due to the cell structure, there is a certain limit on the number of times data can be rewritten, for example, 100,000 times. For this reason, in general, a spare storage area is provided in addition to the main storage area, and when the number of rewrites or bit errors of a specific block reaches a predetermined number, the physical block is replaced with a spare block and a rewrite process is performed. To ensure that there are no memory errors. In the case of this method, the number of spare storage areas decreases as the number of rewrites increases, and a storage error may occur. Therefore, a method of constantly monitoring the number of remaining spare storage areas and notifying the user of the replacement timing of the flash memory Has been proposed (Patent Document 4). This method is useful particularly when the data is required to be reliable, such as when the flash memory is an industrial device. However, if the write error frequency of each block in the main storage area is approximate, there may be a case where the number of blocks in the spare storage area decreases rapidly, and an unexpected situation may occur.

In particular, in recent years, not only the conventional binary memory but also a multi-value memory has appeared in the flash memory. In the case of a binary memory, only one value (“0” or “1”) can be expressed by one cell (intersection of a bit line and a word line). Four values (2 bits) of “00”, “01”, “10”, and “11” can be expressed. This is due to the fact that charges can be stored in the cell in four stages from 0 to 3, but the writing error at the time of writing and the secular change of the stored value are naturally different from those of the binary memory. Further, the circuit line width is further reduced from 90 nm to 70 nm, and further to 56 nm, and the influence of the reduction of the cell area and the margin between the lines on the storage error and the secular change of the stored value is immeasurable.
JP 2006-048893 A JP 2006-351056 A JP 09-288899 A Patent No. 3242890 (US Pat. No. 6,993,690)

Here, the first problem to be solved by the present invention is that the inherent writing accuracy can be individually estimated and contributed to the quality control in the factory shipment stage, and the flash memory is used in the use stage by the user. It is possible to provide a new method for detecting the state of a flash memory that can detect the overall writing accuracy and the secular change (deterioration) of a stored value and thereby predict the end of the life of the flash memory. Other problems will become apparent from the specification, drawings, and claims.

In order to solve the above problem, the method of the present invention detects a data error for all physical blocks to which user data is to be written. That is, the first feature of the method of the present invention is that for all physical blocks associated with logical block addresses, regardless of whether the block is a data-written block or a data-erased block. The configuration employs a configuration of a flash memory state detection method that detects data errors in bit units, totals these as bit errors, and calculates a BER (Bit Error Rate) of the flash memory.

Here, “all physical blocks associated with a logical block address” are 1) a physical block with system information stored, usually a physical block with an address number “0”, and 2) a reserved area on the system (reserved) all physical blocks except physical blocks that are not associated with logical block addresses, 3) physical blocks that were determined to be bad at the manufacturing stage, and 4) physical blocks that became bad blocks after use It is a block. That is, all blocks into which user data can be written. Among them, the data erased block includes both a block formatted at the time of factory shipment and a block from which data has been erased once written by a user after factory shipment. Data erasure of a block is to remove charges accumulated in cells (intersections of bit lines and word lines) of the block, but this charge removal processing may not be executed successfully due to a structural defect of the cell. is there. When the charge removal of all the cells in the block is completely executed, data of ALL “1” is read at the time of reading. If there is a cell in which this charge removal processing is not executed successfully due to a structural defect, the cell is read as a value of “0” at the time of reading. That is, data is programmed in the cell. In the present application, this is defined as an erasing error. This erase error, which is a data error, can occur on a cell-by-cell basis, that is, in units of bits. At the factory shipment stage, all blocks are formatted after the endurance test, but the erasure error at this time is detected in units of bits, and the BER is obtained. The BER is a value obtained by dividing the number of bits having an erasure error by the total number of bits of all data subjected to error detection. This makes it possible to estimate the individual and initial writing quality at the factory shipment stage.

After the user starts its use, data written blocks and data erased blocks (including formatted blocks) are mixed. When writing predetermined data to the block, charge accumulation processing is performed on the cell to which data is to be written. At this time, if there is a cell in which the charge accumulation process is not executed successfully due to the structural defect, a value different from the value for which the write command has been issued is read out. In the present application, this is defined as a data writing error. This data error can also occur on a cell-by-cell basis, that is, in bit units. In addition, when data is written, a phenomenon called a write disturb error may occur. A write disturb error is a charge accumulated in a non-selected cell in a page where data is written or in a non-selected cell in another page where data is written, and "0" is programmed incorrectly. The phenomenon that ends up. This data error can also occur on a cell-by-cell basis, that is, in bit units. In addition, when data reading is executed, a phenomenon called read disturb error may occur. Read disturb is a phenomenon in which when a page in the same block is read, charges are accumulated in one or a plurality of cells on another page and “0” is erroneously programmed. This may occur for each cell, that is, in units of bits, and may cause a phenomenon called data retention error In flash memory, charges are accumulated in a floating gate existing between a bit line and a word line, and data is stored. However, the charge accumulated in this floating gate gradually escapes over time, and eventually the data cannot be retained, or the charge is unintentionally accumulated in the cell that does not retain the charge, A phenomenon in which data is programmed, and the floating gate deteriorates as the number of times of writing increases. It can occur in place.

In the method of the present invention, a physical block address is designated, the above-mentioned data errors are detected in units of bits for all blocks in which user data can be written, and the total is calculated to calculate the BER. This BER is a value obtained by dividing the total number of bit errors by the total number of bits of all data that is the target of error detection. In the present application, a bit error is an error in bit units detected as an error by ECC, and includes any data error other than those described above.

As described above, according to the present invention, the data erased block is also subject to error check, and its significance is as follows. In other words, in the embodiment described in Patent Document 4, only the block (data-written block) in the main storage area is subjected to error check, but a spare block (spare block) is used for averaging writing. ) May be reused many times. In other words, both the spare block and the data where no data has been written at that time may have been written many times before, and the overall writing accuracy (in other words, deterioration) of the flash memory is checked. From the viewpoint of doing, it is preferable to make an error check target. The present invention exactly solves that point.

As described above, according to the present invention, in the factory shipment stage, it is possible to individually estimate the inherent writing accuracy of the flash memory and contribute to quality control thereof, and after the user starts use, The flash memory writing accuracy and the secular change (data deterioration) of the stored value can be known as a whole for the flash memory.

More specifically, in the present application, in order to solve the above-described problems, the present invention solves the above-described problems by adopting a novel characteristic configuration ranging from a superordinate concept to a subordinate concept listed below.

That is, the second feature of the method of the present invention is the first feature of the method of the present invention. (A) When writing data to a block, user data and sector / block information are inverted and sequentially input to the encoder. A step of inverting the user data output from the encoder and storing it in the data area of the flash memory; and a step of inverting the sector / block information and ECC output from the encoder and storing them in the redundant area of the flash memory. (B) detection of a bit error for a data-written block is performed by reading user data stored in the data area, inverting it and sequentially inputting it to a decoder; The sector / block information and ECC that are present are read, inverted, and sequentially input to the decoder. And generating a syndrome based on the user data, sector / block information and ECC input to the decoder, and if the syndrome reveals that the block has a bit error, collect the syndrome And (C) detecting a bit error for a data erased block reads out the data from the data area of the block, inverts it, and sequentially outputs it to the decoder. A step of inputting, reading the data from the sector / block information storage area of the redundant area of the block and inverting it, sequentially inputting the data to the decoder, and reading and inverting the data from the ECC storage area of the redundant area of the block And sequentially inputting these into the decoder; Generating the syndrome based on the data input to the coder, and if the syndrome reveals that the data erased block has a bit error, the syndrome is input to the collector and the bit in the block is The present invention employs a configuration of a flash memory state detection method including a step of counting the number of errors.

  According to this method, it is possible to reliably detect, in bit units, an erasure error that has conventionally been an ECC error and has been difficult to detect even when attempting to read a data erased block.

The third feature of the method of the present invention is the first feature of the method of the present invention. (A) When writing data to a block, user data sent from the host side by 1 byte is inverted and 2 bits are added at the head. The dummy data is added as a single information symbol, and a step of sequentially inputting 512 symbols to the encoder in total, and the sector / block information is inverted and a 2-bit dummy data is added to the head, and this is also used as one information symbol. A step of sequentially inputting a total of 6 symbols as symbols to the encoder, and removing the first 2 bits of the dummy data of the user data of one information symbol output from the encoder, the original user data obtained by inverting the remaining 1 byte is a total of 512 bytes Steps to store sequentially in the data area of the flash memory and output from the encoder Removing the first 2 bits of the dummy data of the sector / block information of the inputted 1 information symbol and sequentially storing the original sector / block information obtained by inverting the remaining 1 byte in the redundant area of the flash memory for a total of 6 bytes; (B) including a step of sequentially processing check symbols including ECCs sequentially output from the encoder in units of 10 bits into ECCs in units of 1-byte units, and sequentially inverting the check symbols in a redundant area of the flash memory. To detect a bit error for a written block, the user data stored in the data area is read one byte at a time and inverted. At the beginning, 2-bit dummy data is added to form one information symbol. Input to the decoder, and the stored in the redundant area In addition to reading out the invertor / block information 1 byte at a time, inverting it, adding 2 bits of dummy data to the head to form one information symbol, which is sequentially input to the decoder, and the ECC stored in the redundant area Are sequentially read into 1-byte units, sequentially processed into a continuous 1-symbol unit format composed of 10 bits, and the original check symbols inverted are sequentially input to the decoder, and the information symbols and check symbols input to the decoder And generating the syndrome based on the above and, when the syndrome is found to have a bit error, inputting the syndrome to a collector and counting the number of bit errors in the block, (C) Bi for data erased blocks The error is detected by reading out 1-byte data from the data area of the block, inverting it, adding 2-bit dummy data to the head to form one information symbol, and sequentially inputting 512 symbols to the decoder. Then, data is read out by 1 byte from the sector / block information storage area of the redundant area of the block and inverted, and 2-bit dummy data is added to the head to make one information symbol, which is equivalent to 6 symbols, Sequentially input to the decoder and data is read out by 1 byte from the ECC storage area of the redundant area of the block, and this is sequentially processed and inverted into a single symbol unit format consisting of 10 bits, and this is checked. A step of sequentially inputting a total of 8 symbols as symbols to the decoder; Generating a syndrome based on the information symbol and check symbol input to the coder, and if the syndrome reveals that there is a bit error, the syndrome is input to the collector, The configuration of the flash memory state detection method includes the step of counting the number of bit errors.

  The fourth feature of the method of the present invention is that in the first feature of the method of the present invention, (A) data writing to the block is performed by inverting the user data sequentially sent from the host one byte at a time and measuring one bit at a time. User data that is sequentially input to the encoder by 512 bytes, the sector / block information that is sequentially transmitted from the controller by 1 byte is inverted, and is input to the encoder by 6 bits in total, and user data that is sequentially output by 1 bit from the encoder Is inverted one byte at a time, and this is sequentially stored in the data area of the flash memory for 512 bytes. The sector / block information sequentially output from the encoder is inverted one byte at a time, and this is flash memory for a total of 6 bytes. Sequentially into redundant areas And the ECC sequentially output 1 bit at a time from the encoder is inverted by 1 byte except for the last byte, and dummy data is appropriately added to the ECC that becomes the final byte, and the format is inverted as 1 byte. And sequentially storing them in a redundant area of the flash memory. (B) The detection of a bit error for a data-written block reads 512 bytes of user data stored in the data area one byte at a time. Are sequentially input to the decoder one bit at a time, the 6-byte sector / block information stored in the redundant area is read one byte at a time, and the inverted one is sequentially input to the decoder one bit at a time. ECC stored in the redundant area Read and invert 1 byte at a time, except for the last byte, 1 bit at a time, removing the dummy data from the last byte and sequentially inputting it to the decoder 1 bit at a time, and the user data, sector / block information and ECC input to the decoder, Generating a syndrome based on the syndrome, and if the syndrome reveals that there is a bit error, inputting the syndrome to a collector and counting the number of bit errors in the block, (C) data The detection of a bit error for an erased block is performed by reading a total of 512 bytes of data from the data area of the block, inputting the inverted version to the decoder one bit at a time, and the sector / block of the redundant area of the block Store A total of 6 bytes of data is read from the area in units of 1 byte, the inverted version is sequentially input to the decoder in increments of 1 bit, and the data is read out and inverted in increments of 1 byte from the ECC storage area of the relevant block, excluding the final byte Removing the same number of bits as the dummy data from the tail of the last byte, and sequentially inputting the data to the decoder one bit at a time, and generating the syndrome based on the data input to the decoder If the syndrome is found to have a bit error, the flash memory state detection method includes the step of inputting the syndrome to the collector and counting the number of bit errors in the block.

The best mode for carrying out the present invention will be described below with reference to the drawings. However, the present invention can take various forms within the scope of the claims, and is not limited to the following embodiments. Absent.

(Configuration of data area of flash memory)
In describing the method of the present invention, first, the page configuration of the flash memory will be described with reference to FIG. The flash memory includes a multi-value large block in addition to a binary small block and a binary large block. In the binary small block, one page is composed of one ECC sector, that is, a data area of 512 bytes and a redundant area of 16 bytes (FIG. 1A), and one block is composed of 16 pages or 32 pages. In the binary large block, for example, one page is composed of 4 ECC sectors and one block is composed of 64 pages. In the multi-value large block, for example, one page can be composed of 4 ECC sectors (FIG. 1B), and one block is composed of 128 pages.

A more specific configuration example includes a data area and a redundant area as shown in FIG. The data area is an area for storing 512-byte user data, and the redundant area is a sector / block information storage area for storing sector / block information for 6 bytes related to a sector or block for storing the user data and a data amount of 10 bytes. ECC storage area for storing ECC (error correcting code). Both the user data and the sector / block information constitute an information symbol to be described later. ECC is a component of a check symbol generated by an encoder described later. The method of the present invention can be applied to both a binary memory and a multi-level memory.

(System configuration)
A system for implementing the method of the present invention is a flash memory comprising a NAND flash memory (hereinafter referred to as a flash memory) and a controller for controlling the writing and reading of data to and from the flash memory based on commands from the host. A device (referred to as a “storage device”) and the host that instructs the storage device to write and read data. The flash memory and the controller may be composed of individual ICs or a single package. The storage device is preferably configured to be detachable from the host and the substrate on which the storage device is mounted so that it can be easily replaced with a new one. The controller has, as hardware, an error correction circuit (Reed-Solomon method) shown in FIG. 3 and a program (firmware) for executing the method of the present invention using the error correction circuit. The error correction circuit is composed of an ENDEC (encoder 1 and decoder 2) that processes 10 bits in units of one symbol, and a collector 3 described later.

(Encoding of user data and sector / block information, storage in memory)
First, a data write process for each ECC sector executed in the method of the present invention will be described with reference to FIG. Here, FIG. 4 shows an encoder and represents its internal processing (FIG. 4 is also used in the description of the decoder processing described later, but it should be noted that the following description relates only to the encoder processing. ). First, when a data write command (Write command) is received from the host, user data is sequentially input to the encoder 1 by 1 byte (ie, 8 bits) (Data_in in the figure). When each bit of 1 byte is XOR 0xff processed, that is, when the value of each bit of 8 bits is XORed with “1”, all data of 8 bits are inverted. Since encoder 1 handles 10-bit data in units of 1 symbol, 2-bit dummy data is added to the head of the inverted 8-bit data, processed into a single symbol format of 10 bits in total, and input to the arithmetic circuit. (Data_in1 in the figure) and execute encoding.

Here, encoding means that an ECC (error check code) is generated based on information (user data and sector / block information described later) input to the encoder 1. When the user data is encoded, user data in units of one symbol (10 bits) is output from the arithmetic circuit (Data_out1 in FIG. 4). Of these, the first 2 bits are dummy and are removed, and the remaining data The XOR 0xff process is executed again on the 8-bit user data (Data_out in FIG. 4). This 1-byte user data is input original user data. The above-described user data processing is sequentially executed for a total of 512 bytes, and is sequentially written in the data area of the block.

When the encoding of the user data is completed, information on the sector to which the user data is to be written and the block to which the sector belongs is obtained from hardware called a data formatter in the controller (not shown). Information ") is input to the encoder 1 by 1 byte (Data_in). This sector / block information is preliminarily specified to be a value other than ALL “1”. When the encoding of the user data of 512 bytes is completed, the sector / block information is processed by the same process as the above-described user data. The data is input to the arithmetic circuit (Data_in1) and encoded. Sector / block information is well known to those skilled in the art, and will not be described in detail herein.

When the sector / block information is encoded, as in the case of user data, sector / block information in units of one symbol (10 bits) is output (Data_out1), but the top 2 bits are similarly dummy data and thus removed. Then, XOR 0xff processing is executed on the remaining 8-bit sector / block information (Data_out). This 1-byte user data is the input original sector / block information. The sector / block information processing described above is sequentially executed for a total of 6 bytes, and is sequentially written in the redundant area of the block.

  Note that when formatting (initializing) the flash memory, or when erasing (deleting) data from a data-written block, there is a process of removing the charges of all cells in the target block. Executed.

(Formation of check symbol, storage in memory)
By the encoding process for user data and sector / block information, the encoder 1 generates an ECC (error check code) for a total of 10 bytes (80 bits) related to the user data and sector / block information and outputs it from the arithmetic circuit. This will be described with reference to FIG. As shown in the figure, ECCs for a total of 8 symbols are sequentially output from the arithmetic circuit of the encoder 1 in units of 10 bits. In the present application, ECC configured in units of symbols is referred to as a check symbol. The generated ECC is an error check code for the user data and sector / block information including the dummy data described above. As shown in FIG. 5, the check symbol CS0 output first, the second check symbol CS1, and then the eighth check symbol (CS7) are output in order. Each time a check symbol is output, these are sequentially cut and pasted into a 1-byte unit structure, and inverted every time the check symbol is processed. The inverted one is reconfigured with the first 1-byte 8-bit ECC as CB0, the next 1-byte ECC as CB1, and the 10th 1-byte ECC (CB9) in order. Then, it is sequentially stored in the redundant area. The check symbol output from the encoder 1 and the ECC stored in the redundant area are both 80 bits in total and the same data amount (see FIG. 7A).

(Decoding information symbols)
Next, an error detection method for user data and sector / block information stored in a block will be described. In the following first embodiment, since the error correction circuit uses ENDEC (encoder 1 and decoder 2) that processes data in units of 10 bits per symbol, when processing is performed by the arithmetic circuit of encoder 1 and decoder 2. The user data and sector / block information are referred to as “information symbols”. First, read processing of data stored in a block will be described with reference to FIG. 4, where FIG. 4 represents the decoder 2. That is, in the following description, it should be noted that the arithmetic circuit in FIG. 4 is an arithmetic circuit that performs decoding processing, and is naturally different from the arithmetic circuit that performs encoding processing described above.

Based on the firmware that specifies the physical block address to be read and executes data reading from the physical block, when Read is executed for the flash memory, the data of the first ECC sector existing in the first page of that block User data is read from the area in 1-byte (8-bit) units by FIFO method and input to the decoder 2 (Data_in in FIG. 4).

The 8-bit data is subjected to XOR 0xff processing, 2-bit dummy data is added to the head of the 8-bit data, is processed into one symbol (10 bits) in form (Data_in1 in FIG. 4), and is sequentially input to the arithmetic circuit as an information symbol. As for the data erase block, as long as there is no erase error, data whose values are all “1” are read from the data area, and the same processing as described above is executed.

When decoded by the arithmetic circuit, one symbol of user data is output from the arithmetic circuit (Data_ont1 in FIG. 4) as when input to the arithmetic circuit. Then, the leading dummy data 2 bits are removed, and XOR 0xff processing is executed on the remaining 8 bits (Data_out). This is the original 8-bit user data input to the decoder 1. This user data decoding process is sequentially executed for a total of 512 bytes and transferred from the decoder 2 to the RAM in the controller.

Subsequently, data is read from the sector / block information stored in the redundant area of the sector by 1 byte (8 bits) by the FIFO method (Data_in). This 8-bit data is also XOR 0xff processed in the same way as the user data, 2 bits of dummy data is added to the head and processed into 1 symbol (10 bits) in form (Data_in1), and sequentially as an information symbol to the decoder as in the user data. Entered. As for the data erased block, as long as there is no erase error, data whose value is all “1” is read from the sector / block storage area, and the same processing as described above is executed. This sector / block information decoding process is sequentially executed for a total of 6 bytes.

(ECC decoding)
Next, following the sector / block information, ECC is read from the redundant area. Then, ECC check symbols are generated and decoded, which will be described with reference to FIG. FIG. 6 shows the decoder 2. In ECC, the above-described CB0 to CB9 are read as they are (ie, 8 bits at a time) in the FIFO method, but since the decoder 2 executes the processing with 10 bits as one symbol, the read ECC is sequentially cut and pasted into a 10-bit symbol format. After that, inversion processing (XOR 0x3ff) is performed on all data of each symbol (10 bits), and sequentially input to the decoder as a total of 8 original check symbols (CS0 to CS7). FIG. 6 shows a state in which the check symbol CS3 is configured and input to the arithmetic circuit of the decoder 2. The ECC (CB0 to CB9) read from the redundant area and the check symbols (CS0 to CS9) inverted and input to the arithmetic circuit of the decoder 2 are both 80 bits in total and the same data amount (FIG. 7b). reference). For the data erased block, as long as there is no erase error, data whose value is all “1” is read from the ECC storage area, and the same processing as described above is executed.

(Data error detection)
The decoder 2 generates a syndrome from a block based on a received word (information symbol and check symbol) input to the arithmetic circuit via a communication path in the controller. When all 512 information symbols composed of user data, 6 information symbols composed of sector / block information, and 8 check symbols composed of ECC are all input to the arithmetic circuit of the decoder 2, the decoder 2 Generate a syndrome for that ECC sector. The decoder 2 determines whether there is a data error in the information symbol (512-byte user data and 6-byte sector / block information) and the check symbol based on this syndrome.

(Bit error count detection)
If it is found that there is a data error in either the information symbol and / or the check symbol, depending on the syndrome, the syndrome is input to the collector 3. The collector 3 generates an error position polynomial using the Berlekamp-Massey Algorithm based on the syndrome input from the decoder 2 and also uses the Chein Search to determine the error position (the symbol position with the error) and its root. Ask. Then, in order to make a symbol with an error a correct value by the Forney Algorithm, a value to be XORed with the symbol with the error is obtained. If there are multiple symbols with errors, this is determined for each symbol. As a result, the number of bit errors in the sector is determined.

This number of bit errors is detected for all sectors of all pages of the physical block. The number of bit errors is accumulated and stored every time an error check is performed on information symbols and check symbols of one ECC sector. This processing is performed in order from the physical block number “1” by designating block numbers (address numbers) such as physical block numbers “2”, “3”. However, a physical block that is not associated with a logical block address, such as 1) a system block in which system information is stored, usually a physical block with an address number “0”, 2) a reserved area on the system that is logical A physical block that is not associated with a block address, 3) a physical block that is determined to be bad at the manufacturing stage (bad block), and 4) a physical block that becomes a bad block after use is excluded. After detecting the bit error of all blocks subject to error detection, the total number of bit errors is divided by the total number of user data, sector / block information and ECC bits of all blocks subject to error check, and the relevant flash Obtain the BER (Bit Error Rate) of the memory. The obtained value is stored in a storage device (a flash memory or a predetermined storage area of the controller).

In the normal data read, if there is no data error in the information read from the block, the user data transferred to the RAM is read to the host. If there is a data error in the information read from the block, the syndrome generated by the decoder 2 is input to the collector 3, and the correct value is obtained by the Forney Algorithm and transferred to the RAM with this correct value. Correct user data. Then, the user data corrected to the correct value is read from the RAM to the host. In this respect, since the method of the present invention is mainly intended to obtain the BER, the user data does not necessarily have to be transmitted to the host.

The detection of the number of bit errors and the calculation of the BER can be performed, for example, once a day (for example, at midnight). At this time, even if the system is in operation, it can be executed while the flash memory is idling, such as between commands received from the host.

Based on empirical rules or experimental values, the relationship between the maintenance time or replacement time of the flash memory and the BER is grasped in advance, and the BER value is set as a threshold value to indicate that the flash memory has reached that time. For example, the system administrator may be notified. As described in Patent Document 4, the notification may be performed by either notification means provided in the storage device, a display device connected to the host, or a speaker built in the host. When the notification is made on the host side, the host reads out the BER stored in the storage device. The threshold value may be set at a plurality of levels such as the first value (caution caution) and the second value (warning warning), and the threshold value may be notified by a different method.

In addition, an external monitoring device with a calendar function, a timer function, and a command issuing function is separately provided, and the external monitoring device is connected to the external monitoring device from the storage device side via a serial interface or GPIO or by Bluetooth wireless communication. The command may be issued at a certain time on a certain day to monitor the state of the flash memory. Furthermore, a communication function may be provided in the external monitoring device so that the state of the flash memory is notified to the administrator's mobile phone or personal computer (PC). When the BER reaches the second threshold value and the external monitoring device is notified of the arrival of the replacement time of the storage device, a flash memory is sent from the administrator's PC to the storage device as a preliminary measure until the replacement. A command such as write protection or data backup may be sent to the controller of the storage device to perform the processing.

Further, the BER history may be recorded in a nonvolatile manner in a storage device or a host so as to be manageable. In particular, since the frequency of error occurrence was generally considered to depend on the number of data rewrites, the number of rewrites was roughly estimated to predict the end of the service life. Has been found to occur. According to the BER obtained by the method of the present invention, the flash memory is used regardless of whether the flash memory is mainly used for data rewriting or reading. It will be of great help in detecting the maintenance period or the end point period in advance and preventing unexpected situations such as data corruption.

In the above embodiment, the encoder 1, the decoder 2 and the collector 3 correspond to the Reed-Solomon code, and 10 bits are processed in units of 1 symbol, so that 1-byte data sent from the host is processed. The process is executed by adding 2 bits of dummy data. In addition, the ECC 1 that outputs a total of 10 bytes per ECC sector can count user data, sector / block information, and ECC bit error counts up to a total of 40 symbols per ECC sector.

Similarly, the encoder 1, decoder 2 and collector 3 corresponding to the Reed-Solomon code are used, and 10 bits are processed in units of one symbol, and the encoder 1 is configured to output a total of 20 bytes per ECC sector. According to the ECC, the number of bit errors can be counted up to a maximum of 8 symbols per ECC sector and a total of 80 bits. At this time, one ECC sector includes a data area for storing user data 512 bytes, and a redundant area for storing 6-byte sector / block information and 20-byte ECC.

In addition, the encoder, decoder and collector used in the method of the present invention are not limited to those using Reed-Solomon codes, but BCH (Bose-Chaudhuri-Hocquenghem multiple
error correction) code may be used. An embodiment of a flash memory state detection method using the BCH method will be described below.

FIG. 8 is a configuration example of one ECC sector when the BCH method is used. As shown in the figure, the ECC storage area stores 78-bit ECC and 2-bit dummy data. This is substantially the same as the configuration in the case where a maximum of four symbols are corrected by the above-described Reed-Solomon error correction circuit. FIG. 9 is an input / output example of user data and sector / block information in the encoder or decoder. The BCH encoder and decoder process data one bit at a time, and therefore, input / output is not performed in units of symbols as in the Reed-Solomon method. Therefore, as shown in the figure, 1-byte user data sent from the host, and 1-byte sector / block information regarding the sector and block to which the user data to be written input from the data formatter are written, are inverted after 1 bit. Each is input to the arithmetic circuit of the encoder or decoder.

When the BCH method is adopted, data is output bit by bit from the arithmetic circuit of the encoder or decoder. The user data and sector / block information output from the arithmetic circuit are inverted together when 8 bits, that is, 1 byte are accumulated, and stored in the flash memory by 1 byte.

The encoder arithmetic circuit outputs a total of 78 bits of ECC per ECC sector, one bit at a time. When 8 bits, that is, 1 byte is accumulated, the ECC is inverted and stored in the redundant area of the flash memory. However, since the ECC of the final 10-byte (CB9) is output only 6 bits, 2-bit dummy data is added after the final ECC, is formed into 1-byte formally, inverted, and stored in the redundant area (CB0 to CB9) : Refer to FIG.

On the other hand, user data read 1 byte from the data area and sector / block information similarly read 1 byte from the redundant area are inverted together in units of 1 byte and then input to the decoder 1 bit at a time. Similarly, the ECC read from the redundant area in units of 1 byte is similarly inverted in units of 1 byte and then input to the decoder bit by bit (CB0 to CB8). However, since the final 2 bits of the final CB9 are dummy data, they are not input to the decoder (the same applies to 4-bit dummy data described later). In this case, a 78-bit ECC can detect a bit error of up to 6 bits per ECC sector.

Alternatively, a BCH code may be used to configure one ECC sector as shown in FIG. 11 so that a bit error of up to 12 bits can be detected. That is, in this case, 156-bit ECC and 4-bit dummy data are stored in the ECC storage area. This is substantially the same as the configuration in the case where a maximum of 8 symbol correction is performed by the above-described Reed-Solomon error correction circuit. Further, the ECC output from the encoder is composed of 1-byte ECC for CB0 to CB18, and the final CB19 is composed of 4 bits for ECC and 4 bits for dummy data (see FIG. 12).

An error correction circuit using the BCH code is shown in FIG. In the BCH method, the decoder 2 'determines whether or not there is a data error, and then outputs the data error position in bits. Since the correct value is uniquely determined, the value of the data error is obtained at the time of error correction. Processing is unnecessary. That is, it is not necessary to obtain a value for XORing the erroneous value in the collector 3 '. In the case of the BCH method, it is possible to calculate the BER of the flash memory by counting and accumulating the number of bit errors by indicating the position of the data error. Needless to say, the encoder 1 ′, the decoder 2 ′, and the collector 3 ′ are all different from the encoder 1, the decoder 2, and the collector 3 that employ the Reed-Solomon method.

As described above, according to the method of the present invention, the state (write accuracy, data deterioration) of the flash memory is monitored on a daily basis, and it is suitable for use in the maintenance thereof. In addition, when the lifetime of the flash memory is predicted using the method of the present invention, the configuration disclosed in Patent Document 4, the total power-on time, and other determination factors are combined. RT (self-monitoring analysis and
It goes without saying that it may be performed by the reporting technology method.

2 is a page configuration example of a flash memory. This is a data configuration example of one ECC sector when the Reed-Solomon system ENDEC is used. This is a configuration of a Reed-Solomon type error correction circuit. It is an example data input / output state of an information symbol in a Reed-Solomon encoder or decoder. It is an example of data output of a check symbol from a Reed-Solomon encoder. This is an example of ECC-check symbol conversion and input to an arithmetic circuit in a Reed-Solomon decoder. It is an example of data processing of check symbols at the time of encoding and decoding when using the Reed-Solomon method ENDEC. It is an example of a data structure of the ECC sector when using the BCH system ENDEC. It is an example of a data input / output state in a BCH encoder or decoder. It is an example of ECC data structure stored in a redundant area when using the BCH system ENDEC. It is another data structure example of the ECC sector when using the BCH system ENDEC. It is another structural example of the ECC data stored in the redundant area when using the BCH system ENDEC. It is an example of a structure of the error correction circuit of a BCH system.

Explanation of symbols

1, 1 'encoder 2, 2' decoder 3, 3 'collector

Claims (11)

Regardless of whether the block is a data-written block or a data-erased block, a data error is detected in bit units for all physical blocks associated with the logical block address. A method for detecting a state of a flash memory, comprising: summing up as bit errors and calculating a BER (Bit Error Rate) of the flash memory. (A) Writing data to the block
Inverting user data and sector / block information, respectively, and sequentially inputting them to the encoder;
Inverting the user data output from the encoder and storing it in the data area of the flash memory;
Including the step of inverting the sector / block information and ECC output from the encoder and storing them in a redundant area of the flash memory,
(B) Detection of a bit error for a data-written block
Reading user data stored in the data area, inverting it and sequentially inputting it to a decoder;
Reading sector / block information and ECC stored in the redundant area, inverting it and sequentially inputting it to a decoder;
Generating the syndrome based on the user data, sector / block information and ECC input to the decoder;
If the syndrome reveals that there is a data error, the syndrome is input to a collector, and the number of bit errors in the block is counted.
(C) Bit error detection for a data erased block is as follows:
Reading and inverting data from the data area of the block, and sequentially inputting it to the decoder;
Reading and inverting data from the sector / block information storage area of the redundant area of the block, and sequentially inputting the data to the decoder;
Reading the data from the ECC storage area of the redundant area of the block, inverting it, and sequentially inputting it to the decoder;
Generating the syndrome based on the data input to the decoder;
If the syndrome reveals that the data erased block has a bit error, the syndrome is input to a collector, and the number of bit errors in the block is counted.
The flash memory state detection method according to claim 1. (A) Writing data to the block
Reversing user data sent 1 byte at a time from the host side, adding dummy data of 2 bits to the head of the user data, and inputting this as one information symbol to the encoder sequentially for a total of 512 symbols;
Inverting the sector / block information and adding 2 bits of dummy data to the head of the information, and sequentially inputting this to the encoder as a single information symbol for a total of 6 symbols;
Removing the first 2-bit dummy data of user data of one information symbol output from the encoder and sequentially storing the original user data obtained by inverting the remaining 1 byte in the data area of the flash memory for a total of 512 bytes;
The step of removing the first 2-bit dummy data of the sector / block information of one information symbol output from the encoder and sequentially storing the original sector / block information obtained by inverting the remaining 1 byte in the redundant area of the flash memory for a total of 6 bytes When,
Including sequentially processing check symbols including ECCs sequentially output from the encoder in units of 10 bits into ECCs in units of 1 byte units, and sequentially storing the inverted symbols in a redundant area of the flash memory;
(B) Detection of a bit error for a data-written block
Reading the user data stored in the data area 1 byte at a time, inverting it, adding a 2-bit dummy data to the head to form one information symbol, and sequentially inputting it to the decoder;
Reading out the sector / block information stored in the redundant area 1 byte at a time, inverting it, adding 2-bit dummy data to the head to form one information symbol, and sequentially inputting it to the decoder;
Sequentially reading the ECC stored in the redundant area one byte at a time, sequentially processing the ECC into a continuous one-symbol format composed of 10 bits, and sequentially inputting the original check symbols to the decoder;
Generating a syndrome based on the information symbols and check symbols input to a decoder;
If the syndrome reveals that there is a bit error, the syndrome is input to a collector, and the number of bit errors in the block is counted.
(C) Bit error detection for a data erased block is as follows:
Reading data from the data area of the block one byte at a time, inverting this, adding 2-bit dummy data to the head to form one information symbol, and sequentially inputting this to the decoder for 512 symbols;
Data is read out from the sector / block information storage area in the redundant area of the block by 1 byte, inverted, and 2-bit dummy data is added to the head to form one information symbol, which is sequentially decoded by 6 symbols. Step to enter
Data is read out by 1 byte from the ECC storage area of the redundant area of the block, and is sequentially processed and inverted into a format of 1 symbol unit composed of 10 bits, and this is used as a check symbol for a total of 8 symbols. Step to sequentially input to,
Generating a syndrome based on the information symbols and check symbols input to a decoder;
If the syndrome reveals that there is a bit error, the syndrome is input to a collector and includes counting the number of bit errors in a symbol with a bit error.
The flash memory state detection method according to claim 1. The encoder, decoder, and collector are compatible with Reed-Solomon codes, and the encoder outputs a total of 10 bytes of ECC per ECC sector, and the number of bit errors can be counted up to a maximum of 40 symbols total of 4 symbols per ECC sector. The flash memory state detection method according to claim 3. The encoder, decoder, and collector support Reed-Solomon codes, and the encoder outputs a total of 20 bytes of ECC per ECC sector, and can count the number of bit errors up to a maximum of 80 bits per ECC sector. The flash memory state detection method according to claim 3. (A) Writing data to the block
Reversing user data sequentially sent from the host in 1-byte units and sequentially inputting the data to the encoder in units of 512 bytes;
Reversing the sector / block information sequentially sent out from the controller in 1-byte units, and inputting it to the encoder sequentially in 6-byte increments;
Inverting user data that is sequentially output from the encoder bit by bit by 1 byte, and sequentially storing the user data in a data area of the flash memory for a total of 512 bytes;
Inverting the sector / block information sequentially output by 1 bit from the encoder by 1 byte, and sequentially storing the inverted information in the redundant area of the flash memory for a total of 6 bytes;
The ECC sequentially output 1 bit at a time from the encoder is inverted by 1 byte except for the last byte, and dummy data is appropriately added to the ECC that is the final byte, and the data is inverted as 1 byte in the format, and these are inverted. Including sequentially storing in a redundant area of the flash memory;
(B) Detection of a bit error for a data-written block
Reading 512 bytes of user data stored in the data area one byte at a time, and inverting the read data one bit at a time into the decoder;
Reading 6-byte sector / block information stored in the redundant area one byte at a time, and sequentially inverting it and inputting it to the decoder one bit at a time;
The ECC stored in the redundant area is read and inverted one byte at a time, except for the last byte, one bit at a time, and the dummy data is removed from the last byte and sequentially input to the decoder one bit at a time;
Generating the syndrome based on the user data, sector / block information and ECC input to the decoder;
If the syndrome reveals that there is a bit error, the syndrome is input to a collector, and the number of bit errors in the block is counted.
(C) Bit error detection for a data erased block is as follows:
Reading a total of 512 bytes of data from the data area of the block one byte at a time, and sequentially inputting the inverted data one bit at a time to the decoder;
Reading a total of 6 bytes of data from the sector / block storage area of the redundant area of the block one byte at a time, and sequentially inputting the inverted data to the decoder one bit at a time;
The data is read out from the ECC storage area of the redundant area of the block by 1 byte, inverted, 1 bit is removed except for the last byte, and the same number of bits as the dummy data is removed from the tail of the last byte to decode 1 bit. Step to sequentially input to,
Generating the syndrome based on the data input to the decoder;
If the syndrome reveals that there is a bit error, the syndrome is input to a collector, and the number of bit errors in the block is counted.
The flash memory state detection method according to claim 1. 7. The flash memory according to claim 6, wherein the encoder and the decoder are of a BCH system, and the encoder outputs a total of 78 bits of ECC per ECC sector, and can count the number of bit errors up to 6 bits per ECC sector. State detection method. 7. The flash memory according to claim 6, wherein the encoder and the decoder are of a BCH system, and the encoder outputs a total of 156 bits of ECC per ECC sector, and can count the number of bit errors up to a maximum of 12 bits per ECC sector. State detection method. 9. The method for detecting a state of a flash memory according to claim 1, wherein the bit error is detected while the flash memory is idling. 9. The method for detecting a state of a flash memory according to claim 1, wherein when the BER reaches a predetermined threshold, the fact that the threshold has been reached is notified to the outside. 11. The flash memory state detection method according to claim 10, wherein the threshold value is set to a value of at least 2 and the notification to the outside is executed by a different method for each threshold value.