CN110459259A - Store test method, system and the storage medium of equipment write error error correcting capability - Google Patents
Store test method, system and the storage medium of equipment write error error correcting capability Download PDFInfo
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- 238000010998 test method Methods 0.000 title abstract description 5
- 238000012360 testing method Methods 0.000 claims abstract description 62
- 238000012937 correction Methods 0.000 claims description 74
- 238000000034 method Methods 0.000 claims description 38
- 238000001514 detection method Methods 0.000 claims description 10
- 238000004590 computer program Methods 0.000 claims description 7
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 4
- 238000005516 engineering process Methods 0.000 description 3
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 238000012545 processing Methods 0.000 description 2
- 238000012795 verification Methods 0.000 description 2
- VTLYHLREPCPDKX-UHFFFAOYSA-N 1,2-dichloro-3-(2,3-dichlorophenyl)benzene Chemical compound ClC1=CC=CC(C=2C(=C(Cl)C=CC=2)Cl)=C1Cl VTLYHLREPCPDKX-UHFFFAOYSA-N 0.000 description 1
- 238000013500 data storage Methods 0.000 description 1
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/14—Implementation of control logic, e.g. test mode decoders
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C2029/4402—Internal storage of test result, quality data, chip identification, repair information
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Abstract
The present invention provides test method, system and the storage mediums of storage equipment write error error correcting capability, and wherein test method includes: the flash block selected blank or be wiped free of data, and data are written in the data page for the flash block selected;It reads the data on all data pages of the flash block of write-in data and saves in the buffer, then wipe the data in the flash block;Write operation again is carried out to the data page for the data block being wiped free of;It tests to the data page for the data block for being again written data, it compares to obtain the first comparing result according to the population size of the population size of the data bit to report an error and the data bit of write-in data, and the address of address data block corresponding with the write-in data bit of data, the address of data page of the address of the data block to report an error, data page compare to obtain the second comparing result, above-mentioned first and second comparing result is the test result of the write error error correcting capability of the storage equipment.
Description
Technical Field
The invention relates to a technology for testing error correction capability in a storage system, in particular to a method for testing write error correction capability of a storage device.
Background
The flash memory chip is a storage medium for storing electronic information by using a flash memory technology, and as the flash memory chip has the characteristics of fast storage, no disappearance of data after power failure and the like, and has the advantages of small volume, large storage capacity and the like, more and more storage devices select the flash memory chip as the storage medium. However, due to the physical characteristics of the flash memory chip, a certain amount of data bit flipping errors occur when data is read out, which results in a decrease in the accuracy of data storage. In order to reduce or avoid the problems, redundant error correction and error handling programs must be added to the controller of the storage device using the flash memory chip as the storage medium to ensure the correctness of the stored data.
In a storage device using flash memory technology, a write operation of a flash memory must be performed under a condition that a target area is in a blank state, i.e., has no data, and if data is written to the target area, the data must be written after being erased, so the erase operation is a basic operation of the flash memory. The flash memory chip is erased in block unit, and is written and read in page unit, and each block includes several pages and has to be erased before being written. In order to ensure the correctness of data, a flash memory controller generates redundant error correction code data according to the data and writes the redundant error correction code data into a flash memory page at the same time when the data is written in, the redundant error correction code data is read into the flash memory controller at the same time when the data is read from the flash memory page and carries out redundant check and error correction, if the number of wrong bits exceeds a threshold value of an error correction algorithm, an error processing program is triggered to carry out subsequent processing, otherwise, correct data is returned to a caller.
At present, the error handling capability of flash memory is gradually becoming one of the important indicators for evaluating the reliability of the whole flash memory chip-based storage device. However, the method for testing and evaluating the write error correction capability of the memory device in the prior art needs to be improved.
Disclosure of Invention
The present invention is made to solve the problem that there is no suitable method for testing and evaluating the write error correction capability of a storage device, and an object of the present invention is to provide a method, a system and a storage medium for testing the write error correction capability of a storage device.
The invention mainly aims at the problem and provides a method for artificially inserting some predefined write errors of a flash memory during development to check the error processing capability of a storage device so as to improve the final reliability of a product.
The invention provides a method for testing the write error correction capability of a storage device, which is characterized by comprising the following steps:
s0, selecting a blank flash memory block or a flash memory block with data erased, and writing data into the data page in the selected flash memory block;
s1, reading the data on all data pages on the flash memory block written with the data and storing the data in a cache, and then erasing the data in the flash memory block;
s2, rewriting the data page of the flash memory block of the erased data;
s3, checking the data page of the data block with the data written again, comparing the number of the error reporting data bits with the number of the data bits written in the step S0 to obtain a first comparison result, and writing the first comparison result into the test result of the write error correction capability of the storage device.
The method for testing the write error correction capability of the storage device, provided by the invention, further has the following characteristics that after the step S2, the method further includes:
and comparing the address of the error-reported data block and the address of the data page with the address of the data block and the address of the data page corresponding to the data bit of the data written in the step S0 to obtain a second comparison result, and writing the second comparison result into the test result of the write error correction capability of the storage device.
The invention provides a method for testing the write error correction capability of a storage device, wherein a first comparison result is used for accurately judging whether write errors exist in data written in a storage chip to be detected or the storage device, and a second comparison result is used for determining whether the address of a data page to be corrected is a data page with preset write errors or not, so that unexpected errors are avoided.
The invention provides a method for testing write error correction capability of a memory device, wherein the flash memory blocks of blank or erased data selected in step S0 are random and may be multiple, and the addresses of the selected data blocks in the memory chip of the memory device are continuous or intermittent or continuous and concurrent with the interval.
The invention provides a method for testing the writing error correction capability of a storage device, wherein the data page in a flash memory block selected can be multiple, wherein the data page is the minimum writing unit.
The invention provides a method for testing the write error correction capability of a storage device, wherein data written in a selected flash memory block is random.
The invention provides a method for testing the writing error correction capability of a storage device, wherein a data block subjected to writing operation in a rewriting step is random, when an effective data page is written into an error-making data page in the writing step, due to the characteristic that a flash memory can only be written once after being erased, a flash memory chip can report a writing error, and the storage device can trigger a subsequent error processing program.
The invention provides a method for testing the write error correction capability of a storage device, wherein the number of data bits written in a selected flash memory block can be determined according to the threshold value of the error correction algorithm of the storage device, data larger than the error correction threshold value of the storage device is written in, and the test result in step S3 is recorded as a first detection result; or writing data equal to the error correction threshold of the storage device, and recording the test result in the step S3 as a second detection result; or writing data smaller than the error correction threshold of the memory device, and recording the test result in step S3 as a third detection result.
The invention also provides a system for testing the write error correction capability of the storage device, which is characterized by comprising the following steps:
the write-in module is used for selecting a blank flash memory block or a flash memory block with erased data on a memory chip or memory equipment to be detected and writing data in a data page in the selected flash memory block;
the reading and erasing module is used for reading the data on all the data pages on the flash memory block written with the data in the writing module, storing the data in a cache and then erasing the data in the flash memory block;
the rewriting module is used for writing the data block data page which is erased in the reading and erasing module;
and the reading and checking module is used for performing reading and checking on the data page of the data block in which the data is written again, comparing the number of the error-reported data bits with the number of the data bits of the data written in the writing module to obtain a first comparison result, and writing the first comparison result into the test result of the writing error correction capability of the storage device.
The invention provides a test system for the write error correction capability of a storage device, which is also characterized in that:
and the reading and checking module is also used for comparing the address of the data block and the address of the data page which are reported with errors with the address of the data block and the address of the data page corresponding to the data bit of the data written in the data writing step to obtain a second comparison result, and writing the second comparison result into the test result of the write error correction capability of the storage equipment.
The invention provides a test system for the write error correction capability of a storage device, wherein the selected blank or erased flash memory blocks in the test system are random and can be a plurality of, and the addresses of the selected data blocks in the storage device are continuous or intermittent or continuous and intermittent.
The invention provides a system for testing the write error correction capability of a storage device, wherein random data is written into the storage device to be tested according to a preset storage address, wherein the storage address is distributed in each data block in a flash memory block for selecting blank or erased data, but the address of a data page in each data block is distributed randomly.
The invention also provides a storage medium, which stores a computer program, wherein the computer program is executed by a processor to implement the steps in the method for testing the write error correction capability of the storage device.
The invention also provides a storage medium, wherein the storage medium is a flash memory chip.
Action and Effect of the invention
According to the method, the system and the storage medium for testing the write error correction capability of the storage device, the test method has a writing step, so that a flash memory block with blank or erased data can be selected, and data can be written in a data page in the selected flash memory block; the method comprises a reading and erasing step, wherein the data on all data pages on a flash memory block in which data are written can be read and stored in a cache, and then the data in the flash memory block is erased; a rewriting step of performing a write operation on a data page of the data block erased in the read/erase step; the method also comprises a reading and checking step, which can check the data page of the data block in which the data is written again, compare the number of error-reported data bits with the number of data bits of the data written in the writing step to obtain a first comparison result, and compare the address of the error-reported data block, the address of the data page with the address of the data block and the address of the data page corresponding to the data bits of the data written in the writing step to obtain a second comparison result, wherein the first and second comparison results are both written in the test result of the writing error correction capability of the storage device, so that the writing error data are inserted in advance at a predetermined position to be written in the data page on the storage chip or the storage device, and then the writing operation and the reading and checking are carried out, and the finally read data pass through the error correction circuit and the algorithm of the storage chip, Comparing the data processed by the program with the write error data inserted in advance, wherein the comparison result represents the write error correction capability of the storage device with the storage chip.
Drawings
FIG. 1 is a schematic structural framework diagram of the storage device in an embodiment of the invention;
FIG. 2 is a schematic diagram illustrating the steps of the method for testing the write error correction capability of the memory device according to the above embodiment of the present invention;
FIG. 3 is a block diagram and a block diagram of a flash memory chip according to the above embodiment of the present invention; and
FIG. 4 is a block diagram of a testing system for the write error correction capability of the storage device according to the above embodiment of the present invention.
Detailed Description
In order to make the technical means, the creation features, the achievement objectives and the efficacy of the present invention easy to understand, the following embodiments are specifically described with reference to the accompanying drawings for the method, the system and the storage medium for testing the write error correction capability of the storage device according to the present invention.
As shown in fig. 1 of the drawings, the storage device of the present invention has a memory chip 10, a control chip 20, an interface 30 for plug-in connection of the storage device with an external data source, and a PCB 40, wherein the memory chip 10 can store written data, wherein the control chip 20 stores a control program to ensure timely handling of errors by the storage device, thereby improving reliability of storage, and the control chip 20 and the interface 30 can bypass an error correction circuit of the storage device to directly connect and communicate with a flash memory block on the storage device and perform read/write operations.
As shown in FIG. 2 of the drawings, the method for testing the write error correction capability of a memory device according to the present invention comprises the following steps:
s0, selecting a blank flash memory block or a flash memory block with data erased, and writing data into the data page in the selected flash memory block;
s1, reading the data on all data pages on the flash memory block written with the data and storing the data in a cache, and then erasing the data in the flash memory block;
s2, rewriting the data page of the flash memory block of the erased data;
s3, checking the data page of the data block with the data written again, comparing the number of the error reporting data bits with the number of the data bits written in the step S0 to obtain a first comparison result, and writing the first comparison result into the test result of the write error correction capability of the storage device.
In step S3, the first comparison result is used to accurately determine whether there is a write error in the data written in the memory chip or the memory device to be tested.
In addition, after step S2 of the test method, the method further includes: and comparing the address of the error-reported data block and the address of the data page with the address of the data block and the address of the data page corresponding to the data bit of the data written in the step S0 to obtain a second comparison result, and writing the second comparison result into the test result of the write error correction capability of the storage device.
Wherein the second comparison result is used to determine whether the address of the error-corrected data page is a data page that is not a preset write error, thereby avoiding encountering an unexpected error.
In the step S0, the data page in the selected flash block may be a plurality of data pages, wherein the data page is the smallest writing unit, and in the step S0, random data is written into the memory chip or the memory device to be detected according to a preset memory address, wherein the memory address is distributed throughout each data block in the selected flash block of blank or erased data, but the address of the data page in each data block is distributed randomly.
Thus, when the data block to which data is written is selected and used normally later, and when a valid data page is written to the error page in step S0 during the rewrite operation in step S2, due to the characteristic that the data block can only be written once after flash erase, the flash chip will report a write error, and the memory device will trigger a subsequent error handling procedure.
For example, in the step S0, 8 data pages in the data block are selected, 300 bits of 15, 30, 45, 60, and 60 are respectively written, then erased and written again in the step S2, and 289bit errors are obtained and corrected through error correction circuit, algorithm, and program feedback, and the write error correction capability of the tested memory chip can be quantitatively evaluated by comparing the preset write error 300 bits with the errors 289 bits found by error correction. Further, under the condition that the addresses of the specific data block and the data page are known, the inspection program and the algorithm of the error correction circuit can make an accurate judgment according to the result of the 289 bits of error correction obtained by the feedback: the address of the data page corrected is a data page that is not a preset write error, thereby avoiding encountering an unexpected error.
In order to realize the testing of the write error correction capability of the storage device by the above testing method of the present invention, the present invention further provides a testing system of the write error correction capability of the storage device, which comprises a write module 100, a read erase module 200, a rewrite module 300 and a read verification module 400, wherein the write module 100 is configured to select a flash block with blank or erased data on the storage chip 10 or the storage device to be tested, and write data on the data page in the selected flash block, wherein the read erase module 200 reads the data on all data pages on the flash block with data written in the write module 100 and stores the data in a cache, and then erases the data in the flash block, wherein the rewrite module 300 performs a rewrite operation on the data page of the data block erased in the read erase step, wherein the read verification module 400 is configured to verify the data page of the data block with data rewritten, comparing the number of the error-reported data bits with the number of the data bits of the data written by the writing module 100 to obtain a first comparison result, and comparing the address of the error-reported data block, the address of the data page with the address of the data block and the address of the data page corresponding to the data bits of the written data to obtain a second comparison result, wherein the first comparison result and the second comparison result are both written into the test result of the error correction capability of the write error of the storage device.
The present embodiment further provides a storage medium, which stores a computer program, and the computer program, when executed by a processor, implements the method for testing write error correction capability of the storage device, wherein the storage medium is preferably a flash memory chip.
As shown in fig. 3 of the drawings, a Flash Memory Chip (Flash Memory Chip) includes a plurality of data blocks, each of which has a plurality of data pages, and is operated to erase in units of data blocks, to write and read in units of data pages, and to include a plurality of pages in one block, and each block must be erased before being written.
It should be noted that the data blocks to which the valid data is written are selected and read randomly, and the addresses of the selected data blocks in the flash memory chip are consecutive or alternate or both. The data block can be a plurality of data blocks, and the addresses of the data blocks can be continuous or selected at intervals. The interval and the continuous two schemes do not affect the result, the effect is not substantially different, and in order to improve the representativeness of the detection method, the inventor proposes to use the data block addresses which are continuously and simultaneously arranged with the interval for selecting the data blocks. In addition, a plurality of data pages may be selected. Generally, the protection unit of the control chip 20 for data is less than or equal to one data page, so each data page is usually protected independently.
In order to comprehensively try out the actual performance of the error correction of the memory chip under various error capacities, the size of data bits written in the data page of the selected flash memory block is determined according to the threshold value of the error correction algorithm of the memory device, the data bits are respectively set to be larger than the error correction threshold value of the memory device, smaller than the error correction threshold value of the memory device and equal to the error correction threshold value of the memory device, and three test results are correspondingly obtained. Obviously, the error correction threshold here is an error correction threshold identified by the chip manufacturer.
Specifically, data larger than the error correction threshold of the storage device is written into the data page of the selected flash memory block, and the test result in step S3 is recorded as a first detection result; or writing data equal to the error correction threshold of the storage device into the data page of the selected flash memory block, and recording the test result in the step S3 as a second detection result; or, writing data smaller than the error correction threshold of the storage device into the data page of the selected flash memory block, and recording the test result in step S3 as a third detection result.
Obviously, the storage medium may be an optical disc, a flash disk or a magnetic disc, a floppy disk, an optical disc, a DVD, a hard disk, a flash Memory, a CF card, an SD card, an MMC card, an SM card, a Memory Stick (Memory Stick), an xD card, a magnetic tape, a magneto-optical disk, etc., a computer program corresponding to the above method is stored or recorded on the storage medium, and a user can execute the method for testing the error correction capability of the write error on a corresponding storage device by installing or running the storage medium after obtaining the storage medium.
Effects and effects of the embodiments
The invention relates to a method, a system and a storage medium for testing the writing error correction capability of a storage device, wherein the testing method comprises a writing step, can select a flash memory block with blank or erased data, and writes data in a data page in the selected flash memory block; the method comprises a reading and erasing step, wherein the data on all data pages on a flash memory block in which data are written can be read and stored in a cache, and then the data in the flash memory block is erased; a rewriting step of performing a write operation on a data page of the data block erased in the read/erase step; the method also comprises a reading and checking step, which can check the data page of the data block in which the data is written again, compare the number of error-reported data bits with the number of data bits of the data written in the writing step to obtain a first comparison result, and compare the address of the error-reported data block, the address of the data page with the address of the data block and the address of the data page corresponding to the data bits of the data written in the writing step to obtain a second comparison result, wherein the first and second comparison results can be written into the data page of the memory device according to the test result of the error correction capability of the write error, so that the write error data is inserted in advance at a predetermined position to be written into the memory chip or the data page on the memory device, and then the writing operation and the reading and checking are carried out, and the finally read data is the data which passes through the error correction circuit and algorithm of the memory chip, Comparing the data processed by the program with the write error data inserted in advance, wherein the comparison result represents the write error correction capability of the storage device with the storage chip.
The present invention is not limited to the above-described embodiments, and it will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the principle of the present invention, and such modifications and improvements are also considered to be within the scope of the present invention.
Those not described in detail in this specification are within the skill of the art.
Claims (10)
1. A method for testing the write error correction capability of a storage device is characterized by comprising the following steps:
s0, selecting a blank flash memory block or a flash memory block with data erased, and writing data into the data page in the selected flash memory block;
s1, reading the data on all data pages on the flash memory block written with the data and storing the data in a cache, and then erasing the data in the flash memory block;
s2, rewriting the data page of the flash memory block of the erased data;
s3, checking the data page of the data block with the data written again, comparing the number of the error-reported data bits with the number of the data bits written in the step S0 to obtain a first comparison result, and writing the first comparison result into the test result.
2. The method according to claim 1, wherein after the step S2, the method further comprises:
and comparing the address of the error-reported data block and the address of the data page with the address of the data block and the address of the data page corresponding to the data bit of the data written in the step S0 to obtain a second comparison result, and writing the second comparison result into the test result.
3. The method according to claim 1, wherein said selecting the flash memory blocks with blank or erased data in step S0 comprises:
a plurality of flash blocks of blank or erased data are randomly selected in a memory chip, and addresses of the plurality of flash blocks are continuous, intermittent or coexisting continuously and intermittently.
4. The method of claim 3, wherein:
in step S0, data is randomly written in the flash memory block of the selected blank or erased data.
5. The method of claim 4, wherein:
writing data larger than an error correction threshold of the memory device in step S0, and recording the test result in step S3 as a first detection result; or,
writing data equal to an error correction threshold of the memory device in step S0, and recording the test result in step S3 as a second detection result; or,
in step S0, data smaller than the error correction threshold of the memory device is written, and the test result in step S3 is recorded as a third detection result.
6. The method of claim 1, wherein:
and randomly writing data in the storage device to be detected according to a preset storage address, wherein the storage address is distributed in each data block in the flash memory blocks for selecting blank or erased data, but the addresses of the data pages in each data block are distributed randomly.
7. A system for testing write error correction capability of a memory device, comprising:
the write-in module is used for selecting a blank flash memory block or a flash memory block with erased data on a memory chip or memory equipment to be detected and writing data into a data page in the selected flash memory block;
the reading and erasing module is used for reading the data on all the data pages on the flash memory block written with the data in the writing module, storing the data in a cache and then erasing the data in the flash memory block;
the rewriting module is used for performing rewriting operation on the data page of the erased data block in the reading and erasing module;
and the reading and checking module is used for performing reading and checking on the data page of the data block in which the data is written again, comparing the number of the error-reported data bits with the number of the data bits of the data written in the writing module to obtain a first comparison result, and writing the first comparison result into the test result.
8. The test system of claim 7, wherein:
and the reading and checking module is also used for comparing the address of the error-reported data block and the address of the data page with the address of the data block and the address of the data page corresponding to the data bit of the data written in the writing module to obtain a second comparison result, and writing the second comparison result into the test result.
9. The test system of claim 7, wherein:
and randomly writing data in the storage device to be detected according to a preset storage address, wherein the storage address is distributed in each data block in the flash memory blocks for selecting blank or erased data, but the addresses of the data pages in each data block are distributed randomly.
10. A storage medium storing a computer program, characterized in that:
the computer program when executed by a processor implements the steps in the method for testing write error correction capability of a memory device of any of claims 1 to 6.
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CN111930302A (en) * | 2020-06-30 | 2020-11-13 | 深圳佰维存储科技股份有限公司 | Data reading method and device, computer readable storage medium and electronic equipment |
CN112083891A (en) * | 2020-09-22 | 2020-12-15 | 深圳芯邦科技股份有限公司 | Method for detecting data block in memory and related equipment |
CN112397136A (en) * | 2021-01-21 | 2021-02-23 | 武汉精鸿电子技术有限公司 | Parameter testing method and device for semiconductor memory testing software |
CN113470728A (en) * | 2021-06-29 | 2021-10-01 | 成都佰维存储科技有限公司 | Error correction capability test method and device, readable storage medium and electronic equipment |
CN113778822A (en) * | 2021-08-04 | 2021-12-10 | 成都佰维存储科技有限公司 | Error correction capability test method and device, readable storage medium and electronic equipment |
CN114090354A (en) * | 2021-11-12 | 2022-02-25 | 深圳宏芯宇电子股份有限公司 | Memory module screening method and testing device |
CN114816833A (en) * | 2022-04-15 | 2022-07-29 | 巨翊科技(上海)有限公司 | Flash data writing method, device and system |
CN116880782A (en) * | 2023-09-08 | 2023-10-13 | 合肥康芯威存储技术有限公司 | Embedded memory and testing method thereof |
CN117435416A (en) * | 2023-12-19 | 2024-01-23 | 合肥康芯威存储技术有限公司 | Memory testing system and method |
Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0548564A2 (en) * | 1991-11-26 | 1993-06-30 | Hitachi, Ltd. | Storage device employing a flash memory |
CN1532829A (en) * | 2003-03-20 | 2004-09-29 | ��ʽ���綫֥ | Information memory medium, informaton reproducing device and method, and information recording method |
CN1577629A (en) * | 2003-07-29 | 2005-02-09 | 华为技术有限公司 | FLASH internal unit testing method |
US20060101304A1 (en) * | 2004-11-09 | 2006-05-11 | Sumihiro Miura | Disk array subsystem |
CN101082872A (en) * | 2006-06-02 | 2007-12-05 | 上海思必得通讯技术有限公司 | Method for error protecting and error correcting of flash memory data in products |
JP2008305451A (en) * | 2007-06-05 | 2008-12-18 | Hagiwara Sys-Com:Kk | State detection method of flash memory |
CN101419841A (en) * | 2008-12-09 | 2009-04-29 | 苏州大学 | Erasing and writing method for FLASH memory |
CN102279776A (en) * | 2010-06-11 | 2011-12-14 | 无锡中星微电子有限公司 | Error checking and correcting ability testing method and device |
CN103218271A (en) * | 2013-04-18 | 2013-07-24 | 华为技术有限公司 | Data error correction method and device |
CN103745753A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Error correction method and system based on flash memory |
CN104317753A (en) * | 2014-10-21 | 2015-01-28 | 中国科学院上海微系统与信息技术研究所 | Storage device and data reading-writing method thereof |
CN105095077A (en) * | 2015-07-17 | 2015-11-25 | 北京奇虎科技有限公司 | Automated testing method and device for user interfaces |
CN105469834A (en) * | 2014-09-12 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Testing method for embedded flash memory |
CN109542666A (en) * | 2017-09-21 | 2019-03-29 | 三星电子株式会社 | For supporting the device and its test method of error correcting code |
-
2019
- 2019-07-31 CN CN201910701427.7A patent/CN110459259A/en active Pending
Patent Citations (14)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0548564A2 (en) * | 1991-11-26 | 1993-06-30 | Hitachi, Ltd. | Storage device employing a flash memory |
CN1532829A (en) * | 2003-03-20 | 2004-09-29 | ��ʽ���綫֥ | Information memory medium, informaton reproducing device and method, and information recording method |
CN1577629A (en) * | 2003-07-29 | 2005-02-09 | 华为技术有限公司 | FLASH internal unit testing method |
US20060101304A1 (en) * | 2004-11-09 | 2006-05-11 | Sumihiro Miura | Disk array subsystem |
CN101082872A (en) * | 2006-06-02 | 2007-12-05 | 上海思必得通讯技术有限公司 | Method for error protecting and error correcting of flash memory data in products |
JP2008305451A (en) * | 2007-06-05 | 2008-12-18 | Hagiwara Sys-Com:Kk | State detection method of flash memory |
CN101419841A (en) * | 2008-12-09 | 2009-04-29 | 苏州大学 | Erasing and writing method for FLASH memory |
CN102279776A (en) * | 2010-06-11 | 2011-12-14 | 无锡中星微电子有限公司 | Error checking and correcting ability testing method and device |
CN103218271A (en) * | 2013-04-18 | 2013-07-24 | 华为技术有限公司 | Data error correction method and device |
CN103745753A (en) * | 2013-12-17 | 2014-04-23 | 记忆科技(深圳)有限公司 | Error correction method and system based on flash memory |
CN105469834A (en) * | 2014-09-12 | 2016-04-06 | 上海华虹宏力半导体制造有限公司 | Testing method for embedded flash memory |
CN104317753A (en) * | 2014-10-21 | 2015-01-28 | 中国科学院上海微系统与信息技术研究所 | Storage device and data reading-writing method thereof |
CN105095077A (en) * | 2015-07-17 | 2015-11-25 | 北京奇虎科技有限公司 | Automated testing method and device for user interfaces |
CN109542666A (en) * | 2017-09-21 | 2019-03-29 | 三星电子株式会社 | For supporting the device and its test method of error correcting code |
Non-Patent Citations (2)
Title |
---|
李进: "ECC嵌入BCH码的NAND闪存纠错算法", 《哈尔滨工程大学学报》 * |
李进: "ECC嵌入BCH码的NAND闪存纠错算法", 《哈尔滨工程大学学报》, 30 November 2012 (2012-11-30), pages 1399 - 1404 * |
Cited By (16)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
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CN111930302A (en) * | 2020-06-30 | 2020-11-13 | 深圳佰维存储科技股份有限公司 | Data reading method and device, computer readable storage medium and electronic equipment |
CN112083891A (en) * | 2020-09-22 | 2020-12-15 | 深圳芯邦科技股份有限公司 | Method for detecting data block in memory and related equipment |
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CN114816833A (en) * | 2022-04-15 | 2022-07-29 | 巨翊科技(上海)有限公司 | Flash data writing method, device and system |
CN114816833B (en) * | 2022-04-15 | 2023-07-18 | 巨翊科技(上海)有限公司 | Writing method, device and system of flash data |
CN116880782A (en) * | 2023-09-08 | 2023-10-13 | 合肥康芯威存储技术有限公司 | Embedded memory and testing method thereof |
CN116880782B (en) * | 2023-09-08 | 2023-12-05 | 合肥康芯威存储技术有限公司 | Embedded memory and testing method thereof |
CN117435416A (en) * | 2023-12-19 | 2024-01-23 | 合肥康芯威存储技术有限公司 | Memory testing system and method |
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