JP2008286963A - Display device and driving method of display device - Google Patents

Abstract

The present invention relates to a display device and a driving method of the display device, and is applied to, for example, an active matrix display device using an organic EL element using a polysilicon TFT to effectively increase power consumption and area of a peripheral circuit. Therefore, the accuracy of the drive signal output to the scanning line is improved as compared with the conventional case.
The present invention generates a selection signal with an amplitude of a second voltage system smaller than an amplitude of a third voltage system suitable for driving a pixel, and then converts the selection signal into an amplitude of a third voltage system. Based on the selection signal based on the amplitude of the third voltage system, the vertical enable signal based on the amplitude of the third voltage system is processed to generate a drive signal.
[Selection] Figure 1

Description

  The present invention relates to a display device and a display device driving method, and can be applied to an active matrix display device using an organic EL (Electro Luminescence) element using, for example, a polysilicon TFT (Thin Film Transistor). In the present invention, after the selection signal is generated with the amplitude of the second voltage system smaller than the amplitude of the third voltage system suitable for driving the pixel, the selection signal is converted into the amplitude of the third voltage system, and this third voltage is converted. By generating a drive signal by processing the vertical enable signal based on the amplitude of the third voltage system on the basis of the selection signal based on the system amplitude, it is possible to effectively avoid an increase in power consumption and area of the peripheral circuit. Compared with the above, the accuracy of the drive signal output to the scanning line is improved.

  2. Description of the Related Art Conventionally, in an active matrix display device using polysilicon, a display unit is formed by arranging pixels in a matrix on an insulating substrate such as a glass substrate, and the display unit is formed around the display unit on the insulating substrate. Are provided with a vertical drive circuit, a horizontal drive circuit, and the like.

  FIG. 15 is a block diagram showing this type of display device. In the display device 1, the display unit 2 is formed by arranging pixels 3 having current-driven light emitting elements using organic EL elements, for example, in a matrix. In the display unit 2, the scanning lines VSCAN1 (1) to VSCAN1 (4) are provided in the horizontal direction for the pixels 3 arranged in a matrix, and the scanning lines VSCAN1 (1) to VSCAN1 (4). Signal lines SIG (1) to SIG (3) are provided for each column so as to be orthogonal to each other. FIG. 15 shows a case where the display unit 2 is formed by 3 × 4 pixels. In the actual display device, a plurality of scanning lines are provided for one pixel 3 according to the configuration of each pixel 3. In the example of FIG. 15, one scanning line VSCAN1 (1) is provided for one pixel 3. The case where ~ VSCAN1 (4) is provided is shown.

  The H scan circuit 4 is a horizontal drive circuit, which receives image data D1 indicating the gradation of each pixel 3, and sequentially latches the image data D1 with a predetermined clock HCK to thereby each signal line SIG (1) to SIG. Sort to (3). Further, the H scan circuit 4 performs analog-digital conversion processing on the distributed image data D1, and generates a drive signal that indicates the gradation of the pixels 3 connected to the corresponding signal lines SIG (1) to SIG (3) by time division. It outputs to each signal line SIG (1) -SIG (3).

  The V scan circuit 5 is provided in the vertical drive circuit, generates drive signals S2 (1) to S2 (4) for controlling the operation of each pixel 3, and outputs them to the scan lines VSCAN1 (1) to VSCAN1 (4). . More specifically, as shown in FIG. 16, the V scan circuit 5 generates a vertical start pulse VST (FIG. 16A) synchronized with a vertical synchronization signal, which is a predetermined reference pulse, as a vertical clock VCK (FIG. B)), and sequentially selects the scanning lines VSCAN1 (1) to VSCAN1 (4) for each of the scanning lines VSCAN1 (1) to VSCAN1 (4). The selection signals S1 (1) to S1 (4) (FIG. 16 (D1) to (D4)). The V scan circuit 5 processes the vertical enable signal VEN (FIG. 16C) based on the selection signals S1 (1) to S1 (4), thereby scanning lines VSCAN1 (1) to VSCAN1 (4). Every time, drive signals S2 (1) to S2 (4) (FIG. 16 (E1) to (E4)) for controlling the operation of the pixels 3 connected to the scanning lines VSCAN1 (1) to VSCAN1 (4) are generated. To do. Here, the vertical enable signal VEN (FIG. 16C) is a reference signal for setting the timing of switching the signal level in each of the drive signals S2 (1) to S2 (4). In the example of FIG. The enable signal VEN (FIG. 16C) is selected by the selection signals S1 (1) to S1 (4), respectively, and the drive signals S2 (1) to S2 (4) (FIG. 16E1 to E4) are selected. Generate.

  In this type of display device 1, the vertical start pulse VST, the vertical clock VCK, and the vertical enable signal VEN are input to the V scan circuit 5 with an amplitude of 3 [V] or less. On the other hand, a polysilicon circuit requires a drive voltage of several V to several tens V, and a larger amplitude is required for driving the organic EL element. Therefore, the V scan circuit 5 uses the vertical start pulse VST, the vertical clock VCK, and the vertical enable signal VEN to drive the drive signals S2 (1) to S2 (4) of the scanning lines VSCAN1 (1) to VSCAN1 (4) (FIG. 16E1). ) To (E4)), the level conversion circuit is used to generate the amplitudes of these vertical start pulse VST, vertical clock VCK, vertical enable signal VEN, etc., and the amplitudes of the drive signals S2 (1) to S2 (4). Correct.

  FIG. 17 is a block diagram showing a specific configuration of the V scan circuit 5. The V scan circuit 5 inputs a vertical start pulse VST, a vertical clock VCK, and a vertical enable signal VEN with amplitudes of 3 [V] and 0 [V], for example, H level and L level. In the following, the amplitude of the input signal of the V scan circuit 5 is referred to as the amplitude of the first voltage system, and is indicated by the symbol I.

  In the V scan circuit 5, the level conversion circuits (L / S) 6 to 8 are adapted to drive the vertical start pulse VST, the vertical clock VCK, and the vertical enable signal VEN with the amplitude of the polysilicon circuit, and the organic EL element. For example, the H level and the L level are corrected to amplitudes of 10 [V] and 0 [V] which are smaller than the amplitude suitable for driving. In the following, the amplitude that is suitable for driving the polysilicon circuit and smaller than the amplitude suitable for driving the organic EL element is referred to as the amplitude of the second voltage system, and is denoted by reference numeral II.

  The shift registers (S / R) 10 (1) to 10 (4) sequentially transfer the vertical start pulse VST output from the level conversion circuit 6 using the vertical clock VCK output from the level conversion circuit 7, and the H level The selection signals S1 (1) to S1 (4) having the L level of 10 [V] and 0 [V] are generated.

  The logic circuits 11 (1) to 11 (4) perform a logical operation process on the vertical enable signal VEN (FIG. 16C) based on the selection signals S1 (1) to S1 (4), thereby scanning lines. For each of VSCAN1 (1) to VSCAN1 (4), drive signals S2 (1) to S2 (4) having H level and L level of 10 [V] and 0 [V] are generated. More specifically, the logic circuits 11 (1) to 11 (4) are configured by AND circuits in the example described above with reference to FIG. 16, and the vertical enable signal VEN output from the level conversion circuit 7 and each selection signal S 1 ( 1) to S1 (4) are respectively calculated to generate drive signals S2 (1) to S2 (4).

  The drive signal may be switched in accordance with a drive signal or the like output to an adjacent scanning line, or may be switched between an odd field and an even field by an interlace method. In such a case, the logic circuit 11 (1) to 11 (4) execute further complicated logical operation processing to generate drive signals S2 (1) to S2 (4).

  The level conversion circuits (L / S) 12 (1) to 12 (4) use the amplitudes of the drive signals S2 (1) to S2 (4) output from the logic circuits 11 (1) to 11 (4) as an organic signal. For example, H level and L level suitable for driving the EL element are converted into amplitudes of 15 [V] and −5 [V] and output. In the following, the amplitude suitable for driving the organic EL element is referred to as the amplitude of the third voltage system, and is denoted by reference numeral III. The buffer circuits 13 (1) to 13 (4) are connected to the scanning lines VSCAN 1 by the drive signals S 2 (1) to S 2 (4) output from the level conversion circuits (L / S) 12 (1) to 12 (4). (1) to VSCAN1 (4) are driven.

  FIG. 18 is a connection diagram showing the configuration of the level conversion circuits 6-8. The level conversion circuits 6 to 8 are so-called current mirror type level conversion circuits, and include P-channel transistors TR1 and TR2 each having a drain connected to the positive power supply VDDII corresponding to the H level of the second voltage system II. A current mirror circuit is provided, and the drains of N-channel transistors TR3 and TR4 are connected to the sources of the transistors TR1 and TR2, respectively. The gates of these transistors TR3 and TR4 are connected to the positive power supply VDDII, respectively. As shown in FIG. 19A, the input signal IN based on the amplitude of the first voltage system I and the inverted signal XIN of the input signal IN are the sources. Is input. Note that the source of the transistor TR4 may be set to a constant voltage reference voltage REF instead of the input of the inversion signal XIN. The reference voltage REF is an approximately average voltage of the H level and L level of the input signal IN. Set to

  As a result, in the level conversion circuits 6 to 8, the transistors TR3 and TR4 are complementarily turned on / off according to the input signal IN by the vertical start pulse VST, the vertical clock VCK, or the vertical enable signal VEN input by the first voltage system I. In operation, the drain voltages of the transistors TR3 and TR4 are changed with the amplitude of the second voltage system II. The level conversion circuits 6 to 8 output the drain voltage of the transistor TR3 via the buffer circuit 15, and thereby output the input signal IN with the amplitude of the first voltage system I with the amplitude of the second voltage system II. In FIG. 19, the voltage VSSII is the voltage of the negative power supply corresponding to the L level of the second voltage system II, and is the ground level in the example of FIG.

  Various circuit configurations can be applied to the level conversion circuits 6 to 8. FIG. 20 is a connection diagram showing a level conversion circuit having another circuit configuration in comparison with FIG. The level conversion circuit 17 in FIG. 20 is a current mirror type level conversion circuit similar to the level conversion circuit in FIG. 18, and is a current mirror composed of P-channel type transistors TR1 and TR2 each having a drain connected to the positive power supply VDDII. A circuit is provided, and the drains of N-channel transistors TR3 and TR4 are connected to the sources of the transistors TR1 and TR2, respectively. Here, in these transistors TR3 and TR4, the input signal IN having the amplitude of the first voltage system I and the inverted signal XIN of the input signal IN are input to the source, respectively, and the drain voltage of the transistor TR3 is output via the buffer circuit 15. The

  In the level conversion circuit 17, the inverted signal XIN and the input signal IN are input to the gates of the common-source transistors TR5 and TR6, respectively, and the drains of the transistors TR5 and TR6 are connected to the gates of the transistors TR3 and TR4. As a result, the inverted signal XIN and the input signal IN are input to the transistors TR3 and TR4 via the transistors TR5 and TR6. The drains of these transistors TR5 and TR6 are connected to the negative power supply VDDII (ground level in FIG. 20) via the transistors TR7 and TR8 whose gates are grounded.

  The drains of the transistors TR9 and TR10, whose gates and sources are connected in common with the transistors TR3 and TR4, are connected to the drains of the transistors TR5 and TR6. As a result, the level conversion circuit 17 turns on and off the transistors TR3 and TR4 with sufficient feedback gain, and outputs the input signal IN from the first voltage system I through the second voltage system II. The time chart of the level conversion circuit 17 in FIG. 20 is the same as the time chart of the level conversion circuit in FIG.

  On the other hand, level conversion circuits 12 (1) to 12 (4) for converting the second voltage system II to the third voltage system III are provided for each of the scanning lines VSCAN1 (1) to VSCAN1 (4). Therefore, the number provided in the V scan circuit 5 increases. Therefore, when the current mirror type level conversion circuit shown in FIGS. 18 and 20 is applied, the power consumption of the display device is remarkably increased.

  Therefore, for example, as shown in FIG. 21, a so-called latch type level conversion circuit is applied to the level conversion circuits 12 (1) to 12 (4). That is, these level conversion circuits 12 (1) to 12 (4) are connected to the gates of the transistors TR1 and TR2 whose drains are respectively connected to the positive power supply VDDII corresponding to the H level of the second voltage system II. The input signal IN and the inverted signal XIN of the input signal IN with the amplitude of the second voltage system II indicated by (A)) are input. Here, the sources of these transistors TR1 and TR2 are connected to the negative power source VSSIII corresponding to the L level of the third voltage system III via the transistors TR3 and TR4, respectively, and these transistors TR3 and TR4 are mutually gated. And the drain are connected. As a result, the level conversion circuits 12 (1) to 12 (4) are complementarily turned on and off according to the input signal IN and the inverted input signal XIN by the second voltage system II, as shown in FIG. The drain voltages of the transistors TR3 and TR4 are switched between the H level of the second voltage system II and the L level of the third voltage system III, and output signals OUT1 and XOUT1 based on the drain voltages are output to the transistors TR5 and TR6. To do.

  The sources of the transistors TR5 and TR6 are connected to the negative power source VSSIII of the third voltage system III, and the output signals OUT1 and XOUT1 are input to the gates, respectively. The gates of these transistors TR5 and TR6 are connected to the positive power supply VDDIII corresponding to the H level of the third voltage system III via the transistors TR7 and TR8, respectively. Is connected. As a result, the level conversion circuits 12 (1) to 12 (4) allow the third conversion circuit 12 according to the input signal IN and the inverted input signal XIN based on the amplitude of the second voltage system II, as shown in FIG. The drain voltages of the transistors TR5 and TR6 are switched between the H level and the L level of the voltage system III, and output signals OUT2 and XOUT2 based on the drain voltages are output.

  In this type of V scan circuit, as shown in FIG. 23 in comparison with FIG. 17, there is also a configuration in which the level conversion circuit 7 for correcting the amplitude of the vertical clock VCK is omitted. Instead of the registers 10 (1) to 10 (4), the vertical start pulse VST is sequentially transferred by the shift registers 19 (1) to 19 (4) having the SR latch circuit configuration shown in FIG.

  That is, the shift registers 19 (1) to 19 (4) (FIG. 24) output the output signals OUT (S 2 (1) to S 2 (4)) via the buffer circuit 21, respectively. An OR circuit 22 generates a logical sum signal of the input signal IN (1) to 19 (4) (FIG. 25B) and the input signal of the buffer circuit 21. In the shift registers 19 (1) to 19 (4), this logical sum signal is input to the source of the transistor TR2 via the inverter 23 and the common source transistor TR1. Here, the transistor TR2 has a drain connected to the positive power supply VDDII of the second voltage system II, and a drain connected to the positive power supply VDDII to input a logical sum signal to the gate. Connected. In the transistor TR2, the drain of the transistor TR4 that inputs the logical sum signal to the gate and inputs the inverted signal XVCK (FIG. 25A) of the vertical clock VCK to the source is connected to the gate, and is connected via the diode-connected transistor TR5. The vertical clock VCK is input to the source.

  In the shift registers 19 (1) to 19 (4), the transistor TR6 is connected to the diode-connected transistor TR5 in a current mirror circuit configuration, and the inverted signal XVCK of the clock VCK is input to the source of the transistor TR6. . The drain of the transistor TR6 is connected to the source of the transistor TR7. Similarly to the transistor TR2, a logical sum signal is input to the gate of the transistor TR7 via the transistor TR8. On the contrary to the transistor TR2, the clock VCK is input via the transistor TR9.

  In the shift registers 19 (1) to 19 (4), the source of the transistor TR7 is pulled up to the power supply voltage VDDII of the second voltage system II by the transistor TR10, and the source voltage of the transistor TR7 is supplied to the inverter 24 and the buffer circuit. 21 is output. As a result, the shift registers 19 (1) to 19 (4) use the vertical start pulse VST generated by the second voltage system as the vertical clock generated by the first voltage system I, as shown in FIGS. VCK and the inverted signal XVCK of the vertical clock VCK are sequentially transferred and output with the amplitude of the second voltage system. As shown in FIG. 26 in comparison with FIGS. 17 and 23, the selection signals S1 (1) to S1 (4) may be generated by the decoder 26 instead of the shift register.

  With regard to a display device using this type of organic EL element, various devices have been proposed in, for example, USP 5,684,365, Japanese Patent Laid-Open No. 8-234683, and the like.

  By the way, in the V scan circuits shown in FIGS. 17, 23 and 26, the amplitude of the second voltage system II is converted into the amplitude of the third voltage system III for each of the scanning lines VSCAN1 (1) to VSCAN1 (4). Level conversion circuits 12 (1) to 12 (4) are provided. On the other hand, the latch type level conversion circuit using the polysilicon circuit has a drawback that the delay time varies among the circuits, and thus the timing varies greatly among the circuits. As a result, in the V scan circuits according to FIGS. 17, 23, and 26, the timing varies between the drive signals S1 (1) to S1 (4) of the scan lines VSCAN1 (1) to VSCAN1 (4). There is a problem that variations affect the displayed image in various ways.

  As one method for solving this problem, instead of the latch-type level conversion circuits 12 (1) to 12 (4) described above with reference to FIG. 21, the timing variation between circuits is small as described above with reference to FIGS. It is conceivable to apply a current mirror type level conversion circuit. However, this method has a drawback that the power consumption is remarkably increased.

A method of operating the entire circuit including the peripheral circuits with the third voltage system III is also conceivable. However, in this method as well, power consumption is remarkably increased. This method also has the disadvantage that the size of the transistor increases and the area of the peripheral circuit increases.
USP 5,684,365 JP-A-8-234683

  The present invention has been made in consideration of the above points, and can effectively avoid an increase in power consumption and the area of peripheral circuits, and can improve the accuracy of a drive signal output to a scanning line as compared with the prior art. The present invention is intended to propose a display device that can be used and a method for driving the display device.

  In order to solve the above-mentioned problem, the invention of claim 1 is directed to driving a pixel by outputting a driving signal from a vertical driving circuit to a scanning line of a display portion formed by arranging pixels in a matrix. When applied to a display device that displays a desired image on the display unit, the vertical drive circuit processes a reference pulse and outputs a second voltage smaller than the amplitude of a third voltage system suitable for driving the pixel. A selection signal generation circuit that generates a selection signal for sequentially selecting the scanning lines for each scanning line according to the amplitude of the system; and the selection signal based on the amplitude of the second voltage system for each scanning line. The level conversion circuit for each scanning line for converting the amplitude to voltage system No. 3 and the output signal of the level conversion circuit for each scanning line for each scanning line are used to switch the signal level in the drive signal. Set the timing By processing the vertical enable signal by the amplitude of the third voltage system, so that and a driving signal generation circuit for each scanning line to generate said driving signal by said third voltage system.

  According to an eighth aspect of the present invention, a desired signal is output from the display unit by driving the pixel by outputting a drive signal from a vertical drive circuit to a scanning line of the display unit formed by arranging pixels in a matrix. Applying to the driving method of the display device for displaying an image, the reference pulse is processed, and the amplitude of the second voltage system smaller than the amplitude of the third voltage system suitable for driving the pixel is used for each scanning line. In addition, a selection signal generation step for generating a selection signal for sequentially selecting the scanning lines, and the selection signal based on the amplitude of the second voltage system is converted into the amplitude of the third voltage system for each scanning line. The timing for switching the signal level in the drive signal is set for each scanning line with reference to the output signal from the level conversion step for each scanning line and the level conversion step for each scanning line. By by the amplitude of the voltage system processes the vertical enable signal, to have a driving signal generation step in each scan line to generate the drive signal by said third voltage system.

  According to the configuration of the first or eighth aspect, the vertical enable signal for setting the timing of switching the signal level in the drive signal can be commonly supplied to each scanning line with the amplitude of the third voltage system. . Therefore, when the level conversion circuit is provided for each scanning line, it is possible to prevent the variation in the timing of the driving signal between the scanning lines, thereby improving the accuracy of the driving signal output to the scanning line as compared with the conventional case. be able to. In the case of the reference pulse, since the selection signal is generated with the amplitude of the second voltage system and then converted into the amplitude of the third voltage system, the whole is processed with the amplitude of the third voltage system. Such an increase in power consumption and the area of the peripheral circuit can be effectively avoided.

  According to the present invention, it is possible to effectively avoid an increase in power consumption and the area of the peripheral circuit, and to improve the accuracy of the drive signal output to the scanning line as compared with the prior art.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings as appropriate.

(1) Configuration of Embodiment FIG. 2 is a connection diagram illustrating a configuration of a pixel applied to the display device of Embodiment 1 of the present invention. In the display device of this embodiment, a display unit, a horizontal drive circuit, and a vertical drive circuit are integrally formed by a polysilicon TFT or the like on a glass substrate that is a transparent insulating substrate. In the display device of this embodiment, a display unit is formed by arranging pixels 33 in a matrix, and a horizontal drive circuit and a vertical drive circuit are provided around the display unit and on a glass substrate.

  Each pixel 33 is formed by an organic EL element 34 that is a current-driven light emitting element and a drive circuit (hereinafter referred to as a pixel circuit) for each pixel 33 that drives the organic EL element 34.

  In the pixel 33, the cathode of the organic EL element 34 is connected to a predetermined negative power source VSS2. In the pixel circuit, the anode of the organic EL element 34 is connected to the source of the transistor TR3, and the drain of the transistor TR3 is positively connected via the P-channel transistor TR2 that is turned on / off by the drive signal S22 supplied by the scanning line VSCAN2. It is connected to the side power supply VDD1. Thereby, the pixel 33 controls the light emission and non-light emission of the organic EL element 34 by this drive signal S22, and drives the organic EL element 34 with a current corresponding to the gate-source voltage of the transistor TR3.

  In the pixel circuit, both ends of a signal level holding capacitor Cs are connected to the gate and source of the transistor TR3. Further, in the pixel circuit, the gate of the transistor TR3 is connected to the signal line SIG via the transistor TR1 that is turned on and off by the drive signal S21 supplied by the scanning line VSCAN1. As a result, the pixel circuit controls the transistor TR1 to be turned on / off by the drive signal S21, sets the voltage at one end of the signal level holding capacitor Cs to the potential Vsig of the signal line SIG, and sets the emission luminance of the organic EL element 34.

  Further, in the pixel circuit, the gate of the transistor TR3 is connected to a predetermined fixed potential Vofs via the transistor TR5 that is turned on / off by the drive signal S24 supplied by the scan line VSCAN4, and the drive signal S23 supplied by the scan line VSCAN3. Thus, the source of the transistor TR3 is connected to a predetermined fixed potential Vini via the transistor TR4 that is turned on / off. The pixel circuit corrects variations in threshold voltage and mobility in the transistor T3 by on / off control of these transistors TR1, TR2, TR4, and TR5 by the scanning lines VSCAN1 to VSCAN4, and emits or does not emit light from the organic EL element 34. Control. In FIG. 2, Ce is a capacity of the organic EL element 34. The transistors TR1, TR3 to TR5 are N-channel transistors.

  That is, as shown in FIG. 3, in the pixel circuit, the transistors TR1, TR4, and TR5 are set in the off state and the transistor TR2 is set in the on state between the time points t1 and t2, thereby the signal level holding capacitor Cs. The organic EL element 34 is driven by a source current corresponding to the inter-terminal voltage to cause the organic EL element 34 to emit light (FIGS. 3A to 3D and 3E to 3G).

  Further, when the transistor TR2 is turned off by the drive signal S22 at the time t2, the pixel circuit gradually discharges the accumulated charge through the organic EL element 34, whereby the gate voltage Vg and the source voltage Vs of the transistor TR3 are changed. Decrease gradually. Also, when the anode potential of the organic EL element 34 is lowered due to the discharge of the accumulated charge and the voltage between the terminals of the organic EL element 34 falls to the threshold voltage, the discharge of the accumulated charge via the organic EL element 34 is stopped. Then, the decrease in the gate voltage Vg and the source voltage Vs stops, and the light emission of the organic EL element 34 stops.

  In the pixel circuit, at a predetermined time t3 after the light emission of the organic EL element 34 is stopped, the transistors TR4 and TR5 are turned on by the drive signals S23 and S24, whereby both ends of the signal level holding capacitor Cs are respectively connected. The fixed potentials Vofs and Vini are set. Here, the fixed potential Vofs is set to a voltage higher than a voltage obtained by adding the threshold voltage Vth of the transistor TR3 to the fixed potential Vini. The fixed potential Vini is set to a voltage sufficiently lower than a voltage obtained by adding the threshold voltage of the organic EL element 34 to the cathode potential Vss1 of the organic EL element 34.

  Thereafter, in the pixel circuit, the transistor TR4 is set to an off state by the drive signal S23, and then the transistor TR2 is set to an on state by the drive signal S22. Here, in this state, a charging current flows from the positive power supply VDD1 to the transistor TR4 side end of the signal level holding capacitor Cs via the transistors TR2 and TR3, and the voltage at the transistor TR4 side end gradually increases. Further, when the voltage across the signal level holding capacitor Cs becomes the threshold voltage Vth of the transistor TR3 due to this voltage rise, the transistor TR3 is switched to the OFF state, so that the positive power supply VDD1 via the transistors TR2 and TR3 is switched. Will stop charging. As a result, the pixel 33 sets the threshold voltage Vth of the transistor TR3 in the signal level holding capacitor Cs, and then sets the potential Vsig of the signal line SIG in the signal level holding capacitor Cs. Variations in emission luminance due to variations in threshold voltage Vth are corrected. A prior set of threshold voltages for this variation correction is shown by Vth correction in FIG.

  In the pixel circuit, the transistors TR2 and TR5 are subsequently turned off by the drive signals S22 and S24, and the transistor TR1 is subsequently turned on by the drive signal S21. As a result, the pixel circuit sets the signal level Vsig of the signal line SIG in the signal level holding capacitor Cs, and corrects it by the threshold voltage Vth of the transistor TR3 set in advance in the signal level holding capacitor Cs. 33 gradations are written in the signal level holding capacitor Cs.

Here, assuming that the signal level Vsig obtained by adding the fixed potential Vofs to the signal level Vdata corresponding to the light emission luminance of the organic EL element 34 is the signal level Vsig of the signal line SIG, when the transistor TR1 is switched on, the signal level holding capacitor Cs. The transistor TR1 side potential rises by the voltage Vdata, and in this state, a current represented by Ids = β / 2 · (Vdata) ² flows through the organic EL element 34. Here, β is represented by β = μ · (W / L) · Cox using the mobility μ of the transistor TR3, the unit capacitance Cox of the gate oxide film, and the gate length L.

  Subsequently, the pixel circuit keeps the signal line SIG connected to one end of the signal level holding capacitor Cs, the transistor TR2 is turned on by the drive signal S22, and the transistor TR3 is connected to the positive power source VDD1, After a certain time T has elapsed, the transistor TR1 is set to an off state. Here, when the transistor TR3 is connected to the power supply VDD1 with one end of the signal line SIG being connected to the signal level holding capacitor Cs, the transistor TR3 has a gate-source voltage based on the voltage between the terminals of the signal level holding capacitor. A corresponding source current flows, and the source side end of the signal level holding capacitor Cs is charged by this source current, so that the voltage gradually increases. Further, the rising speed of the source side end voltage becomes faster as the mobility of the transistor TR3 is larger. On the other hand, when the organic EL element 34 is driven by the transistor TR3, the greater the mobility of the transistor TR3, the greater the drive current of the organic EL element 34 and the higher the emission luminance.

  Thus, the pixel circuit connects the transistor TR3 to the power supply VDD1 in a state where the signal line SIG is connected to one end of the signal level holding capacitor Cs for a predetermined period T, and thus according to the mobility of the transistor TR3. The voltage between the terminals of the signal level holding capacitor Cs is corrected by an amount corresponding to the drive current of the organic EL element 34 that changes, and the variation in light emission luminance due to the variation in mobility is corrected.

Here, the current Ids flowing through the organic EL element 34 at the time of correcting the mobility is expressed by Ids = β / 2 · (1 / Vdata + β / 2 · T / C) ² . Here, C is the sum of the capacitance of the signal level holding capacitor Cs and the capacitance Ce of the organic EL element 34. Therefore, by appropriately setting the period T, variation in mobility of the transistor TR3 can be corrected.

  Accordingly, after the period T, when the transistor TR1 is switched off by the drive signal S21 after this period T, the organic EL element 34 is driven by the drive current corresponding to the inter-terminal voltage held in the signal level holding capacitor Cs. Light emission will start.

  In the display device of this embodiment, a V scan circuit is provided for each of the four scan lines VSCAN1 to VSCAN4 connected to the pixel 33, and the drive signal S21 of the scan lines VSCAN1 to VSCAN4 corresponding to each V scan circuit is provided. ~ S24 are generated. Thus, as described above with reference to FIGS. 2 and 3, in this display device, the transistor TR3 is set to the power supply VDD1 for a certain period T while the signal line SIG is connected to one end of the signal level holding capacitor Cs. Since the connection is used to correct the variation in mobility of the transistor TR3, if the period T varies from line to line, the image quality significantly deteriorates. In addition, the variation in the period T is caused by the variation in timing in the drive signals S21 and S22 related to the on / off control of the transistors TR1 and TR2.

  Therefore, in this embodiment, four V scan circuits for generating the drive signals S21 to S24 are provided in the vertical drive circuit, and at least the drive signals S21 and S22 related to the correction of the mobility are shown in FIG. It is generated by the V scan circuit 36. The other drive signals S23 and S24 may be configured in the same manner as the V scan circuits of these drive signals S21 and S22, or may be configured by any of the V scan circuits described above for the conventional example.

  The V scan circuit 36 converts the vertical start pulse VST and the vertical clock VCK based on the amplitude of the first voltage system I into the amplitude of the second voltage system II by the level conversion circuits 6 and 7, and shift register (S / R) The vertical start pulse VST is sequentially transferred by the vertical clock VCK by 10 (1) to 10 (4), thereby generating the selection signals S1 (1) to S1 (4) by the second voltage system II. .

  The V scan circuit 36 sends the selection signals S1 (1) to S1 (4) to the level conversion circuit 12 via the first logic circuits 38 (1) to 38 (4) respectively operating in the second voltage system II. Input to (1) to 12 (4) and convert to the amplitude of the third voltage system III. Here, the level conversion circuit described above with reference to FIG. 21 with low power consumption is applied to the level conversion circuits 12 (1) to 12 (4).

  The V scan circuit 36 corrects the vertical enable signal VEN based on the amplitude of the first voltage system I to the amplitude of the third voltage system III via the level conversion circuit 37. The V scan circuit 36 inputs the vertical enable signal VEN from the third voltage system III to the second logic circuits 39 (1) to 39 (4) operating in the third voltage system III, and converts the level. The output signals of the circuits 12 (1) to 12 (4) are respectively input. The V scan circuit 36 includes drive signals S21 (1) to S21 (1) to 38 (1) to 38 (4) and logical operations by the corresponding second logic circuits 39 (1) to 39 (4), respectively. S21 (4) and S22 (1) to S22 (4) are generated, and the drive signal output from the logic circuits 39 (1) to 39 (4) is output via the inverters 13 (1) to 13 (4). To do.

  For example, a drive signal that can be obtained by a simple logical product of the selection signal S2 and the enable signal VEN, such as the drive signal S22, can be set to the first logic circuits 38 (1) to 38 ( 4) may be omitted.

  On the other hand, the horizontal drive circuit has the same configuration as the horizontal drive circuit described above with reference to FIG.

(2) Operation of Embodiment In the above configuration, in the display device of this embodiment (see FIG. 15), display is performed by a horizontal drive circuit provided around a display portion formed by arranging pixels 33 in a matrix. The drive signal Vsig indicating the gradation of each pixel 33 is output to the signal line SIG of the part. In response to the output of the drive signal Vsig, drive signals S21 to S24 are generated by a vertical drive circuit provided around the display unit, and the signal level of the signal line SIG is set to each pixel by the drive signals S21 to S24. At the same time, the operation of each pixel 33 is controlled, whereby the organic EL element 34 provided in each pixel 33 emits light according to the signal level of the signal line SIG. Thereby, in this display device, a desired image can be displayed on the display unit 2.

  In each pixel 33 (FIGS. 2 and 3), the transistors TR1, TR2, TR4, and TR5 are turned on and off by the drive signals S21 to S24 from the vertical drive circuit, and the transistors TR4 and TR5 are set to the on state to maintain the signal level. After both end potentials of the capacitor Cs are set to predetermined fixed potentials Vofs and Vini, respectively, the source side end of the signal level holding capacitor Cs is separated from the fixed potential Vini by the drive signal S23 from the vertical drive circuit, and the transistor TR3 is connected to the power supply VDD1, thereby the potential difference between both ends of the signal level holding capacitor Cs is set to the threshold voltage Vth of the transistor TR3, thereby preventing variations in light emission luminance due to variations in the threshold voltage Vth of the transistor TR3. Is done.

  Thereafter, in the pixel 33, the gate side end of the signal level holding capacitor Cs is connected to the signal line SIG, and the potential Vsig of the signal line SIG is set to the signal level holding capacitor Cs, and driving according to the set voltage is performed. The organic EL element 34 emits light by current.

  When setting the potential Vsig of the signal line SIG to the signal level holding capacitor Cs, the pixel 33 is connected to the signal line SIG at the gate side end of the signal level holding capacitor Cs for a certain period T. After the transistor TR3 is connected to the power supply VDD1, thereby correcting the potential difference between both ends of the signal level holding capacitor Cs according to the mobility of the transistor TR3, one end of the signal level holding capacitor Cs is connected to the signal level Vsig of the signal line SIG. Set to As a result, the pixel 33 can be prevented from having variations in emission luminance due to variations in mobility of the transistor TR3.

  However, when the transistor TR3 is connected to the power supply VDD1 and the mobility variation of the transistor TR3 is corrected with the gate side end of the signal level holding capacitor Cs connected to the signal line SIG for a certain period T as described above. If the period T varies between the scanning lines VSCAN1 (1) to VSCAN1 (4), the image quality deteriorates. On the other hand, in the V scan circuit according to the conventional configuration that generates the drive signals for the scan lines VSCAN1 (1) to VSCAN1 (4) in the vertical drive circuit, the second scan line VSCAN1 (1) to VSCAN1 (4) Level conversion circuits 12 (1) to 12 (4) for correcting the amplitude of the voltage system II to the amplitude of the third voltage system III are provided (FIGS. 17, 23, and 26). In 1) to 12 (4), there is a disadvantage that the timing variation in the output signal is large between circuits.

  Therefore, if the drive signals S21 and S22 for determining the period T relating to the mobility correction among the drive signals S21 to S24 of the pixel 33 are configured by the V scan circuit of the conventional configuration, the period T varies between lines. As a result, the light emission luminance varies between the lines.

  Therefore, in this embodiment, the V scan circuit of the drive signals S21 and S22 for determining at least the period T related to the mobility correction (FIG. 1) is suitable for driving the polysilicon TFT with the vertical start pulse VST and the vertical clock VCK. In addition, the processing is performed by the second voltage system II having a smaller amplitude than the third voltage system III suitable for driving the organic EL element, and the output signal of the processing result and the timing at which the signal level is switched in the drive signals S21 to S24 are set. After the vertical enable signal VEN to be corrected to the amplitude of the third voltage system III, drive signals S21 and S22 are generated.

  In this case, the vertical enable signal VEN whose amplitude is corrected by one level conversion circuit 37 is supplied to the system of each scanning line, thereby effectively varying the timing of the drive signals S21 and S22 between the scanning lines. It can be avoided. Therefore, in the display device, it is possible to effectively avoid the variation between lines in the period T for correcting the mobility, and display a high-quality image with a high yield.

  In particular, the variation in timing of the drive signals S21 and S22 relating to the correction of the mobility variation can be prevented, so that the mobility correction variation between the scanning lines can be effectively avoided, and a display device with higher image quality can be obtained. Obtainable.

  In this embodiment, the selection signals S1 (1) to S1 (4) are processed by the second voltage system which is smaller than the amplitude of the third voltage system suitable for driving the organic EL element. As a result, the power consumption and the increase in the area of the peripheral circuit can be effectively avoided as compared with the case where the whole is processed with the amplitude of the third voltage system.

(3) Effects of the embodiment According to the above configuration, after the selection signal is generated with the amplitude of the second voltage system smaller than the amplitude of the third voltage system suitable for driving the pixel, the third voltage system By converting the signal into amplitude and processing the vertical enable signal based on the amplitude of the third voltage system on the basis of the selection signal based on the amplitude of the third voltage system to generate the drive signal, the power consumption, the area of the peripheral circuit Therefore, the accuracy of the drive signal output to the scanning line can be improved as compared with the conventional case.

  In addition, after converting the amplitude of the vertical start pulse, which is a reference pulse based on the amplitude of the first voltage system smaller than the amplitude of the second voltage system, into the amplitude of the second voltage system, it is sequentially transferred to the second voltage system. By generating the selection signal based on the amplitude, the previous circuit block for generating the vertical start pulse can be created by a general-purpose integrated circuit technique.

  In addition, it can be applied to the generation of a drive signal for a fixed period that corrects at least the variation in light emission luminance due to the variation in the mobility of the transistor, and the accuracy of the drive signal is improved so that the mobility variation can be corrected with high accuracy. The desired image can be displayed with high image quality.

  FIG. 4 is a block diagram showing a V scan circuit applied to the display device according to the second embodiment of the present invention in comparison with FIGS. The display device of this embodiment is configured in the same way as the display device of the first embodiment except that the V scan circuit 46 shown in FIG. 4 is applied instead of the V scan circuit 36 described above with reference to FIG. The

  In this V scan circuit 46, instead of the shift registers 10 (1) to 10 (4), the vertical start pulse VST is sequentially applied by the shift registers 19 (1) to 19 (4) having the SR latch circuit configuration described above with reference to FIG. Forward.

  As in this embodiment, the same effect as that of the first embodiment can be obtained when the vertical start pulse VST is transferred by the shift register having the SR latch circuit configuration to generate the selection signal.

  FIG. 5 is a block diagram showing a V scan circuit applied to the display device according to the third embodiment of the present invention, in comparison with FIGS. 1 and 26. The display device of this embodiment is configured in the same way as the display device of the first embodiment except that the V scan circuit 47 shown in FIG. 4 is applied instead of the V scan circuit 36 described above with reference to FIG. The

  The V scan circuit 46 generates selection signals S1 (1) to S1 (4) by the decoder 26 instead of the shift registers 10 (1) to 10 (4).

  As in this embodiment, when the selection signal is generated by the decoder, the same effect as in the first embodiment can be obtained.

  FIG. 6 is a time chart for explaining drive signals applied to the display device according to the fourth embodiment of the present invention in comparison with FIG. In this embodiment, in the drive signal S21 for determining the end of the period T for correcting the mobility, the signal level is set to gradually fall, and as a result, the signal level Vsig set to the signal line SIG is higher. The transistor TR1 is set to be turned off at a fast time. The display device of this embodiment is configured in the same manner as the display device of the above-described embodiment except that the configuration relating to the drive signal S21 is different.

  That is, in the period T for correcting the mobility described in the first embodiment, the current Ids flowing through the transistor TR3 changes according to the voltage between the gate and the source of the transistor TR3, so that the signal level Sig of the signal line SIG is higher. That is, as the organic EL element 34 emits light at a higher luminance level, a larger current flows. Therefore, the mobility variation can be corrected in a shorter time as the organic EL element 34 emits light at a higher luminance level.

  Accordingly, in this embodiment, the drive signal S21 for determining the end of the period T for correcting the mobility is set so that the signal level gradually falls, and the organic EL element 34 emits light at a high luminance level. The transistor TR1 is quickly turned off, and the period for correcting the mobility variation is shortened. As described above, when the organic EL element 34 emits light at a higher luminance level, if the period for correcting the variation in mobility is shortened, the image quality can be further improved and the uniformity can be improved. FIG. 6 shows the case where the drive signal S21 is generated so that the signal level decreases almost linearly with the passage of time. However, in practice, the signal level is decreased exponentially and appropriately Variations in mobility can be corrected.

  In this embodiment, the vertical enable signal VEN is generated with the amplitude of the first voltage system I by a predetermined signal generation circuit so that the signal level on the falling side gradually falls so as to correspond to the drive signal S21. Is done. Also, the enable signal VEN having the amplitude of the voltage system I is amplified by the amplifier circuit having the analog signal processing circuit configuration, and the enable signal VEN having the amplitude of the third voltage system is generated. In this embodiment, this amplifier circuit functions as a level conversion circuit.

  In this embodiment, in the V scan circuit of FIG. 1, FIG. 4, or FIG. 5, the level conversion circuit 37 is omitted, and the vertical enable signal VEN based on the amplitude of the third voltage system is directly output from the logic circuits 39 (1) to 39 (1). 39 (4). The logic circuits 39 (1) to 39 (4) are constituted by analog signal processing circuits, and the enable signal VEN based on the amplitude of the third voltage system is selected by the selection signals S1 (1) to S1 (4), respectively. Drive signals S21 (1) to S21 (4).

  The drive signal S22 that defines the start point of the period T for correcting the mobility variation is generated in the same manner as in the above-described embodiment.

  According to this embodiment, when the signal level of the drive signal is gradually lowered and the organic EL element emits light at a higher luminance level, the period for correcting the variation in mobility is shortened to improve the image quality. Even if it exists, the effect similar to the above-mentioned Example can be acquired.

  FIG. 7 is a connection diagram illustrating a configuration of a pixel applied to the display device according to the fifth exemplary embodiment of the present invention in comparison with FIG. 2, and FIG. 8 is a time chart for explaining the operation of the pixel 53. is there.

  In the pixel 53 of this embodiment, the transistor TR2 (see FIG. 2) that connects the organic EL element 34 to the power supply VDD1 is omitted, and the light emission and non-light emission of the organic EL element 34 are controlled by directly controlling the potential of the power supply VDD1. (FIG. 8 (B), (D) to (F)). Further, the transistor TR4 for connecting the signal level holding capacitor Cs to the fixed potential Vini is omitted, and the voltage at the end of the signal level holding capacitor Cs on the side of the organic EL element 34 is made sufficiently low by discharging through the organic EL element 34. Then, the threshold voltage Vth of the transistor TR3 is set in the signal level holding capacitor Cs (FIGS. 8C and 8D). Even after the threshold voltage Vth is set in the signal level holding capacitor Cs, the drain voltage of the transistor TR3 is held as it is raised, and the variation in mobility of the transistor TR1 is corrected only by the on / off control of the transistor TR1. Further, the signal level Vsig of the signal line SIG is set in the signal level holding capacitor Cs (FIGS. 8A, 8D to 8F).

  Corresponding to the configuration of the pixel 53, in the vertical drive circuit of this embodiment, at least the drive signals S21 (1) to S21 (4) for driving the transistor TR1 are the V scans of FIG. 1, FIG. 4, or FIG. Generated by the circuit.

  According to this embodiment, the pixel can be configured with a simpler configuration, and the same effect as in the above-described embodiment can be obtained.

  FIG. 9 is a connection diagram illustrating a configuration of a pixel applied to the display device according to the sixth embodiment of the present invention in comparison with FIG. 2, and FIG. 10 is a time chart for explaining the operation of the pixel 54. is there. In the pixel 54, the source of the P-channel transistor TR3 is connected to the positive power supply VDD1, and the source of the transistor TR3 is connected to the organic EL element 34 via the transistor TR2 that is turned on / off by the drive signal S22. Thus, the pixel 54 controls light emission and non-light emission of the organic EL element 34 by on / off control of the transistor TR2 by the drive signal S22 (FIGS. 10B, 10E to 10G), and further the transistor TR3. The organic EL element 34 is driven by a drive current corresponding to the gate-source voltage.

  The transistor TR3 for driving the organic EL element 34 includes a series circuit of a predetermined capacitor Cc and a signal level holding capacitor Cs provided between the gate and the positive power supply VDD1, and is connected via a transistor TR5 that is turned on / off by a drive signal S24. Thus, the connection midpoint of this series circuit is connected to the fixed potential Vofs, and the gate / drain is short-circuited by the transistor TR4 that is turned on / off by the drive signal S23. Further, a transistor TR1 is provided which is turned on / off by the drive signal S21 and connects the signal level holding capacitor Cs to the signal line SIG.

  When the pixel 54 switches the transistor TR2 to the OFF state by the driving signal S22 and stops the light emission of the organic EL element 34, as shown in the preparation in FIG. 10G, the transistor TR5 is driven by the driving signal S24 after a certain period of time has elapsed. Is switched on, and the capacitor Cc side end of the signal level holding capacitor Cs is set to the fixed potential Vofs (FIGS. 10D and 10E). In addition, the transistor TR2 is turned on by the drive signal S22, and the transistor TR4 is turned on by the drive signal S23. The accumulated charge of the capacitor Cs is discharged through the organic EL element 34, and the gate voltage of the transistor TR3 is changed. It is lowered (FIGS. 10B, 10C, and 10F).

  In the pixel 54, the transistor TR2 is subsequently turned off by the drive signal S22, whereby the transistor TR3 side end of the capacitor Cc is charged by the positive power supply VDD1 via the transistor TR3, and the gate voltage Vg of the transistor TR3 gradually increases. (FIGS. 10B and 10F). When the gate voltage Vg of the transistor TR3 becomes a voltage that falls by the threshold voltage Vth of the transistor TR3 from the potential of the positive power supply VDD1 due to the rise of the gate voltage Vg, the transistor TR3 is turned off, and the transistor TR3 The charging of the capacitor Cc via the terminal is stopped, whereby the rise of the gate voltage Vg is stopped. As a result, the pixel 54 sets a voltage corresponding to the threshold voltage Vth of the transistor TR3 in the capacitor Cc, thereby preventing variations in emission luminance due to variations in the threshold voltage Vth of the transistor TR3.

  Subsequently, in the pixel 54, the transistors TR4 and TR5 are set to the off state by the drive signals S23 and S24. Thereafter, in the pixel 54, the transistor TR1 is turned on by the drive signal S21, and the potential at the capacitor Cc side end of the signal level holding capacitor Cs is set to the potential Vsig of the signal line SIG. However, the potential Vsig of the signal line SIG is Vofs + Vdata. As a result, the gate voltage Vg of the transistor TR3 becomes a voltage biased by the threshold voltage Vth set in the capacitor Cc with respect to the potential Vsig of the signal line SIG, and the gate-source voltage of the transistor TR3 is A voltage obtained by correcting Vsig of SIG with a threshold voltage Vth is set.

  Subsequently, in the state where the signal level holding capacitor Cs is connected to the signal line SIG, in the pixel 54, the transistor TR3 is switched on by the drive signal S23 for a certain period T, whereby the capacitor Cc via the transistor TR3 is switched. Thus, the mobility of the transistor TR3 is corrected. After that, the transistors TR4 and TR1 are sequentially switched off by the drive signals S23 and S21, and then the transistor TR2 is switched on by the drive signal S22 and driving of the organic EL element 34 is started.

  As a result, in this embodiment, if the timing varies with the drive signal S23 for correcting the mobility variation, the mobility variation correction varies between the scanning lines, and the image quality deteriorates. Therefore, in this embodiment, at least the drive signal S23 related to the mobility variation correction is generated by the V scan circuit of FIG. 1, FIG. 4, or FIG.

  According to this embodiment, even when the organic EL element 34 is driven by the P-channel transistor TR3, the same effect as that of the above-described embodiment can be obtained.

  FIG. 11 is a block diagram showing a V scan circuit applied to the display device according to the seventh embodiment of the present invention in comparison with FIG. The display device of this embodiment is the same as the display device of each embodiment described above except that the V scan circuit 66 shown in FIG. 11 is applied instead of the V scan circuit of each embodiment described above. Composed.

  Here, the V scan circuit 66 is configured in the same manner as the V scan circuit 36 of the first embodiment except that the vertical start pulse VST and the vertical clock VCK are directly input by the second voltage system.

  Even if the vertical start pulse VST and the vertical clock VCK are input by the second voltage system as in this embodiment, the same effect as in the above-described embodiment can be obtained.

  FIG. 12 is a block diagram showing a V scan circuit applied to the display device according to the eighth embodiment of the present invention in comparison with FIG. The display device of this embodiment is the same as the display device of each embodiment described above except that the V scan circuit 67 shown in FIG. 12 is applied instead of the V scan circuit of each embodiment described above. Composed.

  Here, the V scan circuit 67 converts the enable signal VEN by the first voltage system into the amplitude of the second voltage system by the level conversion circuit 37A, and then converts it to the amplitude of the third voltage system by the level conversion circuit 37B. Convert.

  As in this embodiment, after the enable signal is converted into the amplitude of the second voltage system, it is converted into the amplitude of the third voltage system, and the same effect as in the above-described embodiment can be obtained.

  FIG. 13 is a block diagram showing a V-scan circuit applied to the display device according to the ninth embodiment of the present invention in comparison with FIG. The display device of this embodiment is the same as the display device of each embodiment described above except that the V scan circuit 68 shown in FIG. 13 is applied instead of the V scan circuit of each embodiment described above. Composed.

  Here, the V scan circuit 69 groups the logic circuits 39 (1) to 39 (4), and sends the enable signal VEN to the logic circuit 39 (1) via the buffers 69 (1) and 69 (2) for each group. ) To 39 (4). In this case, the output lines of the buffers 69 (1) and 69 (2) may be connected as shown in FIG. 14 in comparison with FIG.

  Even if the logic circuits are grouped and driven as in this embodiment, the same effects as in the above-described embodiment can be obtained.

  In the above-described embodiment, the case where the drive signals and the like related to the control of the transistors TR1 and TR2 are each configured by the V scan circuit shown in FIG. 1 and the like has been described. If the deterioration of the accuracy of the drive signal can be tolerated, the present invention may be applied only to the V scan circuit of any drive signal.

  In the above-described embodiment, the case where the vertical start pulse synchronized with the vertical synchronization signal is applied to the reference pulse and processed by the V scan circuit has been described. However, the present invention is not limited to this, and the generation of the scanning line drive signal is performed. The present invention can be widely applied to a V scan circuit that processes various reference pulses as a reference to generate a drive signal.

  In the above-described embodiments, the case where the pixel is configured by various pixel circuits has been described. However, the present invention is not limited to this, and the present invention is widely applied to the case where the pixel is configured by various pixel circuits other than those described above. be able to.

  In the above-described embodiments, the case where the present invention is applied to a display device using an organic EL element has been described. However, the present invention is not limited thereto, and the display device includes various current-driven light emitting elements, and further includes a liquid crystal display. The present invention can be widely applied to other display devices.

  The present invention can be applied to an active matrix display device using an organic EL (Electro Luminescence) element using, for example, a polysilicon TFT (Thin Film Transistor).

It is a block diagram which shows the V scan circuit applied to the display apparatus of Example 1 of this invention. It is a connection diagram which shows the pixel applied to the display apparatus of Example 1 of this invention. 3 is a time chart of the pixel in FIG. 2. It is a block diagram which shows the V scan circuit applied to the display apparatus of Example 2 of this invention. It is a block diagram which shows the V scan circuit applied to the display apparatus of Example 3 of this invention. It is a time chart of the pixel in the display apparatus of Example 4 of this invention. It is a connection diagram which shows the pixel applied to the display apparatus of Example 5 of this invention. It is a time chart of the pixel of FIG. It is a connection diagram which shows the pixel applied to the display apparatus of Example 6 of this invention. 10 is a time chart of the pixel in FIG. 9. It is a block diagram which shows the V scan circuit applied to the display apparatus of Example 7 of this invention. It is a block diagram which shows the V scan circuit applied to the display apparatus of Example 8 of this invention. It is a block diagram which shows the V scan circuit applied to the display apparatus of Example 9 of this invention. FIG. 13 is a block diagram showing a V scan circuit according to another example. It is a block diagram which shows the conventional display apparatus. It is a time chart of the display apparatus of FIG. FIG. 16 is a block diagram showing a V scan circuit applied to the display device of FIG. 15. FIG. 18 is a connection diagram illustrating a level conversion circuit of the V scan circuit of FIG. 17. It is a time chart of the level conversion circuit of FIG. FIG. 18 is a connection diagram illustrating another example of the level conversion circuit in the V scan circuit of FIG. 17. FIG. 18 is a connection diagram illustrating another level conversion circuit of the V scan circuit of FIG. 17. It is a time chart of the level conversion circuit of FIG. FIG. 16 is a block diagram illustrating another example of a V scan circuit applied to the display device of FIG. 15. FIG. 24 is a connection diagram illustrating a shift register of the V scan circuit of FIG. 23. It is a time chart of the shift register of FIG. FIG. 16 is a block diagram illustrating another example of a V scan circuit applied to the display device of FIG. 15.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Display apparatus, 2 ... Display part, 3, 33, 53, 54 ... Pixel, 4 ... H scan circuit 5, 18, 36, 46, 47, 66, 67, 68, 69 ... V Scan circuit 6, 7, 8, 12 (1) to 12 (4), 37, 37A, 37B... Level conversion circuit, 10 (1) to 10 (4), 19 (1) to 19 (4). ... shift registers, 11 (1) to 11 (4), 38 (1) to 38 (4), 39 (1) to 39 (4) ... logic circuits, 26 ... decoders, TR1 to TR10 ... transistors, Cc, Cs: Capacitor

Claims (8)

In a display device that displays a desired image on the display unit by driving the pixel by outputting a drive signal from a vertical drive circuit to a scanning line of the display unit formed by arranging pixels in a matrix.
The vertical drive circuit includes:
A reference pulse is processed to generate a selection signal for sequentially selecting the scanning lines for each scanning line with the amplitude of the second voltage system smaller than the amplitude of the third voltage system suitable for driving the pixels. A selection signal generation circuit;
A level conversion circuit for each scanning line for converting the selection signal based on the amplitude of the second voltage system into the amplitude of the third voltage system for each scanning line;
For each scanning line, the vertical enable signal based on the amplitude of the third voltage system for setting the timing of switching the signal level in the drive signal is processed with reference to the output signal of the level conversion circuit for each scanning line. Thus, a display device comprising: a drive signal generation circuit for each scanning line that generates the drive signal by the third voltage system. The selection signal generation circuit includes:
A reference pulse level conversion circuit that converts the amplitude of the reference pulse with the amplitude of the first voltage system smaller than the amplitude of the second voltage system into the amplitude of the second voltage system;
The display device according to claim 1, further comprising: a shift register that sequentially transfers reference pulses based on the second voltage system to generate the selection signal based on the amplitude of the second voltage system. The selection signal generation circuit includes:
A reference pulse level conversion circuit that converts the amplitude of the reference pulse with the amplitude of the first voltage system smaller than the amplitude of the second voltage system into the amplitude of the second voltage system;
The display device according to claim 1, further comprising: a decoder that processes a reference pulse and a vertical clock generated by the second voltage system to generate the selection signal based on an amplitude of the second voltage system. . The display device according to claim 1, wherein the reference pulse is a vertical start pulse synchronized with a vertical synchronization signal. A vertical enable signal level converting circuit for converting the amplitude of the vertical enable signal from the amplitude of the first voltage system smaller than the amplitude of the second voltage system to the amplitude of the third voltage system; The display device according to claim 1. The level conversion circuit for the vertical enable signal includes:
After the vertical enable signal is inputted with the amplitude of the first voltage system and converted into the amplitude of the second voltage system, the vertical enable signal having the amplitude of the second voltage system is converted to the third voltage system. The display device according to claim 5, wherein the display device converts the amplitude. The pixel is
A current-driven light emitting device;
A capacitor for holding the signal level;
A driving transistor for driving the light emitting element in accordance with a voltage across terminals of the signal level holding capacitor;
A signal line transistor for setting the potential of the one end to the potential of the signal line by connecting one end of the signal level holding capacitor to the signal line;
After correcting the variation in mobility of the driving transistor by changing the voltage between the terminals of the signal line capacitor by the driving transistor for a certain period, the voltage between the terminals of the signal level holding capacitor is corrected. The light emitting element is caused to emit light with a corresponding current,
The drive signal is
The display device according to claim 1, wherein the display device is a signal for driving the transistor for the signal line and / or the transistor for driving. Driving a display device that displays a desired image on the display unit by driving the pixel by outputting a drive signal from a vertical drive circuit to a scanning line of the display unit formed by arranging pixels in a matrix. In the method
A reference pulse is processed to generate a selection signal for sequentially selecting the scanning lines for each scanning line with the amplitude of the second voltage system smaller than the amplitude of the third voltage system suitable for driving the pixels. A step of generating a selection signal;
A level conversion step for each scanning line for converting the selection signal based on the amplitude of the second voltage system into the amplitude of the third voltage system for each scanning line;
For each scanning line, a vertical enable signal based on the amplitude of the third voltage system that sets a timing for switching the signal level in the drive signal with reference to an output signal from the level conversion step for each scanning line. And a step of generating a drive signal for each scanning line for generating the drive signal by the third voltage system by processing. A method for driving a display device, comprising:

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