JP2008218651A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device capable of accurately evaluating a crystal defect density and the like existing in the vicinity of a pn junction interface formed on a back surface side of a semiconductor substrate.
A semiconductor device has a trench formed on the back surface. The trench 120 extends from the rear surface of the p-type collector layer 32 toward the front surface side, passes through the surface of the p-type collector layer 32, and enters the base region 110. The trench 120 penetrates the base region 110 through the p-type collector layer 32. The wall surface in contact with the p-type collector layer 32 and the wall surface in contact with the back-side base layer 80 of the trench 120 are covered with trench insulating films 44a and 44b. A conductive material 10 is embedded inside thereof. An insulating film is not formed on the wall surface of the trench 120 in contact with the n ⁺ -type buffer layer 30, and the conductive material 10 is electrically connected to the n ⁺ -type buffer layer 30.
[Selection] Figure 1

Description

  The present invention relates to a semiconductor device in which a pn junction interface is formed in the vicinity of the back surface of a semiconductor substrate and crystal defects existing in the vicinity of the pn junction interface can be evaluated.

Development of vertical semiconductor devices for power control is underway. In particular, an IGBT (Insulated Gate Bipolar Transistor) that realizes a low on-voltage by utilizing the conductivity modulation phenomenon has attracted attention.
The vertical IGBT includes a pn junction interface in the vicinity of the back surface of the semiconductor substrate, for example, where an n-type base layer and a p-type collector layer are in contact with each other. The density of crystal defects existing in the vicinity of the bonding interface greatly affects the characteristics of the IGBT. There is a need for a semiconductor device that can measure the density of crystal defects existing in the vicinity of the pn junction interface formed in the vicinity of the back surface of the semiconductor substrate.

  In order to measure the density of crystal defects existing in the vicinity of the pn junction interface, a DLTS (Deep Level Transient Spectroscopy) method disclosed in Non-Patent Document 1 has been developed. In this method, a transient response speed of a capacitance generated when a pulse voltage is applied to a diode composed of a pn junction is measured.

  FIG. 9 shows an example of an IGBT improved so that the density of crystal defects existing in the vicinity of the pn junction interface can be measured. This is disclosed in Patent Document 1. The IGBT includes an n-type base layer 28, a p-type body region 18 in contact with a part of the surface of the base layer 28, and an n-type emitter region 24 in contact with a part of the surface of the body region 18. A gate electrode 42 facing the body region 18 separating the emitter region 24 and the base layer 28 via the gate insulating film 26, and in contact with the emitter region 24 and from the gate electrode 42 by the oxide insulating film 86. An insulated emitter electrode 20, a p-type collector 32 layer in contact with the back surface of the base layer 28, and a collector electrode 34 in contact with the back surface of the collector layer 32 are provided.

  Measurement in contact with the surface of the n-type base layer 28 in order to make it possible to measure the density of crystal defects existing in the vicinity of the pn junction interface existing between the n-type base layer 28 and the p-type collector layer 32 by the DLTS method. A working electrode 14 is formed. When the measurement electrode 14 is added, a diode structure is obtained between the measurement electrode 14 and the collector electrode 34. That is, a diode structure is obtained in which the measurement electrode 14 becomes a cathode electrode and the collector electrode 34 becomes an anode electrode. Therefore, the transient response speed of the capacitance generated when a pulse voltage is applied between the measuring electrode 14 and the collector electrode 34 is measured by the DLTS method, so that it exists between the n-type base layer 28 and the p-type collector 32 layer. The density of crystal defects existing in the vicinity of the pn junction interface to be measured can be measured.

  FIG. 10 shows an outline of the DLTS method. A measurement diode 94 having a pn junction interface is accommodated in a cryostat 92, and a pulse voltage 90 is applied between the measurement electrode 14 and the collector electrode 34. When a pulse voltage is applied, a depletion layer grows or disappears from the pn junction interface, and the parasitic capacitance changes with time. By measuring the transient response speed of the capacitance with the high-accuracy capacitance detector 96, the density of crystal defects existing near the pn junction interface can be evaluated. It is also possible to measure while changing the temperature of the measuring diode 94.

JP-A-5-3205 D.V.Lang “Deep-level transient spectroscopy: A new method to characterize traps in semiconductors”, J. Appl. Phys., Vol. 45, No. 7, July 1974

When the pulse voltage 90 is applied between the measurement electrode 14 and the collector electrode 34 of the IGBT having the conventional structure shown in FIG. 9, the capacitance of the pn junction cannot be accurately measured.
In a normal IGBT, the breakdown voltage is increased by lowering the carrier concentration of the n-type base layer 28, and the resistance of the n-type base layer 28 is high. When the pulse voltage 90 is applied between the measurement electrode 14 and the collector electrode 34, current is shared by the presence of the n-type base layer 28 having high resistance, and it is difficult to accurately measure the capacitance of the pn junction. It becomes.

In order to evaluate crystal defects related to minority carriers existing in the vicinity of the pn junction interface, a forward bias is applied to the pn junction interface to inject holes that are minority carriers into the n-type base layer 28. After that, it is necessary to apply a reverse bias to the pn junction interface and measure the capacitance transient response when the reverse bias is applied.
At this time, in the method in which the pulse voltage 90 is applied between the measurement electrode 14 and the collector electrode 34, the transient transient response when a reverse bias is applied cannot be measured.
As shown in FIG. 9, the side surface of the IGBT is diced and rough. That is, crystal defects exist at a high concentration on the dicing end face 38, and a leak current tends to flow. Due to the presence of this leakage current, it is difficult to accurately measure the capacitance of the pn junction. In the system in which a voltage is applied between the measurement electrode 14 and the collector electrode 34, the capacitive transient response cannot be accurately measured due to the leak current flowing along the dicing end face 38.

  In the present invention, the cathode electrode is exposed on the back side of the IGBT. For this purpose, a conductor region passing through the collector layer and in contact with the base layer is provided. According to the present invention, it is possible to accurately measure the capacitance of the pn junction by suppressing the influence of the measurement current being lowered due to the high resistance of the base layer and the leakage current flowing along the dicing end face. It becomes.

The semiconductor device of the present invention includes a first conductivity type base layer, a second conductivity type collector layer in contact with the back surface of the base layer, and a collector electrode formed on the back surface of the collector layer. That is, it has the same structure as the back side structure of the IGBT. However, this semiconductor device only needs to accurately measure the capacitance of the pn junction between the base layer and the collector layer formed in the same wafer. May differ from those for IGBTs.
The semiconductor device of the present invention includes a conductor region passing through the collector layer and in contact with the base layer, and further includes the following features. The collector electrode is separated into at least two regions that are insulated from each other. The conductor region is insulated from the collector layer in contact with one region of the collector electrode. The other region of the collector electrode is insulated from the collector layer in contact with the one region of the collector electrode and is electrically connected to the conductor region.

According to the semiconductor device of the present invention, a diode using a pn junction formed at the junction interface between the base layer and the collector layer is formed between a pair of electrodes (a pair of regions) formed on the back surface of the collector layer. The That is, a structure is obtained in which the collector layer, the base layer, and the conductor region are connected in series between one region side of the electrode and the other region. Since both the other region of the electrode and the conductor region are insulated from the collector layer in contact with one region of the electrode, a short circuit that prevents the realization of the diode structure is not formed.
According to the semiconductor device of the present invention, the capacitance transient response of the diode formed by the junction of the base layer and the collector layer is measured by observing the displacement current flowing between the pair of electrodes formed on the back surface of the collector layer. can do. It is possible to suppress the influence of the measurement current being lowered due to the high resistance of the base layer, the leakage current flowing along the dicing end face, and the like. The capacitance transient response of the pn junction formed between the base layer and the collector layer can be accurately measured, and the crystal defect density and the like existing in the vicinity of the pn junction interface can be accurately evaluated.

  It is preferable to have an insulator region that penetrates the collector layer and penetrates into the base layer and forms a closed loop when the back surface of the collector layer is viewed in plan. In this case, the collector layer is divided into two regions that are insulated from each other by an insulator region forming a closed loop. In this case, one region of the collector electrode is formed in a range in contact with the collector layer inside the closed loop. The conductor region is disposed outside the closed loop. In this case, the other region of the collector electrode may or may not be in contact with the collector layer outside the closed loop. It is only necessary that the other region is in contact with at least the conductor region. Since the collector layer is divided by the insulator region forming the closed loop, even if the other region of the collector electrode is in contact with the collector layer outside the closed loop, the collector region in which one region of the collector electrode is in contact The layer (inside the closed loop) and the other region of the collector electrode are insulated so that a diode structure can be realized.

It is preferable to provide a trench that penetrates the collector layer and penetrates into the base layer and forms a closed loop when the back surface of the collector layer is viewed in plan. In this case, it is preferable that at least the wall surface of the trench in contact with the collector layer inside the closed loop is covered with an insulator region, and the conductor is filled in the trench.
In this case, the wall surface of the trench in contact with the collector layer inside the closed loop is covered with the insulator region, and the conductor filled in the trench is insulated from the collector layer inside the closed loop. Also by this, a diode structure can be realized.

  When an insulator region that penetrates through the collector layer and penetrates into the base layer and forms a closed loop when the back surface of the collector layer is viewed in plan view, the back surface of the collector layer also extends along the closed loop. An insulating film is formed, and the collector electrode is preferably separated into two regions by the insulating film. In this case, a diode structure can be realized between the inner electrode and the outer electrode of the closed loop.

  An insulator region may be formed at the interface between the conductor region and the collector layer to insulate them. In this case, there is no need to divide the collector layer. If the other region of the collector electrode is insulated from the collector layer, a diode structure can be realized between the pair of regions of the electrode.

Usually, a plurality of semiconductor devices are built in one wafer. In this case, at least one semiconductor device of the plurality of semiconductor devices may be the semiconductor device according to any one of claims 1 to 6.
When another semiconductor device includes a base layer and a collector layer, since processing is performed on a wafer basis, the base layer and the collector layer of the other semiconductor device are almost the same as the base layer and the collector layer of the semiconductor device of the present invention. It can be assumed that it has the same characteristics. If the crystal defect density etc. existing in the vicinity of the pn junction interface is evaluated using the semiconductor device of the present invention, the crystal defect density existing in the vicinity of the pn junction interface of another semiconductor device in the same wafer is evaluated. Etc. can be evaluated.

The other semiconductor device in the same wafer is preferably an IGBT. In this case, the other semiconductor device is in contact with the first conductivity type base layer, the second conductivity type body region in contact with at least part of the surface of the base layer, and at least part of the surface of the body region. An emitter region of the first conductivity type, a gate electrode facing the body region separating the emitter region and the base layer through a gate insulating film, and being in contact with the emitter region and insulated from the gate electrode An emitter electrode, a collector layer of a second conductivity type in contact with the back surface of the base layer, and a collector electrode in contact with the back surface of the collector layer. Other semiconductor devices operate as IGBTs.
In this case, the semiconductor device of the present invention is exclusively for measurement and does not have to operate as an IGBT. The base layer or collector layer referred to in the present invention refers to a layer formed in the same process as the base layer or collector layer of another semiconductor device in the same wafer and operating as an IGBT, and is not necessarily the base layer or collector. It may not operate as a layer. When measuring characteristics as a diode, the base layer becomes the cathode region and the collector layer becomes the anode region.

  According to the present invention, it is possible to accurately measure the junction capacitance at the pn junction interface formed on the back side of the semiconductor substrate using the DLTS method, and accurately determine the crystal defect density and the like existing in the vicinity of the pn junction interface. It becomes possible to evaluate.

Preferred features of the embodiments described below are listed.
(First Feature) In the base layer, a first conductivity type cathode layer that is electrically connected to the bottom of the trench penetrating the base layer is formed.

  FIG. 1 schematically shows a cross-sectional view in the vicinity of a dicing end face 38 of a semiconductor device 100 according to an embodiment of the present invention. The semiconductor device 100 includes an n-type base region 110, a p-type collector layer 32 in contact with the back surface thereof, and a pair of electrodes 34a and 34b formed on the back surface. The n-type base region 110 and the p-type collector layer 32 are part of the semiconductor structure that constitutes the IGBT. The pair of electrodes 34a and 34b is for measuring the density of crystal defects existing in the vicinity of the junction interface between the n-type base region 110 and the p-type collector layer 32, and is another semiconductor device (semiconductor that operates as an IGBT). In the other semiconductor device formed in the same wafer as the device 100), the pair of electrodes 34a and 34b are not divided, and both operate as a collector electrode.

The n-type base region 110 of the semiconductor device 100 is formed by stacking an n ⁺ -type carrier storage layer 12, an n-type base layer 28, an n ⁺ -type buffer layer 30, and an n-type back side base layer 80. Yes.
A p-type body region 18 is formed on the surface of the semiconductor device 100. The p-type body region 18 is in contact with the n-type base layer 28 and the n ⁺ -type carrier storage layer 12.
An n ⁺ -type emitter region 24 is formed on a part of the surface of the p-type body region 18. A p ⁺ -type contact region 22 is formed on another part of the surface of p-type body region 18. The p-type contact region 22 contains more p-type impurities than the p-type body region 18.
A gate electrode trench 36 extending from a position in contact with the emitter region 24 to a position in contact with the base region 110 is formed through the body region 18 separating the emitter region 24 and the base region 110. The wall surface of the gate electrode trench 36 is covered with a gate insulating film 26 and filled with polysilicon. Polysilicon is a conductor and forms the gate electrode 42.
20 shown in the figure is an emitter electrode, which is in contact with the emitter region 24 and the p ⁺ -type contact region 22. The emitter electrode 20 is insulated from the gate electrode 42 by the oxide insulating film 86.
The p-type collector layer 32 is in contact with the back surface of the n-type base region 110, and a pair of electrodes 34a and 34b are formed on the back surface. In other semiconductor devices that operate as IGBTs (other semiconductor devices formed in the same wafer as the semiconductor device 100), they are not divided into a pair of electrodes 34a and 34b, and they are integrated as collector electrodes. Operate.

A trench 120 is formed on the back surface of the semiconductor device 100. The trench 120 extends from the rear surface of the p-type collector layer 32 toward the front surface side, passes through the surface of the p-type collector layer 32, and enters the base region 110. The trench 120 penetrates the base region 110 through the p-type collector layer 32.
The wall surface in contact with the p-type collector layer 32 and the wall surface in contact with the back-side base layer 80 of the trench 120 are covered with insulating films 44a and 44b. A conductive material 10 is embedded inside thereof. An insulating film is not formed on the wall surface of the trench 120 in contact with the n ⁺ -type buffer layer 30, and the conductive material 10 is electrically connected to the n ⁺ -type buffer layer 30. The material of the conductive material 10 is first conductivity type polysilicon.

  FIG. 2 shows a perspective view of the semiconductor device 100 from the back side. However, for clarity of illustration, the pair of electrodes 34a and 34b is not shown. The trench 120 makes a round around the periphery of the back surface of the semiconductor device 100. The conductive material 10 is insulated from the collector layer 32a inside the closed loop by the trench insulating film 44a inside the trench 120 forming the closed loop. The conductive material 10 only needs to be insulated from the collector layer 32a inside the closed loop, and may be in contact with the collector layer 32b outside the closed loop. The trench insulating film 44b outside the trench 120 forming the closed loop can be omitted.

As shown in FIG. 1, the insulating film 16 is formed at a position along the trench 120 on the back surface of the collector layer 32 of the semiconductor device 100. The collector electrode is divided into an electrode 34a positioned inside and an electrode 34b positioned outside by an insulating film forming a closed loop. The inner electrode 34 a is in contact with the collector layer 32 a inside the trench 120 forming a closed loop, and the outer electrode 34 b is in contact with the collector layer 32 b outside the trench 120 and the conductive material 10. Yes. The insulating film 16 is continuous with the insulating film 44a, and insulates between the inner electrode 34a and the outer collector layer 32b, and insulates between the outer electrode 34b and the inner collector layer 32a.
In this case, a structure in which the p-type collector layer 32a, the n ⁺ -type buffer layer 30, and the conductive material 10 are connected in series between the inner electrode 34a and the outer electrode 34b is realized. A diode structure having the anode and the outer electrode 34b as the cathode electrode is obtained.

The inner collector layer 32a in contact with the inner electrode 34a and the outer collector layer 32b in contact with the outer electrode 34b are insulated by the inner trench insulating film 44a, and the inner electrode 34a and the outer electrode 34b are short-circuited by the p-type collector layer 32. Never do. The conductive material 10 is insulated from the inner collector layer 32a in contact with the inner electrode 34a by the insulating film 44a, and the inner collector layer 32a in contact with the inner electrode 34 and the conductive material 10 are not short-circuited.
In other semiconductor devices operating as IGBTs (other semiconductor devices formed in the same wafer as the semiconductor device 100), they are not divided into a pair of electrodes 34a and 34b, and they are integrated into a collector electrode. Operates as In this case, the insulating film 16 does not exist.
FIG. 8 shows a cross-sectional view of the semiconductor device 200. The structure of the surface side of the semiconductor device 200 is the same as the surface of the semiconductor device 100 shown in FIG. In the semiconductor device 200, the collector electrode 35 is formed on the entire surface of the p-type collector layer 32. The semiconductor device 200 operates as an IGBT.
Actually, a large number of semiconductor devices 200 and a small number of semiconductor devices 100 are mixed in one wafer. A large number of semiconductor devices 200 and a small number of semiconductor devices 100 are manufactured by dicing.

In the case of a semiconductor device that is not divided into a pair of electrodes 34a and 34b and that operates as a collector electrode together, it operates as an IGBT. When a positive voltage is applied to the collector electrode 34 and a positive voltage is applied to the gate electrode 42 with the emitter electrode 20 grounded, a portion separating the emitter region 24 and the base region 110 (the gate insulating film 26 is removed). The portion of the body region 18 facing the gate electrode 42 is inverted, and electrons are injected from the emitter region 24 into the base region 110. As a result, holes are injected from the collector layer 32 into the base region 110, and a conductivity modulation phenomenon occurs in the base region 110. As a result, a current flows between the collector electrode 34 and the emitter electrode 20. The n ⁺ -type carrier storage layer 12 prevents holes from being excluded from the base region 110 to the emitter electrode 20, increases the hole density in the base region 110, and increases the voltage between the collector electrode 34 and the emitter electrode 20. Reduce the difference.
When the application of a positive voltage to the gate electrode 42 is stopped, the inversion layer formed in the body region 18 disappears and no current flows between the collector electrode 34 and the emitter electrode 20. The n ⁺ -type buffer layer 30 prevents a depletion layer extending from the interface between the body region 18 and the base region 110 toward the base region 110 from extending beyond the buffer layer 30 when the IGBT is turned off. This type of IGBT operates as a punch-through IGBT. The conductive material 10 facilitates an operation in which electrons accumulated in the base region 110 are discharged toward the collector electrode 34 when the IGBT is turned off. The conductive material 10 prevents the switching loss from decreasing by increasing the turn-off speed of the IGBT.

The switching characteristics of the IGBT vary greatly depending on the amount of crystal defects present in the vicinity of the interface between the base region 110 and the collector layer 32. If there are too few crystal defects, the switching loss when the IGBT is turned off increases. When there are too many crystal defects, the withstand voltage when the ON voltage is off decreases. There is a need to measure the amount of crystal defects present in the vicinity of the interface between the base region 110 and the collector layer 32.
For this purpose, the semiconductor device 100 is divided into an inner electrode 34a and an outer electrode 34b.

FIG. 3 shows a three-dimensional schematic diagram of the semiconductor device 100. For clarity of illustration, the pair of electrodes 34a and 34b are not shown.
In the present embodiment, the inner p-type collector layer 32a is completely surrounded by the trench 120 in which the conductive material 10 is embedded. Therefore, the junction area between the p-type collector layer 32a and the n-type base region 110 constituting the diode structure in which the inner electrode 34a is an anode electrode and the outer electrode 34b is a cathode electrode can be accurately calculated and measured. The crystal defect density and the like can be evaluated from the capacity and voltage characteristics. Further, the current flowing between the inner electrode 34a (anode electrode) and the outer electrode 34b (cathode electrode) of the diode does not flow on the dicing end face 38. The leak current flowing through the dicing end face 38 does not deteriorate the measurement accuracy of the capacitance of the pn junction.
Further, since the current flowing between the inner electrode 34a (anode electrode) and the outer electrode 34b (cathode electrode) of the diode does not flow through the high resistance region such as the n-type base layer 28, a high current such as the n-type base layer 28 is obtained. The resistance does not reduce the measurement accuracy of the capacitance of the pn junction.

FIG. 5 shows an equivalent circuit between the inner inner collector layer (anode region) 32a and the conductive material 10 for the pn junction on the back surface side of the semiconductor device 100. Reference numeral 74 denotes a junction diode formed by the inner collector layer (anode region) 32a and the n-type back surface base layer 80, and has a junction capacitance. Reference numeral 76 denotes a resistance component of the n-type backside base layer 80 and the n ⁺ -type buffer layer 30, and is connected in series to the junction diode 74. Reference numeral 70 denotes a parasitic capacitance between the conductive material 10 and the inner collector layer (anode region) 32a, which is connected in parallel to the junction diode 74. 78 shows a parasitic capacitance between the back surface side base layer 80, n ⁺ -type buffer layer 30 of conductive material 10 and the n-type, the resistance component of the back-side base layer 80, n ⁺ -type buffer layer 30 of n-type Are connected in parallel.
The resistance component 76 of the n-type back side base layer 80 and the n ⁺ -type buffer layer 30 is extremely small because the effective resistance path is very short, and can be substantially ignored. This is shown in FIG. As apparent from FIG. 6A, if the resistance component 76 is small enough to be ignored, the voltage across the capacitor 78 becomes equal, and the presence of the capacitor 78 can be ignored. This is shown in FIG. 6 (b).
As shown in FIG. 6B, when the capacitance between the inner collector layer (anode region) 32a and the conductive material 10 is measured, the inner collector layer (anode region) 32a and the n-type back side base layer 80 are formed. The capacitance of the circuit in which the junction capacitance and the parasitic capacitance between the conductive material 10 and the inner collector layer (anode region) 32a are joined in parallel is measured. As will be described later, the parasitic capacitance between the conductive material 10 and the inner collector layer (anode region) 32a is small, and is substantially formed by the inner collector layer (anode region) 32a and the n-type back side base layer 80. Junction capacitance can be measured.

FIG. 4 is a schematic cross-sectional view in which the back surface pn junction portion of the semiconductor device 100 is enlarged. Each parameter indicates the following.
t _ox : film thickness of the trench insulating film 44a,
N _A : acceptor concentration of the inner collector layer (anode region) 32,
x _j : junction depth of the inner collector layer (anode region) 32 N _D : carrier concentration of the n-type back side base layer 80,
n: donor concentration of the n-type backside base layer 80,
W _dep : Depletion layer width d _trench : Trench depth

When the parameters shown in FIG. 4 are used, the junction capacitance between the inner collector layer (anode region) 32a and the n-type back side base layer (cathode region) 80 (capacitor capacity indicated by 74 in FIG. 6B), and The parasitic capacitance between the inner collector layer (anode region) 32a and the conductive material 10 (capacitance of the capacitor indicated by 70 in FIG. 6B) can be obtained by the equation shown in FIG.
Equation (1) indicates the parasitic capacitance of the capacitor 70 constituted by the inner collector layer (anode region) 32 a and the conductive material 10. In the formula, a indicates the length of one side of the region surrounded by the conductive material 10, x _j indicates the junction depth of the anode region 32a, ε ₀ indicates the vacuum dielectric constant, and ε _s indicates the semiconductor material. The relative dielectric constant is indicated, and t _ox indicates the film thickness of the trench insulating film.
Expression (2) represents the junction capacitance of the capacitor 74 configured by the p-type collector layer anode region 32a and the n-type back side base layer (cathode region) 80. w _dep indicates the width of the depletion layer.
Equation (3) represents an equation for obtaining the width of the depletion layer. phi _bi represents a diffusion potential, V _R represents the reverse bias voltage, q denotes the electron charge.
Expression (4) represents an expression for obtaining the diffusion potential. k represents Boltzmann's constant, T represents the thermodynamic temperature, N _A denotes an acceptor concentration in the anode region 32a, N _D represents a donor concentration of the n-type rear surface side base layer 80, n _i is the intrinsic semiconductor material The carrier concentration is shown.
Here, as representative values, the length a of one side of the region surrounded by the trench 120 is 1 cm, the thickness _tox of the gate insulating film is 100 nm, the junction depth of the anode region 32a is 0.2 μm, and n The respective capacities are calculated assuming that the carrier concentration of the mold back side base layer 80 is 1.0 × e ¹⁴ cm ⁻³ . As a result, C _j = 2160 pF and C _ac = 8.3 pF. C _ac is extremely small compared to C _j . In FIG. 6B, the parasitic capacitance of the capacitor 70 composed of the anode region 32a and the conductive material 10 is extremely small. If the capacitance between the anode region 32a and the conductive material 10 is measured, the anode region 32a and the n-type are measured. It can be seen that the junction capacitance of the capacitor 74 composed of the back side base layer 80 can be accurately measured.

In the embodiment, the collector layer 32 is separated into the inner region 32a and the outer region 32b by the inner trench insulating film 44a forming a closed loop. When the conductive material 10 is insulated from the collector layer 32 by the insulating film 44a, it is not necessary to divide the collector layer 32 into two. As long as the cathode electrode 34b is electrically connected to the conductive material 10 and insulated from the collector layer 32, a diode structure can be formed without dividing the collector layer 32 into two.
When the collector layer 32 is divided into two by the inner trench insulating film 44a forming the closed loop, and the conductive material 10 is disposed on the outer collector layer 32b, it is not necessary to insulate the conductive material 10. . As long as the cathode electrode 34b is electrically connected to the conductive material 10 and insulated from the inner collector layer 32a, a diode structure can be formed without insulating the conductive material 10.

  The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

A cross-sectional view of the semiconductor device 100 is shown. The figure which looked at the back surface of the semiconductor device 100 is shown. The three-dimensional state seen from the back surface of the semiconductor device 100 is shown. FIG. 3 shows an enlarged cross-sectional view of a back surface pn junction portion of the semiconductor device 100. FIG. 2 shows an equivalent circuit of a pn junction portion of the semiconductor device 100. (A) and (b) show the approximate equivalent circuit of the pn junction part of the semiconductor device 100. FIG. A calculation formula of the parasitic capacitance and the junction capacitance of the pn junction portion of the semiconductor device 100 is shown. A cross-sectional view of the semiconductor device 200 is shown. 1 shows a cross-sectional view of a prior art IGBT. A measurement method using the DLTS method is shown.

Explanation of symbols

10: Conductive material 12: n ⁺ type carrier storage layer 14: n type base region electrode 16: insulating film 18: p type body region 20: emitter electrode 22: p type contact region 24: n ⁺ type emitter region 26: Gate insulating film 28: n-type base layer 30: n ⁺ -type buffer layer 32: collector layer 32a: inner collector layer (anode region)
32b: outer collector layer (cathode region)
34: Collector electrode 34a: Inner electrode (anode electrode)
34b: outer electrode (cathode electrode)
36: trench 38 for gate electrode: dicing end face 40: p-type anode region 42: gate electrode 44a: inner trench insulating film 44b: outer trench insulating film 70: parasitic capacitance 74 between conductive material and p-type collector (anode): pn junction diode 76: resistance component 78 of n-type cathode layer 78: parasitic capacitance between conductive material and n-type base layer 80: n-type back side base layer 86: oxide insulating film 90: pulse voltage 92: cryostat 94: crystal defect evaluation Element 96: high-precision capacitance detector 100: semiconductor device 110: n-type base region 120: trench 200: semiconductor device

Claims (8)

A base layer of a first conductivity type;
A collector layer of a second conductivity type in contact with the back surface of the base layer;
A collector electrode formed on the back surface of the collector layer;
A first conductivity type conductor region penetrating the collector layer and contacting the base layer;
The collector electrode is separated into at least two regions that are insulated from each other;
The conductor region is insulated from the collector layer in contact with one region of the collector electrode,
A semiconductor device characterized in that the other region of the collector electrode is insulated from the collector layer in contact with the one region of the collector electrode and is electrically connected to the conductor region. It has an insulator region that penetrates through the collector layer and penetrates into the base layer, and forms a closed loop when the back surface of the collector layer is viewed in plan,
One region of the collector electrode is in contact with the collector layer inside the closed loop,
The semiconductor device according to claim 1, wherein the conductor region is disposed outside the closed loop.   3. The semiconductor device according to claim 2, wherein the other region of the collector electrode is in contact with the outer collector layer of the closed loop and the conductor region. It has a trench that penetrates the collector layer and penetrates into the base layer, and forms a closed loop when the back surface of the collector layer is viewed in plan,
At least the walls of the trench in contact with the collector layer inside the closed loop are covered with an insulator region,
4. The semiconductor device according to claim 2, wherein a conductor is filled in the trench.   5. The semiconductor device according to claim 4, wherein an insulating film extending along a closed loop is formed on the back surface of the collector layer, and the collector electrode is separated into two regions by the insulating film. An insulator region is formed at the interface between the conductor region and the collector layer to insulate the two.
2. The semiconductor device according to claim 1, wherein the other region of the collector electrode is insulated from the collector layer. A wafer on which a plurality of semiconductor devices are built,
A wafer, wherein the at least one semiconductor device is the semiconductor device according to claim 1. The semiconductor device according to any one of claims 1 to 6 and the following vertical semiconductor device are mixed,
The vertical semiconductor device
A base layer of a first conductivity type;
A body region of a second conductivity type in contact with at least a part of the surface of the base layer;
An emitter region of a first conductivity type in contact with at least a part of the surface of the body region;
A gate electrode facing the body region separating the emitter region and the base layer through a gate insulating film;
An emitter electrode in contact with the emitter region and insulated from the gate electrode;
A collector layer of a second conductivity type in contact with the back surface of the base layer;
A collector electrode in contact with the back surface of the collector layer;
A wafer characterized by comprising:

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