JP2008217577A - Internal voltage generation circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an internal voltage generation circuit for stably generating internal voltage at a necessary voltage level from a step-up voltage generated by charge pump operation in a small occupation area with low current consumption. <P>SOLUTION: According to a comparison result between output voltage Vcpr of an output node 50 and reference voltage Vref, an amount of drive current of a drive transistor 46 for driving the output node 50 is adjusted. With regard to the output node, current is supplied by an output voltage line 38 of a charge pump circuit. Breakdown voltage reduction circuits 52 and 53 are provided between the output voltage line 38 of the charge pump circuit and a differential amplifying circuit 44 and between the output voltage line 38 and the output node 50. A breakdown voltage reduction circuit 54 is provided also between the transistor and the output node. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an internal voltage generation circuit, and more particularly to a configuration of a circuit that generates an internal voltage of a desired voltage level in accordance with a voltage from a pump circuit that generates a boosted voltage by a pump operation. More specifically, the present invention relates to a configuration of an internal voltage generation circuit that generates an internal voltage of a desired voltage level with a small area and low power consumption.

  In semiconductor devices, a voltage level different from the power supply voltage and the ground voltage is often used. When such a voltage is supplied from the outside of the device, there is a problem that the number of terminals of the semiconductor device increases or the consumption current increases due to the charge / discharge current of the external signal line. Therefore, a voltage of a necessary voltage level is generated inside the semiconductor device. As a circuit for generating such an internal voltage, a pump circuit using a charge pump operation of a capacitive element is widely used.

  In a nonvolatile semiconductor memory device, a configuration for generating a necessary internal voltage using this pump circuit is shown in Japanese Patent Application Laid-Open No. 2006-185530. In Patent Document 1, the number of stages of the charge pump circuit is changed according to the operation mode. Further, the current driving force is increased by connecting the pump stages of the charge pump circuit in parallel according to the operation mode. In this patent document 1, one power supply circuit is provided in common for a plurality of macros, and the number of stages of the charge pump circuit included in the power supply circuit and the current driving force are adjusted according to the operation mode. In the case where a power supply circuit is provided for each memory block (macro), the problem of an increase in the number of power supply circuits and an increase in the occupied area accordingly is to be solved.

  Further, Japanese Patent Application Laid-Open No. 2006-201807 discloses a configuration in which a voltage when driving a data line and a source line by a liquid crystal driving circuit is generated by a charge pump circuit. In the configuration shown in Patent Document 2, a booster circuit is provided corresponding to each internal voltage, and voltages that require high-speed response and low current consumption are generated by different charge pump circuits. A voltage requiring stability uses an external voltage.

  In Patent Document 2, as a prior art, when an output voltage of a charge pump circuit is divided by a resistor and impedance conversion is performed by an operational amplifier to generate a high voltage VH and a low voltage VL, a reactive current is a resistance when a data line is driven. It is intended to solve the problem of wasteful current consumption in the operational amplifier for impedance conversion that flows in the voltage dividing circuit.

  An internal voltage generation circuit that generates an internal voltage of a necessary voltage level from a power supply voltage is disclosed in Patent Document 3 (Japanese Patent Laid-Open No. 2004-133554). In Patent Document 3, a current is supplied from a power supply line to an output node via a constant current source. The voltage of the output node is compared with the reference voltage, and current is drawn from the output node according to the comparison result. The voltage level of the output node is maintained at a voltage level determined by the reference voltage.

  A configuration that guarantees the breakdown voltage characteristics of a transistor in a circuit that generates a high voltage using a constant current is disclosed in Patent Document 4 (Japanese Patent Laid-Open No. 2005-222301). In Patent Document 4, a high voltage MOS transistor and a low voltage MOS transistor are connected in series between a load and a ground node. A high voltage MOS transistor is connected to the load side. These MOS transistors are depletion transistors, and their gates are connected to the ground node. The absolute value of the threshold voltage of the high voltage MOS transistor is made larger than the absolute value of the threshold voltage of the low voltage MOS transistor. An operating power supply voltage and current are supplied from the power supply node to the load. A constant current is extracted from the load by the MOS transistor. The drain currents of the high voltage MOS transistor and the low voltage MOS transistor change reciprocally with respect to the drain-source voltage of the low voltage MOS transistor. The operating point of this constant current circuit is that the currents flowing through these MOS transistors coincide. In this case, the drain-source breakdown voltage of the low breakdown voltage MOS transistor is only required to be equal to or greater than the absolute value of the threshold voltage of the high breakdown voltage MOS transistor.

This patent document 4 guarantees the breakdown voltage of the low breakdown voltage MOS transistor by limiting the upper limit value of the voltage applied to the low breakdown voltage MOS transistor by the threshold voltage of the high breakdown voltage MOS transistor. Further, stability is improved by setting a current value using a low breakdown voltage MOS transistor. Also, by using the load side node as a power supply node, the operating power supply voltage range of this constant current circuit is expanded to the absolute value of the threshold voltage of the low voltage MOS transistor, and stable even when the power supply voltage fluctuates. To generate a constant current.
JP 2006-185530 A JP 2006-201807 A Japanese Patent Application Laid-Open No. 2004-133554 JP-A-2005-222301

  In Patent Document 1, a power supply circuit is provided in common to a plurality of memory blocks, and the number of charge pump stages included in the power supply circuit is changed according to the operation mode. By increasing the number of stages of the charge pump circuit, the voltage level of the boosted voltage is increased and a voltage necessary for writing and erasing is generated. This writing and erasing is executed in units of memory blocks. On the other hand, at the time of data reading, the read voltage is stably supplied to a plurality of memory blocks by reducing the number of charge pump stages and connecting them in parallel. In this current driving force adjustment, a medium speed pump clock signal is supplied during erasing and writing, and a high speed clock signal is supplied during reading. During standby, a low-speed clock signal is supplied to reduce current consumption during standby. However, this Patent Document 1 only shows a configuration in which the output voltage of the charge pump circuit itself is used for writing, erasing and reading. From the output voltage of this charge pump circuit, a desired voltage is further shown. No consideration is given to the configuration that generates the internal voltage of the level. Further, no consideration is given to the breakdown voltage of the transistor when a high voltage is generated.

  Patent Document 2 is a liquid crystal driver, which generates a data line driving voltage required inside using a dedicated charge pump circuit. Thereby, it is aimed to reduce the power consumption when the resistance voltage dividing circuit is used. However, in Patent Document 2, only a dedicated charge pump circuit is provided for each internal voltage, and a configuration for generating internal voltages at a plurality of voltage levels from the output voltage of the common charge pump circuit is considered. Not done. Further, although Patent Document 2 discloses a circuit configuration for discharging residual charges at a high speed when the charge pump operation is stopped, no consideration has been given to the withstand voltage of the internal voltage generation unit when this high voltage is generated. Absent.

  This Patent Document 2 solves the problem that the circuit area and current consumption increase in the case of a configuration in which a high voltage is divided into a plurality of voltage levels by a resistance voltage dividing circuit and a required internal voltage is selected. Plan. However, when the pump circuit is provided corresponding to the required internal voltage level, the problem that the circuit occupation area is still not solved.

  In Patent Document 3, a constant current is supplied from a power supply line, and an internal voltage is generated by extracting a current from an output node according to a difference between the internal voltage and a reference voltage. This internal voltage is at a voltage level lower than the power supply voltage. Patent Document 3 does not consider any circuit configuration that generates a voltage higher than the power supply voltage.

  Patent Document 4 aims to extend the operating voltage range of the constant current circuit without degrading the withstand voltage characteristics. In Patent Document 4, a high voltage transistor is connected in series to a low voltage transistor in order to guarantee the breakdown voltage of a depletion type transistor that draws a constant current. The generated internal voltage (the operating power supply voltage of the constant current circuit) is a voltage lower than the power supply voltage. Patent Document 4 does not consider the stable generation of a voltage higher than the power supply voltage. In addition, although a constant current is generated, only a constant current source that keeps the current flowing through the load constant is shown, and it is not specifically shown how to use this constant current. . “Load” is merely meant to indicate various circuits including transistors, diodes, signal lines, and combinations thereof.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide an internal voltage generation circuit capable of stably generating an internal voltage with a low current consumption and a small occupied area without depending on the output voltage level of the charge pump circuit. is there.

  In summary, the internal voltage generation circuit according to the present invention provides a current source between the output of the charge pump circuit and the internal voltage output node, and allows a current to flow between the internal voltage output node and the output node of the pump circuit. At the same time, the conductance of the drive element connected between the output node and the reference node is adjusted based on the comparison result between the voltage level of the internal voltage output node and the reference voltage. The voltage level of the reference voltage is set according to the operation mode. A withstand voltage relaxation circuit that relaxes the applied voltage is provided for the current source, the drive element, and the comparison circuit.

  In other words, according to one embodiment of the present invention, the internal voltage generation circuit is coupled between the pump circuit that generates the boosted voltage by the pump operation, and the output of the pump circuit and the internal voltage output node. A current source for passing a current between the node and the pump circuit output, a comparison circuit for comparing the voltage of the internal voltage output node with a reference voltage, and an internal voltage output node and a reference voltage node according to an output signal of the comparison circuit A drive element for passing a current therebetween, and a withstand voltage relaxation circuit for relaxing an applied voltage to the comparison circuit, the drive element, and the current source.

  The current source preferably has a drive current amount set according to the selection signal and supplies a current to the internal voltage output node. The reference voltage generation circuit generates a reference voltage whose voltage level is adjusted according to the operation mode. The comparison circuit is supplied with an operation current from the output of the pump circuit, and compares the reference voltage from the reference voltage generation circuit with the voltage of the internal voltage output node during operation, and generates a signal corresponding to the comparison result.

  An internal voltage is generated from the output of the charge pump circuit by a current source and a drive element. Therefore, a high resistance element for dividing the output voltage of the charge pump circuit becomes unnecessary, and the occupied area can be reduced.

  Further, by providing a withstand voltage relaxation circuit, when applied to a nonvolatile memory, the withstand voltage of the transistor element is ensured even when a high voltage unique to the nonvolatile memory is generated, and a high voltage of a predetermined voltage level is stably generated. be able to.

  Moreover, the following effects are acquired by utilizing the current source which can change a drive current amount according to an operating condition as such a current source. That is, the drive current amount can be adjusted according to the output load and the operation mode. Thereby, it is possible to prevent current from being consumed more than necessary, and to reduce power consumption.

  Further, the conductance of the drive element is adjusted based on the comparison with the internal voltage with the reference voltage. As a result, the internal voltage can be accurately set to the voltage level defined by the reference voltage. Further, by changing the voltage level of the reference voltage according to the operation mode, it is possible to generate a plurality of levels of internal voltages from the output of one pump circuit. Depending on the level of the internal voltage, it is not necessary to individually provide a charge pump circuit, and the layout area of the internal voltage generation circuit can be reduced.

  Further, the voltage level of the internal voltage can be set by charging / discharging the internal voltage line. For this reason, it is not necessary to charge and discharge the internal voltage line via a high resistance unlike a resistance voltage dividing circuit, and an internal voltage of a predetermined voltage level can be generated at high speed.

[Embodiment 1]
FIG. 1 schematically shows an example of the entire configuration of a semiconductor integrated circuit device including a nonvolatile semiconductor memory device to which the present invention is applied. In FIG. 1, a semiconductor integrated circuit device 1 includes a logic 2 that executes operation control and arithmetic processing, a RAM (Random Access Memory) 3, and a nonvolatile memory 4. The RAM 3 is used as a work area for storing data to be processed by the logic 2, and is also used as a buffer area at the time of data transfer with the outside.

  The nonvolatile memory 4 can rewrite data, and stores an application program, a boot program, a large amount of download data, and the like.

  Logic 2, RAM 3 and nonvolatile memory 4 are interconnected via an internal data bus 6. Internal data bus 6 is coupled to the outside via interface circuit 5. Therefore, the logic 2 transfers data to the outside via the internal data bus 6 and the interface circuit 5, and the RAM 3 or the non-volatile memory 4 is an interface in the DMA (direct memory access) mode. Data is transferred to and from the outside via the circuit 5.

  FIG. 2 is a diagram schematically showing an example of the configuration of the memory cell MC included in the nonvolatile memory 4 shown in FIG. In FIG. 2, a memory cell MC includes a memory cell transistor MT for storing data and a selection transistor ST for selecting the memory cell MC. The memory cell transistor MT includes a channel formation region 12 in which a channel is formed when conducting, a charge storage film 11 formed on the channel formation region 12, and a memory that controls injection / extraction of charges into the charge storage film 11. Cell gate 10. The charge storage film 11 has a laminated structure of an ONO film (oxide film-nitride film-oxide film), and charges are stored in the nitride film according to stored data. The select transistor ST includes a channel formation region 14 and a control gate 13 formed on the channel formation region 14 via a gate insulating film (not shown). Each of memory cell transistor MT and select transistor ST is formed of an N-channel transistor, for example.

  In memory cell MC, memory cell transistor MT and select transistor ST are connected in series between source line SL and bit line BL. Memory cell transistor MT is coupled to source line SL, and select transistor ST is coupled to the bit line. Control gate 13 of select transistor ST is coupled to control gate line CG, and memory cell gate 10 of memory cell transistor MT is coupled to memory gate line MG.

  At the time of data writing to the memory cell MC, the selection transistor ST is set to a weak ON state (a voltage slightly higher than the threshold voltage of the selection transistor ST is applied to the control gate line CG). For example, a voltage of 11 V is applied to the memory gate line MG, and a voltage of 5 V, for example, is applied to the source line SL. The bit line BL is set to about 0.8V, for example. In this case, a current flows from the source line SL to the bit line BL. The channel formation region 14 of the selection transistor ST is in a high resistance state, and in this memory cell transistor MT, hot electrons are generated by a high electric field on the source side. The hot electrons are attracted toward the charge storage film 11 by the high voltage of the memory cell gate 10 and injected into the nitride film in the charge storage film 11 to be trapped. In this state, the memory cell transistor MT has a high threshold voltage.

  When erasing data, conversely, a negative voltage of about -7V, for example, is applied to the memory cell gate 10, and a voltage of about 5V is applied to the source line SL. The selection transistor ST is set to a weak ON state as in the writing. Similarly, the bit line is about 0.8V. When a current flows from the source line SL to the bit line BL, a high electric field is generated on the drain side (conduction node (impurity region) connected to the source line SL) of the memory cell transistor MT, and a hot hole is generated. This hot hole is injected into the charge storage film 11 by band-to-band tunneling. As a result, neutralization of electrons and holes accumulated in the charge storage film 11 occurs, and erasure is performed. In the erased state, the memory cell transistor MT has a low threshold voltage.

  At the time of data reading, memory gate line MG is set to a read voltage level, for example. The read voltage is a voltage level between the erased state and the written state threshold voltage of the memory cell transistor MT. The control gate line CG is driven to the H level, and the selection transistor ST is set to a strong ON state. The memory cell transistor MT has a high threshold voltage when it is in a writing state where the amount of electrons stored in the charge storage film 11 is large, while it is in an erased state where the amount of electrons stored in the charge storage film 11 is small. In this case, the threshold voltage is low. Since the read voltage is set to a voltage level between the threshold voltage of the write state and the erase state, the bit line BL changes to the source line SL according to the storage data (threshold voltage) of the memory cell transistor MT. Current flows. The amount of current is detected by a sense amplifier or the like to read data.

  As described above, in memory cell MC, various levels of voltage are required for writing, erasing and reading. In addition, a verify voltage is generated to internally verify whether data writing / erasing has been performed reliably. These various voltages are generated internally. The voltage levels described above are merely examples, and the voltage levels of these various voltages are not limited to the voltage levels described above. The same applies to the following description.

  FIG. 3 is a diagram schematically showing the overall configuration of the nonvolatile memory 4 shown in FIG. In FIG. 3, the nonvolatile memory 4 includes a memory cell array 20 in which memory cells MC are arranged in a matrix. In memory cell array 20, control gate line CG and memory gate line MG are arranged corresponding to each row of memory cells MC. A bit line BL is arranged corresponding to each column of memory cells. FIG. 3 shows that source line SL is arranged corresponding to each memory cell column in parallel to bit line BL. However, source line SL may be arranged to extend in the row direction corresponding to the memory cell row.

  The nonvolatile memory 4 further writes a row selection drive circuit 22 for driving the control gate line CG and the memory gate line MG of the selected row to a selected state in accordance with an address signal (not shown), and a source line SL for writing data. / A source line selection drive circuit 24 that drives to a predetermined voltage level at the time of erasing, and a bit line selection drive circuit 26 that selects a bit line BL and transmits a voltage corresponding to an operation mode to the selected bit line.

  Row selection drive circuit 22 sets the voltage levels of memory gate line MG and control gate line CG in accordance with voltages Vmg and Vcg from internal voltage generation circuit 28. The voltage level when the memory gate line MG and the control gate line CG are selected and the voltage level when not selected are set in accordance with the operation mode. For example, at the time of writing, the selection voltage of the memory gate line MG is 11V, and the non-selection voltage is 3.5V. The selection voltage of the control gate line CG is 1V, and the non-selection voltage is 0V.

  When writing and erasing are performed in units of blocks, source line selection drive circuit 24 selects a source line for each block, and sets the voltage level of the selected source line according to voltage Vs from internal voltage generation circuit 28. To do. At the time of data reading, source line selection drive circuit 24 maintains source line SL at the ground voltage level. For example, at the time of writing, the selected source line voltage is 5V, and the unselected source line voltage is 1.5V or 0V.

  Bit line selection drive circuit 26 selects bit line BL corresponding to the selected column in accordance with an address signal (not shown), and also transmits an erase voltage to the bit line of the selected block at the time of erasure (when erasing is performed in units of blocks). . At the time of data writing, bit line selection drive circuit 26 transmits a write inhibition voltage to the bit line of the non-selected column, and a current flows to the memory cell in the selected row / non-selected column. To prevent. A write voltage is transmitted to the bit line of the selected column, and a current flows in the selected memory cell. The write inhibition voltage is, for example, 1.5V, and the write voltage is, for example, 0.8V. When reading data, bit line selection drive circuit 26 transmits a read voltage to the bit line of the selected column and couples the selected column to input / output circuit 29. The bit line read voltage is applied to cause a current to flow through the bit line and the memory cell and detect the bit line current by a sense amplifier (not shown).

  Input / output circuit 29 writes / reads data DQ to / from an external logic or interface circuit (see FIG. 1). In the nonvolatile memory 4, a control circuit 30 for controlling internal operations is provided. The control circuit 30 is composed of, for example, a sequence controller, and generates an internal control signal for executing each operation mode in accordance with a command CMD that instructs the operation mode from the outside. Internal voltage generation circuit 28 sets internal voltages Vmg, Vcg, Vs and Vbl to voltage levels according to the operation mode, respectively, according to the internal control signal from control circuit 30.

  FIG. 4 is a diagram schematically showing a configuration of a portion 28A that generates one type of internal voltage of internal voltage generation circuit 28 shown in FIG. Internal voltage generation circuit 28A is provided corresponding to each internal voltage Vmg, Vcg, Vs and Vbl. In FIG. 4, an internal voltage generation circuit 28A includes a charge pump circuit 32 that generates a high voltage Vcp according to a pump operation, a reference voltage generation circuit 34 that generates a reference voltage Vref whose voltage level is set according to an operation mode, In accordance with this operation mode, there is included a step-down circuit 36 for stepping down voltage Vcp transmitted on output voltage line 38 from charge pump circuit 32 to generate internal voltage Vcpr.

  The charge pump circuit 32 generates a pump high voltage Vcp of, for example, 11V to 12V using the charge pump operation of the capacitive element. Charge pump circuit 32 includes a voltage level detection circuit for monitoring the voltage level of pump high voltage Vcp. The pump operation is controlled internally according to the output signal of the level detection circuit, and the voltage level of the pump high voltage Vcp is maintained at a predetermined voltage level.

  The step-down circuit 36 steps down the pump high voltage Vcp from the charge pump circuit 32 to generate the internal voltage Vcpr. The structure of the step-down circuit 36 will be described in detail later. The reference voltage Vref from the reference voltage generation circuit 34 is compared with the voltage level of the internal voltage Vcpr, and the current is drawn from the output node 50 according to the comparison result. Vcpr is maintained at the voltage level of the reference voltage Vref.

  The control circuit 30 performs setting of the voltage level of the reference voltage Vref generated by the reference voltage generation circuit 34 and operation control of the step-down circuit 36.

  FIG. 5 is a diagram more specifically showing the configuration of step-down circuit 36 shown in FIG. In FIG. 5, the step-down circuit 36 is supplied with a constant current source 40 that supplies current from the output voltage line 38 of the charge pump circuit 32, and is supplied with an operating current from the constant current source 40, and compares the reference voltage Vref and the output voltage Vcpr. A current is drawn from the output node 50 to the ground node (reference voltage node) according to the output signal of the differential amplifier circuit (comparator circuit) 44, the constant current source 42 that supplies current from the output voltage line 38, and the output signal of the differential amplifier circuit 44. And a drive transistor 46 to be removed.

  Each of constant current sources 40 and 42 is a voltage transmitted from charge pump circuit 32 shown in FIG. 4 to output voltage line 38 when amplifier activation signal AMPEN is activated (when H level: pump high voltage Vcp level). Vcp is converted into current. Each of constant current sources 40 and 42 conducts, for example, with a current source MOS transistor (P-channel insulated gate field effect transistor) and when amplifier activation signal AMPEN is inactive (at L level), and current source MOS A P-channel MOS transistor that electrically couples the gate of the transistor to the output voltage line 38, and a transmission that conducts when the amplifier activation signal AMPEN is activated and transmits a current control voltage at a constant voltage level to the gate of the current source MOS transistor It consists of a gate. When the current control voltage is at the ground voltage level, on / off of the current source MOS transistor is controlled by an inverted signal of the amplifier activation signal AMPEN. The constant current source 40 passes a current of, for example, 8 μA when activated. The constant current source 42 passes a current of, for example, 40 μA when activated.

  Differential amplifier circuit 44 includes P channel MOS transistors PQ1 and PQ2 whose source nodes are coupled to operating power supply node 41, and N channel MOS transistors NQ1 and NQ2 whose source nodes are connected to a ground node (VSS node). MOS transistor PQ1 receives reference voltage Vref at its gate, and supplies current to MOS transistor NQ1. MOS transistor PQ2 receives voltage Vcpr on output node 50 at its gate, and supplies current to MOS transistor NQ2. MOS transistors NQ1 and NQ2 form a current mirror circuit. MOS transistor NQ2 has its gate and drain interconnected and functions as a master of this current mirror circuit.

  In operation, differential amplifier circuit 44 compares reference voltage Vref and output voltage Vcpr by MOS transistors PQ1 and PQ2. When the reference voltage Vref is higher than the output voltage Vcpr, the amount of current flowing through the MOS transistor PQ2 is larger than that of the MOS transistor PQ1. In MOS transistor NQ1, a current having the same magnitude as the current flowing through MOS transistor NQ2 flows (mirror ratio is 1). Therefore, the amount of current discharged by MOS transistor NQ1 is larger than the amount of current supplied by MOS transistor PQ1, and the voltage level of internal node 49 decreases. Conversely, when the reference voltage Vref is lower than the output voltage Vcpr, the amount of current supplied by the MOS transistor PQ1 is larger than the amount of current supplied by the MOS transistor PQ2. Therefore, in this case, MOS transistor NQ1 cannot discharge all the current from MOS transistor PQ1, and the voltage level of internal node 49 rises.

  The signal voltage at internal node 49 of differential amplifier circuit 44 is applied to the gate of drive transistor 46 as a comparison result instruction signal. Therefore, when the reference voltage Vref is higher than the output voltage Vcpr, the conductance of the drive transistor 46 is reduced or turned off, the amount of current drawn from the output node 50 is reduced, and the voltage level of the output node 50 is constant current. It rises due to the current from the source 42. On the other hand, when the output voltage Vcpr is higher than the reference voltage Vref, the conductance of the drive transistor 46 increases, the amount of current drawn from the output node 50 increases, and the voltage level of the output node 50 decreases. Accordingly, the feedback loop control by the differential amplifier circuit 44 and the drive transistor 46 causes the voltage level of the output node 50 to be equal to the reference voltage Vref.

  The step-down circuit 36 further includes a breakdown voltage relaxation circuit (second breakdown voltage relaxation circuit) 52 connected between the constant current source 40 and the operation power supply node 41 of the differential amplifier circuit 44, a constant current source 42, and an output node 50. And a withstand voltage relaxation circuit (first withstand voltage relaxation circuit) 53 provided between them. Breakdown voltage reducing circuit 52 includes a P-channel MOS transistor PQ3 connected between constant current source 40 and operating power supply node 41 of differential amplifier circuit 46 and receiving withstand voltage control signal Vscpr at its gate. The withstand voltage control signal Vscpr is set to 0V or 3.5V depending on the operation mode or application.

  By supplying the withstand voltage control signal Vscpr to the gate of the MOS transistor PQ3, a high voltage is prevented from being applied to the constant current source 40 by the pump high voltage Vcp from the charge pump circuit 32. In other words, the voltage level of the pump high voltage supplied to the step-down circuit 36 differs depending on the application. For example, when the step-down circuit 36 generates the memory gate line voltage of the MONOS memory, the memory gate line voltage Vmg is 11 V at the maximum. From this maximum voltage, a voltage of a voltage level corresponding to the operation mode is generated by the step-down circuit. At this time, if there is no breakdown voltage reducing MOS transistor PQ3, a voltage of 11V-0V = 11V may be applied to the constant current source 40. At the time of generating such a high voltage, if the withstand voltage relaxation control signal Vscpr is set to 3.5 V, for example, the connection node between the constant current source 40 and the MOS transistor PQ3 is 3.5V + the absolute value of the threshold voltage of the MOS transistor PQ3. It will only be greater than the value Vthp. Therefore, the voltage applied to the constant current source 40 is relaxed to 11V− (3.5V + Vthp).

  Breakdown voltage reduction circuit 53 includes a P-channel MOS transistor PQ4 connected between constant current source 42 and output node 50 and receiving a breakdown voltage control signal Vscpr at its gate. MOS transistor PQ 4 also supplies current from constant current source 42 to output node 50.

  When the pump high voltage Vcp is high, a voltage drop is caused between the constant current source 42 and the output node 50 by the withstand voltage control signal Vspr, and a high voltage is applied between the source and drain of the transistor of the constant current source 42. And the breakdown voltage characteristic of the transistor of the constant current source 42 is guaranteed. Further, the breakdown voltage reducing circuit 53 ensures that the voltage at the output node 50 is lower than the pump high voltage Vcp so that a high voltage is applied between the gate and the source of the MOS transistor PQ2 of the differential amplifier circuit 44. Suppress.

  The step-down circuit 36 further includes a withstand voltage relief circuit (third withstand voltage mitigation circuit) 54 connected between the output node 50 and the drive transistor 46, and mirror compensation for phase compensation of the input / output response of the differential amplifier circuit 44. A circuit 55 and an N channel MOS transistor 60 which selectively receives an amplifier activation signal AMPEN at its gate via an inverter 59 are included.

  Breakdown voltage reduction circuit 54 includes an N-channel MOS transistor NQ3 connected between output node 50 and drive transistor 46 and receiving breakdown voltage control signal Vcrd at its gate. The withstand voltage relaxation control signal Vcrd is set to a voltage level of 5.5 V, for example, when the pump high voltage Vcp is a high voltage of 11 V, for example. In this state, MOS transistor NQ3 transmits a voltage having a magnitude obtained by subtracting the threshold voltage from gate voltage Vcrd. As a result, application of a high voltage between the source and drain of the drive transistor 46 can be suppressed.

  Inverter 59 receives withstand voltage relaxation control voltage Vcrd as the high-side power supply voltage. The amplifier activation signal AMPEN makes the constant current sources 40 and 42 non-conductive when the step-down circuit 36 is inactive, so that the H level is the pump high voltage level. Level conversion is performed by the inverter 59 to avoid application of a high voltage between the gate and source of the MOS transistor 60.

  When the step-down circuit 36 is in an inactive state, the amplifier activation signal AMPEN is at the L level, and the MOS transistor 60 is turned on. In this state, internal node 49 of differential amplifier circuit 44 is set to ground voltage VSS level, and drive transistor 46 is turned off. The constant current sources 40 and 42 are in a non-conductive state and do not supply current. Therefore, the internal voltage generation operation from the output node 50 is stopped. At this time, internal node 49 in differential amplifier circuit 44 is at the ground voltage level, and the presence of a node in floating state in differential amplifier circuit 44 is avoided (power supply node 41 is also driven to the ground voltage level). )

  As for the output node 50, the output node 50 is accompanied by a capacitance of the load circuit, and the voltage is stably held by the capacitance of the load circuit even when the output node 50 is in a floating state.

  When the amplifier activation signal AMPEN is at the H level, the MOS transistor 60 is turned off, and the conductance of the drive transistor 46 is adjusted according to the comparison result between the reference voltage Vref and the voltage of the output node 50 as described above. Is called.

  Miller compensation circuit 55 includes a capacitive element C and a resistive element R connected in series between output node 50 and internal node 49. The mirror compensation circuit 55 applies negative feedback at the input / output of the differential amplifier circuit 44 to prevent the differential amplifier circuit 44 from oscillating. That is, when the voltage Vcpr of the output node 50 varies during the operation of the differential amplifier circuit 44, the voltage variation changes the internal node 49, that is, the gate voltage of the drive transistor 46 via the mirror capacitance C of the mirror compensation circuit 55. Let Accordingly, the conductance of drive transistor 46 is adjusted in a direction to suppress the voltage fluctuation of output node 50, and the voltage of output node 50 is stabilized. In the mirror compensation circuit 55, the resistance element R adjusts the sensitivity of the response, reduces the sensitivity to instantaneous noise voltage fluctuations, and responds excessively to the voltage fluctuations of the output node 50 to output node 50 prevents ripples from occurring.

  When the differential amplifier circuit 44 operates at high speed, phase inversion does not occur in the input / output response, and can substantially follow the voltage fluctuation of the output node 50, the mirror compensation circuit 55 needs to be particularly provided. Absent.

Next, the arrangement position of the withstand voltage relaxation circuit will be described.
(1) Consider that the constant current sources 40 and 42 are disposed between the output voltage line 38 and each of the constant current sources 40 and 42. The constant current sources 40 and 42 each use a PMOS transistor as a current source transistor. In this case, although the gate voltage of the current source transistor can be fixed, the source voltage varies due to the insertion of the withstand voltage relaxation circuit (due to variations in channel resistance of the withstand voltage relaxation MOS transistor). In addition, since the voltage level of the withstand voltage relaxation control signal Vscpr varies according to the operation mode, the gate-source voltage of the current source transistor varies according to the operation mode, and the drive current amount varies. For this reason, it becomes difficult to operate the differential amplifier circuit 44 with a constant driving current amount, and the supply current of the output node 50 also varies, and the time required to stabilize the internal voltage from the output node 50 Changes, and high-speed and stable operation cannot be guaranteed. Therefore, it is not preferable to arrange a withstand voltage relaxation circuit between the constant current sources 40 and 42 and the pump output voltage line 38.

  (2) When a withstand voltage relaxation circuit is arranged at the internal node of the differential amplifier circuit 44, a voltage drop occurs at the internal node of the differential amplifier circuit 44. In this case, in order to stably operate the differential stage MOS transistors PQ1 and PQ2 of the differential amplifier circuit 44, the voltage difference between the source and drain of these MOS transistors PQ1 and PQ2 cannot be increased. Therefore, when the voltage of output node 50 is a low voltage of 1 V, for example, a large current change cannot be generated in these MOS transistors PQ1 and PQ2, and the internal voltage can be generated stably by the differential amplification operation. Disappear. In addition, the gate-source voltages of the MOS transistors PQ1 and PQ2 increase when a low voltage is generated, and the breakdown voltage cannot be guaranteed. Therefore, it is not preferable to arrange a withstand voltage relaxation circuit at the internal node of the differential amplifier circuit.

  (3) A breakdown voltage reducing circuit is arranged between MOS transistors NQ 1 and NQ 2 and drive transistor 46. In this case, in order to operate the MOS transistors NQ1 and NQ2 in the saturation region in the differential amplifier circuit 44, it is necessary to increase the voltage level of the internal node (49) of the differential amplifier circuit 44. Therefore, similarly to the case considered in the above (2), it is impossible to stably generate a low voltage as the output voltage Vcpr.

  Also in the drive transistor 46, the gate-source voltage difference is reduced, and the response speed is lowered. In particular, when the voltage Vcpr at the output node 50 is low, the gate voltage when the drive transistor 46 is in an on state is higher than when a high voltage is output from the output node. Therefore, in this case, current cannot be drawn from the output node 50, and operation at the time of low voltage output cannot be guaranteed.

  Therefore, as shown in FIG. 5, the withstand voltage relaxation circuit is arranged between the constant current source 40 and the differential amplifier circuit 44, between the constant current source 42 and the output node 50, and between the output node 50 and the drive transistor 46. As a result, the breakdown voltage of the transistor of the step-down circuit can be guaranteed over a wide voltage range of the output voltage without causing a problem with the stability of the low voltage output and the step-down circuit.

  As described above, according to the first embodiment of the present invention, the step-down circuit 36 receives the operating power supply voltage and current from the output voltage line 38 of the charge pump circuit 32, and outputs based on the comparison with the reference voltage Vref. A voltage Vcpr is generated. Therefore, a high resistance element is not required and a circuit occupation area is reduced as compared with a configuration in which a necessary internal voltage is generated using a resistance voltage dividing circuit. In addition, the output voltage Vcpr at a necessary voltage level is only generated according to the operation mode. Therefore, it is not always necessary to flow current through the resistance voltage dividing circuit, and current consumption can be reduced.

  In addition, a breakdown voltage reducing circuit is provided at each of the operation power supply node and the output node of the comparison circuit, so that a low voltage output can be performed stably and the breakdown voltage of the transistor of the step-down circuit can be guaranteed.

[Embodiment 2]
FIG. 6 shows an overall configuration of the step-down circuit according to the second embodiment of the present invention. The step-down circuit shown in FIG. 6 differs from the step-down circuit shown in FIG. 5 in the following points.

  That is, in breakdown voltage relaxing circuit 52, P channel MOS transistor PQ5 is connected between the gate and source of P channel MOS transistor PQ3. MOS transistor PQ5 has a gate and a source coupled to constant current source 40, and a drain connected to the gate of MOS transistor PQ3.

  In breakdown voltage relaxing circuit 53, P channel MOS transistor PQ6 is connected between the gate of MOS transistor PQ4 and constant current source. MOS transistor PQ6 has a gate and a source connected to constant current source 42, and a drain connected to the gate of MOS transistor PQ4.

  In breakdown voltage relaxing circuit 54, N-channel MOS transistor NQ4 is connected between the gate of MOS transistor NQ3 and drive transistor 46. MOS transistor NQ4 has a back gate (substrate region) and a source connected to the gate of MOS transistor NQ3, and a gate and a drain connected to a connection node between drive transistor 46 and MOS transistor NQ3.

  In the step-down circuit 36, a breakdown voltage reducing circuit 62 is further provided between the output node 50 and the gate of the transistor PQ2 of the differential amplifier circuit 44. Further, a P voltage reduction circuit 62 is provided between the pump voltage output line 38 and the breakdown voltage relaxing circuit 53. A short-circuit transistor 64 composed of a channel MOS transistor is connected.

  The short-circuit transistor 64 receives the complementary short-circuit instruction signal SRTN at the gate, and is selectively turned on, and shorts the constant current source 42 when turned on. Breakdown voltage reducing circuit 62 includes an N channel MOS transistor NQ5 and a P channel MOS transistor PQ7 connected in parallel. MOS transistor NQ5 receives a withstand voltage relaxation control signal Vcrd at its gate, and MOS transistor PQ7 receives a short-circuit instruction signal SRT at its gate.

  The other configuration of the step-down circuit shown in FIG. 6 is the same as the configuration of the step-down circuit shown in FIG. 5, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  The reason why the diode-connected MOS transistors PQ5, PQ6, and NQ4 are provided in the breakdown voltage relaxing circuit 52-54 is as follows.

  Constant current sources 40 and 42 are selectively activated according to amplifier activation signal AMPEN. These constant current sources 40 and 42 usually receive a current control voltage (constant voltage) at their gates and cause a constant current to flow. When the gate voltage of the constant current source transistor is equal to the voltage of the pump output voltage line 36 (for example, when the step-down circuit is inactivated), the constant current source transistor is turned off. At this time, the source nodes of MOS transistors PQ3 and PQ4 of breakdown voltage relaxing circuits 52 and 53 may be in a floating state. In this case, when the voltage of the floating node is lowered due to the leakage current, a high voltage is applied between the source and drain of the constant current source transistor in the constant current sources 40 and 42, and the withstand voltage of the constant current source transistor is guaranteed. become unable.

  MOS transistor PQ5 operates in a diode mode, and clamps the source voltage of MOS transistor PQ3 to a voltage level lower than the withstand voltage relaxation control voltage Vscpr to the absolute value Vthp of its threshold voltage. At the time of high voltage generation, by setting the withstand voltage relaxation control voltage Vscpr to 3.5V, the lower limit value of the voltage of the source node of the MOS transistor PQ3 can be set to Vscpr−Vthp, and the transistor of the constant current source 40 The withstand voltage can be guaranteed. The same applies to the withstand voltage relaxation circuit 53. The lower limit value of the source voltage of the MOS transistor PQ4 is clamped to the voltage level of Vscpr−Vthp by the MOS transistor PQ6.

  In the breakdown voltage reducing circuit 54, when the drive transistor 46 is in an off state, the drain node of the drive transistor 46 is in a floating state. There is a possibility that the voltage of the floating node rises due to a leakage current from the output node 50 and a high voltage is applied between the drain and source of the drive transistor 46. MOS transistor NQ4 operates in a diode mode, and clamps the drain node of drive transistor 46 in a floating state to a voltage level of voltage Vcrd + Vthn. Here, Vthn represents the threshold voltage of MOS transistor NQ4.

  Short-circuit instruction signals SRT and SRTN are used when outputting pump high voltage Vcp as voltage Vcpr of output node 50 without stepping down. In this case, short circuit instruction signal SRT is set to H level (pump high voltage Vcp level), and complementary short circuit instruction signal SRTN is set to L level. In this case, the feedback control of the voltage level of the output voltage Vcpr is unnecessary, and the amplifier activation signal AMPEN is set to the inactive state (L level).

  In this state, MOS transistor PQ7 is turned off in breakdown voltage relaxing circuit 62. MOS transistor NQ5 receives withstand voltage control voltage Vcrd at its gate, and transmits voltage Vcpr-vthn from output node 50 to the gate of MOS transistor PQ2. This prevents a high voltage from being applied between the gate and source / drain of the MOS transistor PQ2. Differential amplifier circuit 44 is in an inactive state, no current is supplied from constant current source 40, the internal node is maintained at the ground voltage level, and the floating state of the internal node is avoided by MOS transistor 60. Is done.

  Further, the short-circuit transistor 64 is turned on, the constant current source 42 is short-circuited, and the voltage from the output node 50 pump output voltage line 38 is transmitted to the output node. At this time, if the withstand voltage control voltage scpr is set to the ground voltage level, in the withstand voltage relaxation circuit 53, the source-drain voltage of the transistor of the constant current source 42 is 0 V by the MOS transistor PQ4, and the withstand voltage is guaranteed. The

  In the withstand voltage relaxation circuit 54, by setting the withstand voltage relaxation control voltage Vcrd to 5.5V, even if the output voltage Vcpr is 11V, the MOS transistor NQ3 sets the drain voltage of the drive transistor 46 to the voltage Vcrd−vthn. Set to level. Therefore, even when the drive transistor 46 is in the OFF state, the drain-source voltage can be sufficiently relaxed.

  When lowering pump high voltage Vcp, short circuit instruction signal SRT is set to L level, and complementary short circuit instruction signal SRTN is set to H level of the pump high voltage level. In accordance with the activation of the amplifier activation signal AMPEN, the step-down operation is performed as in the first embodiment.

  In the step-down circuit shown in FIG. 5, the clamping transistors PQ5, PQ6, and NQ4 shown in FIG.

  As described above, according to the second embodiment of the present invention, the clamp transistor for preventing floating is provided in the breakdown voltage relaxing circuit. Therefore, the breakdown voltage of the current source transistor and the voltage extracting drive transistor can be reliably maintained. Further, the output node and the pump output voltage line 38 can be short-circuited using a short-circuit transistor. Therefore, the voltage range of the output node voltage can be expanded.

[Embodiment 3]
FIG. 7 shows a structure of step-down circuit 36 according to the third embodiment of the present invention. The step-down circuit 36 shown in FIG. 7 differs from the step-down circuit 36 shown in FIG. 5 in the following points. That is, in the step-down circuit shown in FIG. 7, a variable current source 65 is used instead of the constant current source 42. A selector 66 is provided to adjust the drive current of the variable current source 65.

  The other configuration of the step-down circuit 36 shown in FIG. 7 is the same as the configuration of the step-down circuit 36 shown in FIG. 5, and corresponding portions are denoted by the same reference numerals and detailed description thereof is omitted. In FIG. 7, clamp transistors PQ5, PQ6, and NQ4 are shown in breakdown voltage reduction circuits 52, 53, and 54, but these clamp transistors PQ5, PQ6, and NQ4 are not provided as in the first embodiment. May be.

  For example, the selector 66 adjusts the supply current amount of the variable current source 65 in accordance with the 4-bit selection signals SEL <3: 0>. The logical values of the 4-bit selection signals SEL <3: 0> are set according to the operation mode. For example, when the system is started up, the drive current amount of variable current source 65 is increased in accordance with the power-on detection signal, and voltage Vcpr of output node 50 is set to a predetermined voltage level at high speed.

  Even at the start of each operation mode, the voltage level of the output voltage Vcpr is increased or decreased at high speed by adjusting the drive current amount of these variable current sources 65. When the voltage level of the output voltage Vcpr is stabilized, the current consumption is reduced by reducing the drive current amount of the variable current source 65 in accordance with the 4-bit selection signal SEL <3: 0>.

  The variable current source 65 may have its drive current amount adjusted by the selector 64 in the standby mode and in accordance with an operation cycle in which data is actually written / erased / read.

  This selection signal SEL <3: 0> is generated according to each operation mode from the control circuit 30 shown in FIG.

  FIG. 8 is a diagram showing an example of the configuration of variable current source 65 and selector 66 shown in FIG. In FIG. 8, variable current source 65 includes P channel MOS transistors PT0-PT3 coupled in parallel between pump output voltage line 38 and internal output node 69. Internal output node 69 is coupled to breakdown voltage relaxing circuit 53 shown in FIG.

  Selector 66 includes NAND gates NG0-NG3 provided corresponding to the MOS transistors. NAND gates NG0-NG3 receive selection signals SEL <0> -SEL <3> and amplifier activation signal AMPEN, respectively, and provide respective output signals to the gates of corresponding MOS transistors PT0-PT3.

  NAND gates NG0-NG3 receive pump high voltage Vcp as a high-side power supply voltage and receive constant voltage Vc as a low-side power supply voltage. With this constant voltage, the drive currents of the MOS transistors PT01 to PT3 are set. These MOS transistors PT0 to PT3 may have the same size (ratio of channel length to channel width), or may have different sizes such as 1, 2, 4, and 8. The control circuit 30 shown in FIG. 4 sets the logical value of each bit of the selection signal SEL <3: 0> according to the operation mode.

  When amplifier activation signal AMPEN is at the H level, NAND gates NG0-NG3 operate as inverters, and MOS transistors PT0-PT3 are selectively set in a conductive state in accordance with 4-bit selection signals SEL <3: 0>.

  When amplifier activation signal AMPEN is at L level, the output signals of NAND gates NG0 to NG3 are at H level of the pump high voltage level, and MOS transistors PT0 to PT3 are turned off.

  As described above, according to the third embodiment of the present invention, the amount of current supplied to the output node can be changed. Therefore, the output voltage can be changed at high speed and stabilized according to the operation mode. Further, the current consumption can be reduced by reducing the supply current from the variable current source after the output voltage is stabilized. Moreover, the same effect as Embodiment 1 can be acquired.

[Embodiment 4]
FIG. 9 shows a structure of internal voltage down converting circuit 36 according to the fourth embodiment of the present invention. The configuration of the internal step-down circuit shown in FIG. 9 is different from that shown in FIG. 6 in the following points. That is, a variable current source 65 and a selector 66 are used in place of the constant current source 42. The other configuration of the step-down circuit shown in FIG. 9 is the same as the configuration of the step-down circuit shown in FIG. 6, and corresponding portions are denoted by the same reference numerals, and detailed description thereof is omitted.

  In the configuration shown in FIG. 9 as well, clamping transistors PQ5, PQ6, and NQ4 may be omitted in breakdown voltage relaxing circuit 52-54.

  In the configuration of the step-down circuit 36 shown in FIG. 9, when the pump high voltage Vcp is output as a voltage from the output node 50, the supply voltage of the variable current source 65 is increased to increase the output voltage Vcr at a high speed. Can be driven to level. Similarly to the third embodiment, by adjusting the output signal of the selector 66 according to the operation mode, an internal voltage having a predetermined voltage level can be generated stably at a high speed with a low current consumption.

  Note that the configuration shown in FIG. 8 can be used as the configuration of the variable current source 65 and the selector 66 shown in FIG.

[Embodiment 5]
FIG. 10 schematically shows an example of the configuration of control circuit 30 shown in FIGS. In FIG. 10, a control circuit 30 receives a power supply voltage VCC as an operation power supply voltage, detects a mode of operation in accordance with an external command CMD, and a withstand voltage relaxation control signal in accordance with a mode instruction signal from the mode detection circuit 70. A relaxation signal generation circuit 72 that generates Vscpr and Vcrd, and a drive current adjustment circuit 74 that generates a 4-bit selection signal SEL <3: 0> according to a mode detection signal from the mode detection circuit 70 are included.

  Relaxation signal generation circuit 72 includes a circuit for generating a voltage level (3.5 V and 5.5 V) different from power supply voltage VCC therein, and these relaxation relaxations according to the operation mode or the voltage level of the pump high voltage. The voltage levels of the control signals Vscpr and Vcrd are adjusted. When the pump high voltage is at a voltage level of 11 V, for example, exceeding the breakdown voltage of the transistor of the step-down circuit, these breakdown voltage relaxation control signals Vscpr and Vcrd are set to 3.5 V and 5.5 V, respectively. When the pump high voltage is at a voltage level that does not exceed the breakdown voltage (for example, 9 V) of the transistor of the step-down circuit, the breakdown voltage relaxation control signal Vscpr is set to 0V. In this case, the voltage level of the withstand voltage relaxation control signal Vcrd may always be maintained at a voltage level of 5.5V. As a result, an internal voltage can be generated using a step-down circuit having the same configuration with respect to the voltage generated internally (the voltage level generated by the pump circuit is set according to the application used internally). .

  The drive current adjustment circuit 74 is provided when the variable current source 65 shown in FIG. 7 is used, and sets each bit value of the 4-bit selection signal SEL <3: 0> according to the operation mode. When the internal voltage (the voltage Vcpr of the output node 50) is increased at high speed when the power is turned on or when the operation mode is changed, the supply current amount of the variable current source 65 is increased by the selection signal SEL <3: 0>. . When the voltage level of the output voltage Vcrd is lowered when the operation mode is changed, the amount of current supplied to the variable current source 65 is lowered according to the selection signal SEL <3: 0>. When the internal voltage stabilizes, the drive current adjustment circuit 74 sets the supply current amount of the variable current source 65 to a default value, supplies the current required during operation, and reduces the current consumption.

  In the case of setting to this default value, the bit value of the selection signal SEL <3: 0> may be set to the default value after a predetermined time has elapsed when the operation mode is changed. Alternatively, the selection signal SEL <3: 0> is set to a default value when the output voltage reaches a desired voltage level (voltage level of the reference voltage) based on a comparison with the reference voltage Vref. May be. By detecting a change in the logic level of the output signal of the circuit that compares the reference voltage and the output voltage, it is possible to detect whether the output voltage has reached the voltage level defined by the reference voltage. For example, it is possible to detect whether the output voltage Vcpr has reached a predetermined value by using a circuit that detects the rise and fall of the output signal of the comparison circuit. In this case, the differential amplifier circuit 44 in the step-down circuit may be used as the comparison circuit.

  Control circuit 30 further includes a step-down control circuit 75 that generates amplifier activation signal AMPEN and short-circuit instruction signals SRT and SRTN in accordance with the output signal of mode detection circuit 70. This step-down control circuit 75 stabilizes the amplifier activation signal AMPEN and the output voltage Vcpr when the voltage level of the output voltage Vcpr is increased at high speed according to the operation mode detection signal when a variable current source is provided. Until inactive. When the output voltage Vcpr is lowered when the operation mode is changed, the amplifier activation signal AMPEN is activated regardless of the output voltage level according to the mode detection.

  When the variable current source is not provided as in the first and second embodiments, step-down control circuit 75 activates amplifier activation signal AMPEN according to the mode detection. When the mode is changed, the voltage level of the output node is adjusted according to the comparison result between the reference voltage and the output voltage.

  Further, step-down control circuit 75 selectively activates short-circuit instruction signals SRT and SRTN according to the mode detection signal when short-circuit transistors are provided as in the second and fourth embodiments. That is, the step-down control circuit 75 sets the voltage level of the output control signal according to whether or not the output voltage Vcpr of the step-down circuit is equal to the voltage level of the pump high voltage Vcp. For example, when a high pump voltage Vcp of 11 V, for example, is used as output voltage Vcpr (in write mode), amplifier activation signal AMPEN is at L level, short circuit instruction signal SRTEN is at L level, and short circuit instruction signal SRT is at H level. Set. As a result, the comparison operation of the differential amplifier circuit 44 is stopped, the short-circuit transistor (64) is turned on, and the pump high voltage Vcp can be transmitted to the output node 50.

  By using the control circuit 30 shown in FIG. 10, the breakdown voltage of the transistor of the step-down circuit can be relaxed regardless of the voltage level of the pump high voltage, and the stability of the circuit operation can be ensured. When a variable current source is provided, the output voltage can be driven to a predetermined voltage level at high speed by adjusting the amount of current of the variable current source, and the internal operation start timing can be advanced. . In addition, current consumption can be reduced by reducing the amount of current supplied to the variable current source after the output voltage has risen to a predetermined voltage level according to the operation mode.

  FIG. 11 is a diagram showing an example of the configuration of reference voltage generating circuit 34 shown in FIG. In FIG. 11, reference voltage generating circuit 34 includes P channel MOS transistors PTR0-PTRk coupled in parallel to a power supply node supplying power supply voltage VCC, and an N channel MOS receiving current supplied from these MOS transistors PTR0-PTRk. Transistor NTR1 and MOS transistor NTR1 and N channel MOS transistor NTR2 forming a current mirror circuit are included.

  MOS transistors PTR0-PTRk receive activation control signals ZEN0-ZENk at their gates. The activation control signals ZEN0 to ZENk are set to respective voltage levels (logic levels) under the control of the control circuit (30) shown in FIG. 4 according to the operation mode.

  MOS transistor NTR1 has its gate and drain interconnected to convert the supply current from MOS transistors PTR0 to PTRk into a voltage. MOS transistor NTR2 passes a mirror current of the current flowing through MOS transistor NTR1. If the mirror ratio is 1, the same current flows through the MOS transistors NTR1 and NTR2.

  Reference voltage generation circuit 34 further includes a pump circuit 76 that generates high voltage Vp higher than power supply voltage VCC, a P-channel MOS transistor PTRm connected between the output node of pump circuit 76 and MOS transistor NTR2, and a pump. P channel MOS transistor PTRn connected between the output node of circuit 76 and reference voltage output node 78, and resistance element RZ connected between reference voltage output node 78 and the ground node.

  MOS transistor PTRm has a gate and a drain connected to each other. Therefore, a current mirror stage is formed by MOS transistors PTRm and PTRn, and a mirror current of a current flowing through MOS transistor PTRm flows through MOS transistor PTRn. If the mirror ratio is 1, the same current I flows through the MOS transistors PTRm and PTn.

  In the configuration of reference voltage generation circuit 34 shown in FIG. 11, activation control signals ZEN0 to ZENk are set to respective voltage levels according to the operation mode. Thereby, the current supplied to MOS transistor NTR1 can be set, and accordingly, the amount of mirror current flowing through MOS transistors NTR2 and PTRm can be adjusted. Therefore, the voltage level of reference voltage Vref from reference voltage output node 78 is set by the product I · RZ of resistance value RZ of resistance element RZ and current I supplied via MOS transistor PTRn. Therefore, even if one resistance element RZ is used, the voltage level of the reference voltage Vref can be adjusted in the range of 1 V to 6.3 V, for example, by adjusting the current value of the current I.

  The MOS transistors PTR0 to PTRk may have the same size (ratio of channel width to channel length), and have different size ratios such as 1 time, 2 times, 4 times,. A different amount may be used. The voltage level of the reference voltage Vref can be changed according to the step value of the current supplied from the MOS transistors PTR0 to PTRk.

  In reference voltage generating circuit 34, reference voltage Vref is only required to set the gate voltage of MOS transistor PQ1 of differential amplifier circuit 44 in the step-down circuit shown in FIG. The gate capacity of MOS transistor PQ1 is small, and the input impedance of the gate of MOS transistor PQ1 is high impedance. Therefore, the drive current amount of the reference voltage generation circuit 34 can be made sufficiently small, and the current consumption is sufficiently suppressed. Further, only one resistance element RZ is used, and the layout area can be sufficiently reduced.

  As an example, the pump circuit 76 is provided exclusively for the reference voltage generation circuit 34. Since the drive current amount of the reference voltage Vref is small, the pump current driving force of the pump circuit 76 can be made sufficiently small. Further, it is only necessary to generate the maximum voltage (for example, 6.3 V) of the reference voltage Vref, and the layout area of the pump circuit 76 can be sufficiently reduced (the element size and the capacity element can be reduced). . As the pump circuit 76, the charge pump circuit 32 shown in FIG. 4 may be used.

  In the reference voltage generation circuit 34, even if the current I flowing through the MOS transistor PTRn is small, if the resistance value of the resistance element RZ is sufficiently large, the voltage change of the reference voltage Vref may be increased by a small change in the current I. it can. Further, by sufficiently increasing the resistance value of the resistance element RZ, the current consumption of the pump circuit 76 can be sufficiently reduced.

  When output voltage Vcpr is at pump high voltage Vcp voltage level, reference voltage generation circuit 34 sets all activation control signals ZEN0 to ZENk to H level and stops pump operation of pump circuit 76. As a result, the reference voltage generation operation can be stopped, and current consumption can be reduced.

  Further, in the standby state or the like, all the activation control signals ZEN0 to ZENk may be set to the H level and the pump operation of the pump circuit 76 may be stopped.

  FIG. 12 schematically shows a structure of internal voltage generation circuit 28 shown in FIG. In FIG. 8, an internal voltage generation circuit 80 (28) corresponds to a voltage used internally, a control gate voltage generation circuit 82, a memory cell gate voltage generation circuit 84, a bit line voltage generation circuit 86, Source line voltage generation circuit 88.

  Control gate voltage generation circuit 82 generates control gate voltage Vcg transmitted to the control gate line. The control gate line is connected to the control gate of the select transistor of the memory cell. In the writing and erasing modes, for example, it is set to 1 V at the time of selection, and in the reading mode, it is set to a power supply voltage level or 3.5 V higher than it.

  Memory cell gate voltage generation circuit 84 transmits memory gate voltage Vmg transmitted to memory gate line Vmg. The gate of the memory cell transistor is connected to the memory gate line. At the time of writing, 11V is used as the selection voltage and 3.5V is used as the non-selection voltage. At the time of reading, a voltage having a voltage level intermediate between the threshold voltages in the erased state and the written state is generated as the selection voltage. The non-selection voltage is a voltage equal to or lower than the threshold voltage in the erased state. When the threshold voltage in the erase state is a negative value, that is, when the memory cell is set to the over-erased state, the memory gate voltage Vmg is maintained at the ground voltage level at the time of reading regardless of selection / non-selection. May be. The selection voltage level of the memory gate voltage Vmg at the time of erasing is a negative voltage, which is generated using a charge pump circuit that generates a negative high voltage provided separately.

  Bit line voltage generation circuit 86 generates bit line voltage Vbl transmitted to the bit line. As for this bit line voltage Vmg, at the time of writing and erasing, the bit line voltage of the non-selected column is 1.5V, and the bit line voltage of the selected column is 0.8V. At the time of reading, a bit line read voltage for transmitting a read current is transmitted to the bit line. This bit line read voltage is at a voltage level lower than the control gate voltage at the time of reading.

  Source line voltage generation circuit 88 transmits source line voltage Vs transmitted to the source line. Source line voltage Vs is 5 V in the selected block and 1.5 V or the ground voltage level in the non-selected block at the time of writing and erasing. The voltage level of the source line voltage Vs at the time of non-selection is set according to the configuration of the block for writing and erasing units. At the time of reading, source line voltage Vs is maintained at the ground voltage level. When transmitting the selection voltage and the non-selection voltage to the corresponding signal line, the selection voltage and the non-selection voltage or vice versa are transmitted to the high-side power supply node and low-side power supply node of the driver (for example, bit line driver), respectively. .

  As shown in FIG. 12, by setting a selection voltage level and a non-selection voltage level for each internal voltage, a voltage required according to the operation mode can be generated for each circuit.

  In addition, these voltage generation circuits 82, 84, 86, and 88 have the same internal configuration as that shown in the first to fourth embodiments, and have the same configuration. In the step-down circuit shown in the first to fourth embodiments and the reference voltage generation circuit shown as an example in FIG. 11, one module is registered as a library with guaranteed operating characteristics. Each voltage generation circuit 82, 84, 86 and 88 is configured using this registration module. As a result, it is possible to easily generate an internal voltage generation circuit having a small occupation area with guaranteed operating characteristics. In addition, even when the number of memory blocks increases when expanding the internal configuration of the non-volatile memory, these internal voltage generation circuits (internal voltage down converters) are arranged for each memory block to support memory expansion. Thus, it is possible to easily cope with the expansion of the internal voltage generation circuit.

  In the above description, the charge pump circuit that generates the pump high voltage is also provided according to the internal voltage. However, a configuration in which a charge pump circuit that generates a pump high voltage is provided in common for a plurality of internal voltages, and a step-down circuit is arranged corresponding to each internal voltage may be used. According to the pump high voltage from the common charge pump circuit, each internal voltage is generated by the step-down circuit according to the reference voltage.

  In the above-described embodiment, the pump high voltage Vcp higher than the power supply voltage VCC is generated. However, the internal voltage generation circuit may be a circuit that generates a negative high voltage. In the step-down circuit shown in the first to fourth embodiments, the structure of the step-down circuit of the internal voltage generation circuit that generates a negative high voltage is easy by making the polarity of the transistor opposite and the voltage polarity of the power supply node reversed. To be realized.

  Further, a MONOS type memory is shown as the nonvolatile memory. However, the configuration of the internal voltage generation circuit according to the present invention can also be applied to a nonvolatile memory that stores data in accordance with the amount of charge accumulated in the floating gate.

  In general, the present invention can be applied to a semiconductor circuit device that uses a plurality of types of internal voltages internally, thereby realizing an internal voltage generating circuit with low current consumption and a low occupied area. In particular, by applying the internal voltage generation circuit according to the present invention to a non-volatile memory that requires a high voltage in programming / erasing, etc., an internal voltage generation circuit having a low current consumption and a low occupation area while guaranteeing a withstand voltage can be obtained. Can be realized. In addition, the current consumption and layout area of the system can be reduced by applying to a use such as a system on chip (SOC) in which the nonvolatile memory according to the present invention is mounted.

  In the description so far, the internal voltage generation circuit 28 (80) is shown to be provided in the nonvolatile memory. However, when a plurality of memories and logic are integrated on one semiconductor chip, such as SOC, this internal voltage generation circuit (28, 80) is external to the block (macro) of the nonvolatile memory 4. May be arranged. In this case, the internal voltage generation circuit is arranged on the chip as one macro.

1 is a diagram schematically showing an overall configuration of a semiconductor integrated circuit to which the present invention is applied. FIG. 2 is a diagram schematically showing an example of an electrically equivalent circuit of memory cells included in the nonvolatile memory shown in FIG. 1. It is a figure which shows schematically the whole structure of the non-volatile memory shown in FIG. FIG. 4 is a diagram schematically showing a configuration of an internal voltage generation circuit shown in FIG. 3. It is a figure which shows the structure of the pressure | voltage fall circuit according to Embodiment 1 of this invention. It is a figure which shows the structure of the pressure | voltage fall circuit according to Embodiment 2 of this invention. It is a figure which shows roughly the structure of the pressure | voltage fall circuit according to Embodiment 3 of this invention. It is a figure which shows an example of a structure of the variable current source and selector which are shown in FIG. It is a figure which shows the structure of the pressure | voltage fall circuit according to Embodiment 4 of this invention. FIG. 4 is a diagram schematically showing a configuration of a control circuit shown in FIG. 3. FIG. 5 is a diagram illustrating an example of a configuration of a reference voltage generation circuit illustrated in FIG. 4. FIG. 4 is a diagram schematically showing an overall configuration of an internal voltage generation circuit shown in FIG. 3.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 Semiconductor integrated circuit device, 4 Nonvolatile memory, MC memory cell, ST selection transistor, MT memory cell transistor, 20 Memory cell array, 22 Row selection drive circuit, 24 Source line selection drive circuit, 26 Bit line selection drive circuit, 28, 28A internal voltage generation circuit, 30 control circuit, 32 charge pump circuit, 34 reference voltage generation circuit, 36 step-down circuit, 40, 42 constant current source, 44 differential amplification circuit, 46 drive transistor, 52, 53, 54 withstand voltage relaxation circuit , PQ1-PQ6 P channel MOS transistor, NQ1-NQ4 N channel MOS transistor, 59 inverter, 60 N channel MOS transistor, 64 short-circuit MOS transistor, 65 variable current source, 66 selector, 70 mode detection circuit, 72 relaxation signal generation Circuit, 74 drive current adjustment circuit, 75 step-down control circuit, 76 pump circuit, 80 internal voltage generation circuit, 82 control gate voltage generation circuit, 84 memory cell gate voltage generation circuit, 86 bit line voltage generation circuit, 88 source line voltage generation circuit.

Claims (5)

A pump circuit that generates a boosted voltage on the voltage output line by pump operation;
A first current source coupled to a voltage output line of the pump circuit and for passing a current between the voltage output line of the pump circuit and an output node;
A reference voltage generation circuit for generating a reference voltage whose voltage level is set according to the operation mode;
In operation, a comparison circuit that compares the reference voltage from the reference voltage generation circuit with the voltage of the output node, and generates a signal according to the comparison result;
A driver element for passing a current between the output node and a reference potential node in accordance with an output signal of the comparison circuit;
A second current source coupled between the voltage output line of the pump circuit and the comparison circuit, for flowing an operating current of the comparison circuit;
The voltage applied between the first current source and the output node is relaxed by causing a voltage difference between the first current source and the output node. A first withstand voltage relaxation circuit,
Connected between the second current source and the comparison circuit, and creates a voltage difference between the second current source and the comparison circuit, thereby relaxing the voltage applied to the components of the comparison circuit. An internal voltage generation circuit comprising: a second withstand voltage mitigating circuit; and a third withstand voltage mitigating circuit that is connected between the output mode and the drive element and that relaxes a voltage applied to the drive element. The comparison circuit has a first comparison input for receiving the reference voltage and a second comparison input node coupled to the output node;
The internal voltage generation circuit further includes:
A first short-circuit element that electrically short-circuits the voltage output line of the pump circuit and the output node according to a short-circuit instruction signal;
A second short-circuit element that conducts complementarily with the first short-circuit element in accordance with the short-circuit instruction signal and electrically couples the output node and the second comparison input node when conducting;
2. The breakdown voltage reducing element connected between the output node and the second comparison input node, and generating a voltage difference between the output node and the second comparison input node. Internal voltage generator circuit. The first current source is a variable current source capable of changing a drive current amount,
The internal voltage generation circuit according to claim 1, further comprising a selector that sets a supply current amount of the variable current source according to an operation mode. The first breakdown voltage reduction circuit includes a first conductivity type first transistor connected between the first current source and a power supply node of the comparison circuit and receiving a first breakdown voltage control signal at a gate. ,
The second breakdown voltage relaxation circuit includes a second transistor of a first conductivity type that is connected between the second current source and the output node and receives the first breakdown voltage control signal at a gate.
The third breakdown voltage mitigating circuit includes a second conductivity type third transistor connected between the output node and the drive element and receiving a second breakdown voltage control signal at a gate. An internal voltage generation circuit according to any one of the above. The first withstand voltage relaxation circuit further includes a first clamp element that clamps a voltage at a connection node between the first transistor and the first current source,
The second breakdown voltage relaxation circuit further includes a second clamp element that clamps a voltage at a connection node between the second transistor and the second current source,
5. The internal voltage generation circuit according to claim 4, wherein the third breakdown voltage relaxation circuit further includes a third clamp element that clamps a voltage at a connection node between the third transistor and the drive element.

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