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JP2008198687A - Printed wiring board - Google Patents

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JP2008198687A
JP2008198687A JP2007030034A JP2007030034A JP2008198687A JP 2008198687 A JP2008198687 A JP 2008198687A JP 2007030034 A JP2007030034 A JP 2007030034A JP 2007030034 A JP2007030034 A JP 2007030034A JP 2008198687 A JP2008198687 A JP 2008198687A
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pad
resistor
main
sub
pads
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JP4403428B2 (en
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Masatoshi Nakabo
真敏 中坊
Makoto Yoshida
吉田  誠
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Onkyo Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a printed wiring board having a Kelvin connection pattern capable of more correct current detection. <P>SOLUTION: Respective pads for soldering both electrodes of a surface-mounted type resistor are divided into rectangular main pads 20 and 21 and L-shaped sub pads 24 and 25. Sub outgoing lines 26 and 27 for detecting current extend from specific positions X1 and Y1 on the sub pads 24 and 25 close to a reference point where a standard resistance value of the resistor 1 is exhibited. An area of the main pads 20 and 21 is approximately the same as that of the sub pads 24 and 25. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

本発明は、プリント配線板に関し、さらに詳しくは、表面実装型電流検出用抵抗器を実装するための配線パターンに関する。   The present invention relates to a printed wiring board, and more particularly to a wiring pattern for mounting a surface mount type current detection resistor.

DC/DCコンバータなどのIC(Integrated Circuit)をプリント配線板上に実装するに際しては、出力電流を検出するために、低抵抗でかつ誤差の小さい精密抵抗器を外付けで実装する場合がある。このような抵抗器として表面実装型抵抗器を用いた場合における従来の配線パターンを図8に示し、表面実装型抵抗器を図9に示す。   When an IC (Integrated Circuit) such as a DC / DC converter is mounted on a printed wiring board, a precision resistor having a low resistance and a small error may be externally mounted in order to detect an output current. FIG. 8 shows a conventional wiring pattern when a surface-mounted resistor is used as such a resistor, and FIG. 9 shows a surface-mounted resistor.

図8を参照して、表面実装型抵抗器1をはんだ付けするための各パッドは2つに分割されている。すなわち、各パッドは、面積の大きい主パッド2,3と、面積の小さい副パッド4,5とからなる。また、図9を参照して、表面実装型抵抗器1は、抵抗体6、一方電極7及び他方電極8からなる。   Referring to FIG. 8, each pad for soldering the surface-mounted resistor 1 is divided into two. That is, each pad is composed of main pads 2 and 3 having a large area and sub pads 4 and 5 having a small area. Referring to FIG. 9, the surface-mounted resistor 1 includes a resistor 6, one electrode 7, and the other electrode 8.

再び図8を参照して、抵抗器1の一方電極7は主パッド2及び副パッド4にまたがって配置され、はんだ付けされる。一方、抵抗器1の他方電極8は主パッド3及び副パッド5にまたがって配置され、はんだ付けされる。ICから出力された大電流は主引出線9、主パッド2、抵抗器1、主パッド3及び主引出線10の順に流れる。副パッド4,5から延び出している副引出線11,12は電圧計に接続され、これにより抵抗器1にかかる電圧が測定され、抵抗器に流れる電流が検出される。このように電流検出用抵抗器に対して、実際の大電流を流すラインと、電流を検出するためのラインとをそれぞれ別々に設けたものを一般に「ケルビン接続」と呼んでいる。ケルビン接続によれば、パッドが一体的な場合と比較して、大電流が流れても電流検出用のラインがその影響を受けにくく、より正確に電流を検出できる。   Referring to FIG. 8 again, the one electrode 7 of the resistor 1 is disposed across the main pad 2 and the sub pad 4 and soldered. On the other hand, the other electrode 8 of the resistor 1 is disposed over the main pad 3 and the sub pad 5 and soldered. The large current output from the IC flows in the order of the main lead wire 9, the main pad 2, the resistor 1, the main pad 3, and the main lead wire 10. The sub lead lines 11 and 12 extending from the sub pads 4 and 5 are connected to a voltmeter, whereby the voltage applied to the resistor 1 is measured and the current flowing through the resistor is detected. In this way, a line in which an actual large current flows and a line for detecting current are separately provided for the current detection resistor are generally called “Kelvin connection”. According to the Kelvin connection, even when a large current flows, the current detection line is less affected by the current, and the current can be detected more accurately than when the pads are integrated.

しかしながら、ケルビン接続にも問題がある。図9を参照して、抵抗器1の規格上の抵抗値は抵抗体6の基準点X及びYの間に現れる。一方電極7が主パッド2に接触する基準点Xの真下の位置をX1とすると、位置X1と副引出線11との間には一定の距離L1がある。他方電極8が主パッド3に接触する基準点Yの真下の位置をY1とすると、位置Y1と副引出線12との間には一定の距離L1(たとえば2.0mm)がある。したがって、抵抗体6の規格上の抵抗値以外に、これらの距離L1に相当する抵抗値が加わってしまい、正確に電流を検出できないという問題がある。ただし、副引出線11,12を副パッド4,5の外側ではなく内側から延び出すように配置すれば、その距離L2(たとえば1.25mm)は少しだけ短くなるが、それ以上短くすることはできない。   However, there are problems with Kelvin connections. Referring to FIG. 9, the standard resistance value of resistor 1 appears between reference points X and Y of resistor 6. On the other hand, when the position immediately below the reference point X where the electrode 7 contacts the main pad 2 is X1, there is a certain distance L1 between the position X1 and the sub lead line 11. If the position immediately below the reference point Y where the other electrode 8 contacts the main pad 3 is Y1, there is a certain distance L1 (for example, 2.0 mm) between the position Y1 and the sub lead line 12. Therefore, in addition to the resistance value on the standard of the resistor 6, a resistance value corresponding to the distance L1 is added, and there is a problem that current cannot be detected accurately. However, if the sub lead lines 11 and 12 are arranged so as to extend from the inside rather than the outside of the sub pads 4 and 5, the distance L2 (for example, 1.25 mm) is slightly shortened. Can not.

また、はんだは主パッド2及び副パッド4にまたがって塊で盛り付けられるが、主パッド2及び副パッド4の面積が異なるため、表面張力の大きい主パッド2にはんだが偏ってしまう。主パッド3及び5側もこれと同様である。そのため、接触不良が起きやすいという問題がある。   Further, the solder is placed in a lump over the main pad 2 and the sub pad 4, but since the areas of the main pad 2 and the sub pad 4 are different, the solder is biased to the main pad 2 having a large surface tension. The same applies to the main pads 3 and 5 side. Therefore, there is a problem that poor contact is likely to occur.

特開2002−372551号公報(特許文献1)には、電流検出用抵抗器の実装構造に関する技術が開示されている。この技術によると、電流検出用抵抗器の電圧検出端子(ケルビン端子)に接続する基板上の配線パターンを、電流検出用抵抗器の抵抗体と電気的絶縁を取りながら抵抗体の被測定電流経路に沿って延長してから、被測定電流経路と直角方向に引き出している。また、被測定電流電極の一部を電圧検出端子として用いている電流検出用抵抗器において、被測定電流電極の電圧検出端子部分と基板上のパターンの接続点を、電流検出用抵抗器の抵抗体の被測定電流に沿った方向の中心軸から、互いに反対方向に離隔して配置している。この構造をとると、抵抗体の被測定電流経路とケルビン端子からの配線パターンが相互インダクタンスにより磁気結合し、ケルビン端子間で検出される電圧には、被測定電流経路のインダクタンスの影響による電流の時間的変化に比例した誤差電圧に対して、相互インダクタンスにより形成される電圧がこれを打ち消すように作用する、というものである。しかしながら、ここで用いられている各パッドは2つに分割されていない。
特開2002−372551号公報
Japanese Unexamined Patent Application Publication No. 2002-372551 (Patent Document 1) discloses a technique related to a mounting structure of a current detection resistor. According to this technology, the wiring pattern on the substrate connected to the voltage detection terminal (Kelvin terminal) of the current detection resistor is electrically insulated from the resistor of the current detection resistor, and the current path to be measured of the resistor is measured. And then drawn in a direction perpendicular to the current path to be measured. In addition, in a current detection resistor that uses a part of the current electrode to be measured as a voltage detection terminal, the connection point between the voltage detection terminal portion of the current electrode to be measured and the pattern on the substrate is the resistance of the current detection resistor. They are spaced apart from the central axis in the direction along the measured current of the body in opposite directions. With this structure, the measured current path of the resistor and the wiring pattern from the Kelvin terminal are magnetically coupled by mutual inductance, and the voltage detected between the Kelvin terminals has a current due to the influence of the inductance of the measured current path. The voltage formed by the mutual inductance acts to cancel the error voltage proportional to the time change. However, each pad used here is not divided into two.
JP 2002-372551 A

本発明の目的は、より正確に電流を検出できるケルビン接続パターンを有するプリント配線板を提供することである。   The objective of this invention is providing the printed wiring board which has a Kelvin connection pattern which can detect an electric current more correctly.

課題を解決するための手段及び発明の効果Means for Solving the Problems and Effects of the Invention

本発明によるプリント配線板は、第1及び第2の主パッドと、第1及び第2の主引出線と、第1及び第2の副パッドと、第1及び第2の副引出線とを備える。第1の主パッドは、表面実装型抵抗器の一方電極がはんだ付けされる。第2の主パッドは、抵抗器の他方電極がはんだ付けされる。第1の主引出線は、第1の主パッドから延び出す。第2の主引出線は、第2の主パッドから延び出す。第1の副パッドは、第1の主パッドに隣接して配置され、抵抗器の一方電極が第1の主パッドと一緒にはんだ付けされる。第2の副パッドは、第2の主パッドに隣接して配置され、抵抗器の他方電極が第2の主パッドと一緒にはんだ付けされる。第1の副引出線は、抵抗器の規格上の抵抗値が現れる一方基準点に近い第1の副パッドの特定位置から延び出す。第2の副引出線は、抵抗器の規格上の抵抗値が現れる他方基準点に近い第2の副パッドの特定位置から延び出す。   The printed wiring board according to the present invention includes first and second main pads, first and second main lead lines, first and second sub pads, and first and second sub lead lines. Prepare. The first main pad is soldered to one electrode of the surface mount resistor. The second main pad is soldered to the other electrode of the resistor. The first main lead line extends from the first main pad. The second main lead line extends from the second main pad. The first sub-pad is disposed adjacent to the first main pad, and one electrode of the resistor is soldered together with the first main pad. The second subpad is disposed adjacent to the second main pad, and the other electrode of the resistor is soldered together with the second main pad. The first sub lead line extends from a specific position of the first sub pad close to the reference point while the resistance value on the standard of the resistor appears. The second sub lead line extends from a specific position of the second sub pad near the reference point on the other hand, where the resistance value on the standard of the resistor appears.

このプリント配線板では、副パッドの特定位置から副引出線が延び出しているので、特定位置と副引出線との間の距離が短くなる。その結果、抵抗器に流れる電流を正確に検出できる。   In this printed wiring board, since the sub leader line extends from the specific position of the sub pad, the distance between the specific position and the sub leader line is shortened. As a result, the current flowing through the resistor can be accurately detected.

好ましくは、第1の主パッドは概略矩形をなす。第1の副パッドは第1の主パッドの互いに隣接する2辺を囲む概略L字形をなす。第2の主パッドは概略矩形をなす。第2の副パッドは第2の主パッドの互いに隣接する2辺を囲む概略L字形をなす。ここで、矩形は長方形だけでなく正方形も含む。   Preferably, the first main pad has a substantially rectangular shape. The first sub pad has a substantially L shape surrounding two adjacent sides of the first main pad. The second main pad is substantially rectangular. The second sub pad has a substantially L shape surrounding two adjacent sides of the second main pad. Here, the rectangle includes not only a rectangle but also a square.

この場合、はんだ付けを完了した抵抗器の両側に主パッド及び副パッドの端部が露出し、はんだ付けの良否を目視で判別できる。   In this case, the ends of the main pad and the sub pad are exposed on both sides of the resistor that has been soldered, and the quality of soldering can be visually determined.

好ましくは、第1の主パッドの面積は第1の副パッドの面積と同じである。第2の主パッドの面積は第2の副パッドの面積と同じである。ここでは、面積は厳密に同じである必要はなく、実質的に同じでよい。具体的には、面積に10%程度の差があってもよい。   Preferably, the area of the first main pad is the same as the area of the first sub pad. The area of the second main pad is the same as the area of the second sub pad. Here, the areas do not have to be exactly the same, but may be substantially the same. Specifically, there may be a difference of about 10% in the area.

この場合、両パッドにわたって盛り付けられたはんだに働く表面張力が同じになる。したがって、はんだが偏ることなく、両方にまたがって均等に盛り付けられる。その結果、抵抗器を確実にはんだ付けでき、接触不良が起こりにくい。   In this case, the surface tension acting on the solder placed over both pads is the same. Therefore, the solder is evenly spread over both without unevenness. As a result, the resistor can be reliably soldered and contact failure is unlikely to occur.

以下、図面を参照し、本発明の実施の形態を詳しく説明する。図中同一又は相当部分には同一符号を付してその説明は繰り返さない。   Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals and description thereof will not be repeated.

図1を参照して、DC/DCコンバータ用のIC13には一般に、抵抗器1及びパワートランジスタ14が外付けで接続される。抵抗器1は出力電流を検出するためのもので、抵抗値が低くかつその誤差が小さい精密抵抗が用いられる。   Referring to FIG. 1, generally, a resistor 1 and a power transistor 14 are externally connected to an IC 13 for a DC / DC converter. The resistor 1 is for detecting the output current, and a precision resistor having a low resistance value and a small error is used.

[第1の実施の形態]
表面実装型抵抗器1をプリント配線板にはんだ付けするためのパッドの構造を図2に示す。図2を参照して、本発明の実施の形態によるプリント配線板は、主パッド20及び21と、主引出線22及び23と、副パッド24及び25と、副引出線26及び27とを備える。
[First Embodiment]
A pad structure for soldering the surface-mounted resistor 1 to the printed wiring board is shown in FIG. Referring to FIG. 2, the printed wiring board according to the embodiment of the present invention includes main pads 20 and 21, main lead lines 22 and 23, sub pads 24 and 25, and sub lead lines 26 and 27. .

主パッド20は、表面実装型抵抗器1の一方電極7がはんだ付けされる。主パッド21は、抵抗器1の他方電極8がはんだ付けされる。主引出線22は、主パッド20から延び出す。主引出線23は、主パッド21から延び出す。副パッド24は、主パッド20に隣接して配置され、抵抗器1の一方電極7が主パッド20と一緒にはんだ付けされる。副パッド25は、主パッド21に隣接して配置され、抵抗器1の他方電極8が主パッド21と一緒にはんだ付けされる。副引出線26は、抵抗器1の規格上の抵抗値が現れる一方基準点Xに近い副パッド24の特定位置X1から延び出す。副引出線27は、抵抗器1の規格上の抵抗値が現れる他方基準点Yに近い副パッド25の特定位置Y1から延び出す。   The main pad 20 is soldered to one electrode 7 of the surface-mounted resistor 1. The other electrode 8 of the resistor 1 is soldered to the main pad 21. The main lead line 22 extends from the main pad 20. The main lead line 23 extends from the main pad 21. The sub pad 24 is disposed adjacent to the main pad 20, and one electrode 7 of the resistor 1 is soldered together with the main pad 20. The sub pad 25 is disposed adjacent to the main pad 21, and the other electrode 8 of the resistor 1 is soldered together with the main pad 21. The sub lead line 26 extends from a specific position X1 of the sub pad 24 close to the reference point X while the resistance value on the standard of the resistor 1 appears. The sub lead line 27 extends from a specific position Y1 of the sub pad 25 close to the reference point Y on the other side where the resistance value on the standard of the resistor 1 appears.

主パッド20は概略矩形をなす。副パッド24は主パッド20の互いに隣接する2辺を囲む概略L字形をなす。主パッド21は概略矩形をなす。副パッド25は主パッド21の互いに隣接する2辺を囲む概略L字形をなす。主パッド20の面積は副パッド24の面積とほぼ同じである。主パッド21の面積は副パッド25の面積とほぼ同じである。   The main pad 20 has a substantially rectangular shape. The sub pad 24 has a substantially L shape surrounding two sides of the main pad 20 adjacent to each other. The main pad 21 is substantially rectangular. The sub pad 25 has a substantially L shape surrounding the two adjacent sides of the main pad 21. The area of the main pad 20 is substantially the same as the area of the sub pad 24. The area of the main pad 21 is substantially the same as the area of the sub pad 25.

図3は、ケルビン接続の等価回路である。ROUTは抵抗器1の値、rF1は主パッド20側の内部抵抗、rF2は主パッド21側の内部抵抗、rS1は副パッド24側の内部抵抗、rS2は副パッド25側の内部抵抗である。抵抗器1の両電極7,8は内部抵抗rS1,rS2を介して電圧計に接続される。したがって、内部抵抗rS1,rS2が小さいほど抵抗器1に流れる電流を正確に検出できる。 FIG. 3 is an equivalent circuit of Kelvin connection. R OUT is the value of the resistor 1, r F1 is the internal resistance on the main pad 20 side, r F2 is the internal resistance on the main pad 21 side, r S1 is the internal resistance on the sub pad 24 side, and r S2 is the internal resistance on the sub pad 25 side. Internal resistance. Both electrodes 7 and 8 of the resistor 1 are connected to a voltmeter via internal resistances r S1 and r S2 . Therefore, the smaller the internal resistances r S1 and r S2 are, the more accurately the current flowing through the resistor 1 can be detected.

このプリント配線板では、特定位置X1,Y1直近の副パッド24,25内側から副引出線26,27が延び出しているので、特定位置X1,Y1から副引出線26,27の端までの距離L3(たとえば0.25mm)が従来よりも短くなる。その結果、内部抵抗rS1,rS2が小さくなるので、抵抗器1に流れる電流を正確に検出できる。 In this printed wiring board, since the sub lead lines 26 and 27 extend from the inside of the sub pads 24 and 25 closest to the specific positions X1 and Y1, the distance from the specific positions X1 and Y1 to the ends of the sub lead lines 26 and 27. L3 (for example, 0.25 mm) is shorter than before. As a result, since the internal resistances r S1 and r S2 are reduced, the current flowing through the resistor 1 can be accurately detected.

また、抵抗器1をリフローではんだ付けする際には、あらかじめクリームはんだを主パッド20,21及び副パッド24,25にまたがるように塊で盛り付けるが、主パッド20,21の面積は副パッド24,25の面積とほぼ同じであるから、はんだに働く表面張力もほぼ同じになる。したがって、はんだが主パッド20,21又は副パッド24,25のいずれかに偏ることはなく、両方にまたがって均等に盛り付けられる。その結果、抵抗器1を主パッド20,21及び副パッド24,25に確実にはんだ付けでき、接触不良が起こりにくい。   In addition, when soldering the resistor 1 by reflow, cream solder is preliminarily placed in a lump so as to straddle the main pads 20 and 21 and the sub pads 24 and 25. The area of the main pads 20 and 21 is the sub pad 24. , 25, the surface tension acting on the solder is almost the same. Therefore, the solder is not biased to any of the main pads 20 and 21 or the sub pads 24 and 25, and is evenly spread over both. As a result, the resistor 1 can be reliably soldered to the main pads 20 and 21 and the sub pads 24 and 25, and contact failure is unlikely to occur.

また、主パッド20,21は概略矩形をなし、副パッド24,25は概略L字形をなしているので、はんだ付けを完了した抵抗器1の両側に主パッド20,21及び副パッド24,25の端部が露出し、はんだ付けの良否を目視で判別できる。   Further, since the main pads 20 and 21 are substantially rectangular and the sub pads 24 and 25 are substantially L-shaped, the main pads 20 and 21 and the sub pads 24 and 25 are arranged on both sides of the resistor 1 which has been soldered. The end of the metal is exposed, and the quality of soldering can be visually determined.

リニアテクノロジー製LTC3728LXを用いたDC/DCコンバータでは、電流制限用に精密抵抗器が使用される。規格によると、制限電流Imaxは精密抵抗器の値をRsenseとすると次の式(1)により求められる。
Imax=50mV/Rsense (1)
In the DC / DC converter using the LTC3728LX made by Linear Technology, a precision resistor is used for current limiting. According to the standard, the limit current Imax can be obtained by the following equation (1) when the value of the precision resistor is Rsense.
Imax = 50 mV / Rsense (1)

Imax=5.000Aとするためには、Rsense=0.01Ωとする必要がある。これは、パッドの抵抗を無視した場合の設計理想値である。   In order to set Imax = 5.000 A, it is necessary to set Rsense = 0.01Ω. This is a design ideal value when the resistance of the pad is ignored.

図1に示したパッドを用いた場合と、図8に示したパッドを用いた場合とについて、制限電流を求めると、次の表1のとおりである。

Figure 2008198687
When the limiting current is obtained for the case where the pad shown in FIG. 1 is used and the case where the pad shown in FIG. 8 is used, the following table 1 is obtained.
Figure 2008198687

幅1mm、厚さ35μmの銅箔の長さ1cm(=10mm)当たりの抵抗値は一般に0.0048Ωであるから、従来のパッドの抵抗は0.00096Ω(=2.0mm×0.0048Ω/10)となるのに対し、本発明のパッドの抵抗は0.00012Ω(=0.25mm×0.0048Ω/10)となる。制限電流は、従来の場合は4.562Aであるが、本発明の場合は4.941Aである。したがって、設計理想値に対する検出誤差は、従来の場合は7.5%であるが、本発明の場合は1.2%である。このように、本発明の制限電流は設計理想値に近く、従来よりも正確に電流を検出できる。   Since the resistance value per 1 cm (= 10 mm) of a copper foil having a width of 1 mm and a thickness of 35 μm is generally 0.0048Ω, the resistance of the conventional pad is 0.00096Ω (= 2.0 mm × 0.0048Ω / 10 ), The resistance of the pad of the present invention is 0.00012Ω (= 0.25 mm × 0.0048Ω / 10). The limiting current is 4.562 A in the conventional case, but is 4.941 A in the present invention. Therefore, the detection error with respect to the design ideal value is 7.5% in the conventional case, but 1.2% in the present invention. Thus, the limiting current of the present invention is close to the design ideal value, and the current can be detected more accurately than in the past.

[第2の実施の形態]
上記第1の実施の形態では、主パッドの面積と副パッドの面積とをほぼ同じにしているが、たとえば図4に示すように、主パッド30,31を概略コの字形にし、副パッド32,33を矩形にし、主パッド30,31の内側に配置してもよい。ただし、この場合、主パッド30,31及び副パッド32,33にわたって盛り付けたはんだが表面張力の違いで主パッド30,31側に偏る可能性がある。また、抵抗器1の実装後は副パッド32,33が隠れてしまうので、はんだ付けの良否を目視で判別できない。
[Second Embodiment]
In the first embodiment, the area of the main pad and the area of the sub pad are substantially the same. For example, as shown in FIG. , 33 may be rectangular and arranged inside the main pads 30, 31. However, in this case, there is a possibility that the solder placed over the main pads 30 and 31 and the sub pads 32 and 33 is biased toward the main pads 30 and 31 due to a difference in surface tension. Further, since the sub pads 32 and 33 are hidden after the resistor 1 is mounted, it is impossible to visually determine whether the soldering is good or bad.

[第3の実施の形態]
また、たとえば図5に示すように、主パッド34,35及び副パッド36,37を全て同じ面積の長方形にし、互いに隣接して配置してもよい。ただし、この場合は、抵抗器1の実装後は副パッド36,37がほとんど隠れてしまうので、はんだ付けの良否を目視で判別しにくい。
[Third Embodiment]
Further, as shown in FIG. 5, for example, the main pads 34 and 35 and the sub pads 36 and 37 may all be rectangular with the same area and arranged adjacent to each other. However, in this case, since the sub pads 36 and 37 are almost hidden after the resistor 1 is mounted, it is difficult to visually determine whether the soldering is good or bad.

[第4の実施の形態]
上記第1〜第3の実施の形態は図9に示した表面実装型抵抗器1に適したパターンであるが、この第4の実施の形態は図6に示した表面実装型抵抗器40に適したパターンである。表面実装型抵抗器40では、規格上の抵抗値が現れる基準点X及びYが両端面の中心にある。両端面から延び出す一方電極41及び他方電極42は抵抗器本体43に沿って折り曲げられ、抵抗器本体43に貼り付けられている。抵抗器本体43は樹脂で形成され、その中に抵抗体が封入されている。
[Fourth Embodiment]
The first to third embodiments have patterns suitable for the surface-mounted resistor 1 shown in FIG. 9, but the fourth embodiment is different from the surface-mounted resistor 40 shown in FIG. It is a suitable pattern. In the surface-mounted resistor 40, the reference points X and Y at which standard resistance values appear are at the centers of both end faces. The one electrode 41 and the other electrode 42 extending from both end faces are bent along the resistor body 43 and attached to the resistor body 43. The resistor main body 43 is made of resin, and a resistor is enclosed therein.

表面実装型抵抗器40を実装するためには、図7に示すように、概略矩形の主パッド44,45を内側に配置し、概略L字型の副パッド46,47を外側に配置する。主引出線48,49は主パッド44,45の内側から延び出す。副引出線50,51は副パッド46,47の外側にある特定位置X1,Y1から延び出す。   In order to mount the surface-mounted resistor 40, as shown in FIG. 7, the substantially rectangular main pads 44 and 45 are disposed on the inner side, and the substantially L-shaped sub pads 46 and 47 are disposed on the outer side. The main lead lines 48 and 49 extend from the inside of the main pads 44 and 45. The sub lead lines 50 and 51 extend from specific positions X 1 and Y 1 outside the sub pads 46 and 47.

以上、本発明の実施の形態を説明したが、上述した実施の形態は本発明を実施するための例示に過ぎない。よって、本発明は上述した実施の形態に限定されることなく、その趣旨を逸脱しない範囲内で上述した実施の形態を適宜変形して実施することが可能である。   While the embodiments of the present invention have been described above, the above-described embodiments are merely examples for carrying out the present invention. Therefore, the present invention is not limited to the above-described embodiment, and can be implemented by appropriately modifying the above-described embodiment without departing from the spirit thereof.

一般的なDC/DCコンバータの回路図である。It is a circuit diagram of a general DC / DC converter. 本発明の第1の実施の形態によるプリント配線板のケルビン接続パターンを示す平面図である。It is a top view which shows the Kelvin connection pattern of the printed wiring board by the 1st Embodiment of this invention. ケルビン接続の等価回路である。It is an equivalent circuit of Kelvin connection. 本発明の第2の実施の形態によるプリント配線板のケルビン接続パターンを示す平面図である。It is a top view which shows the Kelvin connection pattern of the printed wiring board by the 2nd Embodiment of this invention. 本発明の第3の実施の形態によるプリント配線板のケルビン接続パターンを示す平面図である。It is a top view which shows the Kelvin connection pattern of the printed wiring board by the 3rd Embodiment of this invention. 本発明の第4の実施の形態によるプリント配線板のケルビン接続パターンを示す平面図である。It is a top view which shows the Kelvin connection pattern of the printed wiring board by the 4th Embodiment of this invention. 表面実装型抵抗器の外観構成を示す斜視図である。It is a perspective view which shows the external appearance structure of a surface mount type resistor. 図7と異なるタイプの表面実装型抵抗器の外観構成を示す斜視図である。It is a perspective view which shows the external appearance structure of the surface mount type resistor different from FIG. 電流検出用抵抗器を実装するための従来の配線パターンを示す平面図である。It is a top view which shows the conventional wiring pattern for mounting the resistor for electric current detection.

符号の説明Explanation of symbols

1,40 表面実装型抵抗器
20,21,30,31,34,35,44,45 主パッド
24,25,32,33,36,37,46,47 副パッド
7,41 一方電極
8,42 他方電極
22,23,48,49 主引出線
26,27,50,51 副引出線
X,Y 基準点
X1,Y1 特定位置
1,40 Surface mount type resistors 20, 21, 30, 31, 34, 35, 44, 45 Main pads 24, 25, 32, 33, 36, 37, 46, 47 Sub pads 7, 41 One electrode 8, 42 Other electrodes 22, 23, 48, 49 Main leader lines 26, 27, 50, 51 Sub leader lines X, Y Reference points X1, Y1 Specific position

Claims (3)

表面実装型抵抗器の一方電極がはんだ付けされる第1の主パッドと、
前記抵抗器の他方電極がはんだ付けされる第2の主パッドと、
前記第1の主パッドから延び出す第1の主引出線と、
前記第2の主パッドから延び出す第2の主引出線と
前記第1の主パッドに隣接して配置され、前記抵抗器の一方電極が前記第1の主パッドと一緒にはんだ付けされる第1の副パッドと、
前記第2の主パッドに隣接して配置され、前記抵抗器の他方電極が前記第2の主パッドと一緒にはんだ付けされる第2の副パッドと、
前記抵抗器の規格上の抵抗値が現れる一方基準点に近い前記第1の副パッドの特定位置から延び出す第1の副引出線と、
前記抵抗器の規格上の抵抗値が現れる他方基準点に近い前記第2の副パッドの特定位置から延び出す第2の副引出線とを備えたことを特徴とするプリント配線板。
A first main pad to which one electrode of the surface mount resistor is soldered;
A second main pad to which the other electrode of the resistor is soldered;
A first main lead line extending from the first main pad;
A second main lead line extending from the second main pad; and a second main lead line disposed adjacent to the first main pad, wherein one electrode of the resistor is soldered together with the first main pad. 1 subpad,
A second subpad disposed adjacent to the second main pad, wherein the other electrode of the resistor is soldered together with the second main pad;
A first sublead line extending from a specific position of the first subpad close to a reference point while a resistance value on the standard of the resistor appears;
A printed wiring board, comprising: a second sub lead line extending from a specific position of the second sub pad near the reference point on the other side where a resistance value on the standard of the resistor appears.
請求項1に記載のプリント配線板であって、
前記第1の主パッドは概略矩形をなし、前記第1の副パッドは前記第1の主パッドの互いに隣接する2辺を囲む概略L字形をなし、前記第2の主パッドは概略矩形をなし、前記第2の副パッドは前記第2の主パッドの互いに隣接する2辺を囲む概略L字形をなす、ことを特徴とするプリント配線板。
The printed wiring board according to claim 1,
The first main pad has a generally rectangular shape, the first sub pad has a generally L-shape that surrounds two adjacent sides of the first main pad, and the second main pad has a generally rectangular shape. The printed wiring board is characterized in that the second sub pad has a substantially L shape surrounding two adjacent sides of the second main pad.
請求項1又は2に記載のプリント配線板であって、
前記第1の主パッドの面積は前記第1の副パッドの面積と同じであり、前記第2の主パッドの面積は前記第2の副パッドの面積と同じである、ことを特徴とするプリント配線板。
The printed wiring board according to claim 1 or 2,
The area of the first main pad is the same as the area of the first sub pad, and the area of the second main pad is the same as the area of the second sub pad. Wiring board.
JP2007030034A 2007-02-09 2007-02-09 Printed wiring board Expired - Fee Related JP4403428B2 (en)

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CN101815400B (en) * 2009-02-20 2012-06-20 沈阳铁路信号有限责任公司 Divided type pad with surface mount elements
JP2013187354A (en) * 2012-03-08 2013-09-19 Koa Corp Mounting structure of resistor for current detection
JP2017216468A (en) * 2014-11-20 2017-12-07 日本精工株式会社 Heat dissipation substrate for mounting electronic component
CN107578867A (en) * 2017-09-01 2018-01-12 郑州云海信息技术有限公司 An integrated packaging structure of precision resistors
JP2018014502A (en) * 2014-11-20 2018-01-25 日本精工株式会社 Heat dissipation board for mounting electronic components
US10388596B2 (en) 2014-11-20 2019-08-20 Nsk Ltd. Electronic part mounting heat-dissipating substrate
CN110557887A (en) * 2018-05-31 2019-12-10 京东方科技集团股份有限公司 Circuit alignment assembly and display device
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101815400B (en) * 2009-02-20 2012-06-20 沈阳铁路信号有限责任公司 Divided type pad with surface mount elements
JP2013187354A (en) * 2012-03-08 2013-09-19 Koa Corp Mounting structure of resistor for current detection
JP2017216468A (en) * 2014-11-20 2017-12-07 日本精工株式会社 Heat dissipation substrate for mounting electronic component
JP2018014502A (en) * 2014-11-20 2018-01-25 日本精工株式会社 Heat dissipation board for mounting electronic components
US10192818B2 (en) 2014-11-20 2019-01-29 Nsk Ltd. Electronic part mounting heat-dissipating substrate
US10249558B2 (en) 2014-11-20 2019-04-02 Nsk Ltd. Electronic part mounting heat-dissipating substrate
US10388596B2 (en) 2014-11-20 2019-08-20 Nsk Ltd. Electronic part mounting heat-dissipating substrate
CN107578867A (en) * 2017-09-01 2018-01-12 郑州云海信息技术有限公司 An integrated packaging structure of precision resistors
CN110557887A (en) * 2018-05-31 2019-12-10 京东方科技集团股份有限公司 Circuit alignment assembly and display device
US11013116B2 (en) 2018-05-31 2021-05-18 Boe Technology Group Co., Ltd. Flexible assembly for display device and display device
CN110557887B (en) * 2018-05-31 2021-10-12 京东方科技集团股份有限公司 Circuit alignment assembly and display device
CN111337726A (en) * 2020-04-10 2020-06-26 深圳市欣旺达电气技术有限公司 Circuit structure based on patch shunt and current detection method

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