JP2008177233A - Compound semiconductor wafer and manufacturing method thereof - Google Patents

Abstract

The present invention provides a compound semiconductor wafer having an orientation flat or an index flat formed at the position of a cleavage plane and having better product reliability as compared with the conventional one and a method for manufacturing the same.
A compound semiconductor wafer according to the present invention has an orientation flat for identifying the orientation of a wafer at a position 48 of a cleavage plane unique to a crystal constituting a wafer 41 obtained by cutting a single crystal of a compound semiconductor. 15 or an index flat 16 for identifying the front and back sides, and a chamfered portion 31 is formed at an edge of the orientation flat 15 or the index flat 16 on the back surface 43 side, and the orientation flat 15 or the front surface 42 of the index flat 16 is formed. The side edge 32 is formed so that the cleavage plane and the front surface 42 are at right angles.
[Selection] Figure 3

Description

  The present invention relates to a compound semiconductor wafer and a manufacturing method thereof, and more particularly to a compound semiconductor wafer having an orientation flat or an index flat and a manufacturing method thereof.

  A GaAs wafer, which is one of compound semiconductor wafers, is widely used as a substrate for light receiving / light emitting elements, high frequency elements and the like. This GaAs wafer is formed by implanting ions directly into the wafer using an ion implantation apparatus or forming an epitaxial layer on the wafer surface. In general, the size of a GaAs wafer used as a substrate of a light emitting element such as a semiconductor laser or an LED is often φ2 inch, φ3 inch, or φ4 inch.

  A wafer constituting such a GaAs wafer is obtained by grinding a GaAs single crystal into a cylindrical shape with a predetermined diameter and then slicing it to a predetermined thickness. Thereafter, as shown in FIGS. 4A and 4B, the outer peripheral surface 44 of the wafer 41 is formed in an R shape, and the peripheral portions 45 and 45 of the front surface 42 and the back surface 43 are chamfered. Thereafter, the wafer thickness is adjusted by lapping and polished to a mirror surface with a polisher to obtain a GaAs wafer.

  In a series of manufacturing steps, the step of forming the outer peripheral surface 44 and the peripheral portions 45, 45 of the wafer 41 into an R shape or chamfering is performed by a chamfering machine. In the chamfering step, a chamfering process is performed on the outer peripheral surface 44 and the peripheral portions 45 and 45 of the sliced wafer 41 with a grindstone rotating around an axis, and a linear shape for identifying the wafer direction is provided on the outer peripheral portion of the wafer. A processing portion (orientation flat (hereinafter referred to as OF)) or a linear processing portion (index flat (hereinafter referred to as IF)) for identifying the front and back of the wafer is formed.

  For example, when forming a GaAs wafer having a diameter of 100 mm, as shown in FIGS. 5 and 6, while the wafer 41 vacuum-sucked on the stage 53 is slowly rotated at, for example, 1 to 3 rpm, its outer peripheral surface 44 and peripheral portion 45 and 45 are sequentially brought into contact with the groove bottom 62, the upper surface portion 63, and the lower surface portion 64 of the groove 61 of the grindstone 51 rotating at high speed. As a result, a wafer is obtained in which the outer peripheral surface 44 is formed in an R shape and the peripheral portions 45 and 45 of the front surface 42 and the back surface 43 are chamfered. At this time, the diameter of the wafer is adjusted to 100 mm by adjusting the distance between the axis of the stage 53 on which the wafer 41 is placed and the axis of the grindstone 51 by NC control.

  Further, when the OF or IF is formed on the wafer, the distance between the axis of the stage 53 and the axis of the grindstone 51 is made shorter than when the outer peripheral surface 44 and the peripheral portions 45 and 45 of the wafer 41 are processed. If the numerical values of these OF and IF lengths are input in advance, the distance between the axes is adjusted accordingly.

  In most cases, OF and IF are chamfered in the same manner as other portions of the wafer. By chamfering the outer peripheral surface, peripheral edge, OF, and IF of the wafer in this way, it is possible to prevent cracking and partial breakage during wafer transport in the processing steps after chamfering and in the process of manufacturing elements. Can do.

  By the way, since the single crystal is grown so as to have a certain crystal direction, the surface of the wafer obtained by slicing and polishing the single crystal also has a certain direction. In most cases, the wafer surface of a semiconductor wafer such as a GaAs wafer is slightly inclined from the <100> direction ([100] direction and equivalent directions) or these two directions. For example, taking a wafer with a plane orientation (100) as an example, the formation position of the OF is one of the <011> direction (the [011] direction and the equivalent direction), and the IF formation position is In many cases, the direction forms an angle of 90 ° or 270 °.

  When manufacturing a semiconductor laser substrate or the like using a GaAs wafer having a plane orientation (100), after forming an epitaxial layer or the like on the GaAs wafer, a chip is cut out parallel or perpendicular to the OF or IF as a reference. Is going. Here, when these OFs and IFs are chamfered with a chamfering machine, grinding is performed with a grindstone, so that the mechanical accuracy such as the eccentricity of the motor shaft that rotates the grindstone causes mechanical accuracy such as a few seconds to several directions in the <011> direction. There may be a “displacement”. When such a shifted OF or IF is used as a reference, the chip may not be cut out accurately.

  Therefore, in order to avoid this deviation, there is a method of forming OF or IF at the position of the cleavage plane unique to the crystal constituting the wafer 41 shown in FIG. According to this method, theoretically, there is no possibility of deviation from the <011> direction, and the chip can be accurately cut out.

JP 2005-19579 A JP-A-2005-101120 JP-A-5-259016 JP 2005-243976 A Japanese Patent No. 2882355 JP 2003-86476 A

  However, as shown in FIGS. 7A, 7B, and 8, in the case of the wafer 71 in which the OF 75 (or IF 76) is formed at the position of the cleavage surface, the front surface 42 of the wafer 71 and the cleavage surface ( OF75) and the angle formed between the back surface 43 of the wafer 71 and the cleavage plane are 90 ° (right angle). In this case, in the lapping step and the polishing step after the chamfering step, the right-angle portions 77 and 77 of the OF 75 or IF 76 are in direct contact with the surface plate of the lapping machine and the polishing cloth of the polishing machine. For this reason, in each process, there is a possibility that a part of these right-angle portions 77 and 77 may be lost due to friction or the like, and the wafer 71 may be damaged starting from these right-angle portions 77 and 77. There is a problem that the processing yield is low as compared with a wafer that is chamfered.

  Further, the wafer having this cleavage plane is polished, epitaxially grown on the wafer, and the epitaxial layer is subjected to mask patterning with a photoresist, and then back-wrap processing is performed. There is also a problem of cracking. As a result, the manufacturing cost of the compound semiconductor wafer has been increased.

  In order to solve these problems, in the invention described in Patent Document 6, the peripheral surface, the front surface and the back surface of the wafer having OF or IF formed at the position of the cleavage surface are ground by a chamfering machine and cleaved. A wafer having a reduced probability of breakage from the part has been proposed.

  This wafer is very effective for a system in which pins are pressed against the cleavage plane to align the cleavage plane with the mask pattern. However, when using an optical mask pattern alignment method in which the cleavage portion is observed with a microscope, there is a problem that mask patterning cannot be performed because the chamfered portion of the front surface of the wafer cannot be focused.

  In view of the above circumstances, an object of the present invention is to provide a compound semiconductor wafer having a product reliability better than that of a conventional wafer in which an orientation flat or an index flat is formed at the position of the cleavage plane. .

  Another object of the present invention is to provide a method for producing a compound semiconductor wafer in which an orientation flat or an index flat is formed at the position of the cleavage plane and has a good processing yield in the steps after chamfering. is there.

  To achieve the above object, the invention of claim 1 is directed to an orientation for identifying the orientation of a wafer at a position of a cleavage plane unique to a crystal constituting a wafer obtained by cutting a single crystal of a compound semiconductor. In a compound semiconductor wafer formed with an index flat for identifying a flat or front and back, a chamfered portion is formed at the edge of the orientation flat or index flat on the back side, and the orientation flat or index flat on the front side The compound semiconductor wafer is characterized in that the edge portion is formed so that the cleavage plane and the front surface are perpendicular to each other.

  A second aspect of the present invention is the compound semiconductor wafer according to the first aspect, wherein a chamfered portion is formed at an edge of the outer peripheral surface of the wafer except for the orientation flat or the index flat.

  The invention according to claim 3 is the compound semiconductor wafer according to claim 1 or 2, wherein the chamfer width of the chamfered portion of the orientation flat or index flat is smaller than the chamfer width of the chamfered portion formed at the edge of the outer peripheral surface of the wafer. It is.

  According to a fourth aspect of the present invention, any one of the first to third aspects, wherein a chamfering width of the chamfered portion on the front side of the orientation flat or index flat is smaller than a chamfered width of the chamfered portion on the back side of the orientation flat or index flat. A compound semiconductor wafer according to claim 1.

  According to a fifth aspect of the present invention, an orientation flat for identifying the orientation of a wafer or an index for identifying the front and back is located at the position of a cleavage plane unique to a crystal constituting a wafer obtained by cutting a single crystal of a compound semiconductor. In the compound semiconductor wafer manufacturing method in which a flat is formed, a chamfering process is performed on the edge of the outer peripheral surface of the wafer to form a chamfered part, and then a lapping process and a polishing process are performed on the front surface of the wafer to obtain an orientation flat. Alternatively, the chamfered portion on the front side of the index flat is removed between the lapping process and the polishing process.

The present invention exhibits the following excellent effects.
(1) The processing yield in the manufacturing process of the compound semiconductor wafer after the chamfering process is improved, and as a result, the product reliability of the compound semiconductor wafer is improved.
(2) In the compound semiconductor wafer manufacturing process after the chamfering process, the rate of occurrence of defects and breakage is reduced, and as a result, the processing yield of the compound semiconductor wafer is improved.
(3) In the semiconductor laser manufacturing process from the epitaxial growth process to the backlapping process after mask patterning, the rate of occurrence of defects and breakage decreases, and as a result, the processing yield of the compound semiconductor wafer is improved.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of the invention will be described with reference to the accompanying drawings.

  In the compound semiconductor wafer according to the present embodiment, a crystal-specific cleavage plane 48 constituting a wafer 41 (see FIG. 4) obtained by cutting and slicing a single crystal of a compound semiconductor is positioned at FIG. As shown, an OF (orientation flat) 15 is formed, and an IF (index flat) 16 is formed in a direction that forms an angle of 90 ° or 270 ° with the formation position of the OF 15. As shown in FIG. 3B, a chamfer 31 is formed on the edge of the OF 15 (or IF 16) on the back surface 43 side, and the edge 32 on the front surface 42 side of the OF 15 has a cleaved surface and a front surface 42. It is formed to be a right angle. Further, as shown in FIG. 1 (d), chamfered portions 21 and 21 are formed on the edge of the wafer outer peripheral surface 24 except for the OF 15 and IF 16 of the wafer 11.

  More specifically, in the portion of OF15 (or IF16), as shown in FIG. 3B, the outer peripheral surface 34 and the front surface 42 of the wafer 11 and the outer peripheral surface 34 and the back surface 43 are perpendicular to each other. The width of the chamfer 31 on the back surface 43 side is L2, the width of the chamfer 31 on the front surface 42 side is L4, and the chamfer angle is θ. Further, except for OF 15 and IF 16, the outer peripheral surface (chamfered portion) 24 of the wafer 11 is formed in an R shape, the width of the chamfered portion 21 on the back surface 43 side is L 1, and the chamfered portion 21 on the front surface 42 side. The width is L3 and the chamfer angle is θ. Here, the chamfering width L2 (or L4) of the chamfered portion 31 of the OF 15 is made smaller than the chamfered width L1 (or L3) of the chamfered portion 21 formed at the edge of the wafer outer peripheral surface 24. The chamfering width L4 of the chamfered portion 31 on the front surface 42 side of the OF15 is made smaller than the chamfered width L2 of the chamfered portion 31 on the back surface 43 side of the OF15.

  Examples of the compound semiconductor constituting the wafer 11 include GaAs, InP, InSb, InAs, or GaP.

  The thickness of the wafer 11 is not particularly limited as long as it has a thickness equivalent to that of a conventional compound semiconductor wafer.

  Next, a method for manufacturing a compound semiconductor wafer according to the present embodiment will be described.

  In the method of manufacturing a compound semiconductor wafer according to the present embodiment, first, a crystal-specific cleavage plane 48 constituting a wafer 41 (see FIG. 4) obtained by cutting a single crystal of a compound semiconductor is positioned at FIG. As shown in FIG. 1A and FIG. 1B, the OF 15 is formed. Further, the IF 16 is formed in a direction that forms an angle of 90 ° or 270 ° with the formation position of the OF 15.

  Thereafter, using a chamfering machine, chamfering is performed on each edge of the outer peripheral surface of the wafer 11 on which the OF 15 and IF 16 are formed.

  As shown in FIGS. 5 and 6, the grinding portion of the chamfering machine is basically composed of a grindstone 51, a spindle 52 that rotates the grindstone 51 at a high speed of 5000 to 6000 rpm, and a stage 53 that vacuum-sucks the wafer 11. Composed. Further, the chamfering machine has a grindstone moving mechanism (not shown) for moving the grindstone 51 in the axial direction (vertical direction (vertical direction in FIG. 6)) and a stage 53 in the radial direction (horizontal direction (in FIG. 5). A stage moving mechanism (not shown) for moving in the directions of arrows A and B)). In most cases, these moving mechanisms are controlled by NC control. Further, as shown in FIG. 6, the grindstone has grooves (two in FIG. 6) 61 having an arcuate section (substantially U-shaped section) formed on the outer peripheral portion 51a. Here, as the number of grooves 61 increases, the number of wafers 11 that can be chamfered simultaneously increases.

  By inserting the wafer 11 into the groove 61 of the grindstone 51, the outer peripheral surface 24 of the wafer 11 and each edge of the outer peripheral surface 24 on the front surface 42 side and the back surface 43 side are chamfered, and the shape of the chamfered portion Is determined.

  Specifically, first, chamfering of the portion of the wafer 11 excluding the OF 15 and the IF 16 is performed.

  Using the grindstone moving mechanism, the height (position) of the groove 61 of the grindstone 51 is adjusted to be the same as the height (position) of the wafer 11 on the stage 53, and then slowly rotated using the stage moving mechanism. The wafer 11 is inserted into the groove 61 of the grindstone 51 that rotates at high speed. As a result, the outer peripheral surface 44 of the wafer 11 is brought into contact with the groove bottom 62 of the groove 61, and the outer peripheral surface 44 of the wafer 11 is chamfered to form an R-shaped outer peripheral surface 24 as shown in FIG. Next, using the grindstone moving mechanism, the grindstone 51 is moved downward in the axial direction, the upper surface portion 63 of the groove 61 is brought into contact with the peripheral edge 45 on the front surface 42 side of the wafer 11, and the chamfered portion 21 is chamfered. Is formed. Next, using the grindstone moving mechanism, the grindstone 51 is moved upward in the axial direction, the lower surface portion 64 of the groove 61 is brought into contact with the peripheral edge 45 on the back surface 43 side of the wafer 11, and the chamfered portion 21 is chamfered. It is formed. Here, the chamfering width L3 of the chamfered portion 21 on the front surface 42 side is made smaller than the chamfered width L1 of the chamfered portion 21 on the back surface 43 side (L3 <L1).

  When the chamfered portion 21 is formed, by adjusting the distance between the shaft of the grindstone 51 and the shaft of the stage 53 and the shape of the groove 61, the position where the groove 61 and the peripheral edge portions 45, 45 of the wafer 11 come into contact with each other is adjusted. Accordingly, the chamfering widths L1 and L3 and the chamfering angle θ of the chamfered portion 21 change accordingly. For example, it is desirable that the chamfer angle θ is 22 °, the chamfer width L1 is 300 μm or less, and the chamfer width L3 is 200 μm or less.

  Next, the edges of the OF 15 and IF 16 in the wafer 11 are chamfered.

  After adjusting the height (position) of the groove 61 of the grindstone 51 to be the same as the height (position) of the wafer 11 on the stage 53 using the grindstone moving mechanism, the stage 11 moves the wafer 11 using the stage moving mechanism. The portion of the OF 15 (or IF 16) is inserted into the groove 61 of the grindstone 51 that rotates at high speed. At this time, the wafer 11 is not rotated. Next, using the grindstone moving mechanism, the grindstone 51 is moved downward in the axial direction, and the upper surface portion 63 of the groove 61 is brought into contact with the edge portion on the front surface 42 side of the OF 15 to chamfer, and FIG. As shown, a chamfered portion 31 is formed. Next, using the grindstone moving mechanism, the grindstone 51 is moved upward in the axial direction, the lower surface portion 64 of the groove 61 is brought into contact with the edge of the OF 15 on the side of the back surface 43, and the chamfered portion 31 is formed. The Here, the chamfering width L4 of the chamfered portion 31 on the front surface side is made smaller than the chamfered width L2 of the chamfered portion 31 on the back surface side (L4 <L2).

  When the chamfered portions 31 and 31 are formed, the stage 53 is moved in the tangential direction of the grindstone 51 by using a stage moving mechanism, so that the OF 15 and the upper surface portion 63 of the groove 61 and the OF 15 and the lower surface portion 64 of the groove 61 abut. The position changes and the entire chamfer of the OF 15 can be performed. Further, by adjusting the distance between the axis of the grindstone 51 and the axis of the stage 53 and the shape of the groove 61, the position where the edges of the groove 61 and the OF 15 come into contact changes, and the chamfered portion 31 accordingly. The widths L2 and L4 and the chamfering angle θ change. For example, the chamfer width L4 is desirably 50 μm or less, and the chamfer width L2 is desirably 150 μm or less.

  After such chamfering, lapping is performed so that the wafer 11 has a uniform thickness and a uniform flatness. The wafer 11 after lapping is subjected to etching with acid or alkali to remove distortion and clean, and then mirror finished by mechanochemical polishing. During the lapping process and the polishing process, the front surface 42 of the wafer 11 is cut, and the chamfered portion 31 on the front surface 42 side of the OF 15 is removed. As a result, the wafer cross-sectional shape after mechanochemical polishing is shown in FIG. 3B, and the edge 32 on the front surface 42 side of the wafer 11 after mechanochemical polishing has a cleavage plane and a front surface 42 perpendicular to each other. Become.

  As described above, according to the method for manufacturing a compound semiconductor wafer according to the present embodiment, the OF 15 or IF 16 is formed at the position 48 of the cleaved surface unique to the crystal constituting the wafer 11, and the outer peripheral surface 44 and the front surface 42 of the wafer 11 are formed. In addition, by chamfering the peripheral portions 45, 45 of the back surface 43, the chamfered portion 31 of the OF 15 (or the chamfered portion of the IF 16) is used in the lapping and polishing steps after the chamfering step. There is no direct contact with the polishing cloth of the machine. For this reason, in each process, there is no possibility that some of these chamfered portions are lost due to friction or the like, and the wafer 11 is damaged from these chamfered portions as a starting point.

  Further, since the chamfered portion 31 is removed between the lapping step and the polishing step on the side of the front surface 42 of the OF 15 or IF 16 after the polishing process, and the edge portion 32 has a right angle, mask alignment by an optical method is possible. Become.

  Further, since the chamfered portion 31 remains on the side of the back surface 43 of the wafer 11, chipping and cracking of the cleaved portion of the wafer 11 due to contact with the surface plate and the wrapping material are caused during back wrapping after epitaxial growth to mask patterning. It becomes possible to prevent.

  Thereby, the product reliability of the wafer 11 is improved, and the processing yield of the compound semiconductor wafer is remarkably improved. As a result, the manufacturing cost of the compound semiconductor wafer can be reduced.

  As mentioned above, it cannot be overemphasized that embodiment of this invention is not limited to embodiment mentioned above, and various things are assumed in addition.

(Example)
1000 GaAs wafers having a diameter of 78 mm, a thickness of 600 μm, and a plane orientation (100) were prepared, and an OF was formed at the position of the cleavage plane (see FIG. 4) of each wafer.

Next, each wafer was chamfered using a chamfering machine to produce the compound semiconductor wafer shown in FIG. Here, the outer peripheral portion of IF was chamfered so as to have the same shape as the outer peripheral portion excluding OF and IF.
(Conventional example)
1000 GaAs wafers having a diameter of 78 mm, a thickness of 600 μm, and a plane orientation (100) were prepared, and an OF was formed at the position of the cleavage plane (see FIG. 4) of each wafer.

  Next, each wafer was chamfered using a chamfering machine to produce the compound semiconductor wafer shown in FIG. Here, the outer peripheral portion of IF was chamfered so as to have the same shape as the outer peripheral portion excluding OF and IF.

  1000 wafers of each of the example and the conventional example were sequentially fed to the lapping process and the polishing process, and a wafer having a thickness of 480 μm and both surfaces mirror-finished was obtained.

  In each wafer of the conventional example, the number of wafers in which defects or breakage occurred in the OF portion of the wafer in the processes after the chamfering process was 20. On the other hand, in each wafer of the example, the number of wafers in which the defect / breakage occurred in the OF portion of the wafer was only two.

  In other words, in the examples, the rate of occurrence of defects / breakage was reduced to 1/10 compared to the conventional example, and from this, it was confirmed that the processing yield of the compound semiconductor wafer was remarkably improved.

It is a figure which shows the shape after a chamfering process and a mirror surface process of the compound semiconductor wafer which concerns on this Embodiment. 1A is a plan view after chamfering, FIG. 1B is a front view of FIG. 1A, FIG. 1C is a plan view after mirror finishing, and FIG. 1D is FIG. It is a front view of c). It is a 2 direction arrow enlarged view of Fig.1 (a). It is sectional drawing after a chamfering process and a mirror surface process of the compound semiconductor wafer which concerns on this Embodiment. 3A is a cross-sectional view taken along line 3A-3A in FIG. 1B, and FIG. 3B is a cross-sectional view taken along line 3B-3B in FIG. It is a figure which shows the shape of the wafer immediately after slicing. 4A is a plan view, and FIG. 4B is a front view of FIG. 4A. It is a perspective view of the grinding part in a chamfering machine. It is a longitudinal cross-sectional view of the grindstone in FIG. It is a figure which shows the shape of the wafer which gave the conventional chamfering process. FIG. 7A is a plan view, and FIG. 7B is a front view of FIG. FIG. 8B is a cross-sectional view taken along line 8-8 in FIG.

Explanation of symbols

11 Wafer 15 OF (Orientation Flat)
16 IF (index flat)
21 Chamfered portion 24 Wafer outer peripheral surface (chamfered portion)
DESCRIPTION OF SYMBOLS 31 Chamfering part 41 Wafer 42 Front side of wafer 43 Wafer back surface 44 Wafer outer peripheral surface 45 Wafer peripheral edge 48 Cleaved surface position 51 Grinding wheel (chamfering machine)
52 Spindle (Chamfering machine)
53 stage (chamfering machine)

Claims (5)

  Compound formed by forming an orientation flat for identifying the orientation of the wafer or an index flat for identifying the front and back at the position of the cleavage plane unique to the crystal constituting the wafer obtained by cutting a single crystal of a compound semiconductor In a semiconductor wafer, a chamfered portion is formed at the edge of the orientation flat or index flat on the back surface side, and the edge of the orientation flat or index flat on the front surface side is perpendicular to the cleaved surface and the front surface. A compound semiconductor wafer characterized in that it is formed.   The compound semiconductor wafer according to claim 1, wherein a chamfered portion is formed at an edge of the outer peripheral surface of the wafer except for the orientation flat or the index flat.   The compound semiconductor wafer according to claim 1 or 2, wherein a chamfering width of the chamfered portion of the orientation flat or index flat is smaller than a chamfered width of a chamfered portion formed at an edge of the outer peripheral surface of the wafer.   The compound semiconductor wafer according to any one of claims 1 to 3, wherein a chamfering width of a chamfered portion on the front surface side of the orientation flat or index flat is smaller than a chamfered width of a chamfered portion on the back side of the orientation flat or index flat. .   Compound formed by forming an orientation flat for identifying the orientation of the wafer or an index flat for identifying the front and back at the position of the cleavage plane unique to the crystal constituting the wafer obtained by cutting a single crystal of a compound semiconductor In the semiconductor wafer manufacturing method, chamfering is performed on the edge of the outer peripheral surface of the wafer to form a chamfered portion, and then lapping and polishing are performed on the front surface of the wafer, and the orientation flat or index flat front surface side A method of manufacturing a compound semiconductor wafer, wherein the chamfered portion is removed between the lapping step and the polishing step.

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