JP2008176485A - Reconfigurable logical device and its debugging system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve debugging using an undefined value similar to a logical simulator in a reconfigurable logical device. <P>SOLUTION: A function for storing an undefined value, and for performing an arithmetic operation including the undefined value, and for propagating the undefined value is applied to a component of a reconfigurable logical device. In a reconfigurable logical device equipped with a register 7 and wiring, the register 7 is configured to record the undefined value, and provided with terminals 9, 11 and 13 for undefined value extension, and the wiring is configured to propagate the undefined value. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a reconfigurable logic device and a debugging system thereof, and more particularly to a reconfigurable logic device having a debugging function by indefinite value propagation and a debugging system thereof.

  In recent years, in LSI development using reconfigurable logic devices (including partially reconfigurable or dynamically reconfigurable logic devices; the same applies hereinafter), development based on rapid prototyping has become popular. The development cycle of design, synthesis, and execution by actual machines is becoming shorter.

  If the scale of the logic circuit or the number of execution cycles is large, even if the synthesis time takes a long time, TAT (Turn Around Time) will be shortened by performing debugging with real heartware compared to simulation. There is also.

  In addition, since the operation may be logically different between the simulation and the mapping to the actual hardware, the verification by the actual hardware is finally required even when the simulation is performed.

  Thus, from the viewpoint of shortening TAT and certainty of verification, a technique for easily realizing debugging in actual hardware is expected.

  A simulation method using indefinite value propagation is disclosed in, for example, Document 1.

JP 05-189516 A

  It is known that logic circuit debugging is effective for analyzing indefinite value propagation using a logic simulator (Patent Document 1). However, conventional real hardware cannot handle indefinite values, and can only handle binary values of 0 or 1, so circuit debugging by indeterminate value detection is impossible.

  Therefore, there is provided a reconfigurable logic device and a debugging apparatus for enabling indefinite value propagation in a real chip and enabling debugging using indefinite value propagation in a real chip as well as a logic simulator. Is a problem.

  A reconfigurable logic device according to a first aspect of the present invention is a reconfigurable logic device including a storage element and a wiring of either a register or a memory, and the storage element holds an indefinite value. The wiring is configured to propagate an indefinite value.

  A reconfigurable logic device according to a second aspect of the present invention is a reconfigurable logic device comprising an arithmetic unit and wiring, wherein the arithmetic unit is configured to perform an operation including an indefinite value, The wiring is configured to propagate an indefinite value.

  A reconfigurable logic device according to a third aspect of the present invention is a reconfigurable logic device including a switch and a wiring for changing an internal configuration, wherein the switch is configured to propagate an indefinite value, The wiring is configured to propagate an indefinite value.

  A reconfigurable logic device according to a fourth aspect of the present invention is a reconfigurable logic device having an input / output terminal, wherein the input / output terminal is configured to propagate an indefinite value. To do.

  The reconfigurable logical device according to the first development mode is characterized in that it can be switched between a normal mode that does not consider indefinite values and a debug mode that takes into account indefinite values.

  The reconfigurable logic device of the second development form is configured to use resources used for error detection or error correction in the normal mode in the debug mode.

  The reconfigurable logic device according to the third development form is configured to add an indefinite value for each bit.

  The reconfigurable logical device according to the fourth development mode is characterized in that an indefinite value is added for each unit of data processing.

  The reconfigurable logic device of the fifth development form is configured to set an indefinite value to any of the storage element, the arithmetic unit, the switch, and the input / output terminal at the time of initialization. Features.

  The debug system for a reconfigurable logic device according to a sixth development mode is configured to initialize the reconfigurable logic device and the reconfigurable logic device when the storage element, the arithmetic unit, the switch, And a debugging device configured to set an indefinite value to any of the input / output terminals.

  The debugging system for a reconfigurable logic device according to a seventh development form writes the configuration information to the reconfigurable logic device and the reconfigurable logic device, and then stores the storage element, the arithmetic unit, And a debug device configured to set an indefinite value to any one of the switch and the input / output terminal.

  The reconfigurable logic device according to the eighth expansion mode acquires indefinite value propagation information generated or propagated in any of the storage element, the arithmetic unit, the switch, the wiring, and the input / output terminal, and is used for debugging. And a controller configured to output the above information.

  A debug system for a reconfigurable logic device according to a ninth development mode includes the logic device, and a debug apparatus configured to input the debug information from the controller and output the debug information. , Provided.

  The reconfigurable logic device according to the tenth development form is configured to generate an event triggered by indefinite value propagation.

  The debug system for a reconfigurable logic device according to an eleventh development mode is characterized in that an event is generated with the indefinite value propagation as a trigger.

  The reconfigurable logic device according to the twelfth mode is characterized in that it is configured to record indefinite value propagation in time series.

  A debugging system for a reconfigurable logic device according to a thirteenth development mode is characterized in that it is configured to record indefinite value propagation in time series.

  The reconfigurable logic device according to the fourteenth development mode is characterized in that the reconfigurable logic device is configured to stop when triggered by indefinite value propagation.

  A debugging system for a reconfigurable logic device according to a fifteenth development mode is characterized in that it is configured to stop when triggered by indefinite value propagation.

  The reconfigurable logic device debugging system according to the sixteenth development mode is characterized in that debugging information is displayed during operation triggered by occurrence of an indefinite value.

  The debug system for a reconfigurable logic device according to a seventeenth development mode is characterized in that it displays information for debugging after being stopped with the occurrence of an indefinite value as a trigger.

  According to the reconfigurable logic device and the debugging system thereof according to the present invention, it is undefined in the real chip of the reconfigurable logic device without performing simulation by a low-speed simulator by software or a high-speed but expensive emulator. It becomes possible to handle the value.

  Therefore, efficient debugging using indefinite values can be performed in the actual chip as in the case of using the simulator.

  In order to achieve the above object, the device of the present invention is a reconfigurable logic device and includes not only binary values of 0 and 1 but also storage elements (including registers and memories; the same applies hereinafter) constituting the device. It has a function capable of holding an indefinite value, and a wiring that propagates an indefinite value in a wiring that constitutes the device.

  Further, the logic device is a reconfigurable logic device, and has a function in which an arithmetic unit constituting the device performs an operation including an indefinite value, and a wiring in which the device constitutes an indefinite value.

  Also, a reconfigurable logic device that generates an indeterminate value due to the setting of the switch element that connects the wires that make up the device, and a wire that propagates the indeterminate value in the wires that make up the device And having.

  Also, a reconfigurable logic device, wherein the input / output terminals that make up the device can send and receive indefinite values to and from external circuits, and the wires that make up the device propagate indefinite values Have.

  A reconfigurable logic device that has a mode switching function between a normal mode and a debug mode, and an existing resource and an indefinite value propagation function (memory element / arithmetic unit / wiring / And a function of sharing some or all of the resources by switching the input / output terminals.

  This is a reconfigurable logic device, and by this, an indefinite value expression is written in an uninitialized part in advance and operated, so that even an actual machine has a function of detecting indefinite value propagation caused by a circuit failure.

  Next, in order to clarify the above and other objects, features, and advantages of the present invention, embodiments of the present invention will be described with reference to the accompanying drawings.

  FIG. 1 shows a reconfigurable logic device with indefinite value functionality. Hereinafter, a configuration of a reconfigurable logical device will be described as an example. However, the present invention can be similarly applied to partially reconfigurable or dynamically reconfigurable logical devices.

  A reconfigurable logic device 1 includes a processing element (PE) 2 composed of a storage element such as a register and a memory or an arithmetic unit, a wiring 3, a switch 4 for connecting the wirings, and a plurality of input / output terminals 5 in a matrix. Prepare. In addition to these, a controller 6 that performs mode setting and detection of indefinite value propagation is provided.

  The components 2 to 6 in FIG. 1 are similarly included in a conventional reconfigurable logic device. However, these components according to the present invention have a function of holding or propagating indefinite values. That is, the storage element 2 further includes a storage element that can hold not only a specific value (any one of the two values) but also an indefinite value, and the computing unit 2 not only performs a calculation between specific values but also a specific value. And an arithmetic unit extension that can perform operations including undefined values such as undefined values, the wiring 3 further includes wiring that can propagate undefined values, and the switch 4 propagates undefined values and sets undefined values. The input / output terminal 5 includes an extension terminal capable of propagating an indefinite value in order to transmit and receive an indefinite value between the reconfigurable logic device and the external circuit.

  Here, the indefinite value function to be added may be the addition of a physical 1-bit line or the addition of a logical 1-bit by multiple values (the same applies to the description regarding the addition of bits).

  Further, the controller 6 has a function of reading / writing an indefinite value in addition to a function of reading / writing a specific value to / from a storage element 2 such as a register or a memory constituting a reconfigurable logic device. The controller 6 has a function of receiving an indefinite value generation or propagation signal from each of the components 2 to 5 of the reconfigurable logic device 1 and detecting the indefinite value.

  A debugging device is provided outside the reconfigurable logic device 1. The reconfigurable logic device 1 and the debug apparatus are collectively referred to as a reconfigurable logic device debug system.

  FIG. 8 is a diagram showing a debugging device comprising a computer and software having an interface connectable to an input / output device and a reconfigurable logic device.

  The debugging device 41 includes a computer 42 and software (not shown), and communicates with the controller 6 of the reconfigurable logic device 1 via the interface device 45 included in the computer 42 to set information necessary for debugging. , Get, generate and display.

  FIG. 2 shows the register 7 subjected to indefinite value expansion. An indefinite value port is added to each of the write, read, and write enable (WE) terminals, and a storage element is added internally so that the indefinite value can be held (recorded). Trivial signal lines in the synchronous circuits such as clock and reset are omitted. Similarly, the obvious signal lines are omitted in the following drawings.

  In the figure, n of n bits is an integer of 1 or more. For example, when n = 8, it indicates that information for an indefinite value is extended by 1 bit for an 8-bit register. Terminals 9 and 11 for indefinite value expansion are added to the write terminal 8 and the read terminal 10, respectively. In addition, a WE (Write Enable) terminal 12 extends the indefinite value expansion terminal 13 by 1 bit as it is to the 1 bit. If the target of indefinite value expansion is not a register but a flip-flop (FF), the WE terminal 12 is not necessary. When the address is a specific value, the specific value and the indefinite value can be written and read. However, when the address is the indefinite value, writing does not occur, and the indefinite value is read in the read. Further, when the input to the WE terminal 12 is an indefinite value, writing is not performed.

  FIG. 3 shows the memory 14 subjected to indefinite value expansion. An indefinite value port is added to each of the write data, read data, address, and write enable (WE) terminals, and a storage element is added internally so that the indefinite value can be held.

  M and n in the figure are integers of 1 or more, respectively. For example, when m = n = 8, it indicates that the storage area for 1 bit indicating an indefinite value is expanded for every 8 bits of the memory. . Indefinite value expansion terminals 16, 18, and 20 are added to the write data, address data, and read data terminals 15, 17, and 19, respectively. Further, the WE terminal 21 extends the indefinite value expansion terminal 22 by 1 bit as it is to the 1 bit.

  FIG. 4 shows an ALU (arithmetic logic unit) 23 that has been expanded with indefinite values. Ports for indefinite values are added to the input p, input q and output r terminals, respectively, and an arithmetic function including indeterminate values is added in the ALU. If the ALU is a selector, a port for an indefinite value is added to the select terminal. In the figure, n is an integer equal to or greater than 1. For example, when n = 8, the arithmetic unit granularity is 8 bits with 2 inputs (terminals 24 and 26) and 1 output (terminal 28), and the indefinite value expansion is performed. The input including the terminals (terminals 24, 25, 26, and 27) is received, the calculation considering the indefinite value is performed, and the calculation result including the indefinite value is output (terminals 28 and 29). When the ALU 23 is a selector (SELECTOR) that selects and outputs one of the inputs, the ALU 23 has a terminal 30 that receives the selector value (control value). Therefore, this indefinite value extension (1 bit) is used for indefinite value extension. The terminal 31 is expanded by 1 bit.

  FIG. 5 shows a truth table of an operation considering indefinite values. Generally, when any one of the inputs is an indefinite value, the calculation result, that is, the output becomes an indefinite value. However, in a logical operation such as AND or OR and a selector, the output may be a specific value even if any of the inputs is an indefinite value. In general, in an operation with multiple inputs and one output, if an indefinite value X is included in any one of the inputs, the output becomes the indefinite value X. However, in the case of logical operations such as AND and OR and selectors, the output value may be specified even if one of the inputs is an indefinite value X. For example, in the case of logical product (AND), if any one of the input terminals is zero, the output is zero. Therefore, only in this case, even if any of the input terminals is an indefinite value X, the output is specified as zero. In the case of logical sum (OR), if any one bit of the input is all 1, the output bits are all 1. Therefore, only in this case, even if the indefinite value X is included in any of the input terminals, the output bits are all specified as 1. When the input is an indefinite value X, the output is also an indefinite value X. In the case of the 2-input 1-output selector, if the select signal is a specific value, the output is specified even if the unselected input is the indefinite value X. When the select signal is an indefinite value X, the output is always an indefinite value X.

  FIG. 6 shows an example of a switch considering an indefinite value. A line 33 with a slash in the figure is a conventional signal line, and a line 34 without a slash is a signal line for an indefinite value. The cloud portion shows the network 32. For the signal line 35 whose input terminal is not connected (NC), an undefined value is set in the undefined value signal line 36. That is, an indefinite value is set for the disconnected signal line 35 of the reconfigurable logic device, and the indefinite value propagates through the wiring.

  FIG. 7 shows an example of sharing an indefinite value function with an existing resource. As an existing resource, when the register 7 and the memory 14 have a function of recalculating the parity bit 37 and the ALU 23 has a function of recalculating the parity bit 38, the parity bit 37 of the register 7 and the memory 14 is exclusively used to hold an indefinite value. Can also be used. In addition, by defining a normal mode that does not consider an indeterminate value and a debug mode that considers an indeterminate value, and incorporating a function for performing an indeterminate value operation in conjunction with mode switching by the mode changeover switch 40, the parity bit 38 and Wiring can be shared between the indefinite value holding bits 39, and an indeterminate value calculation function can be added while minimizing overhead.

  This mode switching is controlled by the controller 6 shown in FIG. Although FIG. 7 shows the case where the existing resource is parity, the existing resource may have a failure detection function such as ECC (Error Checking and Correcting).

  FIG. 8 shows the debugging device 41. The debugging device 41 includes a computer 42, an input device 43, and an output device 44. The computer 42 includes an interface device 45 that can be connected to the reconfigurable logical device 1. In addition, debug software operates on the computer 42.

  A reconfigurable logic device functions by setting a user circuit as configuration information. Referring to FIG. 1, in the reconfigurable logic device 1 according to the first embodiment, before the configuration information is written, the contents of the storage elements 2 such as all registers and memories are filled with indefinite values, and all the switches 4 Is set to non-connection, and an indefinite value is set so that the non-connection portion has an indefinite value.

  This indefinite value setting operation may be incorporated in the reset operation of the reconfigurable logic device 1 or may be embedded as a function of the debug device 41 of the reconfigurable logic device with reference to FIG. good.

  Note that the indefinite value setting operation may be performed so that only an arbitrary portion has an indefinite value after the configuration information is written. At this stage, indefinite values are set for the storage elements 2 for which configuration information has not been set and the wires 3 in a disconnected state.

  Next, the user circuit is operated.

  When there is no bug in the configuration information of the user circuit, the indefinite value set in the reconfigurable logic device 1 is not used and does not propagate through the wiring 3. On the other hand, when a bug is included in the configuration information, an indefinite value can be propagated.

  When the indeterminate value is read by the memory and the arithmetic unit arranged in the PE 2 and the operation result becomes the indefinite value, the information is collected in the controller 6 of the reconfigurable logic device 1 to generate the indefinite value. And its occurrence location is detected.

  Referring to FIG. 8, information on the occurrence of an indefinite value and the occurrence location is transmitted to the debug device 41 connected to the outside of the reconfigurable logic device 1 via the interface device 45 of the computer 42, and the output device 44. Is displayed to the circuit designer.

  As a result, the circuit designer can detect a problem portion of the circuit, that is, a bug included in the configuration information.

  In the first embodiment, a bug can be detected by setting an undefined value in an unset portion of the configuration information. In the second embodiment, an indefinite value is set in a specific part of interest, a specific value is set in the other part, and then the propagation of the indeterminate value is analyzed, so that a bug affects the propagation range of the indefinite value. The range can be specified.

  First, specific values are set for all the configuration information including the configuration information of the user circuit. Next, an indefinite value is set for a specific component whose influence range on the circuit structure is to be examined.

  Thereafter, the user circuit is operated over a specific cycle.

  Then, an indefinite value propagates in a cone shape starting from the attention point. Referring to FIG. 1, this information is collected in the controller 6 of the reconfigurable logic device 1. Further, referring to FIG. 8, the information collected in the controller 6 is transferred to an externally connected debug device 41 via an interface device 45 of the computer 42, and a circuit design is performed by the output device 44 of the debug device 41. It is presented to the person.

  Thereby, the circuit designer can grasp the influence range of the bug included in the specific component and can use it as auxiliary information for debugging.

It is a figure which shows the reconfigurable logic device provided with the indefinite value function. It is a figure which shows the example which added the indefinite value holding | maintenance function to the register. It is a figure which shows the example which added the indefinite value holding | maintenance function to 2 port memory of 1 read 1 write. It is a figure which shows the example which added the indefinite value calculation function to 2 input 1 output ALU (arithmetic unit). It is a truth table of an operation including an indefinite value. It is a figure which shows propagation of the indefinite value in a switch. It is a figure which shows sharing the holding resource of an indefinite value with the existing resources, such as a parity, in a register | resistor and memory. It is a figure which shows the debug system of the reconfigurable logic device which consists of a debug apparatus and a reconfigurable logic device.

Explanation of symbols

1 Reconfigurable Logic Device 2 Processing Element (PE) Composed of Storage Element and Arithmetic Unit
3 Wiring 4 Switch 5 Input / output terminal 6 Controller 7 Register 8, 15 Write terminal 9, 11, 13, 16, 18, 20, 22, 25, 27, 29, 31 Undefined value expansion terminal 10, 19 Read terminal 12, 21 WE terminal 14 Memory 17 Address terminal 23 ALU (arithmetic unit)
24, 26 Input terminal 28 Output terminal 30 Select terminal 32 Network 33, 34, 35, 36 Signal line 37 Parity (undefined value holding) bit 38 Parity bit 39 Undefined value holding bit 40 Mode changeover switch (SW)
41 Debugging Device 42 Computer 43 Input Device 44 Output Device 45 Interface Device

Claims (21)

In a reconfigurable logic device with storage elements and wiring, either registers or memories,
The storage element is configured to hold an indeterminate value;
A reconfigurable logic device, wherein the wiring is configured to propagate an indefinite value. In a reconfigurable logic device with a computing unit and wiring,
The arithmetic unit is configured to perform an operation including an indefinite value;
A reconfigurable logic device, wherein the wiring is configured to propagate an indefinite value. In reconfigurable logic devices with switches and wiring that change the internal configuration,
The switch is configured to propagate an indeterminate value;
A reconfigurable logic device, wherein the wiring is configured to propagate an indefinite value. In a reconfigurable logic device with input / output terminals,
The reconfigurable logic device, wherein the input / output terminal is configured to propagate an indefinite value.   5. The reconfigurable logic according to claim 1, wherein the reconfigurable logic is configured to be switchable between a normal mode not considering an indefinite value and a debug mode considering an indefinite value. device.   The reconfigurable logic device according to claim 5, wherein resources used for error detection or error correction in the normal mode are configured to be used in the debug mode.   5. The reconfigurable logic device according to claim 1, wherein the reconfigurable logic device is configured to add an indefinite value for each bit.   5. The reconfigurable logic device according to claim 1, wherein an indefinite value is added to each unit of data processing.   5. The device according to claim 1, wherein an undefined value is set to any one of the storage element, the arithmetic unit, the switch, and the input / output terminal at the time of initialization. Reconfigurable logical device. Reconfigurable logic device according to any of claims 1 to 4,
A debugging device configured to set an indefinite value to any of the storage element, the arithmetic unit, the switch, and the input / output terminal when initializing the reconfigurable logic device;
A debug system for a reconfigurable logic device, comprising: Reconfigurable logic device according to any of claims 1 to 4,
A debugging device configured to set an indefinite value to any of the storage element, the arithmetic unit, the switch, and the input / output terminal after writing configuration information to the reconfigurable logic device;
A debug system for a reconfigurable logic device, comprising:   A controller configured to acquire indefinite value propagation information generated or propagated in any of the storage element, the arithmetic unit, the switch, the wiring, and the input / output terminal, and to output information for debugging; The reconfigurable logic device according to claim 9, comprising: a reconfigurable logic device. Reconfigurable logic device according to claim 12,
A debugging device configured to input the debugging information from the controller and output the debugging information;
A debug system for a reconfigurable logic device, comprising:   The reconfigurable logic device according to claim 9, wherein the reconfigurable logic device is configured to generate an event triggered by indefinite value propagation.   12. The debug system for a reconfigurable logic device according to claim 10, wherein the debug system is configured to generate an event triggered by indefinite value propagation.   The reconfigurable logic device according to claim 9, wherein the reconfigurable logic device is configured to record indefinite value propagation in time series.   12. The debug system for a reconfigurable logic device according to claim 10, wherein the debug system is configured to record indefinite value propagation in time series.   The reconfigurable logic device according to claim 9, wherein the reconfigurable logic device is configured to stop when an undefined value propagation is triggered.   12. The debugging system for a reconfigurable logic device according to claim 10, wherein the debugging system is configured to stop when undefined value propagation is triggered.   18. The reconfigurable logic device debugging system according to claim 15, wherein debugging information is displayed during operation triggered by occurrence of an indefinite value.   20. The debug system for a reconfigurable logic device according to claim 17, wherein the debug information is displayed after being stopped with the occurrence of an indefinite value as a trigger.

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