JP2008078389A - Manufacturing method of semiconductor device - Google Patents

Abstract

In a ferroelectric memory having a ferroelectric film formed by a sol-gel method, a semiconductor device for improving electrical characteristics of a ferroelectric capacitor and a manufacturing method thereof are provided.
According to a method for manufacturing a semiconductor device including a ferroelectric film, a sol-gel solution in which a perovskite ferroelectric material is dissolved in a solvent is applied onto a lower electrode layer 72, and the coating film of the ferroelectric material is applied. A step of forming, a film forming step of removing the solvent from the coating film, and forming a ferroelectric film 73 made of an amorphous state or microcrystals on the lower electrode 72, and the amorphous state or microscopic state. A first heat treatment step of heat-treating the ferroelectric film 73 made of crystals at a first temperature in the vicinity of the crystallization temperature of the ferroelectric material, and crystallizing in accordance with the crystal orientation of the lower electrode layer; A second heat treatment step for heat-treating the crystallized ferroelectric film 73 at a second temperature higher than the first temperature in an oxidizing atmosphere to compensate for oxygen vacancies in the crystallized ferroelectric film. And execute.
[Selection] Figure 6G

Description

  The present invention generally relates to semiconductor devices, and more particularly to a semiconductor device having a ferroelectric capacitor and a method for manufacturing the same.

  A ferroelectric memory is a voltage-driven non-volatile semiconductor memory element, which operates at high speed, has low power consumption, and has preferable characteristics that do not lose stored information even when the power is turned off. Ferroelectric memories are already used in IC cards and portable electronic devices.

  FIG. 1 is a cross-sectional view showing the structure of a so-called stack type ferroelectric memory device 10.

  Referring to FIG. 1, a ferroelectric memory device 10 is a so-called 1T1C type device, in which two memory cell transistors are provided in a bit line in an element region 11A defined by an element isolation region 11I on a silicon substrate 11. Is formed by sharing.

  More specifically, an n-type well is formed as the element region 11A in the silicon substrate 11, and a first MOS transistor having a polysilicon gate electrode 13A and polysilicon are formed on the element region 11A. A second MOS transistor having a gate electrode 13B is formed through gate insulating films 12A and 12B, respectively.

The further in the silicon substrate 11, the p in correspondence to respective sidewalls of the gate electrode 13A ^- -type LDD region 11a, and 11b are formed, also in correspondence to respective sidewalls of the gate electrode 13B p ^- -type LDD regions 11c and 11d are formed. Here, since the first and second MOS transistors are formed in common in the element region 11A, the same p ⁻ type diffusion region is shared as the LDD region 11b and the LDD region 11c.

  A silicide layer 14A is formed on the polysilicon gate electrode 13A, and a silicide layer 14B is formed on the polysilicon gate electrode 13B. Further, both side walls of the polysilicon gate electrode 13A and the polysilicon gate are formed. Each side wall insulating film is formed on both side wall surfaces of the electrode 13B.

Further, in the silicon substrate 11, p ⁺ type diffusion regions 11e and 11f are formed outside the respective side wall insulating films of the gate electrode 13A, and each of the side wall insulating films of the gate electrode 13B is formed. On the outside, p ⁺ -type diffusion regions 11g and 11h are formed. However, the diffusion regions 11f and 11g are composed of the same p ⁺ -type diffusion region.

Further, on the silicon substrate 11, the gate electrode 13A including the silicide layer 14A and the sidewall insulating film is covered, and the gate electrode 13B including the silicide layer 14B and the sidewall insulating film is covered. A SiON film 15 is formed, and an interlayer insulating film 16 made of SiO ₂ is formed on the SiON film 15. Further, contact holes 16A, 16B, and 16C are formed in the interlayer insulating film 16 so as to expose the diffusion regions 11e, 11f (and hence the diffusion regions 11g) and 11h, respectively, and are formed in the contact holes 16A, 16B, and 16C. The via plugs 17A, 17B, and 17C made of W (tungsten) are formed through the adhesion layers 17a, 17b, and 17c in which the Ti film and the TiN film are stacked.

  Further, a first ferroelectric capacitor C1 in which a lower electrode 18A, a polycrystalline ferroelectric film 19A, and an upper electrode 20A are stacked on the interlayer insulating film 16 in contact with the tungsten plug 17A is also provided. A second ferroelectric capacitor C2 in which a lower electrode 18C, a polycrystalline ferroelectric film 19C, and an upper electrode 20C are stacked is formed in contact with the tungsten plug 17C.

Further, a hydrogen barrier film 21 made of Al ₂ O ₃ is formed on the interlayer insulating film 16 so as to cover the ferroelectric capacitors C 1 and C ₂ , and the next interlayer insulating film 22 is further formed on the hydrogen barrier film 21. Is formed.

  Further, in the interlayer insulating film 22, a contact hole 22A exposing the upper electrode 20A of the ferroelectric capacitor C1, a contact hole 22B exposing the via plug 17B, and an upper electrode 20C of the ferroelectric capacitor C2 are provided. An exposed contact hole 22C is formed, and tungsten plugs 23A, 23B, and 23C are formed in the contact holes 22A to 22C through adhesion layers 23a, 23b, and 23c in which a Ti film and a TiN film are laminated, respectively.

Further, Al wiring patterns 24A, 24B, and 24C are formed on the interlayer insulating film 22 with a barrier metal film having a Ti / TiN laminated structure corresponding to the tungsten plugs 23A, 23B, and 23C, respectively. .
JP 2001-126955 A JP 11-292626 A JP 2004-335491 A JP 2005-183850 A JP 2002-246564 A JP 2005-183842 A

  Conventionally, a technique for forming a ferroelectric film constituting a ferroelectric memory by a sol-gel method, a sputtering method, or a MOCVD method has been proposed. However, in the sol-gel method that does not require a vacuum process, the ferroelectric film is inexpensive. Can be formed.

  On the other hand, in the ferroelectric memory as shown in FIG. 1, the crystal orientation of the polycrystalline ferroelectric films 19A and 19C to be the ferroelectric capacitor insulating film is very important. Ferroelectric materials such as PZT have a tetragonal perovskite structure, and ferroelectric properties are manifested when metal atoms such as Ti and Zr are displaced in the c-axis direction in the perovskite structure. Therefore, in a ferroelectric capacitor having a configuration in which a ferroelectric film is sandwiched between upper and lower electrodes, as in the ferroelectric memory 10 of FIG. 1, the electric field direction is strong so that it is parallel to the c-axis direction of the ferroelectric. Ideally, the dielectric film has a (001) orientation. When the ferroelectric film has a (100) orientation, ferroelectricity does not appear.

However, in the perovskite film, the difference between the c-axis and the a-axis is small even though it is tetragonal. Therefore, in the PZT film formed by the usual manufacturing method, the (001) -oriented crystal grains and (100) Considering that almost the same number of oriented crystal grains are generated and those with other orientations are also generated, the proportion of crystals that actually contribute to the operation of the ferroelectric capacitor was small. Under such circumstances, conventionally, in the technical field of ferroelectric memory, the ferroelectric films 19A and 19C are formed as a (111) orientation film as a whole, and the orientation direction is aligned in the <111> direction. The switching charge amount _QSW is ensured.

  Under such circumstances, in a ferroelectric memory, a Pt film is formed as a lower electrode of a ferroelectric capacitor on an orientation control film such as a self-aligned Ti film with a (111) orientation, and a ferroelectric such as PZT is formed thereon. The body film is formed with (111) orientation. Here, the self-oriented Ti film exhibits a (002) orientation.

  When forming a ferroelectric film by the sol-gel method, apply the sol-gel solution of the ferroelectric film to be formed on the underlying layer on which the lower electrode is formed, and heat-treat it at a low temperature so that crystallization does not occur After removing the solvent in the sol-gel solution, the remaining amorphous phase or microcrystalline film is heat-treated in an oxidizing atmosphere, for example, 650 ° C., which greatly exceeds the crystallization temperature, for example, an oxygen gas atmosphere, The dielectric film is crystallized in an orientation that matches the crystal orientation of the lower electrode. By such heat treatment in a high-temperature oxidizing atmosphere, the ferroelectric film is crystallized in a predetermined orientation, and at the same time, oxygen vacancies in the film are compensated.

  By the way, the inventors of the present invention conducted research to improve the electrical properties of a ferroelectric film formed by the sol-gel method, particularly a PZT film, in the research that is the basis of the present invention. As shown in FIGS. 2A and 2B, it has been found that PZT crystal grains may be formed on the surface of the PZT film with different orientations. 2A is a scanning electron micrograph of the PZT film thus obtained, and FIG. 2B is a schematic cross-sectional view thereof.

  Referring to FIGS. 2A and 2B, the PZT film has been subjected to crystallization heat treatment at 650 ° C. in a 100% oxygen atmosphere, and shows the state of the central portion of the sample substrate. The PZT film is formed on a (111) -oriented Pt film, while the Pt film is formed on a (111) -oriented IrOx film.

  As can be seen from FIGS. 2A and 2B, the PZT film is composed of a columnar PZT crystal grown from the Pt film, and takes on the (111) orientation of the Pt film and is (111) oriented.

  On the other hand, FIG. 2A shows that another large PZT crystal is formed on the surface portion of the film composed of such PZT columnar crystals. This other PZT crystal is not grown from the interface of the Pt film, and therefore has a random orientation without taking over the orientation direction of the Pt film.

  In a ferroelectric capacitor, if there are many ferroelectric crystals whose orientations are not restricted in the ferroelectric film, the electrical characteristics of the ferroelectric capacitor such as the switching charge amount deteriorate.

  In one aspect, the present invention provides a method for manufacturing a semiconductor device including a ferroelectric film, wherein a sol-gel solution in which a perovskite ferroelectric material is dissolved in a solvent is applied on a lower electrode layer, Forming a coating film of a body material; removing the solvent from the coating film; forming a ferroelectric film made of an amorphous state or a microcrystal on the lower electrode; and the amorphous A first heat treatment step of heat-treating a ferroelectric film made of a crystalline state or microcrystals at a first temperature near the crystallization temperature of the ferroelectric material and crystallizing in accordance with the crystal orientation of the lower electrode layer And heat treating the crystallized ferroelectric film at a second temperature higher than the first temperature in an oxidizing atmosphere to compensate for oxygen vacancies in the crystallized ferroelectric film. And a heat treatment step. The method of manufacture, and provides.

  According to the present invention, when crystallizing an amorphous or microcrystalline ferroelectric film formed by the sol-gel method, by controlling the heat treatment temperature, the surface of the ferroelectric film is lowered from the surface portion. The crystallization process can be controlled so that the crystallization of the ferroelectric film proceeds only upward from the interface with the lower electrode below the crystallization process. Thus, it is possible to obtain a ferroelectric film whose crystal orientation matches the crystal orientation on the surface of the lower electrode over the entire film.

[First Embodiment]
3A to 3E show a manufacturing process of the high-electric capacitor according to the first embodiment of the present invention.

Referring to FIG. 3A, a Ti film 42 having (002) orientation is formed by sputtering as an orientation control film on a silicon oxide film 41 covering a silicon substrate (not shown). On the surface 42, a TiAlN film 43 is formed as an oxygen diffusion barrier film by a reactive sputtering method. The silicon oxide film 41 may carry an Al ₂ O ₃ film on its surface. As will be described later, by terminating oxygen atoms on the surface of the silicon oxide film 41 or the surface of the Al ₂ O ₃ film with NH groups, (002) of the Ti film 42 is obtained. Orientation can be promoted.

For example, the Ti film 42 has a sputtering power of 2.6 kW at a substrate temperature of 20 ° C. in an Ar atmosphere having a pressure of 0.15 Pa in a DC sputtering apparatus with a distance between the substrate to be processed and the target set to 60 mm. It is formed by supplying for 2 seconds. The TiAlN film 43 uses Ti and Al alloy targets in the same DC sputtering apparatus and supplies Ar gas at a flow rate of 40 sccm and nitrogen gas at a flow rate of 10 sccm in an Ar / N ₂ atmosphere at a pressure of 253.3 Pa. The film is formed to a thickness of 100 nm by supplying a sputtering power of 1.0 kW at a substrate temperature of 400 ° C.

  Further, on the oxygen diffusion barrier film 43, a lower electrode 44 is formed by laminating an Ir film having a thickness of 50 to 100 nm, an IrOx film having a thickness of 30 nm, and a Pt film having a thickness of 50 nm. Here, the Pt film has a (111) orientation, and the orientation of the ferroelectric film formed thereon is effectively restricted to the (111) orientation. On the other hand, the Ir film is provided as a diffusion barrier for a metal element such as Pb, and suppresses diffusion of the metal element such as Pb in the ferroelectric film into the TiAlN film 13 and separation of the ferroelectric film. Further, the IrOx film formed between the Ir film and the Pt film is formed in an amorphous phase, and promotes the (111) orientation of the Pt film formed thereon. Here, the Pt film is formed in an Ar atmosphere at a substrate temperature of 400 ° C. and a pressure of 0.2 Pa to a film thickness of 100 nm with a sputtering power of 0.5 kW, while the Ir film has a substrate temperature of 400 ° C. Further, the IrOx film is formed in an amorphous phase by sputtering at a substrate temperature of 50 ° C. as described above.

  Next, in the step shown in FIG. 3A, the structure obtained in this manner is subjected to rapid heat treatment at a temperature of 650 ° C. for 60 seconds in an Ar atmosphere. The IrOx film and the Ir film are densified to improve adhesion and crystallinity.

  In place of the Pt film, a noble metal alloy containing Pt can be used.

  Next, in the step of FIG. 3B, a sol-gel PZT solution is spin-coated on the lower electrode 44 to form a PZT coating film 45a. The spin coating of the sol-gel PZT solution uses, for example, a sol-gel solution for forming a ferroelectric thin film composed of an organic solvent in which a precursor of a constituent element of a desired PZT film is mixed in a predetermined molar ratio, for example, a 10 wt% butanol solution, This is formed by spin-coating the substrate to be processed at a room temperature in a 40% humidity atmosphere at room temperature for 30 seconds. In the present embodiment, the sol-gel containing Pb, La, Zr, and Ti at a molar ratio of 1.10: 2: 40: 60 (Pb, La, Zr, Ti = 1.10: 2: 40: 60). PZT solution is used. This PZT solution is actually a PLZT solution, but in the following, the PLZT composition is also collectively referred to as PZT.

  Next, in the process of FIG. 3 (B), the structure of FIG. 3 (A) is heat-treated at a temperature of 200 to 450 ° C. such as 240 ° C. so as not to cause crystallization of PZT in an oxygen atmosphere at normal pressure. A solvent such as butanol contained in the PZT coating film 45a is vaporized.

  In the process of FIG. 3B, the PZT coating film 45a contracts with the vaporization of the solvent, and the density of the gel constituting the film 45a is increased toward the next crystallization process.

  Here, the optimum heat treatment temperature in FIG. 3B varies depending on the material composition of the ferroelectric film to be formed, and 240 ° C. is optimum in this embodiment.

  3B is repeated four times, for example, an amorphous phase or a microcrystalline PZT film 45A having a thickness of 120 nm is formed on the lower electrode 44 with a thickness of 120 nm.

  Next, in the step of FIG. 3C, the structure of FIG. 3B is subjected to 40 to 150 at normal pressure or reduced pressure in an appropriate atmosphere such as an oxygen atmosphere or an oxygen atmosphere containing an inert gas. Rapid thermal processing (RTA) is performed at a high temperature rising rate of about 125 ° C./minute, for example, 125 ° C./minute to crystallize the amorphous phase or the microcrystalline PZT film 45A and convert it into a crystallized PZT film 45B. .

  In particular, in the present embodiment, when the crystallization heat treatment of FIG. 3C is performed at normal pressure, the heat treatment temperature at this time is higher than the crystallization temperature of the PZT film 45A in the amorphous phase or the microcrystalline state. The temperature is set to a temperature range where the lower temperature is 15 ° C. and the upper temperature is 50 ° C. higher than this. When the crystallization heat treatment of FIG. 3C is performed under reduced pressure, for example, at 100 Pa, the heat treatment temperature is set to 25 ° C. lower than the crystallization temperature of the amorphous phase or the microcrystalline PZT film 45A. The lower limit is set at a temperature range having an upper limit of 40 ° C., for example, 550 ° C.

  By performing the crystallization heat treatment of the PZT film 45A in the step of FIG. 3C at a temperature close to the crystallization temperature of the film 45A in this way, the crystallization of the PZT film 45A in the amorphous phase or the microcrystalline state is performed. However, although it proceeds upward from the interface with the lower electrode 44, crystallization does not proceed downward from the surface portion of the PZT film 45A. Accordingly, the crystallized PZT film 45B has a microstructure composed of (111) -oriented columnar PZT crystals as shown in FIG. 4, and has the orientation as described above with reference to FIGS. 2 (A) and 2 (B). Crystal grains whose orientation is not regulated are not generated.

  Note that the heat treatment step in FIG. 3C can be performed in an appropriate atmosphere such as an oxidizing atmosphere or an inert atmosphere, and is not limited to a specific atmosphere.

  Next, in the step of FIG. 3D, the structure of FIG. 3C is heat-treated in an oxidizing atmosphere at a temperature higher than the heat treatment temperature of the step of FIG. Oxygen deficiency compensation is performed in the crystallized PZT film 45B. In the step of FIG. 3D, since the crystallization of the amorphous phase or microcrystalline PZT film 45A has already been substantially completed in the step of FIG. 3C, even if the heat treatment is performed at a high temperature. Irregular crystal growth does not occur. Further, even if the crystallization of the PZT film 45B further proceeds at the stage of FIG. 3D, if the degree is slight, the crystallization is restricted to the (111) -oriented PZT columnar crystal grains already formed. Therefore, a PZT crystal having an irregular crystal orientation does not grow.

  On the other hand, if the crystallization process of FIG. 3C is insufficient, irregular crystal growth may occur in the high-temperature heat treatment process of FIG. 3D. Needs to be set so as not to fall below the lower limit described above, based on the crystallization temperature of the ferroelectric film.

  Further, in the step of FIG. 3E, the upper electrode 46 is formed on the PZT film 45B by sputtering using IrOx that forms a good interface with the PZT. In the present embodiment, the use of Pt in catalytic action as the upper electrode 46 is avoided, whereby the reduction of the PZT film 45B by activated hydrogen is suppressed.

  More specifically, after the step of FIG. 3D, an IrOx film having a thickness of 50 nm is first sputtered on the PZT film 45B by sputtering, for example, at a substrate temperature of 300 ° C. Oxygen gas is supplied at a flow rate of 120 sccm and 80 sccm, respectively, and a sputtering power of 1 to 2 kW is applied to form, for example, a film thickness of 50 nm and in a state already crystallized at the time of film formation.

  Next, the IrOx film thus formed is rapidly crystallized at a temperature of 725 ° C. for 60 seconds while supplying oxygen gas at a flow rate of 20 sccm and Ar gas at a flow rate of 2000 sccm, and is completely crystallized. In addition, this rapid heat treatment compensates for oxygen vacancies caused by the formation of the upper electrode 46 in the PZT film 45B.

Next, a second iridium oxide film (IrOy film) is formed on the first iridium oxide film (the IrOx film) thus formed by sputtering in an Ar atmosphere of 0.8 Pa by 1.0 kW. With a sputtering power of 100 to 300 nm, for example, a thickness of 200 nm is formed. The second iridium oxide film thus formed has a composition close to the stoichiometric composition of IrO ₂ , and does not cause a catalytic action such as Pt against hydrogen or water. Even when the multilayer wiring structure is formed on the structure (E), the problem that the PZT film 45B is reduced by hydrogen released from the interlayer insulating film containing moisture is suppressed, and the hydrogen resistance of the ferroelectric capacitor is suppressed. Will improve.

  By making the upper electrode 46 in this two-layer structure, excellent adhesion is secured between the lower IrOx film and the PZT film 45B below it, and the upper IrOy film described above. As described above, the hydrogen resistance of the ferroelectric capacitor is improved.

In the present embodiment, Ir, Ru, Rh, Re, Os, Pd, or an oxide thereof, or a conductive oxide such as SrRuO ₃ can be used as the upper electrode 46 instead of IrOx. In addition, the upper electrode 46 may have a laminated structure of these metals or conductive oxide layers.

In this embodiment, an Ir film may be formed on the surface of the upper electrode 46, although not shown. Thereby, the penetration of H ₂ O into the ferroelectric film 15B through the upper electrode 46 is suppressed, and the contact characteristics with the wiring pattern are improved.

FIG. 5A shows the switching charge amount Q _SW of the ferroelectric capacitor thus obtained. FIG. 5B shows the switching charge amount Q _SW of the ferroelectric capacitor. It is a figure which shows each about the state after forming the multilayer wiring structure of a three-layer structure on a capacitor, ie, the state where an actual ferroelectric capacitor is used. However, in FIG. 5A, curve A shows the characteristics of the ferroelectric capacitor (sample 1) according to the above embodiment, and curves B and C show the PZT film formed by the sol-gel method immediately after the solvent removal step. Formed by a conventional method in which crystallization heat treatment and oxygen deficiency compensation processing are performed at 650 ° C. in an oxygen atmosphere. Curve B shows the case where the upper electrode is made of Pt (sample 2), and curve C shows the case of IrOx. (Sample 3) is shown.

  Referring to FIGS. 5A and 5B, in the state immediately after the formation of the ferroelectric capacitor in FIG. 5A, the sample with the Pt film formed as the upper electrode under the conventional conditions has the largest switching. In contrast to the charge amount, when the multilayer wiring structure is actually formed on the ferroelectric capacitor as shown in FIG. 5B, the electrical characteristics of the sample using Pt for the upper electrode are remarkably deteriorated. On the other hand, it can be seen that the sample of the present invention indicated by curve A shows the largest switching charge amount.

In the sample 2, the phenomenon that the switching charge amount greatly decreases after the formation of the multilayer wiring structure is apparently formed as a result of H ₂ O in the interlayer insulating film constituting the multilayer wiring structure being activated by the Pt upper electrode. It is shown that hydrogen radicals penetrated into the ferroelectric capacitor and reduced the ferroelectric film.

[Second Embodiment]
Next, a manufacturing process of the ferroelectric memory according to the second embodiment of the present invention will be described with reference to FIGS.

  Referring to FIG. 6A, an n-type well is formed as an element region 61A in a silicon substrate 61. A first MOS transistor having a polysilicon gate electrode 63A and a polysilicon gate are formed on the element region 61A. A second MOS transistor having an electrode 63B is formed through gate insulating films 62A and 62B, respectively.

The further in the silicon substrate 61, the p in correspondence to respective sidewalls of the gate electrode 63A ^- -type LDD region 61a, and 61b are formed, also in correspondence to respective sidewalls of the gate electrode 13B p ^- -type LDD regions 61c and 61d are formed. Here, since the first and second MOS transistors are formed in common in the element region 61A, the same p ⁻ type diffusion region is shared as the LDD region 61b and the LDD region 61c.

  A silicide layer 64A is formed on the polysilicon gate electrode 63A, and a silicide layer 64B is formed on the polysilicon gate electrode 63B. Further, both side walls of the polysilicon gate electrode 63A and the polysilicon gate are formed. Each side wall insulating film is formed on both side wall surfaces of the electrode 63B.

Further, in the silicon substrate 61, p ⁺ type diffusion regions 61e and 61f are formed outside the respective side wall insulating films of the gate electrode 63A, and each of the side wall insulating films of the gate electrode 63B is formed. On the outside, p ⁺ -type diffusion regions 61g and 61h are formed. However, the diffusion regions 61f and 61g are composed of the same p ⁺ -type diffusion region.

Further, on the silicon substrate 61, the gate electrode 63A is covered including the silicide layer 64A and the sidewall insulating film, and the gate electrode 63B is covered including the silicide layer 64B and the sidewall insulating film. The SiON film 65 is formed to a thickness of 200 nm, for example, and an interlayer insulating film 66 made of SiO ₂ is formed on the SiON film 65 by a plasma CVD method using TEOS as a material to a thickness of 1000 nm, for example. ing. Further, the interlayer insulating film 66 is planarized by CMP, and contact holes 66A, 66B, 66C are exposed in the interlayer insulating film 66 so as to expose the diffusion regions 61e, 61f (and hence the diffusion regions 61g), 61h, respectively. Is formed. Via plugs 67A, 67B made of W (tungsten) are formed in the contact holes 66A, 66B, 66C through adhesion layers 67a, 67b, 67c in which a Ti film having a thickness of 30 nm and a TiN film having a thickness of 20 nm are laminated. , 67C are formed.

Further, in the structure of FIG. 6A, the next interlayer insulating film 68 made of a silicon oxide film is formed on the interlayer insulating film 66 through another SiON film 67 having a thickness of, for example, 130 nm in the same manner as the interlayer insulating film 66. The film is formed to a thickness of, for example, 300 nm by a plasma CVD method using TEOS as a raw material. Here, instead of the SiON film 67, an SiN film or an Al ₂ O ₃ film can be used.

  Next, in the step of FIG. 6B, via holes 68A and 68C exposing the via plugs 67A and 67C are formed in the interlayer insulating film 68, and the via plugs are made of tungsten and are in contact with the via plugs 67A. 69A is formed through an adhesion layer 69a in which the same Ti film and TiN film as the adhesion layer 67a are laminated. A via plug 69C is formed in the via hole 68C to be in contact with the via plug 67C through a contact layer 69c formed by laminating a Ti film and a TiN film similar to the contact layer 67c.

Next, in the step of FIG. 6C, the surface of the interlayer insulating film 68 is treated with NH ₃ plasma, NH groups are bonded to oxygen atoms on the surface of the interlayer insulating film 68, and then the Ti film 70 is sputtered to form the interlayer insulating film 68. For example, a thickness of 20 nm is formed on the insulating film 68 so as to cover the via plugs 69A and 69B under the same conditions as those of the Ti film 42 shown in FIG. By treating the surface of the interlayer insulating film 68 with NH ₃ plasma in this way, the oxygen atoms on the surface of the interlayer insulating film 68 are terminated by NH groups, and are preferentially bonded to Ti atoms to have their orientation. Since there is no restriction, the Ti film 70 has an ideal (002) orientation.

  Further, in FIG. 6C, the Ti film 70 is rapidly heat-treated at a temperature of 650 ° C. in a nitrogen atmosphere to convert it into a (111) -oriented TiN film 70.

  Next, in the step of FIG. 6D, a TiAlN film 71 is formed on the TiN film 70 as an oxygen diffusion barrier under the same conditions as the TiAlN film 43 of FIG. 3A, and in the step of FIG. Similarly to the lower electrode 44 in FIG. 3A, an Ir film having a thickness of 50 to 100 nm, an IrOx film having a thickness of 30 nm, and a Pt film having a thickness of 50 nm are formed on the TiAlN film 71 by sputtering. The lower electrode layer 72 is formed by stacking.

  Next, the structure of FIG. 6E is heat-treated in an Ar atmosphere at a temperature of 650 ° C. or higher for 60 seconds as in the previous embodiment. Subsequently, in the process of FIG. 6F, a PZT coating film is formed on the lower electrode layer 72. First, it is formed by the sol-gel method similarly to the PZT coating film 45a of FIG. Further, by removing the solvent by heat treatment at 240 ° C., the PZT film 73a in the amorphous phase or the microcrystalline state is formed on the lower electrode layer 72 from the PZT coating film in the same manner as the PZT film 45A in FIG. For example, it is formed to a thickness of 120 nm.

  Next, in the process of FIG. 6G, the PZT film 73a in the amorphous phase or microcrystalline state thus obtained is heated at a temperature of 550 ° C. while supplying oxygen gas at 1000 sccm and Ar gas at a flow rate of 1000 sccm. As a result of the heat treatment for 120 seconds, the PZT film 73a is crystallized in the same manner as the PZT film 45B in FIG. 3C and converted into the crystallized PZT film 73.

  As described above, the crystallization heat treatment of the PZT film 73 is performed at a temperature in the vicinity of the crystallization temperature of the PZT, particularly at a temperature at which crystallization from the surface portion of the PZT film does not occur. As a result, as described above with reference to FIG. 4, (111) oriented columnar PZT crystals grow upward from the surface of the lower electrode 72.

In the present invention, the ferroelectric film is not limited to the PZT film, but is a PZT film, a PLZT film, or a BLT ((Bi, La) doped with at least one element selected from La, Ca, Sr and Si. ₄ Ti ₃ O ₁₂ ) film, SBT film, and Bi layered structure, such as (Bi _1-x R _x ) Ti ₃ O ₁₂ (R is a rare earth element, 0 <x <1), SrBi ₂ Ta ₂ O ₉ , SrBi It is also possible to use ₄ Ti ₄ O ₁₅ or the like. These dielectric materials also have a perovskite structure as in PZT, but the optimum crystallization temperature is different, and PZT or PZT to which a small amount of La, Ca, Sr, Si, etc. is added is crystallized at 600 ° C. or lower. On the other hand, BLT is preferably crystallized at 670 ° C. or lower, and SBT is preferably crystallized at 750 ° C. or lower.

  For this reason, in the present invention, the crystallization heat treatment temperature in FIG. 6G is set based on the crystallization temperature of the ferroelectric material as in the crystallization step in FIG. When performing the crystallization heat treatment, the upper limit of the crystallization heat treatment temperature is set within 50 ° C. of the crystallization temperature, and the lower limit is set within 15 ° C. When the crystallization heat treatment is performed under reduced pressure, the upper limit of the crystallization heat treatment temperature is set within 40 ° C. of the crystallization temperature, and the lower limit is set within 25 ° C. If the crystallization heat treatment temperature is too low, the crystallization of the ferroelectric film will not proceed sufficiently, and will cause crystallization from the surface of the ferroelectric film during the oxygen deficiency compensation heat treatment at a higher temperature described below. There is a fear.

  In the step of FIG. 6G, after the crystallization heat treatment step, heat treatment is performed in the same manner as in the step of FIG. 3D in an oxygen atmosphere that is 50 ° C. higher than the crystallization heat treatment temperature, for example, 650 ° C. Oxygen deficiency in the PZT film 73 is compensated. In the illustrated example, this oxygen deficiency compensation is performed in an atmosphere of 100% oxygen, but the present invention is not limited to such a specific case, and in a mixed gas of oxygen and inert gas. It is also possible to perform this oxygen deficiency compensation heat treatment.

  Next, in the step of FIG. 6H, an upper electrode film 74 made of IrOx having a two-layer structure is formed on the PZT film 73 by the sputtering method in the same manner as the upper electrode layer 46 of FIG. 3E of the previous embodiment. 6I, a TiAlN film 75 and a silicon oxide film 76 are formed on the upper electrode film 74 as a hard mask layer by a reactive sputtering method and a plasma CVD method using a TEOS material, respectively.

  Further, in the step of FIG. 6J, the silicon oxide film 76 is patterned to form hard mask patterns 76A and 76B corresponding to desired ferroelectric capacitors C1 and C2.

Further, in the next step of FIG. 6K, using the hard mask patterns 76A and 76B as a mask, the TiAlN film 75, the upper electrode layer 74, the PZT film 73 and the lower electrode layer 72 thereunder are exposed until the TiAlN film 71 is exposed. , HBr, O ₂ , Ar, and C ₄ F ₈ are used for patterning, and under the hard mask pattern 76A, corresponding to the ferroelectric capacitor C1, the lower electrode pattern 72A, the PZT pattern 73A, the upper part The structure in which the electrode pattern 74A and the TiAlN mask pattern 75A are stacked corresponds to the ferroelectric capacitor C2 below the hard mask pattern 76B, and the lower electrode pattern 72B, the PZT pattern 73B, the upper electrode pattern 74B, and the TiAlN mask. Structure with layered pattern 75B It is obtained. Here, the lower electrode pattern 72A, PZT pattern 73A, and upper electrode pattern 74A constitute a ferroelectric capacitor C1, and the lower electrode pattern 72B, PZT pattern 73B, and upper electrode pattern 74B constitute a ferroelectric capacitor C2.

  Next, the hard mask patterns 76A and 76B are removed by dry etching or wet etching in the step of FIG. 6L, and the TiN film on the interlayer insulating film 68 is masked using the ferroelectric capacitors C1 and C2 in the step of FIG. 6M. 70 and the TiAlN film 71 thereon are removed by dry etching.

Further, in the process of FIG. 6N, the interlayer insulating film 68 exposed in the process of FIG. 6M is very thin and has a film thickness so as to continuously cover the side wall surface and the upper surface of the ferroelectric capacitors C1 and C2. An Al ₂ O ₃ film having a thickness of 20 nm or less is formed as a hydrogen barrier film by sputtering or ALD, and then heat treatment is performed at 550 to 750 ° C., for example, 650 ° C. in an oxygen atmosphere in the step of FIG. In the PZT films 73A and 73B in the ferroelectric capacitors C1 and C2, damage caused by the dry etching process of FIG. 6K is recovered.

Further, in the step of FIG. 6P, the next Al ₂ O ₃ film 78 is formed as a hydrogen barrier film to a thickness of, for example, 20 nm by the MOCVD method on the Al ₂ O ₃ film of FIG. 6O. An interlayer insulating film 79 made of a silicon oxide film is formed to a thickness of 1500 nm by plasma CVD using a mixed gas of TEOS, oxygen and helium as a raw material so as to cover the Al ₂ O ₃ hydrogen barrier films 77 and 78 formed. Is done. In the step of FIG. 6Q, the surface of the interlayer insulating film 79 formed in this way is flattened by the CMP method, and then heat-treated in plasma using N ₂ O or nitrogen gas. Remove moisture. 6Q, an Al ₂ O ₃ film 80 is formed as a hydrogen barrier film on the interlayer insulating film 79 to a thickness of 20 to 100 nm by sputtering or MOCVD. In the process of FIG. 6Q, the interlayer insulating film 79 has a film thickness of, for example, 700 nm as a result of the planarization process by the CMP method.

  Next, in the step of FIG. 6R, an interlayer insulating film 81 made of a silicon oxide film is formed on the hydrogen barrier film 80 to a thickness of 300 to 500 nm by a plasma CVD method using a TEOS material, and is flattened by a CMP method. 6S, a via hole 81A exposing the upper electrode 74A of the ferroelectric capacitor C1 and a via hole 81C exposing the upper electrode 74C of the ferroelectric capacitor C2 are formed in the interlayer insulating film 81. The

  Further, in the step of FIG. 6S, heat treatment is performed in an oxidizing atmosphere through the via holes 81A and 81C thus formed, and the PZT films 73A and 73C are compensated for oxygen vacancies caused by the via hole forming step. To do.

  Next, the bottom and inner wall surfaces of the via holes 81A and 81C are respectively covered with barrier metal films 82a and 82c made of a single layer film of TiN, the via hole 81A is filled with a tungsten plug 82A, and the via hole 81C is filled with a tungsten plug 82C. To do.

  Further, after the formation of the tungsten plugs 82A and 82C, a via hole 81B exposing the via plug 67B is formed in the interlayer insulating film 81, and this is filled with the tungsten via plug 82B. The tungsten via plug 82B is accompanied by an adhesion film 82b having a Ti / TiN laminated structure as usual.

  Further, in the step of FIG. 6T, on the interlayer insulating film 81, a wiring pattern 83A made of an AlCu alloy corresponding to the via plug 82A is sandwiched between adhesion films 83a and 83d having a Ti / TiN laminated structure. A wiring pattern 83B made of an AlCu alloy corresponding to the via plug 82B is sandwiched between adhesion films 83b and 83e having a Ti / TiN laminated structure, and a wiring pattern 83C made of an AlCu alloy corresponding to the via plug 82C It is formed so as to be sandwiched between adhesion films 83c and 83f having a Ti / TiN laminated structure.

  Further, a further wiring layer is formed on the structure of FIG. 6T as necessary.

  Since the ferroelectric memory formed in this way is composed of uniform (111) -oriented columnar PZT crystals in the PZT films 73A and 73C constituting the ferroelectric capacitors C1 and C3, As shown in FIGS. 5A and 5B, it has excellent electrical characteristics.

  In FIG. 7, the curve A shows the switching charge amount of the PZT films 73A and 73C in the ferroelectric memory of FIG. 6T, and the curve B shows the crystallization process and the oxygen deficiency compensation process of FIG. In the case of performing in a 100% oxygen atmosphere at a temperature of 0 ° C., and curve C is similar to the curve B, the crystallization step and the oxygen deficiency compensation step of FIG. The amount of switching charge is shown when the PZT film is used in the upper atmosphere and the PZ film is used as the upper electrode.

  Referring to FIG. 7, in the ferroelectric memory according to the present embodiment, the maximum switching charge amount is ensured as compared with the other methods B and C, and the rise with respect to the applied voltage is steep, and the ferroelectric memory It can be seen that the memory can operate at a low voltage.

The results of FIG. 7 show that the PZT films 73A and 73C constituting the ferroelectric capacitors C1 and C3 are formed of uniform (111) -oriented columnar PZT crystals by the method of the present invention. This shows that the formation of PZT crystal grains is suppressed.

[Third Embodiment]
8A to 8C show a part of the manufacturing process of the ferroelectric memory according to the third embodiment of the present invention.

  FIG. 8A is a process subsequent to FIG. 6E in the previous embodiment, and a PZT film 73M is formed on the lower electrode layer 72 by MOCVD.

More specifically, Pb (DPM) 2 is used as a raw material for Pb, Zr (dmhd) ₄ is used as a raw material for Zr, and Ti (O-iOr) ₂ (DPM) ₂ is used as a raw material for Ti, both in a THF solvent. Each liquid raw material thus formed was dissolved in a raw material vaporizer of the MOCVD apparatus together with a THF solvent at a flow rate of 0.474 ml / min, 0.326 ml / min, respectively. Supply is performed at a flow rate of 0.200 ml / min and 0.200 ml / min to form source gases of Pb, Zr and Ti.

  Further, the source gas thus formed is introduced into the MOCVD apparatus, and the PZT film 73M is formed on the lower electrode layer 71 at a substrate temperature of 620 ° C. under a pressure of 665 Pa, for example, with a film thickness of 80 nm. .

  The PZT film 73M formed in this way is inferior in surface morphology, and when the upper electrode is formed as it is, not only the interface characteristics are inferior, but also the process deterioration increases. Therefore, in this embodiment, in the process of FIG. A PZT coating film is formed on the PZT film 73M by the sol-gel method in the same manner as in FIG. 6F, and the PZT film 73a in an amorphous phase or a microcrystalline state is removed by heat-treating the film at, for example, 240 ° C. Form.

  Further, in the step of FIG. 8C, the PZT film 73a is first crystallized in a crystallization heat treatment step at 550 ° C., and then a higher oxidation heat treatment step at 650 ° C. is performed as in the step of FIG. 6G. The defect is compensated, and a PZT film 73 is formed on the PZT film 73M. Here, since the PZT film 73 is formed from a coating film, it has an excellent surface morphology.

  Further, in the step of FIG. 8D, the upper electrode 74 is formed on the PZT film 73, and the steps after FIG. 6I are continued.

According to the present invention, the surface morphology of a PZT film formed by the MOCVD method can be improved, and the yield and reliability of a semiconductor device can be improved.

[Fourth Embodiment]
FIG. 9 shows a configuration of a ferroelectric memory according to the fourth embodiment of the present invention. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  In the embodiment of FIGS. 6A to 6T described above, in the step of FIG. 6B, the via plugs 69A and 69C are formed after the via holes 68a and 68c are filled with a tungsten film, and then an extra layer on the interlayer insulating film 68 is formed. It is formed by removing the tungsten film by the CMP method. However, it is difficult to completely flatten the surfaces of the via plugs 69A and 69B by such a CMP method. In general, a recess whose depth reaches 20 to 50 nm is formed.

  Such a recess greatly affects the crystal orientation of the ferroelectric capacitor formed thereon. Therefore, in the present embodiment, the interlayer insulation is performed after the step of FIG. 6B and before the step of FIG. 6C. A (002) -oriented Ti film is deposited on the film 68 so as to fill the recesses, and is converted into a (111) -oriented TiN film by nitriding, and then the surface is planarized by CMP. ing.

  As a result, in the ferroelectric memory of FIG. 9, the (111) -oriented TiN film 70a is interposed between the interlayer insulating film 68 and the TiN film 70A so as to fill the recess above the via plug 69A. In addition, a (111) -oriented TiN film 70c is interposed between the interlayer insulating film 68 and the TiN film 70C so as to fill the recess above the via plug 69C. Such TiN films 70a and 70c are patterned together with other films constituting the ferroelectric capacitors C1 and C2 in the patterning step of FIG. 6K.

  According to the present invention, even if a recess is formed in the upper part of the via plugs 69A and 69C in the CMP process, the orientation of the ferroelectric films 73A and 73C can be reliably regulated in the (111) direction. It is.

  FIG. 10 shows a configuration of a ferroelectric memory according to a modification of FIG. However, in the figure, the same reference numerals are given to the parts described above, and the description will be omitted.

  Referring to FIG. 10, in this embodiment, when the TiN films 70a and 70c are planarized by CMP, the portions on the interlayer insulating film 68 are removed. As a result, the TiN films 70a and 70c are removed. Remains only in the via holes 68A and 68C.

Others are the same as those in FIG.

[Fifth Embodiment]
FIG. 11 shows the configuration of a ferroelectric memory according to the fifth embodiment of the present invention.

  Referring to FIG. 11, in this embodiment, after forming the interlayer insulating film 79 in the process of FIG. 6Q after the process of FIG. 6P, a via hole exposing the via plug 67B is immediately formed in the interlayer insulating film 79. The via plug 82B is formed by filling it with tungsten.

  Further, after the via plug 82B is formed, an oxygen barrier film such as a SiON film is formed on the interlayer insulating film 79. In this state, the upper electrode 74A of the ferroelectric capacitor C1 and the upper electrode 74A of the ferroelectric capacitor C1 are formed in the interlayer insulating film 79. A contact hole exposing the upper electrode 74C of the ferroelectric capacitor C2 is formed.

  Further, the PZT film 73A in the ferroelectric capacitor C1 and the PZT film 73C in the ferroelectric capacitor C2 are heat-treated in an oxygen atmosphere through the contact holes to compensate for oxygen vacancies, and then the oxygen barrier film is removed. On the interlayer insulating film 79, electrode patterns 83A, 83B, 83C are formed corresponding to the upper electrode 74A, the via plug 82B of the ferroelectric capacitor C1, and the upper electrode 74C of the ferroelectric capacitor C2, respectively. To do.

Even in such a configuration, the PZT films 73A and 73B are formed of (111) -oriented columnar PZT films, and the formation of irregularly oriented PZT particles is suppressed. The same excellent electrical characteristics as described above with reference to FIG.

[Sixth Embodiment]
In each of the above embodiments, a ferroelectric memory having a so-called stack structure in which a ferroelectric capacitor is formed immediately above a memory cell transistor is used. However, as shown in FIG. This is also effective in the production of a body memory.

  Referring to FIG. 9, in the silicon substrate 101, for example, an n-type element region 101A is defined by an element isolation region 101I. On the silicon substrate 101, p-type polysilicon is formed in the element region 101A. A gate electrode 103 is formed with a gate insulating film 102 interposed therebetween.

In the silicon substrate 101, a p − type first diffusion region 101a is formed on the first side of the gate electrode 103 in the element region 101A, and the same p − type first region is formed on the second side. Two diffusion regions 101b are formed. Further, a sidewall insulating film is formed on the gate electrode 103, and p + type diffusion regions 101c and 10d are formed in the silicon substrate 101 on the outside of the sidewall insulating film corresponding to the diffusion regions 101a and 101b, respectively. Has been.

  Further, a SiON film 105 is formed on the silicon substrate 101 so as to cover the gate electrode 104, and an interlayer insulating film 106 is formed on the SiON film 105.

  Further, the interlayer insulating film 106 is covered with another SiON film 107 constituting an oxygen barrier film. On the SiON film 107, the lower electrode 108, the ferroelectric film 109, and the upper part are formed on the element isolation structure 101I. A ferroelectric capacitor C in which the electrodes 110 are stacked is formed.

  Here, the lower electrode 108 is formed by the sputtering method in the same manner as the lower electrode layer 72 described above, and the ferroelectric film 109 is formed by the sol-gel method similarly to the ferroelectric film 73. The upper electrode is formed by a sputtering method in the same manner as the upper electrode layer 74 described above.

The ferroelectric capacitor is covered by the hydrogen barrier film 111 made of Al ₂ O ₃ film, further thereon, the SiON film 107 Another of the Al ₂ O ₃ film 112 formed to cover the can, also hydrogen The barrier film 111 is formed.

  Further, an interlayer insulating film 113 is formed on the hydrogen barrier film 112 so as to cover the ferroelectric capacitor C. In the interlayer insulating film 113, a via hole 113A exposing the upper electrode 110 and the lower electrode 108 is formed. 113B are formed, and after the oxygen deficiency compensation of the ferroelectric film 109 is performed through the via holes 113A and 113B, via plugs 114A and 114B are formed in the via holes 113A and 113B, respectively.

  Further, after the formation of the via plugs 114A and 114B, a tungsten via plug 114C is formed in the via hole 113C exposing the diffusion region 101c.

  Even in such a configuration, the ferroelectric film 109 formed by the sol-gel method is first heat-treated at a temperature close to the crystallization temperature and then heat-treated at a higher temperature in an oxidizing atmosphere. It is composed of (111) -oriented columnar crystals, and the problem described above with reference to FIG. 2 is avoided.

  As mentioned above, although this invention was described about preferable embodiment, this invention is not limited to this specific embodiment, A various deformation | transformation and change are possible within the summary described in the claim.

(Appendix 1) A method of manufacturing a semiconductor device including a ferroelectric film,
Applying a sol-gel solution obtained by dissolving a perovskite ferroelectric material in a solvent on the lower electrode layer to form a coating film of the ferroelectric material;
A film forming step of removing the solvent from the coating film and forming a ferroelectric film made of an amorphous state or a microcrystal on the lower electrode;
The ferroelectric film made of the amorphous state or microcrystal is heat-treated at a first temperature in the vicinity of the crystallization temperature of the ferroelectric material, and is crystallized in accordance with the crystal orientation of the lower electrode layer. Heat treatment process of
A second heat treatment step of heat-treating the crystallized ferroelectric film at a second temperature higher than the first temperature in an oxidizing atmosphere to compensate for oxygen vacancies in the crystallized ferroelectric film. A method of manufacturing a semiconductor device, comprising:

(Appendix 2)
The semiconductor according to claim 1, wherein the first temperature is selected such that crystallization of the ferroelectric film made of the amorphous state or microcrystals occurs only from the interface with the lower electrode. Device manufacturing method.

(Appendix 3)
The method of manufacturing a semiconductor device according to appendix 1 or 2, wherein the second temperature is higher by 50 ° C. than the first temperature.

(Appendix 4)
The first heat treatment step is performed by a rapid heat treatment under normal pressure, and the first temperature does not exceed 50 ° C. with respect to the crystallization temperature of the ferroelectric film, and the crystallization 4. The method of manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the temperature is set in a temperature range in which the temperature does not exceed 15 [deg.] C. and does not decrease.

(Appendix 5)
The first heat treatment step is performed by rapid heat treatment under reduced pressure, and the first temperature does not exceed 40 ° C. with respect to the crystallization temperature of the ferroelectric film, and the crystal 4. The method of manufacturing a semiconductor device according to any one of appendices 1 to 3, wherein the temperature is set in a temperature range in which the temperature does not become lower than 25 ° C. with respect to the annealing temperature.

(Appendix 6)
4. The method of manufacturing a semiconductor device according to appendix 3, wherein the first temperature is set in a temperature range of 480 to 700 ° C.

(Appendix 7)
The method of manufacturing a semiconductor device according to appendix 6, wherein the second temperature is 650 ° C. or higher.

(Appendix 8)
The ferroelectric film is a PZT film, and the first heat treatment is performed in a temperature range of 200 to 550 ° C., and the second heat treatment is performed in a temperature range of 480 to 700 ° C. The manufacturing method of the semiconductor device as described in any one of appendices 1-7.

(Appendix 9)
Any one of Supplementary notes 1 to 5, wherein the lower electrode layer has (111) orientation on a surface thereof, and the ferroelectric film is composed of columnar crystal grains having (111) orientation. A method for manufacturing a semiconductor device according to one item.

(Appendix 10)
A method of manufacturing a semiconductor device including a ferroelectric film,
Forming a first ferroelectric film made of a perovskite ferroelectric material on the lower electrode layer by MOCVD;
Applying a sol-gel solution obtained by dissolving a perovskite ferroelectric material in a solvent on the first ferroelectric film to form a coating film of the ferroelectric material;
A film forming step of removing the solvent from the coating film and forming a second ferroelectric film made of an amorphous state or a microcrystal on the lower electrode;
The second ferroelectric film made of the amorphous state or microcrystal is heat-treated at a first temperature near the crystallization temperature of the ferroelectric material, and crystallized in accordance with the crystal orientation of the lower electrode layer. A first heat treatment step,
The crystallized second ferroelectric film is heat-treated at a second temperature higher than the first temperature in an oxidizing atmosphere to compensate for oxygen vacancies in the crystallized second ferroelectric film. And a second heat treatment step. A method for manufacturing a semiconductor device, comprising:

It is a figure which shows the structure of the ferroelectric memory by the related technique of this invention. (A), (B) is a figure explaining the subject of this invention. (A)-(E) are figures which show the manufacturing process of the ferroelectric capacitor by the 1st Embodiment of this invention. It is a figure which shows the surface state of the ferroelectric film formed at the process of FIG. It is a figure which shows the electrical property of the ferroelectric capacitor formed at the process of FIG. 3 (A)-(E). It is FIG. (1) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (2) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (3) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (4) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (5) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (6) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (7) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (8) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (9) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (10) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (11) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (12) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (13) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (14) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (15) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (16) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (17) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (18) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (19) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is FIG. (20) explaining the manufacturing process of the ferroelectric memory by the 2nd Embodiment of this invention. It is a figure which shows the electrical property of the ferroelectric memory of 2nd Embodiment of this invention. It is FIG. (1) which shows the manufacturing process of the ferroelectric memory by the 3rd Embodiment of this invention. It is FIG. (2) which shows the manufacturing process of the ferroelectric memory by the 3rd Embodiment of this invention. It is FIG. (3) which shows the manufacturing process of the ferroelectric memory by the 3rd Embodiment of this invention. It is FIG. (4) which shows the manufacturing process of the ferroelectric memory by the 3rd Embodiment of this invention. It is a figure which shows the structure of the ferroelectric memory by the 4th Embodiment of this invention. It is a figure which shows the structure of the ferroelectric memory by the modification of 4th Embodiment. It is a figure which shows the structure of the ferroelectric memory by the 5th Embodiment of this invention. It is a figure which shows the structure of the ferroelectric memory by the 6th Embodiment of this invention.

Explanation of symbols

41 Insulating layer 42, 70, 70A, 70C Ti film 43, 71, 71A, 71C75 TiAlN film 44, 72, 72A, 72C, 108 Lower electrode 45a PZT coating film 45A, 73a Amorphous PZT film 45B, 73, 73A, 73C, 109 Crystallized PZT film 46, 74, 74A, 74C. 110 Upper electrode 61, 101 Substrate 61A, 101A Element region 61I, 101I Element isolation structure 61a-61f, 101a-101d Diffusion region 62A, 62B, 102 Gate insulating film 63A, 63B, 103 Gate electrode 64A, 64B, 104 Gate silicide layer 65, 67, 107 SiON film 66, 68, 79, 81, 106, 113 Interlayer insulating film 66A, 66B, 66C, 68A, 68C, 81A, 81B, 81C Via hole 67A-67C, 69A, 69C, 82A-82C, 114A -114C Via plug 67a, 67b, 67c, 69a, 69c, 82a, 82b, 82c Adhesion film 76 Hard mask film 76A, 76B Hard mask pattern 77, 78, 80, 111, 112 Al ₂ O ₃ hydrogen barrier film 83A, 83B, 8 3C wiring pattern

Claims (5)

A method of manufacturing a semiconductor device including a ferroelectric film,
Applying a sol-gel solution obtained by dissolving a perovskite ferroelectric material in a solvent on the lower electrode layer to form a coating film of the ferroelectric material;
A film forming step of removing the solvent from the coating film and forming a ferroelectric film made of an amorphous state or a microcrystal on the lower electrode;
The ferroelectric film made of the amorphous state or microcrystal is heat-treated at a first temperature in the vicinity of the crystallization temperature of the ferroelectric material, and is crystallized in accordance with the crystal orientation of the lower electrode layer. Heat treatment process of
A second heat treatment step of heat-treating the crystallized ferroelectric film at a second temperature higher than the first temperature in an oxidizing atmosphere to compensate for oxygen vacancies in the crystallized ferroelectric film. A method of manufacturing a semiconductor device, comprising:   2. The first temperature according to claim 1, wherein the first temperature is selected such that crystallization of the ferroelectric film made of the amorphous state or microcrystals occurs only from an interface with the lower electrode. A method for manufacturing a semiconductor device.   The method of manufacturing a semiconductor device according to claim 1, wherein the second temperature is 50 ° C. or more higher than the first temperature.   The first heat treatment step is performed by a rapid heat treatment under normal pressure, and the first temperature does not exceed 50 ° C. with respect to the crystallization temperature of the ferroelectric film, and the crystallization 4. The method for manufacturing a semiconductor device according to claim 1, wherein the temperature is set in a temperature range that does not become lower than 15 [deg.] C. with respect to the temperature. A method of manufacturing a semiconductor device including a ferroelectric film,
Forming a first ferroelectric film made of a perovskite ferroelectric material on the lower electrode layer by MOCVD;
Applying a sol-gel solution obtained by dissolving a perovskite ferroelectric material in a solvent on the first ferroelectric film to form a coating film of the ferroelectric material;
A film forming step of removing the solvent from the coating film and forming a second ferroelectric film made of an amorphous state or a microcrystal on the lower electrode;
The second ferroelectric film made of the amorphous state or microcrystal is heat-treated at a first temperature near the crystallization temperature of the ferroelectric material, and crystallized in accordance with the crystal orientation of the lower electrode layer. A first heat treatment step,
The crystallized second ferroelectric film is heat-treated at a second temperature higher than the first temperature in an oxidizing atmosphere to compensate for oxygen vacancies in the crystallized second ferroelectric film. And a second heat treatment step. A method for manufacturing a semiconductor device, comprising: