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JP2008078164A - Semiconductor device and manufacturing method thereof - Google Patents

Semiconductor device and manufacturing method thereof Download PDF

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JP2008078164A
JP2008078164A JP2006251979A JP2006251979A JP2008078164A JP 2008078164 A JP2008078164 A JP 2008078164A JP 2006251979 A JP2006251979 A JP 2006251979A JP 2006251979 A JP2006251979 A JP 2006251979A JP 2008078164 A JP2008078164 A JP 2008078164A
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wiring board
wiring
semiconductor element
semiconductor device
dimensional
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Tomohiro Tamaoki
友博 玉置
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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    • H—ELECTRICITY
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    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/42—Wire connectors; Manufacturing methods related thereto
    • H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
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    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
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    • H01L2224/32145—Disposition the layer connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
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    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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    • H01L2224/732—Location after the connecting process
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    • H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
    • H01L2224/85909—Post-treatment of the connector or wire bonding area
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  • Engineering & Computer Science (AREA)
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Abstract

【課題】半導体パッケージ内の複数の半導体素子の結線数を増やし、なおかつ電気特性と熱伝導性を向上させ、さらに基板を連結部で折り曲げることによる、金ワイヤの接合部への応力を緩和するものである。
【解決手段】積層した第1の半導体素子１２および第２の半導体素子１３と、立体配線基板の各配線基板９を折り曲げることによって垂直に連結した複数の配線基板９とを金ワイヤ６で直接結線する。所定の配線基板９に金属板またはセラミック板からなる板材１７を張り合わせて高い電気特性と高い放熱性を得る。さらに、金ワイヤ６同士が近接せず電気的相互干渉の影響を低下させる。また、金ワイヤ６の接合部１５へ絶縁性樹脂１４を塗布し、折り曲げによる応力を緩和する。
【選択図】図１１An object of the present invention is to increase the number of connections of a plurality of semiconductor elements in a semiconductor package, improve electrical characteristics and thermal conductivity, and further relieve stress on the joint portion of the gold wire by bending the substrate at the connecting portion. It is.
The first semiconductor element 12 and the second semiconductor element 13 that are stacked and a plurality of wiring boards 9 that are vertically connected by bending each wiring board 9 of a three-dimensional wiring board are directly connected by gold wires 6. To do. A plate material 17 made of a metal plate or a ceramic plate is bonded to a predetermined wiring board 9 to obtain high electrical characteristics and high heat dissipation. Furthermore, the gold wires 6 are not close to each other, and the influence of electrical mutual interference is reduced. Further, the insulating resin 14 is applied to the joint 15 of the gold wire 6 to relieve the stress caused by bending.
[Selection] Figure 11

Description

本発明は半導体装置とその製造方法に関し、複数の半導体素子をワイヤボンディングで接続して３次元的に実装する半導体パッケージ技術に係るものである。   The present invention relates to a semiconductor device and a method for manufacturing the same, and relates to a semiconductor package technology in which a plurality of semiconductor elements are connected by wire bonding and three-dimensionally mounted.

従来、複数の半導体素子を三次元的に実装する半導体パッケージ（以下においては３次元半導体パッケージと呼称する）の製造方法としては、例えば図１２から図１５に示すものがある。図１２（ａ）は従来の３次元半導体パッケージの製造に用いる基板の平面図、１２（ｂ）は同基板の側面図である。図１３（ａ）は半導体素子を搭載した従来の基板の平面図、図１３（ｂ）は同基板の側面図である。図１４（ａ）は従来の３次元半導体パッケージの組み立て工程を示す側面図、図１４（ｂ）は同３次元半導体パッケージの封止樹脂注入工程を示す側面図である。図１５（ａ）は従来の３次元半導体パッケージの側面図、図１５（ｂ）は同３次元半導体パッケージの斜視図である。   2. Description of the Related Art Conventionally, as a method for manufacturing a semiconductor package in which a plurality of semiconductor elements are three-dimensionally mounted (hereinafter referred to as a three-dimensional semiconductor package), for example, there are those shown in FIGS. FIG. 12A is a plan view of a substrate used for manufacturing a conventional three-dimensional semiconductor package, and FIG. 12B is a side view of the substrate. FIG. 13A is a plan view of a conventional substrate on which a semiconductor element is mounted, and FIG. 13B is a side view of the substrate. FIG. 14A is a side view showing the assembly process of the conventional three-dimensional semiconductor package, and FIG. 14B is a side view showing the sealing resin injection process of the three-dimensional semiconductor package. FIG. 15A is a side view of a conventional three-dimensional semiconductor package, and FIG. 15B is a perspective view of the three-dimensional semiconductor package.

図１２（ａ）および図１２（ｂ）に示すように、３次元半導体パッケージの製造に用いる基板は、ボンディングパッド１を形成した複数の成形用基板２を所定形状に配列してなり、各成形用基板２の相互間は屈曲できる程度の柔軟性を有する部材によって連結している。ボンディングパッド１と成形用基板２はその相互間が容易に剥離するように材料を設定している。成形用基板２の１つには封止樹脂注入孔３を設けている。   As shown in FIGS. 12A and 12B, a substrate used for manufacturing a three-dimensional semiconductor package is formed by arranging a plurality of molding substrates 2 on which bonding pads 1 are formed in a predetermined shape. The substrates 2 are connected to each other by a member having flexibility that can be bent. The material is set so that the bonding pad 1 and the molding substrate 2 can be easily separated from each other. One of the molding substrates 2 is provided with a sealing resin injection hole 3.

図１３（ａ）および図１３（ｂ）に示すように、所定の成形用基板２の上にそれぞれ半導体素子４を配置し、半導体素子４のパッド５と成形用基板２のボンディングパッド１とを金ワイヤ６で接続する。   As shown in FIGS. 13 (a) and 13 (b), the semiconductor element 4 is arranged on a predetermined molding substrate 2, and the pad 5 of the semiconductor element 4 and the bonding pad 1 of the molding substrate 2 are connected. Connect with gold wire 6.

この接続には、半導体素子４のパッド５と当該半導体素子４を配置した成形用基板２のボンディングパッド１とを接続するものと、半導体素子４のパッド５と当該半導体素子４を配置した成形用基板２に隣接する成形用基板２のボンディングパッド１とを接続するものがある。   For this connection, the pad 5 of the semiconductor element 4 and the bonding pad 1 of the molding substrate 2 on which the semiconductor element 4 is arranged are connected, and the molding 5 in which the pad 5 of the semiconductor element 4 and the semiconductor element 4 are arranged. There is one that connects the bonding pad 1 of the molding substrate 2 adjacent to the substrate 2.

図１４（ａ）に示すように、隣接する配線基板２を接続部で屈曲させて、全体として立方体になるように組み立てる。図１４（ｂ）に示すように、立法体に組み立てた複数の成形用基板２で囲んだ内部空間に封止樹脂注入孔３から封止樹脂８を注入し、複数の成形用基板２で囲まれた内部空間に封止樹脂８を充填して熱硬化させる。   As shown in FIG. 14A, the adjacent wiring boards 2 are bent at the connecting portion and assembled so as to form a cube as a whole. As shown in FIG. 14 (b), the sealing resin 8 is injected from the sealing resin injection hole 3 into the internal space surrounded by the plurality of molding substrates 2 assembled in a legislature and surrounded by the plurality of molding substrates 2. The sealed internal space 8 is filled with the sealing resin 8 and thermally cured.

図１５（ａ）および図１５（ｂ）に示すように、封止樹脂８が硬化した後に、全ての成形用基板２を除去することで、半導体素子４と金ワイヤ６とボンディングパッド１だけを封止した半導体パッケージが完成する。   As shown in FIGS. 15A and 15B, after the sealing resin 8 is cured, all the molding substrate 2 is removed, so that only the semiconductor element 4, the gold wire 6 and the bonding pad 1 are removed. A sealed semiconductor package is completed.

前述したように、ボンディングパッド１と成形用基板２は容易に剥離できるように予め選定した材料からなるので、成形用基板２を除去する際には、ボンディングパッド１と金ワイヤ６が破断することなくボンディングパッド１が成形用基板２から容易に剥離し、ボンディングパッド１は封止樹脂８の内部に残って３次元半導体パッケージの外部端子として機能する。この様な従来の３次元半導体パッケージは、例えば、特許文献１に記載されている。
特開２００１−３０８１１９ As described above, since the bonding pad 1 and the molding substrate 2 are made of a material selected in advance so that they can be easily separated, the bonding pad 1 and the gold wire 6 are broken when the molding substrate 2 is removed. The bonding pad 1 is easily peeled off from the molding substrate 2, and the bonding pad 1 remains inside the sealing resin 8 and functions as an external terminal of the three-dimensional semiconductor package. Such a conventional three-dimensional semiconductor package is described in Patent Document 1, for example.
JP 2001-308119 A

しかしながら、上記の３次元半導体パッケージの構造では、複数の半導体素子の各パッドに対して金ワイヤで結線したボンディングパッドのみが外部端子として機能するために、信号電極の必要数の増加に対して対応できないという問題があった。   However, in the structure of the above three-dimensional semiconductor package, only the bonding pads connected to the pads of the plurality of semiconductor elements with gold wires function as external terminals. There was a problem that I could not.

また、封止樹脂が複数の半導体素子を内包するが、各半導体素子の発熱に対して、その放熱経路は主に封止樹脂層を介した空気への熱伝導だけであり、熱伝導性が低いという問題があった。   In addition, the sealing resin contains a plurality of semiconductor elements, but for the heat generation of each semiconductor element, the heat dissipation path is mainly the heat conduction to the air through the sealing resin layer, and the heat conductivity is There was a problem of being low.

また、各成形用基板を連結部で折り曲げることにより、金ワイヤの接合部に応力が発生することも課題であった。
本発明は上記の従来の問題点を解決した半導体装置とその製造方法を提供するものであり、３次元半導体パッケージ内の結線数（回路数）を増加させることで信号電極の必要数の増加に対応し、電気特性を向上させるとともに、放熱性も向上させ、さらに金ワイヤの接合部に生じる応力を緩和することを目的とする。 Another problem is that stress is generated at the joint portion of the gold wire by bending each molding substrate at the connecting portion.
The present invention provides a semiconductor device that solves the above-described conventional problems and a method for manufacturing the same. By increasing the number of connections (number of circuits) in a three-dimensional semiconductor package, the required number of signal electrodes is increased. Correspondingly, an object is to improve electrical characteristics, improve heat dissipation, and further relieve stress generated in the joint portion of the gold wire.

上記の課題を解決するために、本発明の半導体装置は、複数の配線基板を相互に折り曲げ自在に連結してなり、内部に底面と側面を有する容器形状に組み立てた立体配線基板と、前記底面をなす配線基板の主面に配置した半導体素子と、前記半導体素子のパッドと前記底面および前記側面をなす配線基板のボンディングパッドとを結線するワイヤと、前記底面と前記側面に囲まれた内部空間に充填して硬化させた封止樹脂とを備えることを特徴とする。   In order to solve the above-described problems, a semiconductor device according to the present invention includes a three-dimensional wiring board in which a plurality of wiring boards are connected to each other so as to be bendable and assembled in a container shape having a bottom face and a side face inside, and the bottom face. A semiconductor element disposed on a main surface of the wiring board, a wire for connecting the pad of the semiconductor element to the bonding pad of the wiring board that forms the bottom surface and the side surface, and an internal space surrounded by the bottom surface and the side surface And a sealing resin filled and cured.

この構成により、１つの半導体素子を複数の配線基板に金ワイヤで直接結線することができる。このため、高密度な半導体素子の集積による信号電極の必要数や結線数の増加に、対応できるという効果を奏するものである。   With this configuration, one semiconductor element can be directly connected to a plurality of wiring boards with gold wires. For this reason, there is an effect that it is possible to cope with an increase in the required number of signal electrodes and the number of connections due to the integration of high-density semiconductor elements.

また、前記底面と前記側面との相互間に形成する内角が垂直または鈍角をなすことを特徴とする。
この構成により、底面をなす配線基板のボンディングパッドと側面をなす配線基板のボンディングパッドとが立体的な位置関係に配置される。よって、半導体素子のパッドと底面をなす配線基板のボンディングパッドとを結線するワイヤおよび半導体素子のパッドと側面をなす配線基板のボンディングパッドとを結線するワイヤは、その相互間に十分な距離があり、信号の高速化により生じる電気的相互干渉の影響を低下させることができる。特に複数の半導体素子を積層する構造においては有効な構造である。 The inner angle formed between the bottom surface and the side surface is vertical or obtuse.
With this configuration, the bonding pads of the wiring board forming the bottom surface and the bonding pads of the wiring board forming the side surface are arranged in a three-dimensional positional relationship. Therefore, the wire that connects the pad of the semiconductor element and the bonding pad of the wiring board that forms the bottom surface and the wire that connects the pad of the semiconductor element and the bonding pad of the wiring board that forms the side surface have a sufficient distance between them. , It is possible to reduce the influence of electrical mutual interference caused by signal speeding up. In particular, this structure is effective in a structure in which a plurality of semiconductor elements are stacked.

また、前記パッドと前記ワイヤの接合部、および前記ボンディングパッドと前記ワイヤの接合部を被覆して硬化した絶縁性樹脂を備えることを特徴とする。
この構成により、隣接し合う配線基板を連結部で相互に折り曲げるときに、接続部に発生する応力を緩和させることができる。 In addition, an insulating resin that covers and hardens the bonding portion between the pad and the wire and the bonding portion between the bonding pad and the wire is provided.
With this configuration, it is possible to relieve the stress generated in the connection portion when the adjacent wiring boards are bent at the connection portion.

また、複数の配線基板の表面を被覆するとともに前記表面に接着した柔軟シートを備え、前記柔軟シートが配線基板の相互間を柔軟に折り曲げ可能に連結する連結部材をなすことを特徴とする。   In addition, a flexible sheet that covers the surfaces of a plurality of wiring boards and is adhered to the surfaces is provided, and the flexible sheets form a connecting member that flexibly connects the wiring boards together.

この構成により、前記柔軟シートが連結部材をなすことで配線基板の相互間を柔軟に折り曲げ可能に連結する構成が容易に実現できる。この柔軟シートには配線がなくとも良く、隣接し合う配線基板間を相互にワイヤで接続することで配線基板間の電気的な接続が実現できる。このため、連結部材としてフレキシブル配線基板を使用する場合よりも低コストで複数の配線基板の連結が可能となる。   With this configuration, the configuration in which the flexible sheets are connected to each other so that the wiring boards can be bent flexibly can be easily realized. The flexible sheet does not need to have wiring, and electrical connection between wiring boards can be realized by connecting adjacent wiring boards with wires. For this reason, it is possible to connect a plurality of wiring boards at a lower cost than when a flexible wiring board is used as the connecting member.

また、前記柔軟シートがフレキシブル配線基板であり、前記フレキシブル配線基板と前記配線基板が内部配線において相互に接続していることを特徴とする。
この構成により、半導体素子のパッドと各配線基板のボンディングパッドとを接続するワイヤの結線に加えて、フレキシブル配線基板により配線基板の相互間を電気的に接続することができる。よって、高密度な半導体素子の集積に起因して信号電極の必要数や結線数が増加しても、十分に対応できる。 The flexible sheet is a flexible wiring board, and the flexible wiring board and the wiring board are connected to each other in internal wiring.
With this configuration, in addition to the wire connection for connecting the pad of the semiconductor element and the bonding pad of each wiring board, the wiring boards can be electrically connected to each other by the flexible wiring board. Therefore, even if the required number of signal electrodes and the number of connections increase due to the integration of high-density semiconductor elements, it is possible to cope with it sufficiently.

また、隣接し合う前記配線基板の双方の前記ボンディングパッドを結線するワイヤを備え、隣接し合う前記配線基板が相互に前記ワイヤで電気的に接続していることを特徴とする。   In addition, a wire for connecting the bonding pads of both of the adjacent wiring boards is provided, and the adjacent wiring boards are electrically connected to each other by the wires.

この構成により、配線基板の相互間を電気的に接続する結線がフレキシブル配線基板以外の手段であるワイヤによっても実現することができ、配線基板の相互間における結線を増やすことができる。   With this configuration, the connection for electrically connecting the wiring boards can be realized by a wire that is a means other than the flexible wiring board, and the number of connections between the wiring boards can be increased.

また、前記立体配線基板の側面をなす少なくとも１枚の前記配線基板の裏面に金属板またはセラミック板からなる板材を貼り合わせたことを特徴とする。
この構成により、半導体素子の発熱に対して高い放熱性をもつことができる。 In addition, a plate material made of a metal plate or a ceramic plate is bonded to the back surface of at least one of the wiring substrates forming the side surface of the three-dimensional wiring substrate.
With this configuration, it is possible to have a high heat dissipation property against the heat generated by the semiconductor element.

また、前記配線基板が裏面に前記板材と電気的に接続するボンディングパッドを有することを特徴とする。
この構成により、金属板またはセラミック板からなる板材が配線基板のグラウンドのボンディングパッドと接続した場合に、板材がグラウンドとなって半導体パッケージの電気特性の向上や、他の実装部品との電気的相互干渉を低減させる効果を奏する。 Further, the wiring board has a bonding pad on the back surface that is electrically connected to the plate material.
With this configuration, when a plate material made of a metal plate or a ceramic plate is connected to the bonding pad on the ground of the wiring board, the plate material becomes the ground, improving the electrical characteristics of the semiconductor package, and electrically connecting with other mounting components. There is an effect of reducing interference.

本発明の半導体装置の製造方法は、容器形状に組み立て可能な立体配線基板が複数の配線基板を相互に折り曲げ自在に連結してなり、前記容器形状の底面をなす前記配線基板の主面に半導体素子を実装する工程と、前記容器形状の底面および側面をなす配線基板のボンディングパッドと前記半導体素子のパッドとをワイヤで結線する工程と、隣接する前記配線基板を連結部で相互に折り曲げて前記立体配線基板を前記容器形状に組み立てる工程と、前記容器形状をなす前記立体配線基板の底面と側面に囲まれた内部空間に封止樹脂を充填して硬化させる工程とを含むことを特徴とする。   According to the method of manufacturing a semiconductor device of the present invention, a three-dimensional wiring board that can be assembled into a container shape is formed by connecting a plurality of wiring boards so that they can be bent to each other, and a semiconductor is formed on the main surface of the wiring board that forms the bottom surface of the container shape. A step of mounting an element, a step of connecting the bonding pad of the wiring board forming the bottom and side surfaces of the container shape and the pad of the semiconductor element with a wire, and bending the adjacent wiring boards to each other at a connecting portion. And a step of assembling the three-dimensional wiring board into the container shape, and a step of filling and hardening the sealing resin in the inner space surrounded by the bottom and side surfaces of the three-dimensional wiring board having the container shape. .

また、隣接する前記配線基板を前記連結部で折り曲げることにより、前記ワイヤで接続した前記半導体素子の前記パッドと前記配線基板の前記ボンディングパッドとを、その相互間に形成する内角が垂直または鈍角をなす位置関係に配置する工程を含むことを特徴とする。   Further, by bending the adjacent wiring board at the connecting portion, the inner angle between the pads of the semiconductor element and the bonding pads of the wiring board connected by the wire is vertical or obtuse. Including a step of arranging in a positional relationship.

また、前記パッドと前記ワイヤの接合部、および前記ボンディングパッドと前記ワイヤの接合部を絶縁性樹脂で被覆して硬化させる工程を含み、前記配線基板を前記連結部で折り曲げるときに前記接合部に発生する応力を緩和することを特徴とする。   And a step of covering the bonding portion between the pad and the wire and the bonding portion between the bonding pad and the wire with an insulating resin and curing the bonding substrate when the wiring board is bent at the connecting portion. It is characterized by relieving the generated stress.

本発明では、１つの半導体素子と複数の配線基板とを金ワイヤで直接結線することができる。そのため、高密度な半導体素子の集積による信号電極の必要数や結線数の増加に対応できるという効果を奏する。複数の配線基板に金属板またはセラミック板を張り合わせて金属板またはセラミック板に囲まれた中に半導体素子を内包することで、半導体素子の発熱に対して高い放熱性の効果を奏する。さらに、金属板またはセラミック板を配線基板のグラウンドに結線することで半導体パッケージの電気特性の向上や、他の実装部品との電気的相互干渉を低減する効果も奏する。複数の半導体素子を垂直方向に積層したスタックパッケージとした場合には、上下の半導体素子に結線する金ワイヤ同士が近接しない構成となる。そのため、信号の高速化によって生じる電気的相互干渉の影響が低下するという効果も奏する。   In the present invention, one semiconductor element and a plurality of wiring boards can be directly connected with gold wires. Therefore, there is an effect that it is possible to cope with an increase in the required number of signal electrodes and the number of connections due to the integration of high-density semiconductor elements. By attaching a metal plate or a ceramic plate to a plurality of wiring boards and enclosing the semiconductor element in a space surrounded by the metal plate or the ceramic plate, a high heat dissipation effect is exerted against the heat generated by the semiconductor element. Furthermore, by connecting a metal plate or a ceramic plate to the ground of the wiring board, the electrical characteristics of the semiconductor package can be improved, and electrical interference with other mounting parts can be reduced. In the case of a stack package in which a plurality of semiconductor elements are stacked in the vertical direction, the gold wires connected to the upper and lower semiconductor elements are not adjacent to each other. Therefore, there is also an effect that the influence of electrical mutual interference caused by signal speeding up is reduced.

（実施例１）
以下、本発明の実施例１における半導体パッケージについて図面を参照しながら説明する。図１は本発明の実施例１における３次元半導体パッケージの断面図を示す。図２（ａ）は同実施例１における立体配線基板の平面図、図２（ｂ）は同立体配線基板の側面図である。図３（ａ）は同実施例１における半導体素子を搭載した立体配線基板を示す平面図、図３（ｂ）同立体配線基板の側面図である。図４（ａ）は同実施例１における立体配線基板の折り曲げ工程の途中を示す側面図、図４（ｂ）は同立体配線基板の折り曲げ工程の完了を示す側面図である。図５は同実施例１における立体配線基板に封止樹脂をモールドした状態を示す断面図である。図６は同実施例１における立体配線基板にはんだボールを搭載した状態を示す断面図である。 (Example 1)
Hereinafter, a semiconductor package in Example 1 of the present invention will be described with reference to the drawings. FIG. 1 shows a cross-sectional view of a three-dimensional semiconductor package in Example 1 of the present invention. 2A is a plan view of the three-dimensional wiring board in the first embodiment, and FIG. 2B is a side view of the three-dimensional wiring board. FIG. 3A is a plan view showing a three-dimensional wiring board on which the semiconductor element in Example 1 is mounted, and FIG. 3B is a side view of the three-dimensional wiring board. 4A is a side view showing the middle of the bending process of the three-dimensional wiring board in the first embodiment, and FIG. 4B is a side view showing the completion of the bending process of the three-dimensional wiring board. FIG. 5 is a cross-sectional view showing a state in which a sealing resin is molded on the three-dimensional wiring board in the first embodiment. FIG. 6 is a cross-sectional view showing a state in which solder balls are mounted on the three-dimensional wiring board in the first embodiment.

図２（ａ）、（ｂ）に示すように、立体配線基板Ｓはベース層をなす複数の配線基板９を所定形状に配列し、表層をなすフレキシブル配線基板１０で複数の配線基板９を被覆しており、各配線基板９の相互間がフレキシブル配線基板１０を連結部材として連結されている。   As shown in FIGS. 2A and 2B, the three-dimensional wiring board S has a plurality of wiring boards 9 forming a base layer arranged in a predetermined shape, and the plurality of wiring boards 9 covered with a flexible wiring board 10 forming a surface layer. The wiring boards 9 are connected to each other using the flexible wiring board 10 as a connecting member.

立体配線基板Ｓは各配線基板９の相対向する辺間が連結部７をなし、連結部７において各配線基板９の間が柔軟に折り曲げ可能である。各配線基板９はフレキシブル配線基板１０と電気的に接続し、複数の配線基板９はフレキシブル配線基板１０を介して相互に電気的に接続している。   The three-dimensional wiring board S has a connecting portion 7 between opposite sides of each wiring substrate 9, and the wiring substrate 9 can be flexibly bent at the connecting portion 7. Each wiring board 9 is electrically connected to the flexible wiring board 10, and the plurality of wiring boards 9 are electrically connected to each other via the flexible wiring board 10.

フレキシブル配線基板１０の絶縁材料は屈曲性の高いポリイミド、ガラスエポキシや不織布などを用いる。不織布はガラス繊維、合成繊維などにエポキシ樹脂などを浸透させて作ったものである。また配線材は銅などである。   As the insulating material of the flexible wiring board 10, highly flexible polyimide, glass epoxy, nonwoven fabric, or the like is used. Nonwoven fabric is made by infiltrating glass fiber, synthetic fiber, etc. with epoxy resin. The wiring material is copper or the like.

各配線基板９はフレキシブル配線基板１０の表面にボンディングパッド１を形成しており、銅からなるボンディングパッド１の表面には金、ニッケルめっきなどを施している。
図３（ａ）、（ｂ）に示すように、フレキシブル配線基板１０を介した配線基板９の主面１１の上に第１の半導体素子１２と第２の半導体素子１３を積層する。立体配線基板Ｓと第１の半導体素子１２と第２の半導体素子１３は、その接触面において絶縁性接着剤で接着する。 Each wiring board 9 has a bonding pad 1 formed on the surface of the flexible wiring board 10, and the surface of the bonding pad 1 made of copper is plated with gold, nickel, or the like.
As shown in FIGS. 3A and 3B, the first semiconductor element 12 and the second semiconductor element 13 are stacked on the main surface 11 of the wiring board 9 with the flexible wiring board 10 interposed therebetween. The three-dimensional wiring board S, the first semiconductor element 12 and the second semiconductor element 13 are bonded to each other at the contact surface with an insulating adhesive.

第１の半導体素子１２と第２の半導体素子１３はパッド５を上に向けた状態で搭載する。第１の半導体素子１２および第２の半導体素子１３のパッド５はアルミからなる。第２の半導体素子１３はその形状を第１の半導体素子１２よりも小さく設定することで、第１の半導体素子１２のパッド５を露出させてワイヤボンディングを可能にする。   The first semiconductor element 12 and the second semiconductor element 13 are mounted with the pads 5 facing upward. The pads 5 of the first semiconductor element 12 and the second semiconductor element 13 are made of aluminum. By setting the shape of the second semiconductor element 13 to be smaller than that of the first semiconductor element 12, the pads 5 of the first semiconductor element 12 are exposed to enable wire bonding.

第１の半導体素子１２のパッド５は第１の半導体素子１２を搭載した配線基板９のボンディングパッド１と金ワイヤ６で接続する。第２の半導体素子１３のパッド５は第２の半導体素子１３を搭載した配線基板９と連結部７を介して隣接する配線基板９のボンディングパッド１と金ワイヤ６で接続する。   The pad 5 of the first semiconductor element 12 is connected to the bonding pad 1 of the wiring board 9 on which the first semiconductor element 12 is mounted by the gold wire 6. The pad 5 of the second semiconductor element 13 is connected to the wiring board 9 on which the second semiconductor element 13 is mounted via the connecting portion 7 and the bonding pad 1 of the adjacent wiring board 9 by the gold wire 6.

このとき、第１の半導体素子１２および第２の半導体素子１３を搭載した配線基板９のボンディングパッド１と、この配線基板９と連結部７を介して隣接する配線基板９のボンディングパッド１とを金ワイヤ６で接続してもよい。これにより、隣接する配線基板９どうしの結線数を増加させる効果がある。   At this time, the bonding pad 1 of the wiring board 9 on which the first semiconductor element 12 and the second semiconductor element 13 are mounted, and the bonding pad 1 of the wiring board 9 adjacent to the wiring board 9 through the connecting portion 7 are connected. A gold wire 6 may be used for connection. This has the effect of increasing the number of connections between adjacent wiring boards 9.

第２の半導体素子１３のパッド５と金ワイヤ６との接合部１４、および配線基板９のボンディングパッド１と金ワイヤ６との接合部１４に対して絶縁性樹脂１５を被覆して硬化させる。これは、配線基板９を次工程において連結部７で折り曲げるときに接合部１４に生じる応力を緩和するために行う。絶縁性樹脂１５の硬化は熱硬貨、あるいは紫外線などの光硬化により行う。   An insulating resin 15 is coated and cured on the bonding portion 14 between the pad 5 and the gold wire 6 of the second semiconductor element 13 and the bonding portion 14 between the bonding pad 1 and the gold wire 6 of the wiring substrate 9. This is performed in order to relieve stress generated in the joint portion 14 when the wiring board 9 is bent at the connecting portion 7 in the next step. Curing of the insulating resin 15 is performed by photocuring such as heat coins or ultraviolet rays.

次に、図４（ａ）に示すように、第１の半導体素子１２と第２の半導体素子１３を搭載した配線基板９と周囲の隣接する配線基板９とを連結部７で折り曲げる。この際に、複数の配線基板９にわたって被覆したフレキシブル配線基板１０が連結部材をなすことで、立体配線基板Ｓは連結部７において各配線基板９を柔軟に折り曲げることができる。   Next, as shown in FIG. 4A, the wiring board 9 on which the first semiconductor element 12 and the second semiconductor element 13 are mounted and the adjacent wiring board 9 in the periphery are bent at the connecting portion 7. At this time, the flexible wiring board 10 covered over the plurality of wiring boards 9 serves as a connecting member, so that the three-dimensional wiring board S can bend each wiring board 9 flexibly at the connecting portion 7.

図４（ｂ）に示すように、第１の半導体素子１２と第２の半導体素子１３を搭載した配線基板９と周囲の隣接する配線基板９とはその相互間に形成する内角が垂直または鈍角をなす位置関係に配置することで、複数の配線基板９に囲まれた内部空間を形成するとともに、配線基板９のボンディングパッド１の位置関係を所定状態に設定する。   As shown in FIG. 4B, the internal angle formed between the wiring substrate 9 on which the first semiconductor element 12 and the second semiconductor element 13 are mounted and the adjacent wiring substrate 9 in the periphery is vertical or obtuse. The internal space surrounded by the plurality of wiring boards 9 is formed, and the positional relation of the bonding pads 1 of the wiring board 9 is set to a predetermined state.

この際に、第２の半導体素子１３のパッド５と金ワイヤ６との接合部１４、配線基板９上のボンディングパッド１と金ワイヤ６との接合部１４に対しては絶縁性樹脂１５を被覆して接合強度を向上しているので、配線基板９を連結部７で折り曲げても接合部１４への応力を緩和させる効果がある。   At this time, the bonding portion 14 between the pad 5 of the second semiconductor element 13 and the gold wire 6 and the bonding portion 14 between the bonding pad 1 on the wiring substrate 9 and the gold wire 6 are covered with the insulating resin 15. Thus, since the bonding strength is improved, even if the wiring board 9 is bent at the connecting portion 7, there is an effect of relieving the stress on the bonding portion 14.

次に、図５に示すように、複数の配線基板９に囲まれた内部空間に封止樹脂８を充填して熱硬化させる。
最後に図６に示すように、第１の半導体素子１２と第２の半導体素子１３を搭載した配線基板９の裏面１６に外部端子をなすはんだボール１７を搭載してパッケージが完成する。 Next, as shown in FIG. 5, an internal space surrounded by the plurality of wiring boards 9 is filled with a sealing resin 8 and thermally cured.
Finally, as shown in FIG. 6, a solder ball 17 constituting an external terminal is mounted on the back surface 16 of the wiring board 9 on which the first semiconductor element 12 and the second semiconductor element 13 are mounted, thereby completing the package.

以上のように、本発明に係る実施例１の３次元半導体パッケージは、特徴的な構成として、複数の半導体素子、ここでは第１の半導体素子１２および第２の半導体素子１３を囲んで複数の配線基板９を立体的に配置している。このため、各半導体素子１２、１３は、それぞれ複数の配線基板９と直接に金ワイヤ６で結線することができる。   As described above, the three-dimensional semiconductor package according to the first embodiment of the present invention has a characteristic configuration in which a plurality of semiconductor elements, here, the first semiconductor element 12 and the second semiconductor element 13 are surrounded. The wiring board 9 is three-dimensionally arranged. For this reason, each of the semiconductor elements 12 and 13 can be directly connected to the plurality of wiring boards 9 by the gold wires 6.

さらに、各配線基板９の相互間をフレキシブル配線基板１０で電気的に接続している。このため、各半導体素子１２、１３のパッド５と各配線基板９のボンディングパッド１とを接続する金ワイヤ６の結線（回路）に加えて、フレキシブル配線基板１０により配線基板９の相互間を接続することができ、さらに配線基板９およびフレキシブル配線基板１０の内部配線がボンディングパッド１と外部端子をなすはんだボール１７との間の結線（回路）をなすので、高密度な半導体素子の集積に起因して信号電極の必要数や結線数が増加しても、十分に対応できる作用効果を奏する。   Further, the wiring boards 9 are electrically connected to each other by the flexible wiring board 10. For this reason, in addition to the connection (circuit) of the gold wire 6 which connects the pad 5 of each semiconductor element 12 and 13 and the bonding pad 1 of each wiring board 9, it connects between the wiring boards 9 by the flexible wiring board 10. Furthermore, since the internal wiring of the wiring board 9 and the flexible wiring board 10 forms a connection (circuit) between the bonding pad 1 and the solder ball 17 forming the external terminal, it is caused by the integration of high-density semiconductor elements. Thus, even if the required number of signal electrodes and the number of connections increase, there is an effect that can sufficiently cope.

さらに、第１の半導体素子１２を搭載した配線基板９のボンディングパッド１と第１の半導体素子１２のパッド５とを金ワイヤ６で結線し、第１の半導体素子１２に積層した第２の半導体素子１３を囲んで立体的に配置した配線基板９のボンディングパッド１と第２の半導体素子１３のパッド５とを金ワイヤ６で結線しているので、第１の半導体素子１２の金ワイヤ６と第２の半導体素子１３の金ワイヤ６間には構造的に十分な距離が形成される。よって、信号の高速化によって生じる電気的相互干渉の影響を低下させることができる。
（実施例２）
以下、本発明の実施例２における半導体パッケージについて図面を参照しながら説明する。図７は本発明の実施例２における３次元半導体パッケージの断面図を示す。図８（ａ）は同実施例２における立体配線基板の平面図、図８（ｂ）は同立体配線基板の側面図である。図９（ａ）は同実施例２における半導体素子を搭載した立体配線基板を示す平面図、図９（ｂ）は同立体配線基板の側面図である。図１０は同実施例２における立体配線基板に封止樹脂をモールドした状態を示す断面図である。図１１は同実施例２における立体配線基板にはんだボールを搭載した半導体パッケージの完成状態を示す断面図である。なお、実施例１の構成要素と同様の構成要素をなすものについては、同一符号を付しその説明を省略する。 Furthermore, the bonding pad 1 of the wiring board 9 on which the first semiconductor element 12 is mounted and the pad 5 of the first semiconductor element 12 are connected by the gold wire 6, and the second semiconductor laminated on the first semiconductor element 12. Since the bonding pad 1 of the wiring board 9 and the pad 5 of the second semiconductor element 13 which are three-dimensionally arranged surrounding the element 13 are connected by the gold wire 6, the gold wire 6 of the first semiconductor element 12 and A structurally sufficient distance is formed between the gold wires 6 of the second semiconductor element 13. Therefore, it is possible to reduce the influence of electrical mutual interference caused by signal speeding up.
(Example 2)
Hereinafter, a semiconductor package in Example 2 of the present invention will be described with reference to the drawings. FIG. 7 shows a cross-sectional view of a three-dimensional semiconductor package in Example 2 of the present invention. FIG. 8A is a plan view of the three-dimensional wiring board in the second embodiment, and FIG. 8B is a side view of the three-dimensional wiring board. FIG. 9A is a plan view showing a three-dimensional wiring board on which the semiconductor element in Example 2 is mounted, and FIG. 9B is a side view of the three-dimensional wiring board. FIG. 10 is a cross-sectional view showing a state in which a sealing resin is molded on the three-dimensional wiring board in the second embodiment. FIG. 11 is a cross-sectional view showing a completed state of a semiconductor package in which solder balls are mounted on a three-dimensional wiring board in the second embodiment. In addition, about the thing which makes the component similar to the component of Example 1, the same code | symbol is attached | subjected and the description is abbreviate | omitted.

図８に示すように、実施例２の立体配線基板Ｓが実施例１ものと異なる第１の相違点は、所定の配線基板９に金属板またはセラミック板からなる板材１８を貼り合わせていることにある。この板材１８に金属板を用いる場合には、表面をレジストコートした銅やアルミなどの熱伝導率の高い材料を用いる。   As shown in FIG. 8, the first difference between the three-dimensional wiring board S of the second embodiment and that of the first embodiment is that a plate material 18 made of a metal plate or a ceramic plate is bonded to a predetermined wiring board 9. It is in. When a metal plate is used for the plate material 18, a material having a high thermal conductivity such as copper or aluminum whose surface is resist-coated is used.

さらに、第２の相違点は、板材１８を設ける配線基板９が裏面１６にもボンディングパッド（図示省略）を有しており、配線基板９の裏面１６に板材１８を導電性接着材１９で貼り合わせており、板材１８と配線基板９の裏面１６のボンディングパッド（図示省略）とが電気的に接続している。   Further, the second difference is that the wiring board 9 on which the plate material 18 is provided also has bonding pads (not shown) on the back surface 16, and the plate material 18 is attached to the back surface 16 of the wiring substrate 9 with the conductive adhesive 19. In addition, the plate 18 and the bonding pads (not shown) on the back surface 16 of the wiring board 9 are electrically connected.

したがって、配線基板９の裏面１６のボンディングパッド（図示省略）をグラウンドに設定している場合には、板材１８はグラウンド面となり、半導体パッケージの電気特性の向上や、他の実装部品との電気的相互干渉を低減する効果を奏する。   Therefore, when the bonding pad (not shown) on the back surface 16 of the wiring board 9 is set to the ground, the plate material 18 becomes the ground surface, and the electrical characteristics of the semiconductor package are improved and the other mounting parts are electrically connected. There is an effect of reducing mutual interference.

図９（ａ）、（ｂ）に示すように、配線基板９はフレキシブル配線基板１０の表面にボンディングパッド１を形成しており、フレキシブル配線基板１０を介した配線基板９の主面１１の上に第１の半導体素子１２と第２の半導体素子１３を積層する。立体配線基板Ｓと第１の半導体素子１２と第２の半導体素子１３は、その接触面において絶縁性接着剤で接着する。   As shown in FIGS. 9A and 9B, the wiring board 9 has bonding pads 1 formed on the surface of the flexible wiring board 10 and is formed on the main surface 11 of the wiring board 9 through the flexible wiring board 10. The first semiconductor element 12 and the second semiconductor element 13 are stacked. The three-dimensional wiring board S, the first semiconductor element 12 and the second semiconductor element 13 are bonded to each other at the contact surface with an insulating adhesive.

第１の半導体素子１２のパッド５は第１の半導体素子１２を搭載した配線基板９のボンディングパッド１と金ワイヤ６で接続する。第２の半導体素子１３のパッド５は第２の半導体素子１３を搭載した配線基板９と連結部７を介して隣接する配線基板９のボンディングパッド１と金ワイヤ６で接続する。   The pad 5 of the first semiconductor element 12 is connected to the bonding pad 1 of the wiring board 9 on which the first semiconductor element 12 is mounted by the gold wire 6. The pad 5 of the second semiconductor element 13 is connected to the wiring board 9 on which the second semiconductor element 13 is mounted via the connecting portion 7 and the bonding pad 1 of the adjacent wiring board 9 by the gold wire 6.

第２の半導体素子１３のパッド５と金ワイヤ６との接合部１４、および配線基板９のボンディングパッド１と金ワイヤ６との接合部１４に対して絶縁性樹脂１５を被覆して硬化させる。絶縁性樹脂１５の硬化は熱硬化、あるいは紫外線などの光硬化により行う。   An insulating resin 15 is coated and cured on the bonding portion 14 between the pad 5 and the gold wire 6 of the second semiconductor element 13 and the bonding portion 14 between the bonding pad 1 and the gold wire 6 of the wiring substrate 9. The insulating resin 15 is cured by heat curing or photocuring such as ultraviolet rays.

次に、図１０に示すように、第１の半導体素子１２と第２の半導体素子１３を搭載した配線基板９と周囲の隣接する配線基板９とを連結部７で垂直に折り曲げる。
この際に、第２の半導体素子１３のパッド５と金ワイヤ６との接合部１４、配線基板９上のボンディングパッド１と金ワイヤ６との接合部１４に対しては絶縁性樹脂１５を被覆して接合強度を向上しているので、配線基板９を連結部７で折り曲げても接合部１４への応力を緩和させる効果がある。 Next, as shown in FIG. 10, the wiring substrate 9 on which the first semiconductor element 12 and the second semiconductor element 13 are mounted and the surrounding adjacent wiring substrate 9 are bent vertically at the connecting portion 7.
At this time, the bonding portion 14 between the pad 5 of the second semiconductor element 13 and the gold wire 6 and the bonding portion 14 between the bonding pad 1 on the wiring substrate 9 and the gold wire 6 are covered with the insulating resin 15. Thus, since the bonding strength is improved, even if the wiring board 9 is bent at the connecting portion 7, there is an effect of relieving the stress on the bonding portion 14.

次に、図１１に示すように、複数の配線基板９に囲まれた内部空間に封止樹脂８を充填して熱硬化させる。最後に、第１の半導体素子１２と第２の半導体素子１３を搭載した配線基板９の裏面１６に外部端子をなすはんだボール１７を搭載してパッケージが完成する。   Next, as shown in FIG. 11, the internal space surrounded by the plurality of wiring boards 9 is filled with the sealing resin 8 and thermally cured. Finally, a solder ball 17 serving as an external terminal is mounted on the back surface 16 of the wiring board 9 on which the first semiconductor element 12 and the second semiconductor element 13 are mounted, thereby completing the package.

この構成により、実施例１と同様に、各半導体素子１２、１３は、それぞれ複数の配線基板９と直接に金ワイヤ６で結線することができる。さらに、各半導体素子１２、１３のパッド５と各配線基板９のボンディングパッド１とを接続する金ワイヤ６の結線（回路）に加えて、配線基板９およびフレキシブル配線基板１０の内部配線がボンディングパッド１と外部端子をなすはんだボール１７との間の結線（回路）をなすので、高密度な半導体素子の集積に起因して信号電極の必要数や結線数が増加しても、十分に対応できる作用効果を奏する。   With this configuration, the semiconductor elements 12 and 13 can be directly connected to the plurality of wiring boards 9 by the gold wires 6 as in the first embodiment. Furthermore, in addition to the connection (circuit) of the gold wire 6 that connects the pad 5 of each semiconductor element 12, 13 and the bonding pad 1 of each wiring substrate 9, the internal wiring of the wiring substrate 9 and the flexible wiring substrate 10 is bonded to the bonding pad. 1 and the solder ball 17 forming the external terminal are connected (circuit), so that even if the required number of signal electrodes and the number of connections are increased due to the integration of high-density semiconductor elements, it can sufficiently cope with the connection. Has an effect.

さらに、連結部７で折り曲げられた配線基板９には、金属板またはセラミック板からなる板材１８を張り合わせているので、この板材１８が放熱板として機能し、第１の半導体素子１２、第２の半導体素子１３の発熱時に半導体パッケージの側面から放熱できる。   Furthermore, since the wiring board 9 bent at the connecting portion 7 is laminated with a plate material 18 made of a metal plate or a ceramic plate, the plate material 18 functions as a heat sink, and the first semiconductor element 12 and the second semiconductor element 12 When the semiconductor element 13 generates heat, heat can be radiated from the side surface of the semiconductor package.

また、上述したように、配線基板９の裏面１６のボンディングパッド（図示省略）をグラウンドに設定する場合には、板材１８がグラウンド面となって半導体パッケージの電気特性の向上や、他の実装部品との電気的相互干渉を低減する効果を奏する。   Further, as described above, when the bonding pad (not shown) on the back surface 16 of the wiring board 9 is set to the ground, the plate 18 becomes the ground surface to improve the electrical characteristics of the semiconductor package, and to other mounting components. This has the effect of reducing electrical mutual interference.

本発明の３次元半導体パッケージは、信号電極の必要数の増加に対応できる能力と、高い放熱性をもち、信号の高速化により発生する電気的相互干渉の影響を低下させる効果があるので、高密度な半導体素子を必要とする電子機器に搭載する３次元半導体パッケージとして有用である。   The three-dimensional semiconductor package of the present invention has the ability to cope with an increase in the required number of signal electrodes and high heat dissipation, and has the effect of reducing the influence of electrical mutual interference caused by the increase in signal speed. It is useful as a three-dimensional semiconductor package mounted on an electronic device that requires a high-density semiconductor element.

本発明の実施例１における３次元半導体パッケージの断面図Sectional drawing of the three-dimensional semiconductor package in Example 1 of this invention （ａ）は同実施例１における立体配線基板の平面図、（ｂ）は同立体配線基板の側面図(A) is a top view of the three-dimensional wiring board in Example 1, (b) is a side view of the three-dimensional wiring board. （ａ）は同実施例１における半導体素子を搭載した立体配線基板を示す平面図、（ｂ）は同立体配線基板の側面図(A) is a top view which shows the three-dimensional wiring board which mounted the semiconductor element in the Example 1, (b) is a side view of the three-dimensional wiring board （ａ）は同実施例１における立体配線基板の折り曲げ工程の途中を示す側面図、（ｂ）は同立体配線基板の折り曲げ工程の完了を示す側面図(A) is the side view which shows the middle of the bending process of the three-dimensional wiring board in the Example 1, (b) is the side view which shows completion of the bending process of the three-dimensional wiring board 同実施例１における立体配線基板に封止樹脂をモールドした状態を示す断面図Sectional drawing which shows the state which molded sealing resin in the three-dimensional wiring board in the Example 1 同実施例１における立体配線基板にはんだボールを搭載した状態を示す断面図Sectional drawing which shows the state which mounted the solder ball in the three-dimensional wiring board in the Example 1 本発明の実施例２における３次元半導体パッケージの断面図Sectional drawing of the three-dimensional semiconductor package in Example 2 of this invention （ａ）は同実施例２における立体配線基板の平面図、（ｂ）は同立体配線基板の側面図(A) is a top view of the three-dimensional wiring board in Example 2, (b) is a side view of the three-dimensional wiring board （ａ）は同実施例２における半導体素子を搭載した立体配線基板を示す平面図、（ｂ）は同基板の側面図(A) is a top view which shows the three-dimensional wiring board which mounted the semiconductor element in the Example 2, (b) is a side view of the board | substrate 同実施例２における立体配線基板に封止樹脂をモールドした状態を示す断面図Sectional drawing which shows the state which molded sealing resin in the three-dimensional wiring board in the Example 2 同実施例２における立体配線基板にはんだボールを搭載した半導体パッケージの完成状態を示す断面図Sectional drawing which shows the completion state of the semiconductor package which mounted the solder ball on the three-dimensional wiring board in Example 2 （ａ）は従来の３次元半導体パッケージの製造に用いる基板の平面図、（ｂ）は同基板の側面図(A) is a top view of the board | substrate used for manufacture of the conventional three-dimensional semiconductor package, (b) is a side view of the board | substrate. （ａ）は半導体素子を搭載した従来の基板の平面図、（ｂ）は同基板の側面図(A) is a plan view of a conventional substrate on which a semiconductor element is mounted, and (b) is a side view of the substrate. （ａ）は従来の３次元半導体パッケージの組み立て工程を示す側面図、（ｂ）は同３次元半導体パッケージの封止樹脂注入工程を示す側面図(A) is a side view showing the assembly process of the conventional three-dimensional semiconductor package, (b) is a side view showing the sealing resin injection process of the three-dimensional semiconductor package （ａ）は従来の３次元半導体パッケージの側面図、（ｂ）は同３次元半導体パッケージの斜視図(A) is a side view of a conventional three-dimensional semiconductor package, (b) is a perspective view of the three-dimensional semiconductor package.

符号の説明Explanation of symbols

Ｓ 立体配線基板
１ ボンディングパッド
２ 成形用基板
３ 封止樹脂注入孔
４ 半導体素子
５ パッド
６ 金ワイヤ
７ 連結部
８ 封止樹脂
９ 配線基板
１０ フレキシブル配線基板
１１ 主面
１２ 第１の半導体素子
１３ 第２の半導体素子
１４ 接合部
１５ 絶縁性樹脂
１６ 裏面
１７ はんだボール
１８ 板材
１９ 導電性接着材 DESCRIPTION OF SYMBOLS S 3D wiring board 1 Bonding pad 2 Molding board 3 Sealing resin injection hole 4 Semiconductor element 5 Pad 6 Gold wire 7 Connection part 8 Sealing resin 9 Wiring board 10 Flexible wiring board 11 Main surface 12 1st semiconductor element 13 1st 2 semiconductor element 14 joint 15 insulating resin 16 back surface 17 solder ball 18 plate material 19 conductive adhesive

Claims (11)

複数の配線基板を相互に折り曲げ自在に連結してなり、内部に底面と側面を有する容器形状に組み立てた立体配線基板と、前記底面をなす配線基板の主面に配置した半導体素子と、前記半導体素子のパッドと前記底面および前記側面をなす配線基板のボンディングパッドとを結線するワイヤと、前記底面と前記側面に囲まれた内部空間に充填して硬化させた封止樹脂とを備えることを特徴とする半導体装置。 A three-dimensional wiring board formed by connecting a plurality of wiring boards so as to be bendable, and assembled in a container shape having a bottom surface and a side surface inside, a semiconductor element disposed on a main surface of the wiring substrate forming the bottom surface, and the semiconductor A wire for connecting a pad of an element to a bonding pad of a wiring board that forms the bottom surface and the side surface, and a sealing resin filled and cured in an internal space surrounded by the bottom surface and the side surface. A semiconductor device. 前記底面と前記側面との相互間に形成する内角が垂直または鈍角をなすことを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, wherein an inner angle formed between the bottom surface and the side surface is vertical or obtuse. 前記パッドと前記ワイヤの接合部、および前記ボンディングパッドと前記ワイヤの接合部を被覆して硬化した絶縁性樹脂を備えることを特徴とする請求項１に記載の半導体装置。 The semiconductor device according to claim 1, further comprising an insulating resin that covers and hardens a bonding portion between the pad and the wire and a bonding portion between the bonding pad and the wire. 複数の配線基板の表面を被覆するとともに前記表面に接着した柔軟シートを備え、前記柔軟シートが配線基板の相互間を柔軟に折り曲げ可能に連結する連結部材をなすことを特徴とする請求項１に記載の半導体装置。 2. A flexible sheet that covers the surfaces of a plurality of wiring boards and is adhered to the surfaces, wherein the flexible sheets form a connecting member that flexibly connects the wiring boards together. The semiconductor device described. 前記柔軟シートがフレキシブル配線基板であり、前記フレキシブル配線基板と前記配線基板が内部配線において相互に接続していることを特徴とする請求項４に記載の半導体装置。 The semiconductor device according to claim 4, wherein the flexible sheet is a flexible wiring board, and the flexible wiring board and the wiring board are connected to each other in an internal wiring. 隣接し合う前記配線基板の双方の前記ボンディングパッドを結線するワイヤを備え、隣接し合う前記配線基板が相互に前記ワイヤで電気的に接続していることを特徴とする請求項１または５に記載の半導体装置。 6. The wiring board according to claim 1, further comprising a wire for connecting the bonding pads of both of the adjacent wiring boards, wherein the adjacent wiring boards are electrically connected to each other by the wire. Semiconductor device. 前記立体配線基板の側面をなす少なくとも１枚の前記配線基板の裏面に金属板またはセラミック板からなる板材を貼り合わせたことを特徴とする請求項１または５に記載の半導体装置。 6. The semiconductor device according to claim 1, wherein a plate material made of a metal plate or a ceramic plate is bonded to the back surface of at least one of the wiring substrates forming the side surface of the three-dimensional wiring substrate. 前記配線基板が裏面に前記板材と電気的に接続するボンディングパッドを有することを特徴とする請求項７に記載の半導体装置。 The semiconductor device according to claim 7, wherein the wiring board has a bonding pad electrically connected to the plate member on a back surface. 容器形状に組み立て可能な立体配線基板が複数の配線基板を相互に折り曲げ自在に連結してなり、前記容器形状の底面をなす前記配線基板の主面に半導体素子を実装する工程と、前記容器形状の底面および側面をなす配線基板のボンディングパッドと前記半導体素子のパッドとをワイヤで結線する工程と、隣接する前記配線基板を連結部で相互に折り曲げて前記立体配線基板を前記容器形状に組み立てる工程と、前記容器形状をなす前記立体配線基板の底面と側面に囲まれた内部空間に封止樹脂を充填して硬化させる工程とを含むことを特徴とする半導体装置の製造方法。 A step of mounting a semiconductor element on a main surface of the wiring board that forms a bottom surface of the container shape, wherein a three-dimensional wiring board that can be assembled into a container shape is connected to a plurality of wiring boards so as to be bendable to each other; Connecting the bonding pads of the wiring board and the pads of the semiconductor element forming the bottom and side surfaces of the semiconductor element with wires, and assembling the three-dimensional wiring board into the container shape by bending the adjacent wiring boards to each other at a connecting portion And a step of filling the internal space surrounded by the bottom surface and the side surface of the three-dimensional wiring substrate having the container shape with a sealing resin and curing the semiconductor device. 隣接する前記配線基板を前記連結部で折り曲げることにより、前記ワイヤで接続した前記半導体素子の前記パッドと前記配線基板の前記ボンディングパッドとを、その相互間に形成する内角が垂直または鈍角をなす位置関係に配置する工程を含むことを特徴とする請求項９に記載の半導体装置の製造方法。 Positions in which the internal angle between the pads of the semiconductor element and the bonding pads of the wiring substrate connected by the wire is perpendicular or obtuse by bending the adjacent wiring substrate at the connecting portion. The method for manufacturing a semiconductor device according to claim 9, further comprising a step of arranging in a relationship. 前記パッドと前記ワイヤの接合部、および前記ボンディングパッドと前記ワイヤの接合部を絶縁性樹脂で被覆して硬化させる工程を含み、前記配線基板を前記連結部で折り曲げるときに前記接合部に発生する応力を緩和することを特徴とする請求項１０に記載の半導体装置の製造方法。 And a step of covering the bonding portion between the pad and the wire and the bonding portion between the bonding pad and the wire with an insulating resin and curing, and is generated in the bonding portion when the wiring board is bent at the connecting portion. The method of manufacturing a semiconductor device according to claim 10, wherein stress is relaxed.
JP2006251979A 2006-09-19 2006-09-19 Semiconductor device and manufacturing method thereof Pending JP2008078164A (en)

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Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015192146A (en) * 2014-03-27 2015-11-02 インテル コーポレイション Flexible electronic system including wire bond
CN106469719A (en) * 2015-08-17 2017-03-01 飞思卡尔半导体公司 There is the IC package of non-horizontal die pad and be used for its flexible substrates
WO2019142253A1 (en) * 2018-01-17 2019-07-25 新電元工業株式会社 Electronic module
US10453820B2 (en) * 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same

Cited By (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015192146A (en) * 2014-03-27 2015-11-02 インテル コーポレイション Flexible electronic system including wire bond
CN106469719A (en) * 2015-08-17 2017-03-01 飞思卡尔半导体公司 There is the IC package of non-horizontal die pad and be used for its flexible substrates
WO2019142253A1 (en) * 2018-01-17 2019-07-25 新電元工業株式会社 Electronic module
JPWO2019142253A1 (en) * 2018-01-17 2020-10-22 新電元工業株式会社 Electronic module
JP7018965B2 (en) 2018-01-17 2022-02-14 新電元工業株式会社 Electronic module
US11322448B2 (en) 2018-01-17 2022-05-03 Shindengen Electric Manufacturing Co., Ltd. Electronic module
US10453820B2 (en) * 2018-02-07 2019-10-22 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
CN111788681A (en) * 2018-02-07 2020-10-16 美光科技公司 Semiconductor assembly using edge stacking and method of manufacturing the same
US10867964B2 (en) 2018-02-07 2020-12-15 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
US11955457B2 (en) 2018-02-07 2024-04-09 Micron Technology, Inc. Semiconductor assemblies using edge stacking and methods of manufacturing the same
CN111788681B (en) * 2018-02-07 2024-08-20 美光科技公司 Semiconductor assembly using edge stacking and method of manufacturing the same

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