JP2008076382A - Serial encoder data conversion circuit, and servo drive system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a serial encoder data conversion system which generates a C-phase pulse with satisfactory responsiveness. <P>SOLUTION: A transmission control part 2 inputs a serial data 1 into a serial/parallel conversion part 5. An original point data 23 out of the data held in the serial/parallel conversion part 5 is held in a register 21 with an original point passing bit 24 indicating the original point passing of a serial encoder. A C-phase pulse generating part 22 compares output data from the register 21 with up-and-down counter output data 18 to output the C-phase pulse when they match each other. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a data conversion circuit for position data sent from an encoder used for motor position detection in a motor control system such as a servo drive system, and more particularly to a serial encoder for converting serial data sent from a serial encoder into a pulse train. The present invention relates to a data conversion circuit and a servo drive system using the data conversion circuit.

  Conventionally, the DDA method (digital differential analyzer) or BRM method (binary binary data) is obtained from the difference data between the serial encoder position data received this time and the previous position data for the data sent from the serial encoder at a fixed cycle. There is disclosed a serial encoder data conversion circuit that generates A-phase and B-phase pulses by hardware using an integration circuit with a fixed number of bits by a late multiplier. (For example, refer to Patent Document 1).

FIG. 8 is a circuit diagram showing a serial encoder data conversion circuit in the prior art.
In the figure, reference numeral 1 denotes serial data, which is transmitted from the serial encoder at a constant cycle, and is input to the HDLC transmission control unit 2. The fetched data 1 ′ is input to the serial / parallel converter 5 by the shift clock 4 and converted to parallel data, and the data is held by the sampling clock 3 at regular intervals.

  Reference numeral 6 denotes serial encoder position data, which indicates position information of the serial encoder among the data held in the serial / parallel converter 5. A subtractor 7 outputs difference data between the serial encoder position data 6 and the output data 18 of the up / down counter 17 which is serial encoder position data in the previous cycle. This difference data is held in the register 8 at the falling edge of the sampling clock 3.

An adder 9 adds the difference data 20 that is output data of the register 8 and the data 20 ′ on the bus 11 and outputs the result to the register 10. The register 10 receives the output of the adder 9 and outputs the added data on the bus 11 at the rising edge of the internal clock signal CP. Here, the adder 9, the register 10, and the bus 11 constitute an integration circuit with a fixed number of bits by the DDA method.
A carry signal 13 generated by the adder 9 serves as a count enable signal for the up / down counter 17. Reference numeral 12 denotes an MSB (most significant bit) of the difference data 20, which is H level when the motor is rotating forward and L level when the motor is rotating backward, and acts as an up / down signal for positive / negative discrimination.

  The up / down counter 17 counts pulses output from the integration circuit. That is, when the count enable signal 13 of the adder 9 of the integration circuit is at the H level and the up / down signal 12 is at the H level, the count up signal is counted up at the rising edge of the internal clock signal CP, and the count enable signal 13 is at the H level and up / down. When the signal 12 is at L level, it counts down at the rising edge of the internal clock signal CP, and outputs up / down counter output data 18. The up / down counter output data 18 is count data that follows the serial encoder position data 6.

  An EXOR element 19 inputs the least significant bit D0 and the next bit D1 of the up / down counter output data 18 to the EXOR element 19, the output signal of the EXOR element 19 is the A phase pulse signal, and the bit D1 is the B phase pulse. A-phase and B-phase pulse trains are output as signals. In this manner, an A / B phase pulse generation unit including the up / down counter 17, the subtractor 7, the register 8, the integration circuit, and the EXOR element 19 is configured.

Next, the operation specifications of this prior art will be described.
This prior art has an integration circuit with a fixed number of bits based on the DDA method using an adder 9 and a register 10, and integrates the difference data 20 updated every sampling period in synchronization with the internal clock signal CP. The carry signal 13 is output from the device 9.

The sampling period T, the bit number n (= the number of integration circuit bits) of differential data that can be converted, and the clock frequency CPf have a relationship represented by (1).
T = 1 / CPf × 2 ⁿ (1)
For example, when the clock frequency CPf is 32 MHz, when the sampling period T (= communication period of the serial encoder) is 32 us, 64 us, and 128 us, the number of integration circuit bits is 10 bits, 11 bits, and 12 bits, respectively.

  As can be seen from the above description, the number of integration circuit bits needs to be changed according to the communication cycle of the serial encoder. Since the communication cycle of the serial encoder differs depending on the product series, etc., the number of integration circuit bits was calculated based on the communication cycle of the serial encoder, and a serial data encoder data conversion circuit corresponding to the specification of the communication cycle was realized.

As described above, the serial data conversion circuit in the prior art receives serial data sent from the serial encoder at a fixed period, and the hardware calculates from the difference data between the serial encoder position data received this time and the previous position data. , A-phase and B-phase pulse trains were generated. Also, the number of integration circuit bits is calculated according to the communication cycle of the serial encoder, and a serial data encoder data conversion circuit corresponding to the specification of the communication cycle has been realized.
JP-A-11-44555

  However, since the serial encoder data conversion circuit of the prior art performs only the A-phase and B-phase pulse generation by hardware and does not have a hardware circuit for generating the C-phase pulse indicating the origin passage, It could not be used for data conversion corresponding to the required incremental encoder. Even when a circuit for generating a C-phase pulse is provided, a procedure for detecting the passage of the origin via software, performing data processing, setting a pulse output timing, etc., and generating a C-phase pulse There is a problem that the load of software increases and the transmission of position information to the host controller is delayed and the performance of the entire system deteriorates.

Also, when serial encoder position data is received for the first time after the power is turned on, there is no previous value of serial encoder position data, so the difference data becomes an indefinite value, and the A and B phase pulse trains are output without meaning. There was also a problem that would be done.
Furthermore, it is necessary to prepare a plurality of serial data encoder data conversion circuits having different numbers of calculation bits of the integration circuit corresponding to the communication cycle of the serial encoder, which causes a problem in versatility.

  The present invention has been made in view of such problems, and is capable of generating a C-phase pulse immediately upon passing through the origin from the origin passing bit and origin position data included in the serial data. An object of the present invention is to provide a highly reliable serial encoder data conversion circuit capable of preventing unnecessary A-phase and B-phase pulse output when serial encoder position data is received for the first time. It is another object of the present invention to provide a versatile serial encoder data conversion circuit capable of commonly supporting serial encoders having different communication cycles.

In order to solve the above problem, the present invention is configured as follows.
The invention described in claim 1 is a serial encoder data conversion circuit that receives serial data sent from a serial encoder at a constant period and converts it into a pulse train, and is output from an integration circuit using the DDA method and the integration circuit. An A / B phase pulse generation unit that includes an up / down counter for counting pulses and generates a previous pulse train following the serial encoder position data included in the serial data; and an origin passing bit included in the serial data as an enable signal A register that holds origin position data included in the serial data, and a C-phase pulse generator that outputs a C-phase pulse when the output data of the register matches the output data of the up / down counter It is characterized by that.
According to a second aspect of the present invention, the A / B phase pulse generator includes a load signal generator that generates a load signal for the up / down counter only once when data is first received from a serial encoder. It is characterized by that.
According to a third aspect of the present invention, the A / B phase pulse generator includes a hysteresis adding circuit that gives a hysteresis characteristic to the output of the A / B phase pulse signal when the phase of the A / B phase pulse signal is inverted. It is characterized by having prepared.
According to a fourth aspect of the present invention, the hysteresis adding circuit includes a hysteresis setting register for setting a hysteresis amount.
According to a fifth aspect of the present invention, a servo drive system includes the serial encoder data conversion circuit according to the first aspect.
According to a sixth aspect of the present invention, there is provided a serial encoder data conversion circuit for receiving serial data sent from a serial encoder at a constant period and converting it into a pulse train, wherein a plurality of integrations with different numbers of operation bits according to the DDA method are provided. A circuit, a bit setting register that commands the number of bits of the integration circuit, a selector that selects one of the integration circuits according to a bit setting signal from the bit setting register, and an output from the integration circuit An up / down counter for counting pulses is provided.
According to a seventh aspect of the invention, a servo drive system includes the serial encoder data conversion circuit according to the sixth aspect.

  According to the first aspect of the present invention, since the origin passage bit and origin position data included in the serial data are processed by hardware and a C-phase pulse is immediately generated when the origin passes, the software load increases. It is possible to generate a high-speed C-phase pulse without doing so.

  According to the second aspect of the present invention, if the load signal generation unit is provided, unnecessary A-phase and B-phase pulse outputs even when serial encoder position data is first received after power-on. And the malfunction of the host controller that is the pulse output destination can be prevented.

  According to the third aspect of the present invention, if the A / B phase pulse generation unit includes a hysteresis addition circuit, a certain amount of pulse width can be secured at the time of phase inversion of the A / B phase pulse. It is possible to prevent count errors of the host controller.

  According to the fourth aspect of the present invention, if the hysteresis adding circuit includes a hysteresis setting register for setting the hysteresis amount, the hysteresis amount can be easily set. Therefore, an appropriate amount of hysteresis can be set according to the type of the host controller, and when there is no need to add hysteresis characteristics, the value of the hysteresis setting register can be set to 0 to operate without hysteresis. .

  According to the invention described in claim 5, since the servo drive system includes the serial encoder data conversion circuit described in claim 1, a high-speed and highly reliable servo drive system can be constructed.

  According to the invention described in claim 6, since a plurality of integration circuits having different numbers of operation bits are provided and can be selected according to the communication cycle, the serial data conversion is versatile and can be applied to a plurality of types of serial encoders having different communication cycles. A circuit can be realized. Accordingly, since it is not necessary to prepare a serial data conversion circuit corresponding to the product series, the cost of the serial data conversion circuit can be reduced.

  According to the invention described in claim 7, since the servo drive system includes the serial data conversion circuit described in claim 6, it is necessary to prepare serial data conversion circuits for servo drive systems having different communication cycles. No. Therefore, a versatile servo drive system can be realized.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a circuit diagram of a serial encoder data conversion circuit showing a first embodiment of the present invention.
In the figure, 21 is a register for holding origin position data, and 22 is a C-phase pulse generator.
The present invention is different from the prior art in that it includes a register that holds origin position data and a C-phase pulse generator.

Next, the operation of the present invention will be described.
Since the operations for generating the A-phase pulse and the B-phase pulse are the same as those in the prior art, description thereof will be omitted.
In FIG. 1, the origin position data 23 indicates origin position information of the serial encoder among the data held in the serial / parallel converter 5. Reference numeral 24 denotes an origin passage bit, which indicates the origin passage of the serial encoder among the data held in the serial / parallel converter 5, and is set to “1” only when the origin passes, and “0” when not passing the origin. "Is set. The register 21 holds the origin position data 23 when the origin passage bit 24 becomes “1”. The C-phase pulse generator 22 compares the output data of the register 21 with the up / down counter output data 18 and outputs a C-phase pulse when they match.

  As described above, in this embodiment, the serial data conversion circuit includes the register that holds the origin position data and the C-phase pulse generation unit that outputs the C-phase pulse, and the C-phase pulse is generated by hardware. A serial data conversion circuit that can immediately output a C-phase pulse when passing through the origin can be realized.

FIG. 2 is a circuit diagram of a serial encoder data conversion circuit showing a second embodiment of the present invention.
In the figure, reference numeral 25 denotes a load signal generation unit for setting initial data of the up / down counter 17 and includes an AND element 251 and a D flip-flop 252.
The present embodiment is different from the first embodiment in that a load signal generation unit 25 is provided.

Next, the operation of this embodiment will be described.
After the power is turned on, when the first sampling clock 3 is output from the transmission control unit 2 and input to the load signal generation unit 25, the AND element 251 outputs the logical product of the sampling clock 3 and the output of the D flip-flop 252 as a load signal. 26, and the initial data of the up / down counter 17 is set. The output of the D flip-flop 252 is initially at the H level, changes from the H level to the L level at the falling edge of the load signal 26, and then continues to hold the L level.

  When the load signal 26 is at the H level, the up / down counter 17 loads the serial encoder position data 6 at the rising edge of the internal clock signal CP regardless of the signal levels of the count enable signal 13 and the up / down signal 12. Thus, after the power is turned on, the position data obtained by the first sampling clock 3 after the power is turned on is input to the + input and the − input of the differencer 7, and the first difference data output from the subtractor 7 is 0. It becomes.

  As described above, this embodiment includes a load signal generation unit that generates the load signal of the up / down counter only once when data is received from the serial encoder for the first time so that the initial difference data of the subtracter becomes zero. Therefore, when the serial encoder position data is first received after the power is turned on, unnecessary A-phase and B-phase pulse outputs can be prevented.

FIG. 3 is a circuit diagram of a serial encoder data conversion circuit showing a third embodiment of the present invention.
In the figure, reference numeral 40 denotes a hysteresis adding circuit. The hysteresis adding circuit includes a hysteresis setting register 41, an adder 42, an adder 9 ′, and a selector 43.
This embodiment is different from the prior art in that it includes a hysteresis adding circuit 40 that gives hysteresis characteristics to the output of the A / B phase pulse signal.

  In the hysteresis adding circuit 40, the adder 42 adds the hysteresis amount 44 output from the hysteresis setting register 41 to the data on the bus 11, and outputs the result to the adder 9 '. The adder 9 ′ adds the difference data 20 that is the output data of the register 8 and the output of the adder 42. The carry signal 13 generated by the adder 9 and the carry signal 13 ′ generated by the adder 9 ′ are input to the selector 43 and counted when the MSB (most significant bit) 12 of the difference data 20 which is a positive / negative discrimination bit is positive. The enable signal 13 is selected, and if it is negative, the count enable signal 13 'is selected. 151 is a count enable signal after the selector 43 selects a signal. The MSB 12 of the difference data 20 becomes H level during forward rotation of the motor and L level during reverse rotation of the motor, and acts as an up / down signal for positive / negative discrimination.

Next, the operation of this embodiment will be described.
FIG. 4 is a timing chart showing the pulse generation operation in the present embodiment. Timing chart in the pulse generation operation that receives serial data sent from a serial encoder attached to a motor (not shown) at a constant cycle and generates A-phase and B-phase pulse signals, especially when the motor changes from forward rotation to reverse rotation Indicates.

  As shown in the figure, the MSB 12 of the difference data 20 is at the H level. During this time, the output value of the adder 9 is counted up by the internal clock signal CP. The output value of the adder 9 'in the circuit 40 is counted up by the internal clock signal CP, and when it overflows, a count enable signal 13' is generated. However, the count enable signal 13 ′ is generated earlier than the count enable signal 13 by the time corresponding to the hysteresis amount 44.

  During the reverse rotation of the motor, the MSB 12 of the difference data 20 is at the L level. During this time, the output value of the adder 9 is counted down by the internal clock signal CP, and when it underflows, the count enable signal 13 is generated. The output value of the adder 9 'is counted down by the internal clock signal CP, and when it underflows, a count enable signal 13' is generated. However, the count enable signal 13 ′ is generated later than the count enable signal 13 by the time corresponding to the hysteresis amount 44.

  Here, the count enable signal 13 is selected during forward rotation, and the count enable signal 13 ′ in the hysteresis adding circuit 40 is selected during reverse rotation. Therefore, in synchronization with the count enable signal 13 during forward rotation. A-phase and B-phase pulses are output, and during reverse rotation, A-phase and B-phase pulses are output in synchronization with the count enable signal 13 '. As a result, as shown in FIG. 4, even when the rotation direction of the motor changes from normal rotation to reverse rotation immediately after the count enable signal 13 is generated, the A-phase pulse output is equivalent to the time corresponding to the hysteresis amount. The pulse width is added and output.

As described above, in this embodiment, since the hysteresis adding circuit that gives the hysteresis characteristic to the output of the A / B phase pulse signal is provided, a certain amount of pulse width can be secured when the phase of the A / B phase pulse is inverted. Therefore, it is possible to prevent a count error of the host controller that is the pulse output destination.
In addition, since the hysteresis addition circuit has a hysteresis setting register, an appropriate amount of hysteresis can be set according to the type of the host controller. It is also possible to set an operation without hysteresis.

FIG. 5 is a circuit diagram of a serial encoder data conversion circuit showing a fourth embodiment of the present invention.
In the figure, reference numeral 27 denotes an integration circuit unit for integrating the difference data 20 and has four integration circuits having different numbers of operation bits. A bit register 28 outputs a bit number setting signal 29 for selecting an integration circuit having an arithmetic processing bit number corresponding to the bit number of the difference data 20.

FIG. 6 is a circuit diagram of the integrating circuit unit in this embodiment.
The integration circuit unit 27 is composed of four integration circuits 27a to 27d each having a different number of arithmetic processing bits. The integrating circuits 27a to 27d are composed of adders 9a to 9d and registers 10a to 10d, respectively. Reference numeral 30 denotes a selector which selects and outputs the carry signal 13 of the integration circuit corresponding to the bit number setting signal 29 from the carry signals 13a to 13d of the adders 9a to 9d.

  The difference between the present embodiment and the prior art is that there is one integration circuit with a fixed number of bits in the prior art, but in this embodiment, there are four integration circuits with different numbers of arithmetic processing bits. A selector for selecting the output of the integrating circuit and a bit register for outputting a bit number setting signal to the selector are provided.

Next, the operation of this embodiment will be described.
The integration circuits 27a to 27d receive the difference data 20 and perform an integration operation. That is, the adders 9a to 9d add the difference data 20 and the data on the respective buses 11a to 11d, and output them to the registers 10a to 10d, respectively. The registers 10a to 10d integrate the difference data 20 by receiving the outputs of the adders 9a to 9d and outputting them on the buses 11a to 11d at the rising edge of the internal clock signal CP.

  Each of the integration circuits 27a to 27d constitutes a DDA 9-bit, 10-bit, 11-bit, and 12-bit integration circuit. The unit 9d outputs carry signals 13a to 13d for each integration of 4096 bits. The selector 30 outputs the carry signal 13 selected by the bit number setting signal 29 from the carry signals 13a to 13d.

FIG. 7 is an operation specification table of the integration circuit in this embodiment.
Each value in the figure shows an example in which the clock frequency of the internal clock signal CP is 32 MHz. From equation (1), the integration cycle when selecting the 9-bit integration circuit 27a is 16us, the integration cycle when selecting the 10-bit integration circuit 27b is 32us, the integration cycle when selecting the 11-bit integration circuit 27c is 64us, and the 11-bit integration circuit 27d is selected. The integration period at that time is 128 us.

  Further, from equation (2), the maximum pulse output number P in one cycle when the 9-bit integration circuit 27a is selected is 512 pulses, and the maximum pulse output number P in one cycle when the 10-bit integration circuit 27b is selected is 1024 pulses and 11-bit integration. The maximum number of pulse outputs P per cycle when the circuit 27c is selected is 2048 pulses, and the maximum number of pulse outputs P per cycle when the 12-bit integrating circuit 27d is selected is 4096 pulses.

  As described above, in this embodiment, a plurality of integration circuits having different numbers of calculation bits are provided, and the integration circuit having the number of calculation bits corresponding to the communication cycle of the serial encoder is selected by the bit number setting register. A versatile serial data conversion circuit that can handle multiple types of serial encoders can be realized. Accordingly, since it is not necessary to prepare a serial data conversion circuit corresponding to the product series, the cost of the serial data conversion circuit can be reduced.

  In the above embodiments, the DDA type integration circuit has been described as an example. However, even if the BRM type integration circuit is used, nothing changes essentially. In the third embodiment, a circuit configuration selected from four integration circuits of 9 bits, 10 bits, 11 bits, and 12 bits has been described as an example. However, the number of bits of the integration circuit is not particularly limited, and the integration circuit The number is not limited.

1 is a circuit diagram of a serial encoder data conversion circuit showing a first embodiment of the present invention. Circuit diagram of serial encoder data conversion circuit showing a second embodiment of the present invention Circuit diagram of serial encoder data conversion circuit showing a third embodiment of the present invention Timing chart showing pulse generation operation in the third embodiment Circuit diagram of serial encoder data conversion circuit showing a fourth embodiment of the present invention. Circuit diagram of the integration circuit section in the fourth embodiment Operation spec table of the integration circuit in the fourth embodiment Circuit diagram showing serial encoder data conversion circuit in the prior art

Explanation of symbols

1, 1 'Serial data 2 Transmission control unit 3 Sampling clock 4 Shift clock 5 Serial / parallel conversion unit 6 Serial encoder position data 7 Subtractor 8, Register
9, 9 ', 9a to 9d, 42 Adder 10, 10a to 10d Register 11, 11a to 11d Bus 12 MSB (most significant bit)
13, 13 ', 13a to 13d Carry signal 17 Up / down counter 18 Up / down counter output data 19 EXOR element 20 Differential data 21 Register 22 C-phase pulse generator 23 Origin position data 24 Origin passage bit 25 Load signal generator 26 Load signal 27 Integration circuit section 28 Bit register 29 Bit number setting signal 30, 43, 44 Selector 40 Hysteresis circuit 41 Hysteresis setting register

Claims (7)

A serial encoder data conversion circuit that receives serial data sent from a serial encoder at a constant cycle and converts it into a pulse train,
An A / B phase pulse generation unit that generates an initial pulse train that follows the serial encoder position data included in the serial data, and includes an integration circuit based on the DDA method and an up / down counter that counts pulses output from the integration circuit;
A register for holding origin position data included in the serial data with an origin passage bit included in the serial data as an enable signal;
A serial encoder data conversion circuit, comprising: a C-phase pulse generation unit that outputs a C-phase pulse when the output data of the register and the output data of the up / down counter match and match.   2. The A / B phase pulse generation unit includes a load signal generation unit that generates a load signal of the up / down counter only once when data is first received from a serial encoder. Serial encoder data conversion circuit.   2. The A / B phase pulse generator includes a hysteresis adding circuit that gives a hysteresis characteristic to the output of the A / B phase pulse signal when the phase of the A / B phase pulse signal is inverted. Serial encoder data conversion circuit.   4. The serial encoder data conversion circuit according to claim 3, wherein the hysteresis adding circuit includes a hysteresis setting register for setting a hysteresis amount.   A servo drive system comprising the serial encoder data conversion circuit according to claim 1. A serial encoder data conversion circuit that receives serial data sent from a serial encoder at a constant cycle and converts it into a pulse train,
A plurality of integration circuits with different numbers of operation bits according to the DDA method;
A bit setting register for instructing the number of bits of the integration circuit; a selector for selecting one of the integration circuits according to a bit setting signal from the bit setting register; and a pulse output from the integration circuit A serial encoder data conversion circuit comprising an up / down counter.   A servo drive system comprising the serial encoder data conversion circuit according to claim 6.

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