JP2007502477A - Power consumption monitoring and control - Google Patents

Abstract

  The present invention relates to electronic circuits, devices and methods for monitoring and controlling power consumption. Thus, an electronic circuit, apparatus and method comprising one or more sequential logic elements (12) capable of receiving a clock signal (CLK) and an input signal (I) and providing an output signal (O) Is provided. The sequential logic element (12) further includes a circuit (20) for monitoring the input and output signals (I, O) and supplying a control signal (CS) according to the input and output signals (I, O). The power consumption of the IC can be controlled to be operable according to the control signal.

Description

  The present invention is an electronic circuit including at least one sequential logic element, wherein the sequential logic element includes at least one clock terminal for receiving a clock signal, and at least one input terminal for receiving an input signal. And at least one output terminal for supplying an output signal. The invention also relates to a device comprising an electronic circuit having the characteristics described above and a method for controlling the power consumption of such an electronic circuit.

  International Patent Application No. 01/48584 “Microprocessor with digital power throttle” describes a scheme for digital monitoring of microprocessor power consumption.

  In general, in the art, the power consumption and waste requirements and standards of modern electronic circuits such as integrated circuits (ICs) increase their performance requirements, ie, function, complexity, die size, clock speed, etc. As such, it is known that it is becoming more important. In addition, power consumption issues are a very important factor in the design and operation of devices such as battery-powered computers, multimedia devices and mobile communications.

  Furthermore, it is well understood in the art that ICs that operate at high clock rates and thus have a substantial portion of active electronic circuitry generate a large amount of heat. This heat must somehow be removed from the IC and associated equipment as quickly and as efficiently as possible and cost-effectively. This heat removal can be very complex and expensive in some cases, which is also well understood in the art.

  Various techniques, circuits and systems for manipulating the power consumption / waste of an IC are known to those skilled in the art. Much research effort is directed to the design of circuits and technologies that achieve the desired performance criteria at an acceptable power consumption level. Because power consumption depends on a number of different factors such as supply voltage, clock frequency, switching capacitance, and circuit switching behavior, to minimize power consumption by either one or a combination of such factors Many different solutions have been proposed. In addition, leakage current is a larger factor in IC power consumption because of the physical effects experienced when changes occur in IC process technology. As a direct result, solutions such as back-biasing the IC substrate or using MTCMOS technology have been proposed as an efficient way to control these leakage currents to manage IC power consumption. Yes.

  Most efforts to reduce IC power consumption are made during the IC design phase, where information about IC power consumption is gathered from status and statistical data. There are commercially available software-based power consumption simulators that assist in the design of optimal circuits from a power consumption perspective. However, these power consumption simulators optimize power resources according to a set of fixed conditions, which is clearly disadvantageous.

  In International Patent Application No. 01/48584, a microprocessor is divided into various functional units, each having a unique fixed 'power weight' encoded in a digital word, which power weight is Must be determined by the adjustment process. When the microprocessor executes a predetermined program, the state of each functional unit is monitored digitally, ie either active or inactive, and this information is passed to a special monitoring unit. The monitor unit ignores the power weights associated with the inactive functional units, but adds the power weights of the active functional units and compares the sum to a threshold that represents the maximum expected power consumption. If the sum exceeds the threshold, the instruction execution rate is reduced by reducing the clock frequency or introducing bubbles in the instruction pipeline. If the sum is below the threshold, no action is taken.

  Some other examples of power consuming operating techniques include adjusting the frequency of the system clock to its optimal rate, especially depending on the data processing task being performed, and adjusting the power supply according to a predetermined set of circumstances Or completely removing the supply of power.

  Some of the many different methods and devices known to those skilled in the art for dissipating the heat generated by an IC include, for example, heat sinks and liquid cooling. Such methods and techniques can often be elaborate and expensive in both cost and space.

  The scheme disclosed in International Patent Application No. 01/48584 has several typical disadvantages. One such disadvantage is that power consumption is monitored digitally. A further disadvantage is that power consumption is highly dependent on the quality and type of input data, so the power consumed by each of the functional units is not well represented by the 'fixed weight' solution, and each of the functional units is The need to adjust to define their proper power weights.

  An object of the present invention is to provide an improved reduction in power consumption.

  The invention is defined by the independent claims.

  The dependent claims define advantageous embodiments of the invention.

  The purpose of the electronic circuit further includes a circuit that monitors an input signal and an output signal and supplies a control signal according to the input signal and the output signal, and the power consumption of the electronic circuit can be operated according to the control signal. It is realized by being able to control to.

  According to one embodiment of the circuit of the present invention, the electronic circuit can be controlled at a rate determined by the clock signal. Such an embodiment has the advantage that any change in the clock rate is applied to the entire electronic circuit. Thus, when power savings are required, this savings can be implemented quickly and on a large scale.

  According to another embodiment of the circuit of the present invention, the electronic circuit can provide information regarding future power consumption. Knowing or predicting future power consumption or its likelihood can have obvious advantages when actively controlling power consumption. A decision can be made prior to a known or 'probable' likely event that would result in increased power consumption under normal circumstances.

  Furthermore, according to another embodiment of the circuit of the present invention, the electronic circuit has the ability to allow future power consumption to be controlled in advance based on past logical events. Knowing or predicting future power consumption or its likelihood based on past events can have obvious advantages when actively controlling power consumption. Again, significant prior power saving decisions can be made for known or 'probable' likely events.

  Other features and advantages of the electronic circuit, apparatus and method of the present invention can be made apparent from or from the accompanying preferred drawings and the following description.

  The circuit of the present invention will be described with reference to ICs, particularly ICs in CMOS process technology, although those skilled in the art will recognize that the underlying principles are applicable to other electronic circuits and IC process technologies. Will be understood.

  The power consumption of digital ICs can be divided into two separate categories. The first category is dynamic power consumption, and the second is static power consumption.

  Dynamic power consumption occurs during logic state changes that occur in the digital circuitry of the IC. On the other hand, static power consumption occurs when the digital circuit is in a stable or stationary state. Dynamic power consumption is a dominant factor in the power consumption of charge control circuits such as CMOS, and occurs when the nodes of the various elements that form the circuit change states with appropriate input stimuli.

  For the sake of brevity, use of the term “power” herein includes either actual power or a value, such as current, voltage or other criteria, that is proportional to or indicative of actual power. .

  Referring to FIG. 1, this particular example of digital circuit 10 comprises a series of D-type data latches 12a-12e, sometimes referred to as flip-flops or sequential logic, and two combinational logic blocks 14,16.

  It should be noted that a D-type flop flop has been described and illustrated to describe the present invention. However, the purpose and advantages of the present invention are to use other types of logic, sequential or otherwise, such as JK or SR type flip-flops, as will be appreciated by those skilled in the art. Can also be achieved. Further, the combinational logic blocks 14 and 16 are intended to be schematic examples of processing logic blocks and data path logic blocks, for example.

  Referring to FIG. 1, the flip-flop 12 a receives an input signal I 1 and generates an appropriate output signal O 1, and this output signal O 1 functions as a first input signal to the first logic block 14. The flip-flop 12 b receives the input signal I 2 that is the first output signal from the first logic block 14 and generates an appropriate output signal O 2, and this output signal O 2 is the first output to the second logic block 16. Functions as an input signal. The flip-flop 12c receives the input signal I3 which is the first output signal from the second logic block 16, and generates an appropriate output signal O3. The flip-flop 12d receives the input signal I4, which is the second output signal from the first logic block 14, and generates an appropriate output signal O4. The output signal O4 is the second input to the first logic block 14. Functions as a signal. The flip-flop 12e receives the input signal I5, which is the second output signal from the second logic block 16, and generates an appropriate output signal O5. The output signal O5 is the second input to the second logic block 16. Functions as a signal. Each of flip-flops 12a-12e also receives a clock signal CLK, which is used for operable gate input and output signals.

  If none of the data contents of flip-flops 12a-12e change, there is no change in logic state, so the dynamic power consumption of the circuit shown in FIG. And zero. However, if a state change occurs in one or more of the flip-flops 12a-12e and / or one or both of the logic blocks 14, 16 with appropriate stimulation, the state change is caused in the circuit 10. Propagate. Such propagation creates a certain amount of dynamic power consumption in the circuit 10. Therefore, power is consumed over a predetermined clock cycle at a rate proportional to the number of state changes that occur in the elements making up the circuit 10. On average, the more elements that change state, i.e., the more 'active' the circuit is, the greater the power consumption. Thus, knowing the number of elements that change state in a given clock cycle provides a direct correlation to power consumption for this particular clock cycle. It should be noted that modern digital IC design methodologies and tools allow designers to know in advance which state changes will occur in response to input stimuli and where such changes will occur. Note that it makes it possible. Such prior knowledge is advantageous as will become apparent from the following description.

  If the power consumption, i.e. activity, of the circuit is known in real time, from this knowledge it is possible to operably control the operation of the circuit 10 and thus the subsequent power consumption. Such control includes, for example, state changes in the elements of the circuit 10, power supply voltage adjustment, IC back-bias or substrate voltage adjustment, or control signal frequency adjustment. Those skilled in the art will appreciate that the exemplary control techniques described above can be used in many other varying degrees and combinations to reduce power consumption and performance. Thus, having the ability to monitor the activity of the circuit 10 and allow the establishment of power consumption is related to increasing the overall performance of the integrated circuit, as will become apparent from the preferred description and illustration of the invention below. It is advantageous.

  If the contents of any flip-flop 12 change in response to an appropriate input stimulus, such changes propagate through circuit 10 and generate a certain amount of dynamic power consumption. Thereafter, but some time before the next clock CLK edge, a new logic state value 11-15 at the input of flip-flop 12 is determined, thus preparing flip-flop 12 for a new active cycle. Thereby, the power consumption of the circuit 10 depends on the number of flip-flops 12 that change state in each clock cycle. Thus, power consumption of the circuit 10 can be established by operably monitoring the activity at each of the appropriate switching nodes, ie, flip-flop input and output terminals, D and Q, during each clock cycle. Appropriate switching nodes can be readily determined as part of the IC design cycle. As previously mentioned, modern design methodologies and tools allow the designer to determine which data path and thus the circuit is active for a known input stimulus. With this prior knowledge, monitors can be strategically placed at the most appropriate nodes in the circuit. This is particularly advantageous because, for example, when the logic block characteristics are known, the number of monitors can be kept to a minimum, thus reducing the power and area occupied by the monitors in other ways.

  In accordance with the present invention, an electronic circuit is added to the circuit 10 to monitor or determine its activity. In essence, this monitoring is accomplished by adding some additional circuitry to all flip-flops 12 or any portion thereof to monitor circuit 10 activity.

  Referring to FIG. 2, an activity monitor 20 is the basic building block used for the purpose of monitoring circuit activity and subsequent power consumption in accordance with the present invention.

  The flip-flop, or logic stage 12, in this particular example, has two associated inputs, one output, and an activity monitor 20. The first input of the activity monitor 20 is connected to the input D of the flip-flop 12, and the second input of the activity monitor 12 is connected to the output Q of the flip-flop 12. The activity monitor 20 generates an output signal CS, which is determined by the state of the input and output signals I and Q at each D and Q terminal of the flip-flop 12.

  Referring to FIG. 3, one method of determining power consumption is between the input and output terminals D and Q of each flip-flop 12 that need to be monitored, as indicated by the number of flip-flops 12 that switch. Connecting two input XOR logic gates 30. In this particular embodiment, flip-flop 12 changes state only if the value of input signal I at input terminal D of flip-flop 12 is not equal to the value of output signal O at its corresponding output terminal Q. .

Table 1 is a logic table showing the state input and output values associated with the XOR logic gate activity monitor of FIG.

If the logic state at the input and output terminals D, Q of the flip-flop 12 changes such that they are not equal, i.e., I ≠ O, the output signal CS from the XOR gate 30 is a logic 'high' or '1'. 'State, which indicates the state change of the flip-flop 12 and thus the switching activity of the circuit. Thus, counting the number of XOR output signals CS that have changed to a logic '1' state in each clock cycle provides the necessary information regarding the switching activity of the circuit. Since it is desirable to obtain this result within one clock cycle, the above-described counting needs to be executed by an adder circuit (not shown). However, in a circuit having N flip-flops 12 where N is an integer, such an implementation based on the illustration of FIG. 3 is implemented by N two-input XOR gates 30, N one-bit inputs and log ₂ N A digital adder (not shown) having a number of outputs would be required. Those skilled in the art will appreciate that this solution where N may be large may not be as attractive as other solutions as described below.

  Referring to FIG. 4, the activity monitor 20 includes two PMOS transistors P1 and P2 and two NMOS transistors N1 and N2.

  The source terminals of the transistors P1 and P2 are both connected to the positive power supply VDD, while the source terminals of the transistors N1 and N2 are connected together to form the output terminal 40 of the activity monitor 20. In this particular preferred illustration, the gate terminals of transistors P1 and N1 are both connected to the input terminal D of flip-flop 12, while the gate terminals of transistors P2 and N2 are both connected to flip-flop 12. Connected to the corresponding output terminal Q. The drain terminals of the four transistors P1, P2, N1, and N2 are all connected to each other.

  In order for the activity monitor 20 to detect a change in state at the flip-flop 12, each arrangement of transistors P1, P2, N1, N2 must essentially show a difference.

Table 2 is a logic table showing both the input and output logic states associated with the activity monitor of FIG. 4 and the conduction state of each of its four transistors.

  As can be seen, the placement and control of the transistors P1, P2, N1 and N2 shown in FIG. 4 and Table 2 is thus a difference that can detect any logic state change, ie activity, of the flip-flop 12. A dynamic current source.

  Therefore, only when the input signals I and O to the flip-flop 12 are not equal, i.e., I ≠ O, either the transistor pair, P1 and N2 or P2 and N1, conducts current. Conversely, if the input signals I and O to the flip-flop 12 are equal, i.e., I = O, then neither transistor pair P1, N2 or P2, N1 conducts, in which case the activity monitor Twenty output terminals 40 exhibit a high output impedance and therefore no current is supplied.

  Referring to FIG. 5, each of the flip-flops 12a-12e has an associated activity monitor 20a-20e operatively connected between their respective input and output terminals D, Q. If required, the sum of the currents generated by the individual activity monitors 20a-20e can be achieved by connecting their respective output terminals 40 together to form a common output terminal 50.

  Again, if a suitable input stimulus causes a state change in one or more of the flip-flops 12a-12e and / or one or both of the logic blocks 14, 16, this state change will occur in the circuit 10. Propagate to. When any of the flip-flops 12a to 12e changes state, each of the activity monitors 20a to 20e generates each current according to the differential mode of operation.

  Those skilled in the art will be able to individually set and / or control the amount of current generated by each activity monitor 20a-20e in response to changes in the state of the associated flip-flops 12a-20e for a particular application or need. It will be appreciated that adaptations are possible.

  One way to set the amount of current generated by the activity monitor 20 uses the aspect ratio, ie the ratio of the gate width W to the length L of the transistors P1, P2, N1 and N2 determined in the design and manufacturing stages. Is. Thus, if a particular activity monitor is expected to exhibit a relatively large amount of power consumption because it is associated with a monitor of a large portion of the circuit, the amount of current supplied by this activity monitor is It can be increased by adjusting only one or more aspect ratios, typically width W, of the transistors P1, P2, N1 and N2. One possible application in which wider transistors P1, P2, N1 and N2 can be used relates to monitoring the switching activity of the clock signal CLK. This adds a dummy flip-flop (not shown) whose nQ output, i.e. its inverse logic Q output, is connected to its D input and monitors its switching activity, i.e. power consumption, which is normally expected to be high. This can be achieved.

  One way to control the amount of current generated by the activity monitor 20 is to operably in or out additional transistors, not shown, connected in parallel with the main transistors P1, P2, N1 and N2. Is to switch. Those skilled in the art will appreciate that many techniques can be used to set and / or control the current generated by individual or groups of transistors P1, P2, N1 and N2. Let's go. Having the ability to set and / or control the current generated by the activity monitor 20 has advantages. One such advantage is that the activity monitor can weight its current output with respect to the associated logic block, eg, function, size, and / or power consumption. Another advantage is that the current from the activity monitor 20 can be set / controlled to overcome parasitic effects associated with its output path 50.

  The speed of operation / response of the activity monitor 20 is limited only by the time required for its output current to charge a parasitic or any other capacitance associated with the current path. If such capacitance is large, for example due to the length of the current path, one or more current mirrors (not shown) are operably placed to counteract such capacitance and thus the speed / response of operation. Can also be increased. An alternative method of overcoming this parasitic or dominant capacitive effect can be used, either in place of or in addition to the method of setting and / or controlling the current from the activity monitor 20. . One advantage of using an amplifier such as a current mirror instead of controlling the current from the series of activity monitors 20 is that the aspect ratio of all transistors P1, P2, N1 and N2 can be kept to a minimum. It is. This helps to reduce area and power consumption and waste for each flip-flop. According to the present invention, the advantages of building an activity monitor with four minimum size transistors can be emphasized as follows. Typically, each D-type flip-flop is itself made up of about 30 transistors. The area overhead of including four transistor activity monitors 20 in a typical D-type flip-flop is therefore 4/30 = 13.3%, which in itself is not a significant burden. However, the number of extra transistors included in most IC design applications in which the activity monitor 20 is typically used is approximately a fraction of the total number of transistors that make up the IC.

  A current from one or more of the activity monitors 20a-20e was generated in response to the switching activity, where current, voltage, I / V, transducers were used to voltage this current, if desired. Can be converted to

  Referring to FIG. 6a, the output terminal 50 of the circuit 10 is connected to a negative supply rail (negative) via a resistive element such as the resistor 60 as shown, or alternatively through an NMOS transistor (not shown) operating in its linear region. supply rail) connected to GND. Current flows to the negative supply rail GND through the resistor 60, which produces an output voltage Va in the resistor 60 that is proportional to the current from the activity monitors 20a-20e.

  Referring now to FIG. 6 b, the output terminal 50 of the circuit 10 is connected to the negative supply rail GND via a capacitor 62. 6b also shows an NMOS transistor N3 connected in parallel with the capacitor 62. This transistor N3 functions as a switch, which is operably controlled to discharge, ie reset or initialize, the capacitor 62. Assuming that switch N3 is open, the current flowing from activity monitors 20a-20e accumulates and charges capacitor 62, resulting in an output voltage proportional to the total amount of current sourced from activity monitors 20a-20e. Va is generated in the capacitor 62. As soon as the switch N3 is operably closed, both terminals of the capacitor 62 are connected to the negative supply rail GND, thereby discharging the capacitor 62, and typically this event occurs at the start of integration. Occurs, usually at the beginning of each clock cycle. When switch N3 is operably opened again and current flows from activity monitors 20a-20e, capacitor 62 again begins to charge and generate output voltage Va proportional to the current sourced from activity monitors 20a-20e. To do. The peak value of the output voltage Va reflects the energy consumed by the circuit 10 during a predetermined integration time, that is, during the charging period of the capacitor 62. For example, the gate terminal of the transistor N3 may be connected to receive the clock signal CLK. In a preferred embodiment of the invention, it is ensured that the output voltage Va is maintained below the value that guarantees operation in the respective saturation region when the transistors P1, P2, N1, N2 are conducting. It is desirable. Such operating conditions will be readily understood by those skilled in the art and can therefore be adapted to specific applications afterwards.

  Referring now to FIG. 5, the outputs of activity monitors 20a-20e perform an analog calculation of the humming distance between the current logic state of circuit 10 and the next logic state. As is known to those skilled in the art, this Hamming distance is correlated to the average power consumption of the circuit 10.

  One further advantage of the present invention is that the activity monitors 20a-20e also generate currents in response to switching transients that may occur at the terminals of the flip-flop 12. Thus, the resulting waveform of the voltage Va at the output terminal 50 of the circuit 10 more accurately reflects its transient power consumption per clock.

  The circuit 10 is divided into two separate parts, a logic 70 and an activity monitor 72, for ease of explanation and simplicity, as shown in FIG. Logic 70 represents each suitable flip-flop 12 and combinational logic 14, 16 in each previous figure, while activity monitor 72, respectively, represents all suitable flip-flops in each previous figure. The individual monitor 20 is shown. In FIG. 7, a controller 74 is shown.

  The controller 74 receives the output voltage Va from the activity monitor 72 and, in response, the logic 70, either in whole or in part, for example, its supply voltage, clock frequency, and / or threshold voltage. Regardless of whether it is a single or various combinations, it can be controlled by changing it.

  Those skilled in the art will appreciate that the block diagram shown in FIG. 7 can be replicated and distributed across various regions of the IC for large ICs. For example, logic 70 may have three separate elements, processing, memory, input / output, each of which may have its own logic, activity monitor and / or controller. it can. By disclosing such changes, other such combinations are readily conceivable and can therefore be adapted to meet individual specific needs as needed.

  Another advantage of the present invention that will be appreciated by those skilled in the art relates to predicting power consumption. Due to the operation of the flip-flop 12, the respective output signal Va of each activity monitor 20 provides a reference for the actual power consumption of the circuit for each clock period. Each output signal Va contains two useful pieces of information. First, it provides information about the past, i.e., how many state changes have occurred in the associated flip-flop during the current clock period, and second, information about the future, i.e., what relates to the flip-flop. State change is generated in the next clock period. Thus, the activity monitor output signal Va actually predicts future power consumption, ie the switching activity of its associated circuit, before it occurs. In addition, situations where a predetermined power level is likely to be exceeded or exceeded can be detected. Such a prediction allows advance reaction and start of some strategy to improve performance.

  Another advantage associated with the present invention stems from the fact that the output signal Va of the activity monitor 20 provides a waveform profile or sign of power consumption that includes glitching activity for a given stream of input data. . Although not shown, such a waveform profile or signature is then analyzed either in real time or otherwise, for example, any anomalies that do not change the logic behavior of the circuit in question but can be potentially dangerous, You may decide. Further, by recording the activity monitor output signal Va, eg, execution of a predetermined instruction or routine, and averaging this data, a baseline for average power consumption associated with this event can be established. This information can then be used by the high-level controller 74 to control the circuit depending on the situation, for example with either hardware and / or software. Hardware control can typically take the form of switching different circuits or portions thereof in and / or out. Software control typically can take the form of execution of alternative instructions or routines.

  Referring to FIG. 8, this block diagram shows a buffer 80, an activity monitor 72, a sample and hold amplifier 82, a voltage regulator 84, and logic 70.

  Input data is buffered in FIFO memory 80, which has an operable connection to activity monitor 72 and logic 70. The FIFO memory receives input data streams before they are added to the logic circuit 70. In the present embodiment, the purpose of the FIFO memory 80 is to adapt the average rate of input data to the processing speed of the logic 70. Although not shown, each flip-flop, or shift register, in the FIFO memory 80 may also include its own activity monitor 20, thus monitoring future activity of the logic 70 by monitoring the FIFO memory 80 activity. Information can be obtained, which is advantageous in controlling and monitoring power consumption.

  During each clock period, the output signal Va from the activity monitor 72 is sampled and readjusted to a more appropriate value by the sample and hold amplifier 82. The output signal Vc of the amplifier 82 is applied to the power supply regulator 84. In response, the power supply regulator 84 operably increases or decreases the supply voltage VDD of the logic 70 based on the signal Vc.

  The block diagram of FIG. 9 includes a microprocessor 90, a summing circuit 92, a comparator 94, and a frequency adjuster 96.

Microprocessor, a set of functional units _FU 1 _{~FU N} for the N is an integer, further comprising. These functional units represent, for example, ALUs, multipliers, shifters, decoders, etc., each of which has its own corresponding activity monitor AM ₁ -AM _N in this particular example. The output signals of each of the activity monitors AM ₁ -AM _N are the criteria by which their corresponding functional units are active over a predetermined period of time and are supplied to the summing circuit 92. A summing circuit 92 generates an output signal Va corresponding to the sum of all input signals from the activity monitor. The comparator receives a 'threshold' reference signal along with the output signal Va of the summing circuit, and the output signal Va from the summing circuit 92 is compared with the threshold reference signal. If the activity represented by voltage Va, for example during N clock cycles, is greater than the threshold voltage signal, the comparator output voltage signal Vb changes state. This change of state in the comparator 94 is detected by the frequency adjuster 96, which correspondingly adjusts the clock signal CLK ′ to be operative to the microprocessor and the activity monitor AM _1. corresponding to the output signal of-Am _N.

  The block diagram of FIG. 10 shows a buffer 80, an activity monitor 72, an analog-to-digital converter 100 including a look-up table, three switches S1-S3, and logic 70.

Input data is buffered in a FIFO memory 80 that has an operable connection to the activity monitor 72 and logic 70. The output signal Va from the activity monitor 72 is supplied to an analog-to-digital converter 100 that also includes a look-up table and converted to a digital word. The digital word is then entered into a lookup table, which determines the best state conditions for each of the switches S1, S2 and S3. In this particular demonstrative example, each switch S1, S2 and S3 each has a logic 70 with two possible values: transistor threshold voltage high Vt _H or transistor threshold voltage low Vt _L , clock frequency high F _H Alternatively, the clock frequency low F _L and the supply voltage high VDD _H or the supply voltage low VDD _L are supplied. Thus, the best combination of supply voltage, transistor threshold voltage and / or clock frequency can be selected via switches S1-S3 according to the measured activity level Va and the contents of the look-up table. Obviously, from the above description, it is clear that any or all of the switches S1-S3 have more than two individual levels shown.

  In summary, the activity monitor disclosed in the present invention can be useful, for example, in applications where it is not convenient or possible to fix the operating conditions of an electronic circuit for average power consumption, and the average power Consumption can be determined largely from simulation and / or statistical analysis. In such cases, the subject matter of the present invention using a control scheme that adapts these conditions to changing consumption is advantageous. Furthermore, the power consumption and computational needs of the circuit are often highly dependent on the input data or the algorithm being executed, in which case some exchange between speed and power is also advantageous.

  According to the present invention, the output signal of the activity monitor provides information regarding power consumption every clock cycle or every N clock cycles where N is an integer. The information obtained is doubled in certain situations. Due to the nature of sequential logic, information can be collected from the past and into the future. Historically, such information is related to the number of logic state changes at the flip-flop input generated during the current clock cycle or the past N clock cycles. Such information is beneficial and advantageous because it allows predictions regarding future power consumption. For the future, such information is related to the number of logic state changes in the flip-flop output generated in the next clock period. This ability to predict future logic changes is advantageous when improving power consumption, performance, or both.

  It should be noted that the above-described embodiments are illustrative of the invention rather than limiting, and that those skilled in the art can design many alternative embodiments without departing from the scope of the appended claims. Please note that. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word “comprising” does not exclude the presence of elements or steps other than those listed in any claim or specification. A single element reference does not exclude a plurality of such element references and vice versa. The invention may be implemented by hardware comprising a number of individual elements and by a suitably programmed computer. In the device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain criteria are set forth in mutually different dependent claims does not indicate that a combination of these criteria cannot be used effectively.

In the drawings intended as a non-limiting example of the principles of the present invention,
FIG. 1 shows a typical state-of-the-art digital circuit. FIG. 2 shows a schematic embodiment of an electronic circuit according to the invention. FIG. 3 shows another embodiment of the electronic circuit according to the present invention. FIG. 4 shows still another embodiment of the electronic circuit according to the present invention. FIG. 5 shows the digital circuit of FIG. 1 incorporating an electronic circuit according to the present invention. FIG. 6a shows a prior art transconductor. FIG. 6b shows a prior art transconductor. FIG. 7 shows a basic system block diagram of an electronic circuit according to the present invention. FIG. 8 shows a block diagram of an electronic circuit used for voltage control according to the present invention. FIG. 9 shows a block diagram of an electronic circuit used for frequency control according to the present invention. FIG. 10 shows a schematic block diagram of an electronic circuit used for controlling power consumption according to the present invention.

Claims (6)

An electronic circuit comprising at least one sequential logic element,
The sequential logic element is
At least one clock terminal for receiving a clock signal;
At least one input terminal for receiving an input signal;
At least one output terminal for supplying an output signal;
With
The electronic circuit is
A circuit that monitors the input signal and the output signal and supplies a control signal in response to the input signal and the output signal;
Means for controlling power consumption of the electronic circuit in response to the control signal;
An electronic circuit characterized by further comprising:   The electronic circuit according to claim 1, wherein the electronic circuit can be controlled at a rate determined by the clock signal.   The electronic circuit according to claim 1 or 2, characterized in that it can supply information relating to future power consumption.   The electronic circuit according to any one of claims 1 to 3, wherein the electronic circuit has a capability of making it possible to control future power consumption in advance based on a past logical event.   An apparatus comprising the electronic circuit according to claim 1. A method for controlling power consumption of an electronic circuit including at least one sequential logic element comprising:
The sequential logic element is
At least one clock terminal for receiving a clock signal;
At least one input terminal for receiving an input signal;
At least one output terminal for supplying an output signal;
With
The method is
Monitoring the input and output signals;
Supplying a control signal in response to the input signal and the output signal;
Operably controlling the power consumption in response to the control signal;
A method comprising the steps of:

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