US5324992A - Self-timing integrated circuits having low clock signal during inactive periods - Google Patents
Self-timing integrated circuits having low clock signal during inactive periods Download PDFInfo
- Publication number
- US5324992A US5324992A US07/908,315 US90831592A US5324992A US 5324992 A US5324992 A US 5324992A US 90831592 A US90831592 A US 90831592A US 5324992 A US5324992 A US 5324992A
- Authority
- US
- United States
- Prior art keywords
- integrated circuit
- clock
- threshold level
- active
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0008—Arrangements for reducing power consumption
- H03K19/0016—Arrangements for reducing power consumption by using a control or a clock signal, e.g. in order to apply power supply
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/30—Modifications for providing a predetermined threshold before switching
- H03K17/302—Modifications for providing a predetermined threshold before switching in field-effect transistor switches
Definitions
- This invention relates generally to electronic circuits, and more particularly the invention relates to self-timing clocked circuits in which clock signal periods are variable.
- Combinatorial logic circuits operate in response to clock signals in operating on input data or numbers.
- the length of the clock period of a typical integrated circuit is determined by a time which is needed to obtain complete stability of all logic states in the longest or critical path of the circuit.
- the time to add two random numbers can vary greatly depending on the number of carry signals. However, if such worse case conditions for processing numbers occur infrequently in the circuit, then during a large percentage of clock periods the circuit is clocked too slowly and the circuit experiences considerable idle time.
- the clock period for a clocked circuit is varied to minimize idle time of the circuit when operating on data.
- the status of the circuit is determined by monitoring a voltage supply current.
- the circuit When the current is below a threshold level, the circuit is inactive or idle. When the current exceeds the threshold, the circuit is actively operating on data. Accordingly, the clock period when the circuit is operating on data is identified by monitoring the voltage supply current with the clock period being lengthened or shortened depending on the active state of the circuit as determined by the current level.
- FIGS. 1A and 1B illustrate a conventional clock signal having a fixed period and a clock signal having a variable period in accordance with the invention, respectively.
- FIGS. 2A and 2B illustrate the voltage supply current for a CMOS integrated circuit operating with the conventional clock of FIG. 1A and a voltage supply current for an integrated circuit operating with the variable clock of FIG. 1B, respectively.
- FIG. 3 is a functional block diagram of a self-timing circuit in accordance with one embodiment of the invention.
- FIG. 4 is a schematic of a circuit for controlling a variable clock in accordance with one embodiment of the invention.
- FIG. 1A illustrates a conventional clock signal having a fixed period or pulse width for the positive pulse between the rising and falling edges, A,B and C,D.
- the time period for each positive pulse depends on the critical path or the logical operation requiring the most time in operating on input data. Since some logic functions require much less time than the critical path time, a circuit can reach a stable state in operating on data long before the end of each positive pulse whereupon the circuit becomes inactive. If the worse case condition or critical path occurs infrequently, then the circuit is being clocked too slowly during a large percentage of clock periods.
- a method of self-timing is provided for an integrated circuit whereby each clock period can be varied by monitoring the level of activity of the circuit whereby inactive or idle time in each clock cycle is eliminated or at least minimized.
- the periods of the clock cycles are determined by monitoring the active and inactive states of the integrated circuit.
- the active and inactive states of a CMOS integrated circuit can be determined by monitoring the voltage supply current to the integrated circuit. Current above a threshold level indicates that the circuit is actively processing data, and supply current below the threshold indicates that the circuit has reached a stable state and has become inactive or idle. This is illustrated in FIG. 2A for the clock pulse of FIG. 1A. At the leading edge A the supply current is above the threshold but becomes inactive long before the falling edge B. The circuit again becomes active at the leading edge C and remains active to the falling edge D. By shortening the clock period as shown in FIG. 1B, the inactive period of the circuit is significantly reduced as illustrated by the active and inactive current levels of FIG. 2B for the pulses of FIG. 1B.
- FIG. 3 is a functional block diagram of circuitry for implementing the clocking strategy illustrated in FIGS. 1B and 2B.
- the supply voltage V DD connected to the logic circuit 10 provides a current through the circuit to a virtual ground and thence through a current sensor 12 to circuit ground.
- the current sensor 12 can be a built-in current sensor of the type disclosed in Maly et al. U.S. Pat. No. 5,025,344.
- the current sensor monitors the supply current as the logic circuit operates on input data, and the threshold information is applied to clock circuit 14 which generates a variable pulse width clock signal which is applied to the clock input of the logic circuit 10. Accordingly, the clock frequency can be increased by varying the durations of the positive pulses. It will be appreciated that clock signals to several interconnected logic circuits can be varied and the time period between positive pulses can be determined in part by the active states of the interconnected logic circuits.
- FIG. 4 is a detailed schematic of a current sensor and flag generating circuit for controlling the clock signal in accordance with one embodiment.
- the CMOS function unit 20 which can be similar to the logic circuit 10 of FIG. 3, is connected between the voltage supply V DD and virtual ground node 22 with the virtual ground connected through a current sensor circuit shown generally at 24 to circuit ground.
- the current sensor 24 includes a field effect transistor 26 serially connected between virtual ground and circuit ground with the gate of FET 26 connected through transmission gate 28 to the virtual ground. By clocking the transmission gate, a voltage is generated on the gates of transistor 26 and transistor 30 which is connected through load transistors 32, 34 to V DD .
- the voltage generated across transistor 30 is a function of the active state of the CMOS function unit 20.
- This voltage is applied to an input of a bistable circuit 36 including cross-coupled transistors M1,M2 with the gate of transistor M1 receiving a voltage reference and the gate of transistor M2 receiving the voltage across transistor 30.
- the bistable circuit drives a CMOS transistor pair shown at 38 with the CMOS pair generating a flag signal, V 0 , which controls provides the clock circuit output.
- FIG. 4 The schematic of FIG. 4 is a test circuit which has been used for circuit level simulation with a 32 bit adder as a test vehicle connected to the ground rail through an integrated sensor of the type disclosed in U.S. Pat. No. 5,025,344, supra. Signals from the sensor were used to determine when the adder became inactive. The simulation was run for a sequence of random numbers applied as inputs for the adder under the test.
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Logic Circuits (AREA)
Abstract
An integrated circuit function unit operating in a data dependent manner in logic operations of variable lengths of time is provided with a clock signal having a pulse width determined by the active period of the function unit. In one embodiment a current sensor monitors power supply current to the integrated circuit, and when the current exceeds a threshold level the integrated circuit is in an active period. Clock means for generating a clock signal for the function unit responds to the sensed current in controlling the clock period.
Description
This invention relates generally to electronic circuits, and more particularly the invention relates to self-timing clocked circuits in which clock signal periods are variable.
Combinatorial logic circuits operate in response to clock signals in operating on input data or numbers. The length of the clock period of a typical integrated circuit is determined by a time which is needed to obtain complete stability of all logic states in the longest or critical path of the circuit. In an adder, for example, the time to add two random numbers can vary greatly depending on the number of carry signals. However, if such worse case conditions for processing numbers occur infrequently in the circuit, then during a large percentage of clock periods the circuit is clocked too slowly and the circuit experiences considerable idle time.
In accordance with the present invention the clock period for a clocked circuit is varied to minimize idle time of the circuit when operating on data.
In a preferred embodiment, the status of the circuit is determined by monitoring a voltage supply current. When the current is below a threshold level, the circuit is inactive or idle. When the current exceeds the threshold, the circuit is actively operating on data. Accordingly, the clock period when the circuit is operating on data is identified by monitoring the voltage supply current with the clock period being lengthened or shortened depending on the active state of the circuit as determined by the current level.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
FIGS. 1A and 1B illustrate a conventional clock signal having a fixed period and a clock signal having a variable period in accordance with the invention, respectively.
FIGS. 2A and 2B illustrate the voltage supply current for a CMOS integrated circuit operating with the conventional clock of FIG. 1A and a voltage supply current for an integrated circuit operating with the variable clock of FIG. 1B, respectively.
FIG. 3 is a functional block diagram of a self-timing circuit in accordance with one embodiment of the invention.
FIG. 4 is a schematic of a circuit for controlling a variable clock in accordance with one embodiment of the invention.
Referring now to the drawing, FIG. 1A illustrates a conventional clock signal having a fixed period or pulse width for the positive pulse between the rising and falling edges, A,B and C,D. As noted above the time period for each positive pulse depends on the critical path or the logical operation requiring the most time in operating on input data. Since some logic functions require much less time than the critical path time, a circuit can reach a stable state in operating on data long before the end of each positive pulse whereupon the circuit becomes inactive. If the worse case condition or critical path occurs infrequently, then the circuit is being clocked too slowly during a large percentage of clock periods.
In accordance with the present invention a method of self-timing is provided for an integrated circuit whereby each clock period can be varied by monitoring the level of activity of the circuit whereby inactive or idle time in each clock cycle is eliminated or at least minimized.
This is illustrated in the clock signal of FIG. 1B in which the time period for the first positive pulse A'B' is reduced to one-fourth the time period for the positive pulse A,B in FIG. 1A, whereas the length of a pulse C'D' is approximately the same as the time period of the pulse between C,D in FIG. 1A.
The periods of the clock cycles are determined by monitoring the active and inactive states of the integrated circuit. In accordance with one embodiment of the invention, the active and inactive states of a CMOS integrated circuit can be determined by monitoring the voltage supply current to the integrated circuit. Current above a threshold level indicates that the circuit is actively processing data, and supply current below the threshold indicates that the circuit has reached a stable state and has become inactive or idle. This is illustrated in FIG. 2A for the clock pulse of FIG. 1A. At the leading edge A the supply current is above the threshold but becomes inactive long before the falling edge B. The circuit again becomes active at the leading edge C and remains active to the falling edge D. By shortening the clock period as shown in FIG. 1B, the inactive period of the circuit is significantly reduced as illustrated by the active and inactive current levels of FIG. 2B for the pulses of FIG. 1B.
FIG. 3 is a functional block diagram of circuitry for implementing the clocking strategy illustrated in FIGS. 1B and 2B. The supply voltage VDD connected to the logic circuit 10 provides a current through the circuit to a virtual ground and thence through a current sensor 12 to circuit ground. The current sensor 12 can be a built-in current sensor of the type disclosed in Maly et al. U.S. Pat. No. 5,025,344. The current sensor monitors the supply current as the logic circuit operates on input data, and the threshold information is applied to clock circuit 14 which generates a variable pulse width clock signal which is applied to the clock input of the logic circuit 10. Accordingly, the clock frequency can be increased by varying the durations of the positive pulses. It will be appreciated that clock signals to several interconnected logic circuits can be varied and the time period between positive pulses can be determined in part by the active states of the interconnected logic circuits.
FIG. 4 is a detailed schematic of a current sensor and flag generating circuit for controlling the clock signal in accordance with one embodiment. The CMOS function unit 20, which can be similar to the logic circuit 10 of FIG. 3, is connected between the voltage supply VDD and virtual ground node 22 with the virtual ground connected through a current sensor circuit shown generally at 24 to circuit ground. The current sensor 24 includes a field effect transistor 26 serially connected between virtual ground and circuit ground with the gate of FET 26 connected through transmission gate 28 to the virtual ground. By clocking the transmission gate, a voltage is generated on the gates of transistor 26 and transistor 30 which is connected through load transistors 32, 34 to VDD. The voltage generated across transistor 30 is a function of the active state of the CMOS function unit 20. This voltage is applied to an input of a bistable circuit 36 including cross-coupled transistors M1,M2 with the gate of transistor M1 receiving a voltage reference and the gate of transistor M2 receiving the voltage across transistor 30. The bistable circuit drives a CMOS transistor pair shown at 38 with the CMOS pair generating a flag signal, V0, which controls provides the clock circuit output.
The schematic of FIG. 4 is a test circuit which has been used for circuit level simulation with a 32 bit adder as a test vehicle connected to the ground rail through an integrated sensor of the type disclosed in U.S. Pat. No. 5,025,344, supra. Signals from the sensor were used to determine when the adder became inactive. The simulation was run for a sequence of random numbers applied as inputs for the adder under the test.
By controlling the positive pulses in a clock signal to when the clocked circuit is active, the inactive time period of the circuit is minimized thereby providing self-timing to the integrated circuit. While the invention has been described with reference to specific embodiments, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. A self-timing integrated circuit comprising:
a clocked function unit responsive to a clock signal for operating on variable numbers in logic operations of variable lengths of time, said function unit having an active period during a logic operation and an inactive period following a logic operation,
sensing means for monitoring said function unit to identify active periods,
clock means for generating a clock signal for said function unit, said clock signal having variable width pulses, and
means coupling said sensing means to said clock means for controlling said variable width pulses in response to identified active periods.
2. The self-timing integrated circuit as defined by claim 1 wherein said sensing means comprises voltage supply current sensing means, an active period being identified when the voltage supply current exceeds a threshold value.
3. The self-timing integrated circuit defined by claim 2 wherein said clock means includes bistable circuit means having two output voltage levels corresponding to voltage supply currents exceeding said threshold level and not exceeding said threshold level, respectively.
4. The self-timing integrated circuit as defined by claim 1 wherein said clock means includes bistable circuit means having two output voltage levels corresponding to voltage supply currents exceeding a threshold level and not exceeding said threshold level, respectively.
5. The self-timing integrated circuit as defined by claim 1 wherein said integrated circuit comprises CMOS circuitry.
6. Apparatus for controlling the clock period for clock pulses applied to a clocked integrated circuit powered by a voltage supply comprising:
sensing means for sensing current from said voltage supply to said integrated circuit and determining when said current exceeds a threshold level indicative of said integrated circuit being in an active state, and
clocking means responsive to said sensing means for controlling pulse width of said clock pulses whereby positive pulses are provided during an active state.
7. Apparatus as defined by claim 6 wherein said clock means includes bistable circuit means having two output voltage levels corresponding to voltage supply currents exceeding said threshold level and not exceeding said threshold level, respectively.
8. A method of clocking an integrated circuit having active periods and inactive periods and which operates in response to positive pulses of a clock signal comprising the steps of:
(a) monitoring said integrated circuit to identify active periods,
(b) providing positive pulses to said integrated circuit during said active periods, and
(c) removing positive pulses from said integrated circuit during inactive periods.
9. The method as defined by claim 8 wherein step (a) includes sensing power supply current to said integrated circuit, supply current above a threshold level being indicative of an active period.
10. A method of providing timing to an integrated circuit function unit which logically operates on variable length numbers during active periods of variable lengths of time comprising the steps of:
(a) generating a clock signal having variable clock pulses for said integrated circuit,
(b) monitoring said integrated circuit to identify active periods, and
(c) controlling said variable clock pulses in response to identified active periods.
11. The method as defined by claim 10 wherein step (b) includes sensing power supply current to said integrated circuit whereby supply current above a threshold level is indicative of an active period.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/908,315 US5324992A (en) | 1992-07-01 | 1992-07-01 | Self-timing integrated circuits having low clock signal during inactive periods |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US07/908,315 US5324992A (en) | 1992-07-01 | 1992-07-01 | Self-timing integrated circuits having low clock signal during inactive periods |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| US5324992A true US5324992A (en) | 1994-06-28 |
Family
ID=25425578
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| US07/908,315 Expired - Lifetime US5324992A (en) | 1992-07-01 | 1992-07-01 | Self-timing integrated circuits having low clock signal during inactive periods |
Country Status (1)
| Country | Link |
|---|---|
| US (1) | US5324992A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5420528A (en) * | 1993-05-06 | 1995-05-30 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit having a function of reducing a consumed current |
| US5450027A (en) * | 1994-04-08 | 1995-09-12 | At&T Corp. | Low-power-dissipation CMOS circuits |
| US5479117A (en) * | 1995-01-11 | 1995-12-26 | At&T Corp. | Hybrid data processing system including pulsed-power-supply CMOS circuits |
| EP1006427A2 (en) * | 1998-12-01 | 2000-06-07 | Robert Bosch Gmbh | Microcontroller with a monitoring device for setting an active and an inactive operating state |
| US6829573B1 (en) * | 1998-01-13 | 2004-12-07 | Advantest Corporation | Method and system to search for critical path |
| WO2004107144A1 (en) * | 2003-05-27 | 2004-12-09 | Koninklijke Philips Electronics N.V. | Monitoring and controlling power consumption |
| US20060083052A1 (en) * | 2002-03-27 | 2006-04-20 | The Regents Of The University Of California | Self reverse bias low-power high-performance storage circuitry and related methods |
| US20060253719A1 (en) * | 2003-07-25 | 2006-11-09 | Tam Simon M | Power supply voltage droop compensated clock modulation for microprocessors |
| US20070121358A1 (en) * | 2005-11-28 | 2007-05-31 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit |
| US20080284504A1 (en) * | 2005-11-28 | 2008-11-20 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4387449A (en) * | 1979-11-08 | 1983-06-07 | Nippon Electric Co., Ltd. | Programmable memory device having reduced power consumption upon unselection |
| US4697097A (en) * | 1986-04-12 | 1987-09-29 | Motorola, Inc. | CMOS power-on detection circuit |
| US4716463A (en) * | 1986-10-24 | 1987-12-29 | Zenith Electronics Corporation | Power down sense circuit |
| US4851987A (en) * | 1986-01-17 | 1989-07-25 | International Business Machines Corporation | System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur |
| US4999516A (en) * | 1989-07-17 | 1991-03-12 | At&E Corporation | Combined bias supply power shut-off circuit |
| US5025344A (en) * | 1988-11-30 | 1991-06-18 | Carnegie Mellon University | Built-in current testing of integrated circuits |
| US5128558A (en) * | 1989-10-18 | 1992-07-07 | Texas Instruments Incorporated | High speed, low power consumption voltage switching circuit for logic arrays |
-
1992
- 1992-07-01 US US07/908,315 patent/US5324992A/en not_active Expired - Lifetime
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4387449A (en) * | 1979-11-08 | 1983-06-07 | Nippon Electric Co., Ltd. | Programmable memory device having reduced power consumption upon unselection |
| US4851987A (en) * | 1986-01-17 | 1989-07-25 | International Business Machines Corporation | System for reducing processor power consumption by stopping processor clock supply if a desired event does not occur |
| US4697097A (en) * | 1986-04-12 | 1987-09-29 | Motorola, Inc. | CMOS power-on detection circuit |
| US4716463A (en) * | 1986-10-24 | 1987-12-29 | Zenith Electronics Corporation | Power down sense circuit |
| US5025344A (en) * | 1988-11-30 | 1991-06-18 | Carnegie Mellon University | Built-in current testing of integrated circuits |
| US4999516A (en) * | 1989-07-17 | 1991-03-12 | At&E Corporation | Combined bias supply power shut-off circuit |
| US5128558A (en) * | 1989-10-18 | 1992-07-07 | Texas Instruments Incorporated | High speed, low power consumption voltage switching circuit for logic arrays |
Cited By (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5420528A (en) * | 1993-05-06 | 1995-05-30 | Kabushiki Kaisha Toshiba | Semiconductor integrated circuit having a function of reducing a consumed current |
| US5450027A (en) * | 1994-04-08 | 1995-09-12 | At&T Corp. | Low-power-dissipation CMOS circuits |
| US5479117A (en) * | 1995-01-11 | 1995-12-26 | At&T Corp. | Hybrid data processing system including pulsed-power-supply CMOS circuits |
| EP0722222A1 (en) * | 1995-01-11 | 1996-07-17 | AT&T Corp. | Hybrid data processing system including pulsed-power-supply CMOS circuits |
| US6829573B1 (en) * | 1998-01-13 | 2004-12-07 | Advantest Corporation | Method and system to search for critical path |
| EP1006427A3 (en) * | 1998-12-01 | 2003-05-14 | Robert Bosch Gmbh | Microcontroller with a monitoring device for setting an active and an inactive operating state |
| EP1006427A2 (en) * | 1998-12-01 | 2000-06-07 | Robert Bosch Gmbh | Microcontroller with a monitoring device for setting an active and an inactive operating state |
| US20060083052A1 (en) * | 2002-03-27 | 2006-04-20 | The Regents Of The University Of California | Self reverse bias low-power high-performance storage circuitry and related methods |
| US7466191B2 (en) * | 2002-03-27 | 2008-12-16 | The Regents Of The University Of California | Self reverse bias low-power high-performance storage circuitry and related methods |
| WO2004107144A1 (en) * | 2003-05-27 | 2004-12-09 | Koninklijke Philips Electronics N.V. | Monitoring and controlling power consumption |
| US20060253719A1 (en) * | 2003-07-25 | 2006-11-09 | Tam Simon M | Power supply voltage droop compensated clock modulation for microprocessors |
| US7409568B2 (en) * | 2003-07-25 | 2008-08-05 | Intel Corporation | Power supply voltage droop compensated clock modulation for microprocessors |
| US20070121358A1 (en) * | 2005-11-28 | 2007-05-31 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit |
| US20080284504A1 (en) * | 2005-11-28 | 2008-11-20 | Oki Electric Industry Co., Ltd. | Semiconductor integrated circuit |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3636477B2 (en) | Precharge output driver circuit | |
| EP0604195B1 (en) | Dual dynamic sense amplifiers for a memory array | |
| JP2621993B2 (en) | Flip-flop circuit | |
| US4806786A (en) | Edge set/reset latch circuit having low device count | |
| EP0141681B1 (en) | Test input multiplexing circuit | |
| US5324992A (en) | Self-timing integrated circuits having low clock signal during inactive periods | |
| EP0887935B1 (en) | Noise isolation circuit | |
| US5546026A (en) | Low-voltage high-performance dual-feedback dynamic sense amplifier | |
| US6201431B1 (en) | Method and apparatus for automatically adjusting noise immunity of an integrated circuit | |
| JP2743878B2 (en) | Input buffer circuit | |
| US4894559A (en) | Buffer circuit operable with reduced power consumption | |
| US5751160A (en) | Output buffer with improved operational speed and transitional current | |
| US4963774A (en) | Intermediate potential setting circuit | |
| US5198709A (en) | Address transition detector circuit | |
| US4736119A (en) | Dynamic CMOS current surge control | |
| US6037827A (en) | Noise isolation circuit | |
| EP0647898B1 (en) | An apparatus for activating a logic device | |
| US5463335A (en) | Power up detection circuits | |
| US5047673A (en) | High speed output structure suitable for wired-OR structure | |
| JP3039146B2 (en) | Data processing system having a programmable mode for selecting operation at one of a plurality of power supply potentials | |
| US6297682B1 (en) | Differential sense amplifier circuit | |
| JP3259304B2 (en) | Microprocessor | |
| JPS63119323A (en) | Insulated gate type output buffer circuit | |
| JP2637734B2 (en) | Output circuit | |
| JP3049713B2 (en) | Drive signal forming circuit and image sensor |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AS | Assignment |
Owner name: CARNEGIE MELLON UNIVERSITY, PENNSYLVANIA Free format text: ASSIGNMENT OF ASSIGNORS INTEREST.;ASSIGNOR:MALY, WOJCIECH;REEL/FRAME:006204/0996 Effective date: 19920625 |
|
| STCF | Information on status: patent grant |
Free format text: PATENTED CASE |
|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| FPAY | Fee payment |
Year of fee payment: 4 |
|
| FPAY | Fee payment |
Year of fee payment: 8 |
|
| FEPP | Fee payment procedure |
Free format text: PAYOR NUMBER ASSIGNED (ORIGINAL EVENT CODE: ASPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY Free format text: PAYER NUMBER DE-ASSIGNED (ORIGINAL EVENT CODE: RMPN); ENTITY STATUS OF PATENT OWNER: LARGE ENTITY |
|
| FPAY | Fee payment |
Year of fee payment: 12 |