JP2007305816A - Method for manufacturing field effect transistor - Google Patents

Abstract

In manufacturing a field effect transistor, a gate resistance is reduced and a parasitic capacitance between a gate and an ohmic electrode is reduced.
A step of forming an insulating film 5 on a surface of a semiconductor active layer 3 on a semiconductor substrate 1, a step of forming an opening 5a penetrating the insulating film 5, and the insulating film 5 and the opening 5a exposed A step of laminating a refractory metal film 6 and a dry-reducible low-resistance metal film 7A on the surface of the semiconductor active layer 3, a step of etching the laminated film to form a T-shaped electrode 9, and an electrode 9 and forming a protective film 12 that covers at least the upper and side surfaces of the low-resistance metal film 7A, and removing part or all of the insulating film 5 with an etchant containing hydrofluoric acid in the presence of the protective film 12. And a step of forming a void 10 in the vicinity of the electrode 9. The insulating film 5 can be removed while protecting the electrode 9 from hydrofluoric acid with the protective film 12.
[Selection] Figure 1

Description

  The present invention relates to a method for manufacturing a field effect transistor.

  A field effect transistor using a compound semiconductor typified by GaAs has been widely put into practical use as a high-frequency semiconductor device for mobile communication portable terminals. In general, for a gate electrode of a field effect transistor using a compound semiconductor, it is desired to achieve both low gate resistance and low parasitic capacitance between the gate / ohmic electrode in order to improve high frequency characteristics. Therefore, in many cases, a method of forming a gate electrode structure having a T-shaped cross section using Au (gold) or Pt (platinum) which is a low resistance metal is used.

  Various techniques for forming a T-shaped gate electrode structure have been devised so far. FIG. 2 shows a process of forming a T-shaped gate electrode, which is disclosed in Patent Document 1 or the like, using Au as a low resistance metal and using an insulating film as a mold.

First, as shown in FIG. 2 (a), a semiconductor active layer 3 (n-GaAs layer) is formed on a semiconductor substrate 1 (GaAs substrate) via a buffer layer 2 (non-doped GaAs layer), and on that. The insulating film 5 (SiO ₂ film) is deposited by the CVD method or the like, the cap layer 4 (n + GaAs layer) is formed with a predetermined gap, and the resist is used as a mask for the insulating film 5 at the part where the gate is to be formed. (Not shown) The opening 5a is formed using a dry etching method or the like.

  Next, as shown in FIG. 2B, a refractory metal film 6 (hereinafter referred to as WSi film 6) made of WSi is formed on the surface of the semiconductor active layer 3 exposed from the insulating film 5 and the opening 5a by sputtering. A low resistance metal film 7 (hereinafter referred to as Au film 7) made of Au (or Pt or the like) is continuously sputter deposited thereon. On the laminated metal film of the WSi film 6 / Au film 7, a mask (hereinafter referred to as a resist mask) 8 made of a resist corresponding to a desired gate electrode width is formed.

  In this state, the WSi film 6 / Au film 7 laminated metal film is processed and removed by an ion milling method, and then the WSi film is applied to the underlying insulating film 5 by the RIE method (reactive ion etching method). By selectively removing by dry etching, as shown in FIG. 2C, a T-shaped gate electrode 9 having a larger upper portion located on the insulating film 5 than the lower portion connected to the semiconductor active layer 3 is formed. Then, the surrounding insulating film 5 is exposed.

Next, the resist 8 is removed, and the insulating film 5 is removed with hydrofluoric acid, thereby forming a gap 10 in the vicinity of the gate electrode 9 as shown in FIG.
Next, after an ohmic electrode (not shown) made of an alloy of Au, Ge, and Ni is formed on the cap layer 4, the gate / ohmic electrode and the semiconductor surface are formed as shown in FIG. A passivation film 11 (SiN film) that protects the surface, that is, a passivation film SiN11 that covers the exposed surfaces of the gate electrode 9, the semiconductor active layer 3, and the cap layer 4 is deposited by a CVD method or the like.

As described above, a field effect transistor in which the parasitic capacitance between the gate and the ohmic electrode is reduced by the gap 10 can be formed.
JP-A-8-306707

  In the conventional method of forming a WSi / Au T-shaped gate electrode using Au as a low resistance metal, it is difficult to dry etch Au, so the ion milling method and the RIE method are used in combination as described above. It was essential to do.

  Therefore, there is a need for an alternative process that uses low-resistance metals such as Al and Cu that can be easily processed by dry etching to improve yield, especially in processes that target compound semiconductor wafers with a large diameter (6 inches). It was done.

  However, since low resistance metals such as Al and Cu are easily dissolved in hydrofluoric acid, when the insulating film is removed with hydrofluoric acid to form a gap in the vicinity of the gate electrode, Al and Cu are also dissolved. Therefore, it was difficult to form a T-shaped gate electrode itself. Therefore, establishment of a method for reducing the parasitic capacitance between the gate / ohmic electrode has been demanded.

  The present invention solves the above-mentioned problems, and it is possible to reduce the parasitic capacitance between the gate / ohmic electrode while reducing the gate resistance by using an electrode material that can be easily processed by a dry etching method. The object is to provide a manufacturing method.

  In order to solve the above problems, the present invention forms a gate electrode using Al, Cu or the like as a low resistance metal, forms a protective film covering the upper surface and side surfaces of the low resistance metal, and the gate electrode is formed with the protective film. The insulating film is removed while protecting from hydrofluoric acid.

  That is, the field effect transistor manufacturing method of the present invention includes a step of forming an insulating film on a surface of a semiconductor active layer on a semiconductor substrate, a step of forming an opening penetrating the insulating film, the insulating film, and its A step of laminating a refractory metal and a low-resistance metal that can be dry-etched on the surface of the semiconductor active layer exposed from the opening; and etching the laminated film of the refractory metal and the low-resistance metal into the opening. A step of forming a T-shaped gate electrode having a larger upper portion located on the insulating film than the lower portion connected to the semiconductor active layer, and protection for covering at least the upper and side surfaces of the low-resistance metal in the gate electrode A step of forming a film, and a step of removing a part or all of the insulating film with an etchant containing hydrofluoric acid in the presence of the protective film to form a gap in the vicinity of the gate electrode Characterized in that it has a.

The low resistance metal may be aluminum or an alloy thereof, or copper or an alloy thereof.
When the insulating film is a silicon oxide film and the protective film is a silicon nitride film, the silicon nitride film is preferably deposited continuously after nitriding the upper and side surfaces of the low resistance metal film.

  When the insulating film is a silicon oxide film and the protective film is a silicon nitride film, the hydrogen atom concentration in the silicon nitride film is preferably 10% or less of the hydrogen atom concentration in the insulating film.

  In the method of manufacturing a field effect transistor according to the present invention, a gate electrode is formed using a refractory metal and a low-resistance metal that can be dry-etched, and a protective film that covers the upper surface and side surfaces of the low-resistance metal is formed. Thus, the parasitic capacitance is reduced by forming the air gap by removing the insulating film while protecting the gate electrode from hydrofluoric acid. Since Al, Cu or the like is used as the low resistance metal, the ion milling method required in the process of forming the conventional electrode structure using Au or Pt becomes unnecessary, and it can be easily processed by dry etching. The cost of the material can be reduced.

Hereinafter, embodiments of the present invention will be specifically described with reference to the drawings.
FIG. 1 is a process cross-sectional view illustrating a method for manufacturing a field effect transistor according to an embodiment of the present invention. In FIG. 1, the same members as those shown in FIG.

First, as shown in FIG. 1 (a), a semiconductor active layer 3 (n-GaAs layer) is formed on a semiconductor substrate 1 (GaAs substrate) via a buffer layer 2 (non-doped GaAs layer), and on that. Insulating film 5 (SiO ₂ film) is deposited by O ₃ / TEOS (tetraethoxysilane) method or PE (Plasma-Enhanced) -CVD method and the like, and a predetermined gap is provided to form cap layer 4 (n + GaAs layer). Then, the opening 5a is formed on the insulating film 5 at the portion where the gate is to be formed by using a resist as a mask (not shown) using a dry etching method or the like. This insulating film 5 is, for the purpose of improving the stability to GaAs surface, it may have a multilayer structure in which second layer (SiO ₂ film) is laminated after depositing the first layer by PE-CVD method or the like (SiNx film) (Not shown).

Then, an opening 5a having a width capable of obtaining a desired gate length is formed in the insulating film 5 at a portion where the gate is formed, using a resist pattern as a mask (not shown), and plasma such as CHF ₃ gas or SF ₆ gas is used. The through-hole is formed by using a dry etching method such as a high frequency inductively coupled plasma etching method. The resist pattern used for the mask is removed by an ashing method or the like.

  Next, as shown in FIG. 1B, on the surface of the semiconductor active layer 3 exposed from the insulating film 5 and its opening 5a, a refractory metal film 6 (hereinafter referred to as WSi film 6) made of WSi, A low-resistance metal film 7A (hereinafter referred to as an Al film 7A) made of Al (or Al alloy) is successively deposited at a desired film thickness by sputtering. Then, a resist mask 8 corresponding to a desired upper electrode width is formed on the laminated metal film of the WSi film 6 / Al film 7A.

  In this state, by performing a dry etching method such as a high frequency inductively coupled plasma etching method using a plasma of Cl gas or the like, as shown in FIG. 1C, a laminated metal of the WSi film 6 / Al film 7A. The film is etched to form a T-shaped gate electrode 9 having a larger upper portion located on the insulating film 5 than the lower portion connected to the semiconductor active layer 3, and the surrounding insulating film 5 is exposed.

  Next, as shown in FIG. 1D, after removing the resist mask 8, the side surface of the WSi film 6 is also covered here so as to cover at least the upper surface and the side surface of the Al film 7A in the gate electrode 9. A protective film 12 (SiN film) is formed so as to cover it.

For this purpose, a protective film 12 having a desired film thickness is deposited by CVD on the entire surface of the substrate having the gate electrode 9 and the insulating film 5 above, and the upper portion of the gate electrode 9 is formed on the protective film 12. A resist mask (not shown) covering an area wider than the width is formed, and in that state, a dry etching method such as a high frequency inductively coupled plasma etching method using a plasma such as CHF ₃ gas or SF ₆ gas is performed. As a result, the protective film 12 is processed to a size corresponding to the resist mask, and the surrounding insulating film 5 is exposed. Then, the resist mask is removed by an ashing method or the like. Before the protective film 12 is deposited on the entire surface of the substrate, the upper surface and the side surface of the laminated metal film of the WSi film 6 / Al film 7A are subjected to nitriding treatment, whereby the protective film 12 and the WSi film 6 / Al film 7A are formed. The adhesion of the laminated metal film may be improved.

  Next, by removing a part or all of the insulating film 5 with an etching solution containing hydrofluoric acid in the presence of the protective film 12 processed into a predetermined shape, as shown in FIG. The entire T-shaped gate electrode 9 (excluding the lower surface) is provided, and an air gap 10 is formed between the lower side, that is, the cap layer 4 disposed on both sides thereof.

  That is, all or part of the insulating film 5 is removed by using the hydrofluoric acid etch rate selectivity between the protective film 12 and the insulating film 5 while protecting the gate electrode 9 from hydrofluoric acid by the protective film 12. . As a result, the T-shaped gate electrode 9 is formed using the insulating film 5 as a mold, and the gap 10 is formed.

At this time, in order to improve the selectivity between the protective film 12 (SiNx film) and the insulating film 5 (SiO ₂ film), the hydrogen atom concentration in the protective film 12 is set to a low hydrogen concentration, specifically, The hydrogen atom concentration is preferably 10% or less. Thereby, the etching rate of the protective film 12 against hydrofluoric acid can be extremely slowed, and the controllability can be further improved.

  Next, an ohmic electrode (not shown) is formed on the cap layer 4 by sintering with an ohmic metal made of an alloy of Au, Ge, and Ni, and then, as shown in FIG. A passivation film 11 (SiNx film) that protects the surface of the ohmic electrode and the semiconductor surface, that is, the passivation film 11 that covers the exposed surface of the gate electrode 9, the semiconductor active layer 3, and the cap layer 4 provided with the protective film 12, etc. Deposit with.

As described above, a field effect transistor in which the parasitic capacitance between the gate and the ohmic electrode is reduced by the gap 10 can be formed.
In this embodiment, it is described that Al or an Al alloy is used as the low resistance metal. However, when the Cu or Cu alloy is used, the T-shaped gate electrode 9 and the gap 10 can be formed in the same manner. It is.

  INDUSTRIAL APPLICABILITY The present invention is useful for manufacturing a field effect transistor using a compound semiconductor that is widely used as a high-frequency semiconductor device for mobile communication portable terminals.

Process sectional drawing explaining the manufacturing method of the field effect transistor in one Embodiment of this invention Process sectional drawing explaining the manufacturing method of the field effect transistor conventionally performed

Explanation of symbols

1 Semiconductor substrate 3 Semiconductor active layer 5 Insulating film
5a Opening 6 High melting point metal film 7 Low resistance metal film 9 Electrode
10 Air gap
12 Protective film

Claims (4)

Forming an insulating film on the surface of the semiconductor active layer on the semiconductor substrate;
Forming an opening that penetrates the insulating film;
Laminating a refractory metal and a low-resistance metal capable of dry etching on the surface of the semiconductor active layer exposed from the insulating film and the opening;
Etching the laminated film of the refractory metal and the low resistance metal to form a T-shaped gate electrode having a larger upper portion located on the insulating film than the lower portion connected to the semiconductor active layer in the opening And a process of
Forming a protective film covering at least the upper and side surfaces of the low-resistance metal in the gate electrode;
And a step of removing a part or all of the insulating film with an etchant containing hydrofluoric acid in the presence of the protective film to form a gap in the vicinity of the gate electrode.   2. The method of manufacturing a field effect transistor according to claim 1, wherein the low resistance metal is aluminum or an alloy thereof, or copper or an alloy thereof.   2. The field effect according to claim 1, wherein the insulating film is a silicon oxide film, the protective film is a silicon nitride film, and the silicon nitride film is continuously deposited after nitriding the upper surface and side surfaces of the low resistance metal film. A method for manufacturing a transistor.   2. The field effect transistor according to claim 1, wherein the insulating film is a silicon oxide film, the protective film is a silicon nitride film, and the hydrogen atom concentration in the silicon nitride film is 10% or less of the hydrogen atom concentration in the insulating film. Manufacturing method.

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