JP7035223B2 - Method for Forming Gate Structure of III-V Field Effect Transistor - Google Patents

Description

This disclosure generally relates to a method of forming a gate structure of a field effect transistor (FET), and more specifically, to form a gate structure of a field effect transistor (FET) without using any subtractive processing or lift-off processing. Regarding how to do it.

As is technically known, many monolithic micros having Group III nitride semiconductors, sometimes referred to as nitride semiconductors, such as gallium nitride based (AlGaN / GaN) high electron mobility transistors (HEMTs). Wave integrated circuits (MMICs) are increasingly being used in high frequency and high power applications. In the following, group III nitrides may also be referred to as group III-N, which is a ternary alloy such as, for example, a binary InN, GaN, AlN alloy, for example an Al _x Ga _1-x N (AlGaN) alloy. , And other nitrogen-based alloys.

To realize the potential of these HEMT devices, low resistance, good edge sensitivity, reliable metal-metal contacts, and metal-semiconductor ohmic contacts and Schottky contacts (gate formation). Because) is necessary to achieve. Most Group III-N foundry metal-metal and metal-semiconductor low resistance ohmic contacts are the lowest metal-semiconductor ohmic contacts to reduce sheet resistance (for transmission lines and ohmic contacts) and for active devices. Gold (Au) is used to reduce the oxidation during high temperature annealing required to achieve contact resistance. A suitable contact metal for Schottky gate contacts is nickel, thanks to its large work function (≧ 5 eV).

As is also known, in many monolithic microwave integrated circuits (MMICs) and other integrated circuits (ICs), electricity is applied to the bottom of the MMIC for both ground and electrical signals to the mounted chips. Connections are made and these connections are also referred to as metallization (also referred to as front side metallization) on the wafer through conductive vias that pass through the substrate and / or at least a portion of the substrate in a semiconductor epitaxial layer. Made for electrical contacts that connect to).

Traditionally, group III-N HEMT MMICs and devices are manufactured in group III-V foundries by lift-off based processing. However, recently, Group III-N HEMTs have begun to be manufactured in a Si CMOS foundry environment using Au-free subtractive processing techniques such as high yield silicon (Si). More specifically, the "lift-off" process is one in which the mask has a window that exposes a selection of the surface on which the material should be deposited. The material is deposited on the mask and a portion of the material passes through the window onto the exposed selection of the surface. Using the solvent, the mask is lifted off with a portion of the material on the mask (an undesired portion of the deposited material), leaving the desired portion of the material on the exposed selection portion of the surface. The "subtractive" process is one in which the material is first deposited over the entire surface. A mask is then formed covering only the selected portion of the deposited material (the portion that will remain after treatment), exposing the undesired portion of the deposited material. The etchant is then brought into contact with the mask, thereby removing the exposed unwanted portion, while preventing the mask from removing the desired portion of the material that is covered.

It is well known that for Si CMOS foundries, the yield and cost of III-V compound semiconductor devices and circuits (processed by traditional III-V foundries) are small wafer yields, processing. It has long been limited by increased substrate handling within, extensive use of lift-off-based processing techniques to define metal lines, and the use of time-consuming electron beam lithography for sub-500nm gate lithography. Si CMOS foundry environment, on the other hand, has large wafer yields, large wafer diameters (≧ 200 mm), highly automated cassette-to-cassette wafer manufacturing or processing tools, subtractive processing technologies, advanced optical lithography cluster tools and technologies ( It is possible to create a sub 100 nm model), and has the benefit of Moore's Law paradigm that drives both the development of equipment and the development of technology nodes.

However, as mentioned above, in order to take advantage of the Si foundry substrate and associated Si CMOS wafer volume, the Group III-N process being developed must be Au-free. Gold is a deep-level trap dopant in Si. Therefore, Au is not allowed on the front-end or back-end of Si CMOS foundry production lines due to serious contamination concerns that can cause fatal yield problems.

Therefore, gold-free processing of GaN (or other III-V) device wafers in a Si foundry environment is a metallization suitable for the Si foundry back end of line (BOOL), such as aluminum (Al) or copper (Cu). Requires the use of. Copper is the most attractive of these metals to use because of its excellent conductivity and electromigration resistance. However, due to the lack of volatile copper dry etching by-products, photoresist masking and plasma etching have been used with great success in aluminum with photolithography techniques that make copper easily subtractive. Cannot be patterned. A damascene process (also subtractive) was developed to process copper. In the Cu damascene process, the host insulator material for copper, which is typically the underlying insulating layer (usually silicon dioxide), is patterned to have an open trench where the copper should be formed. A thick coating of copper is deposited on this insulating layer that significantly overfills the trench, and chemical mechanical flattening (CMP) is used to remove excess copper extending over the top surface of the insulating layer. The Cu filled in the trench of the insulating layer is not removed, but becomes a patterned conductive interconnect.

As is also technically known, Cu is manageable, but it also poses its own risk of contamination to the Si foundry. The barrier layer should completely surround all copper interconnects as the diffusion of copper into the surrounding material will degrade their properties. Typically as part of a thin tantalum (Ta) and / or tantalum nitride (TaN) metal layer (Ta / TaN / Cu plated seed metal stack) that acts as a diffusion barrier along the bottom and sides of the Cu metal interconnect. ), The trench is lined. After Cu CMP, the top surface of the interconnect metal is coated with SiN _x , which acts as a top interfacial diffusion barrier to prevent oxidation during interlayer oxide deposition and for further interconnect formation (trench etching of silicon dioxide). Acts as an etching stop layer (inside). However, additional process complexity is added when back-to-front metal interconnects are assisted by wafer-penetrating vias or semiconductor layer-penetrating vias that require chlorine (or other oxidant) -based etching to form vias. Occurs. Chloride-based etching by-products are non-volatile and this etching process results in a degraded Cu interface.

As is also technically known, field effect transistors (FETs) used in high frequency applications are typically III-V devices such as gallium nitride (GaN) HEMT FETs. Today, many of these GaN FETs are manufactured in foundries specifically designed to make these GaN FETs, but these devices are currently designed to make silicon (Si) devices. It is also desirable to be manufactured in a foundry that has been manufactured.

According to the present disclosure, a method for forming a gate structure of a field effect transistor is provided, in which a semiconductor is prepared and a dielectric layer having an opening on a selected portion of the semiconductor is placed on the semiconductor. The gate metal is formed and selectively deposited on the dielectric layer and in the openings using a gate metal deposition process, and the deposited gate metal does not adhere to the dielectric layer by the gate metal deposition process. Have that.

In one embodiment, the deposited gate metal does not adhere to the dielectric layer by the gate metal deposition process, but to the semiconductor.

In one embodiment, an insulating layer is formed on the semiconductor, the openings expose the insulating layer, and the deposited gate metal does not adhere to the dielectric layer by the gate metal deposition process, but to the insulating layer.

In one embodiment, the method comprises chemically reducing the original gate metal.

In one embodiment, the deposition process is atomic layer growth (ALD).

In one embodiment, a method of forming a gate structure of a field effect transistor is provided. The method comprises preparing a semiconductor, forming a dielectric layer having an opening on a selected portion of the semiconductor on the semiconductor, and forming the original gate metal in the opening.

In one embodiment, the method comprises chemically reducing the original gate metal to a gate structure.

In one embodiment, chemical reduction involves annealing the deposited original gate metal in a reducing agent.

In one embodiment, the initial gate metal is an oxide.

In one embodiment, the initial gate metal is nickel oxide.

In one embodiment, the initial gate metal formation has atomic layer deposition (ALD).

In one embodiment, a method of forming a nickel structure on a selected portion of a group III-V semiconductor is provided. The method forms a dielectric layer with an opening over a selected portion of the semiconductor on the semiconductor, forms nickel oxide on the surface exposed by the opening, and anneals nickel oxide in a reducing agent. It involves converting nickel oxide to nickel.

In one embodiment, a method of forming a gate structure of a field effect transistor is provided. The method comprises preparing a semiconductor, forming a dielectric layer having an opening on a selected portion of the semiconductor on the semiconductor, and selectively depositing a gate metal in the opening.

In one embodiment, depositing gate metal has atomic layer growth (ALD).

In one embodiment, a method of forming a gate structure of an electric field effect transistor is provided, in which a semiconductor is prepared, a non-oxide dielectric layer is formed on the surface of the semiconductor, and the non-oxide is formed. The dielectric layer has openings placed on selected parts of the surface of the semiconductor, the non-oxide dielectric layer, and the exposed selected parts of the surface of the semiconductor are gate metal deposition processes. The gate metal deposited on the semiconductor has not adhered to the dielectric layer of the non-oxide, but to the oxide formed on the exposed and selected portion of the surface of the semiconductor.

In one embodiment, the method comprises forming an oxide insulating layer on the surface of the semiconductor, the openings exposing the oxide insulating layer and the deposited gate metal being a gate metal deposition process. Does not adhere to the non-oxide dielectric layer, but to the oxide insulating layer.

In one embodiment, a method of forming a gate structure on a selected portion of a group III-V semiconductor is provided, wherein the method comprises a dielectric layer having an opening over the selected portion of the semiconductor, the semiconductor. It has the ability to form on top of and form nickel oxide on the surface exposed by the openings and anneal the nickel oxide in a reducing agent to convert the nickel oxide to nickel.

In one embodiment, a method of forming a gate structure of a field effect transistor is provided, wherein the semiconductor is prepared and a dielectric layer having an opening over a selected portion of the semiconductor is formed on the semiconductor. Then, by atomic layer growth, gate metal is selectively deposited in the opening, and the deposited gate metal is chemically reduced.

The inventor has recognized that the selective deposition of NiO for the production of nickel-based gates of GaN HEMTs is based on traditional lift-off in both III-V foundries and subtractive silicon foundries. Overcome the limitations of gate manufacturing. Treatments based on lift-off in III-V foundries can lead to unwanted photoresist residues that adversely affect the FET, which is one or more of the low yield, performance degradation, and / or reliability degradation of the FET. On the other hand, in the subtractive treatment of Ni-based gates in Si foundries, nickel (Ni), which is a suitable gate structure metal, is dry-etched (usually sputter / physical etching, not chemical etching). It is difficult because it is difficult. As a result, the etching of Ni is primarily a physical etching that is essentially non-selective and typically uses a sacrificial dielectric layer to form the gate structure of the FET. The use of sacrificial dielectric layers instead can negatively impact the ability to freely design gamma gate structures with optimal gamma gate top-channel distances. This is because the inside of the gate channel can be inadvertently etched during the etching process of the nickel gate structure. Moreover, in both gamma-gate and T-gate structures, the low volatility of Ni dry etching products often leads to redeposition of Ni-containing etching products, which in turn it yields and / or performance and /. Or it can cause defects that affect reliability. Alternatively, the use of wet etching to define nickel-based gates with subtractive treatment can lead to undercuts in gate metal formation, which in turn leads to poor dimensional control (increased performance variation and low yield). ), And causes a decrease in reliability.

The inventor also recognized that here, using ALD, a nickel oxide (NiO) gate metal layer was selectively deposited in the openings, and the NiO layer was deposited on a non-oxide layer such as SiNx. Will not adhere and will adhere to a semiconductor layer such as an AlGaN layer terminated by a natural oxide film that tends to form -OH groups during the NiO ALD deposition process, thereby supporting ALD deposition. That is, AlGaN, which is a semiconductor, has some natural oxide film on which NiO adheres in ALD, whereas on the non-oxide layer called SiNx, NiO has a significant concentration of -OH to be bonded. Since there are no groups (such as those present on an oxide layer such as SiO ₂ or Al ₂ O ₃ ), NiO metal deposition on the non-oxide layer is suppressed. The inventor's perception of the -OH group dependence of this deposit is that the deposited oxide (eg, SiO ₂ or Al ₂ O ₃ ), a natural oxide film, or an oxygen plasma treated surface (eg, an oxidized AlGaN surface or). It is the basis of selective gate metal deposition on the SiNx surface).

Therefore, the present invention utilizes selective atomic layer growth of nickel oxide (NiO) for the formation of Ni-based gates, which deposits NiO only where Ni (or NiO) is needed. It is a thing. As a result, there is no risk of resist residue trapping as in lift-off based treatments (III-V foundries), and there is no need for subtractive wet or dry etching (Si foundries). In addition, the use of atomic layer growth (ALD) prevents damage to the device surface that can be caused by sputtering-based Ni deposition (as is common in Si foundries). NiO may itself be a gate (which has a work function of 5 eV or higher like Ni) or is reduced (completely or partially) to Ni in hydrogen for Ni gate formation. May be done. Finally, ALD metal deposition avoids physical impact-induced surface damage that can be inflicted by physical vapor deposition techniques.

Details of one or more embodiments of the present disclosure are described in the accompanying drawings and the description below. Other features, objectives and advantages of the present disclosure will be apparent from these descriptions and drawings and claims.

According to the present disclosure, here is a simplified cross-sectional view of a field effect transistor (FET) which is a high electron mobility transistor (HEMT). It is a simplified plan view of a part of the FET of FIG. 1A taken along the straight line 1B-1B of FIG. 1A. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. The portion surrounded by the arrow in FIG. 2D is an enlarged portion of FIG. 2D. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. 2A-2U are schematic cross-sectional views of a semiconductor structure at various stages of manufacturing the semiconductor structure in accordance with the present disclosure. It is an exploded schematic cross-sectional view of a part of FIG. 2U pointed out by an arrow 2U'-2U'. FIG. 2 is a schematic cross-sectional view of one of the plurality of gate electrode structures used in the structure of FIG. 2A-2T according to the present disclosure. FIG. 2 is a schematic cross-sectional view of another exemplary embodiment of the plurality of gate electrode structures that may be used in the structure of FIG. 2A-2T. FIG. 2 is a schematic cross-sectional view of one of a plurality of electrodes used as source and drain electrode structures in the structure of FIG. 2A-2U according to the present disclosure. FIG. 2 is a schematic cross-sectional view of one of a plurality of electrodes used as source and drain electrode structures in the structure of FIG. 2A-2U, according to another embodiment of the present disclosure. 4A and 4A1 are a pair of schematic cross-sectional views useful for understanding the low temperature annealing process used in forming semiconductor structures according to the present disclosure. 4A and 4A1 are a pair of schematic cross-sectional views useful for understanding the low temperature annealing process used in forming semiconductor structures according to the present disclosure. 4B and 4B1 are a pair of schematic cross-sectional views useful for understanding other low temperature annealing processes used in forming semiconductor structures according to the present disclosure. 4B and 4B1 are a pair of schematic cross-sectional views useful for understanding other low temperature annealing processes used in forming semiconductor structures according to the present disclosure. 5A-5C are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view of a semiconductor structure according to another embodiment of the present disclosure. 5A-5C are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 5B is a schematic cross-sectional view showing an enlarged portion of FIG. 5B of a portion surrounded by arrows 5B'-5B' in FIG. 5B. 5A-5C are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 6A-6D are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 6A-6D are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 6A-6D are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 6C is a schematic cross-sectional view showing an enlarged portion of FIG. 6C of a portion surrounded by arrows 6C'-6C'in FIG. 6C. 6A-6D are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. FIG. 3 is a schematic cross-sectional view showing an enlarged portion of a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 7A-7G are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 8A-8H are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 9A-9E are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 9A-9E are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 9A-9E are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 9A-9E are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 9A-9E are schematic cross-sectional views at various stages of manufacturing a semiconductor structure according to another embodiment of the present disclosure. 10A-10G are schematic cross-sectional views at various stages of manufacture of the semiconductor structure of FIG. 2A-2U and gate electrode structures used at various stages of manufacture thereof, in accordance with the present disclosure. 10A-10G are schematic cross-sectional views at various stages of manufacture of the semiconductor structure of FIG. 2A-2U and gate electrode structures used at various stages of manufacture thereof, in accordance with the present disclosure. 10A-10G are schematic cross-sectional views at various stages of manufacture of the semiconductor structure of FIG. 2A-2U and gate electrode structures used at various stages of manufacture thereof, in accordance with the present disclosure. 10A-10G are schematic cross-sectional views at various stages of manufacture of the semiconductor structure of FIG. 2A-2U and gate electrode structures used at various stages of manufacture thereof, in accordance with the present disclosure. 10A-10G are schematic cross-sectional views at various stages of manufacture of the semiconductor structure of FIG. 2A-2U and gate electrode structures used at various stages of manufacture thereof, in accordance with the present disclosure. 10A-10G are schematic cross-sectional views of the semiconductor structure of FIG. 2A-2U and the gate electrode structures used in the various stages of manufacture according to the present disclosure at various stages of manufacture. 10A-10G are schematic cross-sectional views of the semiconductor structure of FIG. 2A-2U and the gate electrode structures used in the various stages of manufacture according to the present disclosure at various stages of manufacture. 11A-11E is a schematic cross-sectional view of a process used to manufacture a HEMT FET according to the present disclosure. 11A-11E is a schematic cross-sectional view of a process used to manufacture a HEMT FET according to the present disclosure. 11A-11E is a schematic cross-sectional view of a process used to manufacture a HEMT FET according to the present disclosure. 11A-11E is a schematic cross-sectional view of a process used to manufacture a HEMT FET according to the present disclosure. 11A-11E is a schematic cross-sectional view of a process used to manufacture a HEMT FET according to the present disclosure. 12A-12C are schematic cross-sectional views of a process used to manufacture a HEMT FET according to another embodiment of the present disclosure. 12A-12C are schematic cross-sectional views of a process used to manufacture a HEMT FET according to another embodiment of the present disclosure. 12A-12C are schematic cross-sectional views of a process used to manufacture a HEMT FET according to another embodiment of the present disclosure. 13A-13C are schematic cross-sectional views of a process used to manufacture a HEMT FET according to yet another embodiment of the present disclosure. 13A-13C are schematic cross-sectional views of a process used to manufacture a HEMT FET according to yet another embodiment of the present disclosure. 13A-13C are schematic cross-sectional views of a process used to manufacture a HEMT FET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure. 14A-14K are schematic cross-sectional views of a process used to manufacture a MISFET according to yet another embodiment of the present disclosure.

Similar reference symbols in various figures point to similar elements.

Next, with reference to FIGS. 1A and 1B, a semiconductor structure 10 in which a HEMT multi-gate field effect transistor (FET) 12 is formed is shown. The FET 12 is interconnected to a gold-free (ie, gold-free) gate pad 16, as shown in FIG. 1A, where, for example, four, a plurality of gold-free finger-shaped gate electrode contact structures 14 ₁ . _-144 and interconnected by, for example, _two , a plurality of gold-free finger-shaped drain electrode structures 18 _1-182 and a gold-free conductive interconnect structure 24 interconnected to a gold-free drain pad 20. These include, for example, _three , a plurality of gold-free source electrode structures 22 _1-223 . It should be understood that the number of gate electrode structures 14 _{1-14 4} , source electrode structures 22 _{1-22 3} , and drain electrode structures 18 1-18 ₂ is greater (or smaller) _than shown. There may be. In any case, each of the gate electrode structures _{14 1-144} is between the corresponding _one of the drain electrode structures 18 1-182 and the corresponding _one of the source electrode structures 22 _{1-22 3} . The flow of carriers in the semiconductor structure 10 between the corresponding _one of the drain electrode structures 18 1-18 ₂ and the corresponding _one of the source electrode structures 22 1-22 ₃ arranged in To control. Further, as shown in the figure, _two pads 26 ₁ and 262 are provided and connected to both ends of the conductive interconnect structure 24. These pads 26 ₁ and 26 ₂ are connected to the conductive layer 28 formed so as to cover the bottom surface of the semiconductor structure ₁₀ by conductive vias 30 ₁ and 302 passing through the semiconductor structure 10, respectively. As will be described in more detail with respect to FIG. 2A-2T, the front surface side or the top surface side of the structure 10 is processed by a silicon foundry so as to form the multi-gate FET 12.

More specifically, with reference to FIG. 2A, a substrate 32 in which the semiconductor structure 10 is, in more detail, here, for example, silicon (Si), silicon carbide (SiC), or silicon on insulator (SOI). Shown to include. On top of the substrate 32 is a layer of group III-N semiconductor layer 34, which here, for example, covers the top surface of the substrate 32 and has a thickness of approximately 1-5 microns and is a group III-N semiconductor layer 34. A second group III-N semiconductor layer, here, for example, aluminum gallium nitride (Al _x Ga _1-x N, where x is 0 <x ≦ 1) having a thickness of approximately 5-30 nm. 36 continues. It should be understood that layer 34 is here a GaN buffer structure, which also includes cambium and strain relief layers not shown, typically aluminum nitride (AlN) and aluminum gallium nitride. (Al _x Ga _1-x N, where x is 0 <x ≦ 1). One of the group III-N semiconductor layer 34 and the group III-N semiconductor layer 36 using the conventional silicon (Si) foundry-compatible subtractive patterning (lithography and etching) technique so as to form the mesa structure shown in FIG. 1A. The part is removed. It should be noted, however, that the electrical isolation provided by the etched mesa structure in FIG. 1A may be provided by ion implantation (here, eg nitrogen) of the same masked layer (instead of etching). good. This will result in a planar structure. As will be described later, the structure 10 is processed to form the multi-gate FET 12 shown in FIGS. 1A and 1B above. The finger-shaped gate electrode structure _{14 1-144} , the drain electrode structure 18 _1-182 , and the source electrode structure 22 _{1-22 3} are located _on the mesa 11, but the gate pad 16, the drain pad 20, and 2 are located on the mesa 11. The two pads 26 ₁ and 26 ₂ are out of the mesa 11.

Next, referring to FIG. 2B, the front surface side or the top surface side of the structure shown in FIG. 2A is covered with a passivation layer 38, for example, silicon nitride SiN _x . As shown in FIG. 2C, conventional silicon (Si) foundry _- adapted subtractive patterning (lithographic and etching) techniques are used to form windows or openings _401-407 that penetrate selected portions of layer 38. Windows 40 ₁ and ₄₀₇ are located below where the layers 38 are processed, thereby forming pads 26 ₁ , ₂₆₂ , gate pads 16 and drain pads 20 (FIGS. 1A and 1B). Window 40 2-40 ₆ where the surface portion of the GaN layer 34 to be formed is exposed and the source electrode structure 22 _{1-22 3} and the drain electrode structure ₁₈ 1-18 ₂ (FIGS. _1A and 1B) are formed. However, the portion of the AlGaN layer 36 located below is exposed.

Next, referring to FIG. 2D, the electrical contact structures 42 _1-427 are the same in configuration, and here, an exemplary _one of the electrical contact structures ₄₂₁ is described in (A)-(C) below. ) Is shown in more detail in FIG. 3B. (A) The bottom layer 42a of titanium (Ti) or tantalum (Ta) and, for example, aluminum or Si-doped aluminum (Al _1-x Si _x ) on the layer 42a (where x in Si doping is typically ≦ 0). .05) layer 42b and layer 42c which is, for example, tantalum (Ta) or metal nitride (here, eg titanium nitride (TiN)), (B) ohmic contact structure 42 placed on _OC , here eg nickel. Alternatively, a gold-free conductive etching stop layer 42 _ES which is molybdenum or platinum, and (C) a gold-free electrode contact which is a copper damascene electrode contact described in connection with FIG. 2K. The etching stop layer is etched with respect to a specific etchant at a rate of less than half (≦ 1/2) of the rate at which the material to be etched before the etchant reaches the etching stop layer. Layers 42a, 42b, 42c and 42 _ES are placed _on the surface of the structure shown in FIG. 2C and through openings _401-407 . It should be noted that the electrical contact structures 42 ₁ and 427 are placed _on and electrically connected to the _two pads 26 ₁ , 262 (FIG. 1B), and the electrical contact structures 42 ₂ , ₄₂₄ , and ₄₂₆ Are placed on the source electrode structures 22 _{1-22 3} and electrically connected to them, and the electrical contact structures 42 ₃ and 425 are placed _on the drain electrode structures 18 ₁ and 18 ₂ and are placed on them. Electrically connected, the electrical contact structures 42 ₁ and ₄₂₇ are formed in contact with the GaN layer 34. After deposition, layers 42a, 42b and 42c of ohmic contact structure 42 _OC are formed (specifically, ohmic contacts) using conventional silicon (Si) foundry compatible subtractive patterning (lithography and etching) techniques. Structure 42 _OC is dry-etched using a chlorine-based dry etching chemistry). Next, during the annealing process described later, the electrical contact structure _422-426 is formed by ohmic contact with the group III _- N semiconductor layer 36, which is an AlGaN layer here. Here, for example, the electrical contact structure _{421-427 has} a thickness larger than 60 nm.

More specifically, each of the ohmic contact structures 42 _OCs is a trimetal stack, (a) into the bottom layer 42a of Ti or Ta, which precedes the deposition of layer 42a, into layer 36. With respect to the structure _422-426 (may be recessed in the upper surface portion of the Group III _- N semiconductor layer 36) by chlorine plasma dry etching (as shown in FIG. 2D1 (FIG. 2D')), (. b) Here, for example, an aluminum-based layer 42b of aluminum or Si-doped aluminum Al _1-x Si _x layer 42b (where x is less than 1 and here x is typically ≦ 0.05). (C) Includes, for example, a top metal layer 42c, which is a layer 42c of, for example, tantalum or metal nitride (here, eg titanium nitride (TiN)) on the aluminum-based layer 42b. The typical thickness of layers 42a and 42c is 5-30 nm, while layer 42b can range from 50-350 nm depending on the metal layer selected for the ohmic contact three-layer structure 42 _OC stack.

More specifically, in order to maintain the optimum contact morphology and to control contamination, the annealing of the ohmic contact structure 42 _OC for forming the semiconductor ohmic contact was kept below the melting point of aluminum (≦ 660 ° C.). Is done. Such cold annealing typically takes longer than 5 minutes (≧ 5 minutes) in a nitrogen atmosphere at steady-state temperatures. More specifically, here, the first metal element of the metal-semiconductor ohmic contact structure 42 _OC , for example Ti or Ta layer 42a, is here, for example, Group III-N, which is, for example, Al _x Ga _1-x N layer 36. Of the temperature lamp from ambient temperature to steady state during ohmic contact forming annealing (also referred to here as ohmic annealing) of ohmic contact structure 42 _OC , deposited directly on the surface or placed in contact with it. In the meantime, a metal nitride is formed by reacting with nitrogen, which is a group V element in the group III-N material interface layer 36. The temperature lamp is typically ≤15 ° C./sec when a linear temperature lamp is used, but the interaction of the first metal layer 42a with the Group III-N surface layer 36 in the formation of metal nitrides. A stepwise temperature lamp profile and a mixing step and linear lamp profile can all be used to optimize. Next, during the steady-state annealing process at ≦ 660 ° C. over ≧ 5 minutes, a second lower resistance metal, here eg aluminum layer 42b, is formed, here the first metal (here layer 42a). It diffuses into the surface of the metal nitride and the group III-N material (here layer 36), resulting in very low resistance ohmic contacts. Finally, ≦ 660 ° C. between the first and second metals, here layers 42a and 42b, of the metal-semiconductor ohmic contact structure 42 _OC forming the ohmic contact and the group III-N material layer 36. In contact with the upper layer of these two layers (here layers 42b) on top of these two layers (here layers 42a and 42b) in order to maximize the amount of interaction at the temperature of It is necessary to prevent mixing with the arranged third metal layer (metal nitride or metal, in this case layer 42c).

Prevention of mixing of the first two layers of the ohmic contact structure 42 _OC (here layers 42a and 42b) and the third layer (here layers 42c) can be achieved by several methods. First, it deposits the ohmic contact structure 42 _OC as a two-layer stack of the first and second metals (layers 42a and 42b) to anneal the ohmic contact structure 42 _OC , and then the third metal (layers 42a and 42b). Here it can be achieved by removing the oxidized interface (by dry etching, wet etching, or in-situ dry sputtering removal of the oxidized interface) prior to the deposition of layer 42c). Second, when all three metal layers 42a, 42b and 42c of the ohmic contact structure 42 _OC are deposited prior to the ohmic annealing of the ohmic contact structure 42 _OC , one of the following two methods is used. Therefore, a low temperature (≦ 660 ° C.) ohmic contact can be formed between the ohmic contact structure 42 _OC and the group III −N semiconductor layer 36. In the first method, with reference to FIG. 4A, the metal nitride layer of the ohmic contact structure 42 _OC (eg TiN or TaN, here layer 42c) is placed in contact with the second aluminum layer (42b). And withstood mixing with the layer 42b during annealing at ≦ 660 ° C., the metal layer 42a is alloyed with the Group III-N layer 36 and the metal layer 42b, as shown in FIG. 4A1 (FIG. 4A'). A metal nitride intermediate layer a (ILa) is formed between the layer 42a and the group III-N layer 36 (even if some unalloyed portion Un-L of the layer 42a is present after annealing). Well, the metal nitride intermediate layer may be discontinuous), forming a post-annealed ohmic contact structure 42 _OC . In the second method (see FIG. 4B), it is present in the gas used in the deposition and / or annealing equipment during the ohmic contact structure 42 _OC deposition process or during the ohmic annealing of the ohmic contact structure 42 _OC . A thin (~ 1-10 nm thick) partially oxidized second metal (here aluminum layer 42b) by reaction with oxygen, which is either done or intentionally introduced into the device. Alternatively, a third metal (here, Ta, TiN, or TaN layer 42c) or an intermediate layer b (ILb) which is a combination thereof is formed. This partially oxidized metal intermediate layer ILb includes a second metal layer (here, an aluminum layer 42b) and a third metal or metal nitride layer (here, as shown in FIG. 4B1 (FIG. 4B'). The post-annealed ohmic contact is formed between the Ta, TiN, or TaN layer 42c) or in contact with the second aluminum layer (42b) that withstands mixing during annealing at ≦ 660 ° C. Structure 42 _OC'is formed. In other words, in the second method (FIGS. 4B and 4B1), the formation of the oxide intermediate layer ILb during the metal deposition process and / or the annealing process results in the formation of the third metal layer 42c (FIG. 4B and FIG. 4B1) during annealing. The metal nitride or metal) is prevented from mixing with the layer 42b, the oxide intermediate layer ILb is formed between the layer 42b and the layer 42c, and the metal layer 42a is a group III-N layer 36. And alloyed with the metal layer 42b to form a metal nitride intermediate layer ILA between the layer 42a and the Group III-N layer 36 (note that some unalloyed moieties Un-L of the layer 42a after annealing). May exist). Therefore, in one embodiment (FIGS. 4B and 4B1), during the electrical contact structure metal deposition process and / or the ohmic annealing process, a portion of the ohmic contact structure 42 _OC is located between the second metal and the third metal. By forming the intermediate layer ILb that has been oxidatively oxidized, mixing is prevented. In the first method (FIGS. 4A and 4A1), mixing is prevented by forming a metal or metal nitride layer as the layer 42c.

As mentioned above, further optimization of the metal-semiconductor ohmic contact resistance can be achieved by adding a small amount of silicon dopant to the ohmic contact structure. Silicon can be applied by multiple methods, such as electron beam deposition and sputtering. Silicon may be applied as a separate layer within the ohmic contact structure 42 _OC (either by sputtering a silicon sputtering target or by electron beam deposition), or multiple pure targets (here, eg silicon and aluminum). It may be imparted by mixing silicon into another layer by simultaneous sputtering or by sputtering a Si-doped target (here, eg Si-doped aluminum, Al _1-x Si). _x layer 42b, where x for Si doping is typically ≦ 0.05).

Therefore, the ohmic contact forming annealing at low temperature can be summarized as follows, i.e., during the temperature ramp step of the annealing process from ambient temperature to steady state annealing temperature, ohmic contact structure 42, here layer 42a. The first metal of the _OC forms a metal nitride, where the second metal of the electrical contact structure, which is layer 42b, is into the first metal, and here is layer 36, Group III-N. First, which diffuses to the upper surface of the semiconductor layer to reduce the resistance of the ohmic contact formed at the interface between the group III-N layer 36 and the ohmic contact structure 42 _OC , and is in contact with the group III-N semiconductor layer 36. And the second metal 42b of the ohmic contact layer are prevented from mixing with the third metal (or metal nitride) 42c of the ohmic contact layer during the ohmic annealing process, and the first metal and The second metal and the third metal (metal nitride or metal) are maintained below their melting point during the ohmic contact forming annealing process. Prevention of mixing of the first two metals (layers 42a and 42b) with a third metal (layers 42c) indirectly indirect the low temperature interaction of the first two metals with the Group III-N interface. Promotes, thereby supporting lower contact resistance. After the annealing process described above, as shown in FIG. 3B, here a conductive etching stop layer 42 _ES , for example nickel, molybdenum or platinum, is placed on the layer 42c.

Next, referring to FIG. 2E, the surface of the structure shown in FIG. 2D is coated with the dielectric layer 44, which is also SiN _x , as shown in the figure.

Next, referring to FIG. 2F, the finger-shaped gate electrode structure ₁₄ 1-144 (FIGS. _1A and 1B) (in this embodiment, shot key contact with the group III-N semiconductor layer 36, which is an AlGaN layer here). In order to expose the portion of the group III-N semiconductor layer 36 that will be formed, an opening or window 46 is formed in the layer 44 using conventional silicon (Si) foundry conforming lithography and etching processing techniques. It is formed.

Next, with reference to FIG. 2G, a finger-shaped gate electrode structure ₁₄ 1-144 (FIGS. _1A and 1B), which will be described in more detail in FIG. 3A, using a silicon (Si) foundry conforming lithography and etching process. As shown, it is formed through an opening or window 46. More specifically, each of the gate electrode structures _{14 1-144} is the same in the configuration, and here, an exemplary _one of the gate electrode structures 141 is described in (A) and (B) below. Is shown in more detail in FIG. 3A so as to include. (A) Here, for example, nickel (Ni), titanium nitride (TiN), nickel / tantalum nitride (Ni / TaN), nickel / tantalum (Ni / Ta), nickel / tantalum, which are in shotkey contact with the AlGaN semiconductor layer 36. / Gate metal layer 14a which is a single material or multiple materials such as tantalum nitride (Ni / Ta / TaN), nickel / molybdenum (Ni / Mo), titanium nitride / tungsten (TiN / W), or doped silicide. A gate electrical contact structure having 14 _GC , and (B) a gold-free electrode contact, which will be described later in connection with FIG. 2K, which is here a copper damanium electrode contact. The gate metal layer 14a formed by using the conventional silicon (Si) foundry-compatible subtractive patterning technique is a Schottky contact metal forming a Schottky contact with the group III-N semiconductor layer 36 here. The gate electrical contact structure 14 _GC is arranged between the gate metal layer 14a and the group III-N semiconductor layer 36 so as to form a metal insulating gate HEMT (MISHEMT), as shown in FIG. 3A. For example, it may have a thin (typically ~ 2-10 nm) dielectric layer 14b which is aluminum oxide (Al ₂ O ₃ ). The gate metal layer 14a may be T-shaped as shown in the figure, or FIG. 3A1 (FIG. 3A1) so as to form a field plate structure having an overhang portion 15 facing the adjacent drain electrode structure. It may be a gamma type (Γ type) as shown in FIG. 3A').

The dry etching of the metal or metal nitride contained in the shot key gate metal layer 14a is typically chlorine-based (for example, for etching Ni and TiN) or fluorine-based (for example, Mo, TiN, W, Ta). , And to etch TaN) or a combination thereof (eg, to etch TiN, W, Ta, and TaN). However, when Ni is used in the shotkey gate metal layer 14a, dry etching can be quite difficult due to the lack of volatile etching by-products. Therefore, here, for example, nickel dry etching, which is a gas mixture of chlorine (Cl ₂ ) and argon (Ar), is mainly physical etching (sputtering), not chemical etching. Since predominantly physical dry etching has poor etching selectivity for the underlying layer, dry etching Ni, including the Schottky layer 14a, may be used in some situations (here, eg, eg, for example). (When the thickness of Ni in the shot key gate metal layer 14a and the thickness of the dielectric in the passivation layer 38 are approximately the same), it may result in unacceptable overetching into the passivation layer 38. In such a case, a sacrificial dielectric layer (not shown), for example, silicon dioxide (SiO ₂ ), is deposited between the passivation layer 38 and the overhang portion 15 of the Schottky gate metal layer 14a. It may be necessary.

Another method of etching the shot key gate metal layer 14a with Ni is to use dry etching on the top metal (here, eg, TaN, Ta, Mo, or a combination thereof) if present, and Wet etching (here, for example, HF, H ₃ PO ₄ , HNO ₃ or H ₂ SO ₄ system, or a combination thereof) is used for the Ni layer. The selection of the Ni wet etchant for the shot key metal layer 14a is such that the bottom shot key metal layer becomes 14a'and the top shot key layer, as described in FIG. 10C-10G below, when used. It is important to be highly selective for (where becomes 14a ”). In addition, the unintended removal of nickel under the masked shotkey gate metal layer 14a feature (here undercut). (Also referred to as) should be minimized so that the gate dimensions obtained from this process are reproducible and the gate functions as intended. As a result, it is masked by the shotkey metal layer 14a. As the overall width of the feature size shrinks, so does the thickness of the nickel layer within the shotkey gate metal layer 14a in order to minimize undercuts. 1 micron defined by the shot key gate metal 14a. For feature sizes less than (≤1 μm), the Ni thickness of the shotkey contact gate metal layer 14a to be deposited is expected here to be, for example, ≤100 nm.

The formation of the gate electrode structure _{14 1-144} is shown in more detail with respect to FIGS. 10A-10G. Therefore, as described above in connection with FIGS. 2E and 2F, the dielectric layer 44, which is also SiN _x , is formed as shown in FIG. 10A, and an opening or window in the layer 44 as shown in FIG. 10B. After forming the 46, as shown in FIG. 10C, on the dielectric layer 44 and on the exposed portion of the AlGaN layer 36 through the window 46, a first gate metal or shot key contact, here eg Ni or TiN. The metal layer 14'a is deposited. Next, as shown in FIG. 10C, a second gate metal layer 14 ″ a, which is, for example, TaN, Ta, Mo, or W, is deposited on the first gate metal or shot key contact layer. ..

Next, as shown in FIG. 10D, either a photoresist or a hard mask 45 is formed on a portion of the surface of the second gate contact metal 14 "a, aligned with the window 46. As shown in 10E, the portion of the second gate contact metal 14 "a exposed by the mask is removed using dry etching. Next, as shown in FIG. 10F, the exposed portion of the first gate contact or shotkey contact metal 14'a is removed using dry etching or wet etching using the same mask 45. The mask 45 is then removed, as shown in FIG. 10G.

After the Schottky Gate metal layer 14a is formed, the treatment is carried out with an exemplary _one of which is here the electrode 542, copper damascene electrode contacts 54 1-54 ₁₁ as shown in _FIG . 2K. The formation of the above-mentioned electrode contacts (shown in detail in FIG. 3A) is continued. Each of the copper damascene electrode contacts 54 ₁ to 54 ₁₁ is formed by depositing two dielectric layers (here, SiN _x layer 48 and SiO ₂ layer 50) as shown in FIG. 2I. Here, the first layer 48, which is SiN _x , functions as a diffusion barrier (when copper is placed beneath it) and an etching stopper. Here, the second layer, which is the SiO ₂ layer 50, is selectively etched with respect to the first layer 48, which is SiN _x , and then the first layer is exposed so as to expose the gate metal layer 14a. The layer 48 is etched, thereby forming a trench in which the gold-free material, here copper, is later deposited.

Typically, the copper damascene electrode contacts 541-54 _{11 first} have a thin metal seed layer (typically) to facilitate copper plating into the trench formed in the second dielectric layer. , Ta / Cu, Ta / TaN, or TaN / Cu, and ≦ 100 nm). The seed layer also functions as a copper diffusion barrier and as an adhesion layer to the dielectric. The excess copper overfill in the trench is then removed by chemical mechanical polishing (CMP), which defines the metal interconnect by leaving only the metal placed in the trench. When other copper damascene layers are added, this process is repeated as described below. Therefore, the damascene electrode contacts 54 1-54 ₁₁ have _a coplanar top surface.

Initiating the damascene process described in the previous paragraph and then referring to FIG. 2H, a dielectric layer 48, eg SiN _x , is deposited over the surface of the structure shown in FIG. 2G. Next, referring to FIG. 2I, overlying the layer 48, a second dielectric layer 50, for example SiO ₂ , is deposited and the source, drain and gate electrodes _541-541 are _co -formed. To this end, conventional silicon (Si) foundry conforming lithography and etching techniques are used to form windows 52 through the selected portions of layers 50 and 48, thereby forming an electrical contact structure 42 ₁ as shown in FIG. 2J. _-427 and the finger-shaped gate electrode structure _{14 1-144} are patterned so as to expose the top surface, whereby the gate electrode structure ₁₄ 1-144 and the drain electrode structure 18 ₁ described above in relation to FIG. _1A are exposed. -18 ₂ and the source electrode structure 22 _{1-22 3} are completed.

Next, referring to FIG. 2K, as described above, after the excess metal, which is Cu here in the damascene process, has been removed by the CMP, the electrical contact structure 42 _1-427 and the _fingered gate electrode, as shown in the figure. Electrode contacts _{541-54 11} are formed on the exposed top surface of the structure _{14 1-144} . _Each of the electrode contacts 54 1-54 ₁₁ is the same in configuration, where here is an exemplary _one of the source electrode structure 22 _{1-22 3} or the drain electrode structure 18 1-182 ₍ here source electrode structure 22 ₁ ). ) Is shown in _FIG . 3B, an exemplary _one of the electrode contacts 54 1-54 ₁₁ (here, the electrode contact 542), which is an exemplary one of the gate electrode contacts (here, the gate electrode structure). 14 ₁ ) is shown in FIG. 3A. Therefore, as more clearly shown in FIGS. 3A and 3B, _each electrode contact 54 1-54 ₁₁ in this example has a bottom and side surfaces in close contact with the copper diffusion barrier layer 54a (here, eg, tantalum or tantalum nitride). Or a combination thereof) contains a copper top layer 54b lined (covered).

Therefore, each of the drain electrode structure 18 1-18 ₂ and _each of the source electrode structures 22 _{1-22 3} is a multi-layered electrical contact structure in contact with the group III-N semiconductor layer 36, and is a group III-N semiconductor layer 36. Gold-free contact layer 42 _OC , gold-free conductive etching stop layer 42 _ES electrically connected to gold-free contact layer 42 _OC , and gold _- free damascene electrode contacts 542, ₅₄₄ , Includes one of ₅₄₆ , ₅₄₈ and 54 ₁₀ . Each of the gate electrode structures 141-144 also includes a gold _- free gate electrical contact and _one of the gold _- free damascene electrode contacts 543 _{, 545} and 547. Also, each of the damascene electrode contacts _542-5410 is the same in configuration, and all eight _damascene electrode contacts _{542-5410 are} formed simultaneously.

Next, referring to FIG. 2L, after the CMP, over the surface, a dielectric layer 56, here silicon nitride (SiNx), is deposited, followed by a layer 56, here an oxide layer 58 (here, here). It is covered with a second dielectric layer 58 (eg, silicon dioxide).

Next, referring to FIG. 2M, the layers 56 and 58 have openings or openings through the layers 56 and 58 over the source electrode structure 22 1-22 ₃ (FIG. _1B ) and the pads 26 ₁ and 26 ₂ (FIG. 1B). Patterned using traditional silicon foundry conforming lithography and etching techniques to have windows _{60 1-605} , thereby electrode contacts 54 ₁ , ₅₄₂ , _{546, 54 10 and} , as shown. The top surface of 54 ₁₁ is exposed.

Next, referring to FIG. 2N, using conventional silicon foundry conformance processing techniques, upper electrical interconnects 62 _1-625 are formed in windows _{60 1-605} , respectively, thereby forming electrode contacts ₅₄₁ , _respectively . , ₅₄₂ , _{546, 54 10 and} 54 ₁₁ , and thus the source electrode structure 22 1-22 ₃ (FIG. _1B ) and the pads 26 ₁ and 26 ₂ (FIG. 1B) are electrically connected. Each of the upper electrical interconnects 62 _1-625 is configured _{similarly to each of the electrode contacts 54 1, 542, 546, 54 10 and 54 11 and here , for example} , tantalum (Ta) or tantalum nitride (TaN). Alternatively, it includes a copper upper layer 62b whose bottom surface and side surfaces are lined with the adhesion / copper diffusion barrier layer 62a which is a combination thereof.

Next, referring to FIG. 2O, overlying the structure shown in FIG. 2N, a dielectric layer 64, which is SiNx, is formed, followed by a dielectric layer 66 of silicon dioxide.

Referring to FIG. 2P, a window 68 is formed through selected portions of layers 64, 66 so as to _expose the top surface of the upper electrical interconnects 62 _1-625 .

Next, referring to FIG. _2Q , here, as in the upper electric interconnect 62 _1-625 , copper whose bottom surface and side surfaces are lined with, for example, tantalum or tantalum nitride or a combination thereof, a close contact / copper diffusion barrier layer 24a. The conductive interconnect structure 24 (FIGS. 1A and 1B) including the upper layer 24b of the above is formed.

Referring to FIG. 2R, a dielectric layer 70 which is SiN _x is formed here over the surface of the structure shown in FIG. 2Q. If necessary, an additional Cu-based interconnect layer may be added in the same manner as the Cu interconnect described above. After the addition of the last interconnect layer, a test pad layer or input / output pads (not shown) may be added, respectively, to facilitate final testing or connection to other circuits (not shown). At this point, the processing on the front side is completed.

After the front side treatment is complete, and with reference to FIG. 2S, the back side treatment is started. More specifically, the wafer is face-down mounted on a temporary carrier (not shown), where the wafer is then thinned, eg, to 50 or 100 microns. The exposed bottom surface of this structure is masked so as to expose the lower portions of the electrode contacts _{541 and 54 11 of} the bottom surface of the substrate 32. Next, here, via holes 72 are formed in the exposed portion by etching from the bottom surface of SiC or Si substrate 32 using fluorine-based dry etching, for example, sulfur hexafluoride (SF ₆ ).

Next, referring to FIG. 2T, the bottom surface of the substrate 32 is exposed to group III-exposed by chlorine-based dry etching, which is a combination of boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ), for example. The portion of the N layer 34 is penetrated and the inner portion of the exposed Ti or Ta layer 42a of the ohmic contact structure 42 _OC of the electrode contacts _{541 and 54 11 is} then exposed, followed by the inner portion of the aluminum-based layer 42b. Etching through the inner portion of the metal nitride layer 42c continued to deepen the via hole 72 (as pointed to by the arrow 74) and, as shown, the electricity under the electrode contacts _{541 and 54 11 .} Etching is stopped at the etching stop layer 42 _ES on the contact structure 42.

Next, referring to FIG. 2U, the bottom surface of the structure of FIG. 2T has a conductive layer 28 (FIG. 1A) arranged on the bottom surface of the substrate 32 and in the via hole 72. Here, for example, the layer 28b is copper with, for example, tantalum or tantalum nitride or a combination thereof, the adhesion / copper diffusion barrier layer 28a (as shown in FIG. 2U1 (FIG. 2U')). Conductive vias 30 ₁ and 30 ₂ (FIG. 1A) and ground plane conductor 30 ₃ are formed. Conductive vias 30 ₁ and 30 ₂ have an interconnect source electrode structure with the ground plane conductor 30 ₃ on the front metallization layer and finally from the etching stop layer 42 _ES through the bottoms of the electrode contacts _{541 and 54 11 .} 22 _1-22 Electrically interconnected to ₃ (FIGS. 1A and 1B). It should be understood that the conductive vias 30 ₁ and 30 ₂ and the ground plane 30 ₃ are here, for example, a gold (Au) layer 28b and a titanium (Ti) or titanium / platinum (Ti / Pt) layer 28a. It can have a layer 28 made of another metal. In this case, the backside treatment is performed in an area where gold does not present a contamination problem.

Therefore, here, in the embodiment described above in relation to FIG. 2A-2U, a two-step etching process ending with the conductive etching stop layer 42 _ES is involved after the treatment on the front side and the thinning of the wafer on the back side. The back side via hole 72 is formed by using chemical dry etching. In the first step of the via hole etching process, via holes are formed in the exposed portion of the bottom surface of the SiC or Si substrate layer 32 by using, for example, fluorine-based dry etching of sulfur hexafluoride (SF ₆ ). This fluorine-based etching selectively stops on the group III-N layer 34 such as gallium nitride (GaN) and aluminum nitride (AlN). In the second step, the bottom surface of the Group III-N layer exposed in the via hole 72 is exposed to chlorine-based dry etching, which is a combination of, for example, boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ). This chlorine-based backside via hole 72 dry etching is performed through Group III-N layers 34 and 36 (in the example shown in FIG. 2, the substrate layer 32 is penetrated, and then "off" mesaetching is performed on the III-N layers 34. It only needs to be etched through) and viahole etching is continued through the metal-semiconductor electrical contact structure and ends with a conductive etching stop layer of the electrical contact structure metal, in this case nickel or molybdenum or platinum. ..

Next, with reference to FIGS. 5A-5C, an embodiment of a part of the MMIC structure 10'will be described here. The MMIC structure 10'has a multi-gate HEMT FET here, for example, as shown in more detail in FIG. 5A, which in ohmic contact with the Group III-N semiconductor layer 36 as shown. At the same time, the gold-free conductive vias 30 _{1-30 3} penetrating the substrate 32, the group III-N layer 34, and the group III-N semiconductor layer 36 into the conductive layer 28 formed on the bottom surface of the structure 10'(FIG. 5C). ), Which provides a gold _- free source electrode structure 22 _1-223 , respectively, and electrode contacts _{542, 546 and 54 10 arranged on the} electrical contact structures ₄₂₂ , ₄₂₄ and 426, respectively. As shown in the figure, gold-free drain electrode structures 18 ₁ and ₁₈₂ are provided, which are in ohmic contact with the Group III-N semiconductor layer 36 and interconnected to a gold-free drain pad 20 (FIG. 1B). , Electrode contacts 544 and 548 arranged _on the electrical contact structures 42 ₃ and 425, respectively, and group III-N semiconductor layer 36 _{in shotkey} contact and connected to a gate pad 16 (FIG. 1B). , Electrode contacts 543 _{, 545} , 547 and 549, respectively, disposed _on gold-free gate electrode structures _{14 1-144} , which provide gold _- free drain electrode structures 18 ₁ , ₁₈₂ . Have. The structure 10'contains a resistor R having a pair of electrodes (both ends of the resistor R) R1 and R2, here for example tantalum nitride (TaN), one electrode R1 having an electrode contact 54 ₁₁ and electricity. Connected to the gold-free conductive layer 28 formed on the bottom surface of the structure _10'by a conductive via 304 ₍ FIG. 5C) connected to the contact 427 and passing through the substrate 32 and the Group III-N layer 34, the other. The electrode _R2 of the above is arranged _on the electrode 5421 arranged on the electric contact 428 arranged on the group III-N layer 34. The structure 10'also includes _a capacitor C, which, as shown, is _a lower plate C1 formed by an electrode contact 541 and an electrical contact structure 421 (FIG. 5A), the bottom surface of the structure 10'. A lower plate C1 interconnected to a gold-free conductive layer 28 formed in the substrate 32 and a conductive via 305 passing through a group III-N layer 34, and here a layer 54a (here, eg, tantalum or tantalum nitride). Or a combination thereof) with an upper plate C2, which is an electrical interconnect 54a having a copper layer 54b lined with a copper layer 54b, and a dielectric 75, which is disposed between the upper plate C2 and the lower plate C1, for example, silicon nitride. have. Finally, in many circuit designs, the capacitor C and the resistor R do not need to be connected to the conductive via 30.

The thickness of copper used for the resistance R while forming the lower plate C1 of the capacitor C is larger than the thickness used for the source electrode structures 22 ₁ , 22 ₂ and 22 ₃ and the drain electrode structures 18 ₁ and ₁₈₂ . However, it is thick for the following two reasons. First, the trench formed in the damascene process is an "on" mesa 11 electrical contact structure (unless an ion implantation separation (not shown) is used instead of the above mesa to achieve a planar structure). “Off” mesas 11 to 42 (FIGS. 1B and 2A) must be deep to achieve vertical interconnects. Second, all contacts formed during metal layer deposition are terminated at the same level on the top surface of the layer by the CMP process.

Further, the above-mentioned electric contact structure 42 _1-428 is formed _in the same manner as described above in relation to FIG. 2A-2T. Therefore, the source electrode structures 22 ₁ , 22 ₂ and 22 ₃ and the drain electrode structures 18 ₁ and 18 ₂ are in ohmic contact with the group _III -N semiconductor layer 36, and the gate electrode structures 14 ₁ , 142 and 14 ₃ are group III-. Shot key contact is made with the N semiconductor layer 36.

Next, the processing on the back surface side proceeds in the same manner as in FIGS. 2S and 2T. More specifically, the wafer is mounted face down on a temporary carrier (not shown), where the wafer is thinned to, for example, 50 or 100 microns. As shown in the figure, the exposed portion of the bottom surface of the substrate 32 that is located below the central or inner surface portion of the electrical contact structures 42 ₁ , 42 ₂ , 42 ₄ , ₄₂₆ and ₄₂₇ is exposed. The bottom surface is masked with a mask 78 and processed using conventional silicon conformance processing techniques, followed by etching via holes 72 penetrating the exposed portion of the substrate 32 as described above in connection with FIG. 2S. First fluoro-based dry etching, here for example sulfur hexafluoride (SF ₆ ), and exposed Group III-N layers 34 and 36 portions as described above in connection with FIG. 2T. And then through the central or inner part 79 _IP of the bottom surface of the electrical contact structures 42 ₁ , 42 ₂ , 42 ₄ , ₄₂₆ and ₄₂₇ , and the etching stop layer 42 _ES of the structure (here, eg, nickel). , Molybdenum or platinum) to continue to deepen the via 72 (an exemplary electrical contact structure, here electrical contact structure 422, is shown in _FIG . 5B1 (FIG. 5B'). ), Here, for example, chlorine-based dry etching, which is a combination of boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ), is performed. It should be noted that the outer portion 79 _OP of the bottom surface of the electrical contact structures 42 ₂ , ₄₂₄ , ₄₂₆ remains unetched and thus remains in ohmic contact with the group III-N layer 36.

Next, with reference to FIG. 5C, the mask 78 is removed and the backside process is performed, as described in connection with FIG. 2U. Therefore, on the bottom surface of the structure of FIG. 5B, as described above in relation to FIG. 2U1 (FIG. 2U'), a conductive layer 28 is formed covering the side surface and the bottom surface of the via hole 72 extending and covering it. As a result, conductive vias 30 _1-305 are formed _on the exposed conductive etching stop layer 42 _ES , and as shown in the figure, the source electrode structure 22 _{1-22 3} , the lower plate C1 of the capacitor C, and the resistance are formed. The electrodes R1 are electrically interconnected.

Here, as shown in FIG. 5A1 (FIG. 5A'), the electrical contact structure 42'is here a silicide layer (here, for example, nickel silicide (NiSi) or cobalt silicide (CoSi ₂ )). It may be a single ohmic contact layer _42'OC . Also, the silicide layer ohmic contact structure _42'OC may also be doped to further improve contact resistance. For example, in the case of NiSi, it can be doped with phosphorus (P), arsenic (As), antimony (Sb) or a combination thereof. Si and Ni or Co are deposited, etched back and then alloyed to form an ohmic contact structure _42'OC . In the case of NiSi, the alloy temperature here is, for example, about 450 ° C. In the case of CoSi ₂ , for example, two-step annealing at ~ 550 ° C and subsequently ~ 700 ° C is used. In order to support better ohmic contact to the group III-N layer 36, the silicide layer ohmic contact structure _{42'OC is such that the bottom surface of the silicide layer ohmic contact structure 42 OC is} 2-from the bottom surface of the group III-N layer 36. It may be recessed in the group III-N semiconductor layer 36 so as to be 20 nm. The etching stop layer 42 _ES is arranged on the ohmic contact structure _42'OC as shown in the figure. Here, the electrical contact structure includes an ohmic contact structure _42'OC having an etching stop layer 42 _ES on the ohmic contact structure _42'OC .

Next, another embodiment will be described with reference to FIGS. 6A-6D. Again, as shown in FIG. 6A, here the substrate 32, for example Si or SiC, and the mesa-like group III (defined by etching or injection separation as described above) on top of the substrate 32-. The N semiconductor layer 34, here, for example, on the group III-N semiconductor layer 34 and the group III-N layer 34, which are layers of gallium nitride having a thickness of about 1-5 microns on the upper surface of the substrate 32. , For example, a structure 10 ”with a group III-N semiconductor layer 36 of Al _x Ga _1-x N, having a thickness of, for example, about 5-30 nm, is shown. As will be described later, the structure 10”. Is processed to form a multi-gate HEMT. However, here, in order to electrically interconnect the source electrode structures 22 1-22 ₃ (FIG. _1B ), the conductive vias 90 described in relation to FIGS. 6B and 6C will be formed-Group III-. Conventional silicon foundry compatible subtractive patterning (lithography and etching) techniques and, here, for example, a combination dry etching of boron trichloride (BCl ₃ ) and chlorine (Cl ₂ ) are used on the N layers 34 and 36. , The aperture 80 is etched.

Referring to FIG. 6B, the aperture 80 can be dry etched with a fluorine-containing gas, here for example SiNx, SiO ₂ , molybdenum or polysilicon or a semiconductor or dielectric or metal material which is a combination thereof. It is filled with 82. This structure is treated as described above in connection with FIG. 2B _{-2K to form the electrical contact structure 42 "1-42" 5 .} It should be noted that here, the electrical contact structure 42 "_{1-42" 5 does} not include a separate etching stop layer such as the above-mentioned etching stop layer 42 _ES related to FIG. 2A-2U, but rather this. In embodiments, as described in connection with FIG. 6B, aluminum or Si-doped aluminum Al _1-x Si _x layer 42b of the ohmic contact structure 42 " _OC of the electrical contact structure 42" 1-42 " _{5 (} provided that it is). , Si doping x typically ≦ 0.05) acts as an etching stop layer. As shown, on top of the ohmic contact structure 42 _{OC1-42 OC5} , the electrode contacts 54 ₁ , 54 ₃ , 54, respectively. ₅ , ₅₄₇ and ₅₄₉ are arranged. Electrical contact structures 42 " ₁ , 42" ₃ and 42 " ₅ are for source electrode structures 22 1-22 ₃ (FIG. _1B ), electrical contact structures 42" ₂ and 42 ” ₄ is for the drain electrode structures 18 ₁ and 18 ₂ (FIG. 1B). The bottom surface of the electric contact structure 42 " ₁ , 42" ₃ and 42 " ₅ is larger in surface area than the surface area of the semiconductor, dielectric or metal material 82, and as shown in the figure, the electric contact structure 42" ₁ , 42 " The outer surface portion of " ₃ and 42" ₅ is in ohmic contact with the group III-N semiconductor layer 36. The gate electrode structure _{14 1-144} makes Schottky contacts with the group III-N semiconductor layer 36 as shown, and the electrode contacts ₅₄₂ , 544, ₅₄₆ , and _{548 on} it, as shown. Have.

The ohmic contact structure layers 42a, 42b, and 42c of the electrical contact structure 42 "_{1-42" 5 and the electrode contacts are described above in connection with FIG. 3B, and the ohmic contact structure 42 OC1-42 OC5 is Ti or} Ta. The bottom layer 42a (which may be recessed into the top portion of the Group III-N semiconductor layer 36) and an aluminum-based layer, here aluminum or Si-doped aluminum Al _1-x Si _x layers. A tantalum or metal nitride on the intermediate layer 42b of the layer and the aluminum or Si-doped aluminum Al _1-x Si _x layer, which is here, for example, tantalum (Ta), tantalum nitride (TaN) or titanium nitride (TiN). With a layer, the electrode contacts _541-549 have conductive metal _interconnect contacts, wherein, for example, the sides and bottom are diffuse barrier layers (here, eg, tantalum or tantalum nitride, or a combination thereof). ) Has lining copper. Therefore, it should be noted that there is no separate etching stop layer 42 _ES (described above in connection with FIG. 2A-2U) in this embodiment, as will be described in more detail with respect to the backside treatment. Rather, due to the fluorochemical etchant used to form the via 90 (FIG. 6C) in this embodiment, here, for example, the aluminum (or Si-doped aluminum Al _1-x ) of the electrical contact structure 42 ”. The etching stop layer is provided by the layer 42b which is Si _x ).

Next, the processing on the back surface side proceeds as shown in FIG. 2U. More specifically, the wafer is mounted face down on a temporary carrier (not shown), where the wafer is thinned to, for example, 50 or 100 microns. The exposed bottom surface of this structure is masked with mask 96 (FIG. 6C) so as to expose the bottom surface portion of the substrate ₃₂ below the source electrode structure 22 _1-223 . The outer peripheral portion of the semiconductor, dielectric or metal material 82 is covered by the mask 96, and therefore, under the inner portion 81 _IP of the electrical contact structure 42 (FIG. 6C1 (FIG. 6C')), the electrical contact structure 42 The other portion 81 _OP remains in ohmic contact with layer 36. Next, here, the via 90 is etched as follows using, for example, SF ₆ fluorine-based dry etching, that is, it penetrates the substrate layer 32 and the internal portion of the material 82 (here, for example, in FIG. 6C1). Through the internal portion 81 _IP of the bottom layer 42a of Ti or Ta (which may be recessed into the top portion of the Group III-N semiconductor layer 36) (SiNx, SiO ₂ , molybdenum or polysilicon). The via 90 is etched using a fluorine-based dry etching that etches the via 90 and stops the by-products of the fluorine-based etching at the inner portion of the non-volatile aluminum-based layer 42b. Therefore, there is no additional (separate) etching stop layer 42 _ES here, but rather the layer 42b functions as an etching stop layer.

Next, with reference to FIG. 6D, the bottom surface of the structure of FIG. 6C is formed to cover the side surface and the bottom surface of the via hole 90 extending and covering it, here, for example, a copper-based conductive layer 28. Has, thereby, as described above in connection with FIG. 2U, for this structure to electrically interconnect the inner or central portion of the electrical contact structure 42 "as shown, and thus the source electrode. Conductive vias 96 and ground plane conductors 95 are formed to interconnect structures 22 _1-223 . In this embodiment, the Group _III -N materials are as described above in connection with FIG. 6A. The aperture 80 (FIG. 6A) is then etched from the front surface of the wafer prior to backside treatment and formation of vias 90. The material layer 82 (here, here) can be etched with a fluoro-based dry etching chemistry. For example, it is filled with SiN _x , SiO ₂ , molybdenum or polysilicon). All layers that need to be etched to form the via 90 are no longer substrate 32 (silicon, silicon carbide (SiC), silicon dioxide (silicon). Assuming SiO ₂ ), silicon nitride (SiN _x ), or a combination thereof) and the semiconductor or dielectric or metal material 82 of the aperture (here, eg SiN _x , SiO ₂ , molybdenum or polysilicon). All of these layers can be etched using a fluoro-based etchant. As a result, in this case, fluoro-based etching is used throughout the via etching process.

Next, another embodiment will be described with reference to FIG. 6D1 (FIG. 6D'). In this embodiment, the via 96 is etched wider than in FIG. 6D, but again the etching is stopped at the inner portion of the aluminum-based layer 42b. Therefore, again, there is no additional (separate) etching stop layer 42 _ES , rather the layer 42b functions as an etching stop layer. In this case (FIG. 6D1), the dielectric layer 82 in the via 90 (shown in FIG. 6C1) does not remain.

Next, with reference to FIGS. 7A-7G, another embodiment is shown. Here, the structure 10'''shown in FIG. 2B is processed as described with respect to FIG. 2C, except that only windows 402-406 are formed as shown. After forming windows 40 _2-406 , conventional silicon (Si) foundry conforming (subtractive) lithography and etching treatments are performed _on the inner surface portion of the layer 36 exposed by windows _{40 2} , ₄₀₄ , 406. Using the technique, an etching stop layer 42 _ES ', which is here, for example, silicon dioxide or SiN _x , is formed. In FIG. 7B, the etching stop layer 42 _ES'is not provided on the outer surface portion of the exposed surface of the layer 36. Alternatively, although not shown, the etching stop layer 42 _ES'may be formed on the inner surface portion of the layer 36 exposed by all windows 40.

Next, referring to FIG. 7C, the layers 42a, 42b and 42c are formed on the etching stop layer 42 _ES '. The outer peripheral portions of the layers 42a, 42b and 42c are in direct contact with the layer 36. Therefore, after the annealing process described above in relation to FIGS. 4A, 4A1, and 4B, 4B1, ohmic contacts are formed between the outer peripheral portions of layers 42a, 42b and 42c and the group III-N layer 36. It should be noted that here, the electrical contact structures 42''' ₁ , 42''' ₃ and 42''' ₅ are not above the layers 42a, 42b and 42c, but below the inner portions of the layers 42a, 42b and 42c. Here, an etching stop layer 42 _ES'is included. Thus, although described above in connection with FIG. 3B where the electrical contact structure 42'''contains the etching stop layer 42 _ES on the layer 42c (on the electrical contact structure 42), it is shown here in FIG. 3B1. As such, the etching stop layer 42 _ES'of the electrical contact structure 42'used in FIGS. 7A-7F is below the inner or central portion of the layer 42a of the electrical contact structure 42'''.

_In FIG. 7C, the electrode contacts _541-549 are the upper layers of the source electrode structure 22 1-22 _{3 ,} the drain electrode structures 18 ₁ and ₁₈₂ , and the gate electrode structure _{14 1-144} , as shown in the figure. Are formed at the same time.

Next, referring to FIG. 7D, after the processing on the front side is completed, the processing on the back side is started with reference to FIG. 2S. More specifically, the wafer is face-down mounted on a temporary carrier (not shown), where the wafer is then thinned, eg, to 50 or 100 microns. The bottom surface of this structure is masked by placing the window in the mask below the etching stop layer 42 _ES '. As shown here, the via 102 penetrating the substrate 32 is etched using, for example, an etchant which is fluorine.

Next, referring to FIG. 7E, the via 102 is extended to the via 102'using, for example, chlorine-based etchants such as BCl ₃ and Cl ₂ , and as shown, this etching is performed on the etching stop layer 42 _ES '. Stop at. Next, when either SiO ₂ or SiN _x is used as the etching stop layer 42 _ES ', the etching stop layer 42 _ES'is removed from the bottom of the via hole 102' using a fluorine-based dry etching chemistry. To. Fluorine-based wet etching is used to remove the etching stop layer 42 _ES'of the SiO ₂ and Al ₂ O ₃ layer 42 _ES , and the etching stop layer 42 _ES'of some SiN _x layers as shown in FIG. 7F. Is preferable.

Next, referring to FIG. 7G, in order to electrically interconnect the source electrode structures 22 _{1-22 3} , a conductive layer 28 is formed over the bottom surface of this structure as described above in connection with FIG. 2U. Will be done.

Next, with reference to FIGS. 8A-8F, another embodiment for forming an ohmic contact to one of the source electrode structures and a connection of the source electrode structure to the backside metallization conductive layer 28 is It is shown. Therefore, as shown in FIG. 8A, after forming the dielectric layer 38 on the upper surface of the AlGaN layer 36, here, for example, using conventional lithography and dry etching processes such as chlorine-based etchants BCl ₃ and Cl ₂ . As shown in FIG. 8B, the window 200 is formed through the dielectric layer 38 and the portions of the AlGaN layer 36 and the GaN layer 34 located below the dielectric layer 38 to the surface of the substrate 32.

Next, with reference to FIG. 8C, as described above in connection with FIG. 2D, the electrical contact structure 42'with layers 42a, 42b and 42c of the ohmic contact structure 42 _OC is sequentially deposited and conventional lithography. It is patterned as shown using an etching process. The ohmic contact structure 42 _OC is a titanium (Ti) or tantalum (Ta) bottom layer 42a and, for example aluminum or Si-doped aluminum Al _1-x Si _x (where Si doping x is typically) on the layer 42a. It has a layer 42b which is (≦ 0.05) and a layer 42c which is, for example, tantalum (Ta) or a metal nitride (here, for example, titanium nitride (TiN)). Next, using the annealing process described above, an ohmic contact region 110 (FIG. 8C) is formed between the ohmic contact structure 42 _OC and the side wall of the AlGaN layer 36. Next, as described above in relation to FIG. 2F-2H, the dielectric layers 44 and 48 are formed as shown.

Next, as described above in connection with FIG. 2I, the damascene process is initiated by depositing the dielectric layer 50 as shown in FIG. 8E, followed in this example in relation to FIG. 2I-2L. As described above, an electrical interconnect including a copper upper layer 54b whose bottom surface and side surfaces are closely lined with a copper diffusion barrier layer 54a (here, for example, tantalum or tantalum nitride or a combination thereof) is formed. As shown in FIG. 8F, _one exemplary of the above-mentioned damascene electrode contacts 54 1-54 ₁₁ (here shown as 54 without subscripts) is obtained.

The process is continued as described above in relation to FIG. 2M-2R, and then the back surface process is initiated as described above in connection with FIGS. 6A-6D. More specifically, the wafer is mounted face down on a temporary carrier (not shown), where the wafer is thinned to, for example, 50 or 100 microns. The exposed bottom surface of this structure is masked so as to expose the bottom surface portion of the substrate ₃₂ below the source electrode structure 22 _1-223 . Next, here, for example, using a fluorine-based dry etching of SF ₆ , the substrate layer 32 is penetrated, the bottom layer 42a of Ti or Ta is penetrated, and the by-product of the fluorine-based etching is non-volatile aluminum. The via 90 is etched by stopping at the base layer 42b. Therefore, there is no additional (separate) etching stop layer 42 _ES here, but rather the layer 42b functions as an etching stop layer, as shown in FIG. 8G.

Next, with reference to FIG. 8H, a conductive layer 28 in which the bottom surface of the structure of FIG. 8G is electrically connected to the layer 42b of the electrical contact structure 42'as described above in connection with FIG. 2S-2U. Have.

Next, with reference to FIGS. 9A-9E, another embodiment is shown. Here, as shown in FIG. 9A, after forming the dielectric layer 38 on the upper surface of the AlGaN layer 36, here, conventional lithography and dry etching processes (here, for example, chlorine-based etchants BCl ₃ and Cl ₂ ). ) Is used to form a window 200 through the dielectric layer 38 and the portions of the AlGaN layer 36 and the GaN layer 34 located below the dielectric layer 38 to the surface of the substrate 32, as shown in FIG. 9B.

Fluorine that laterally etches the dielectric layer 38 (as shown in FIG. 9C) so as to expose the surface portion of the group III-N semiconductor layer 36 around the edge of the window 200 (shown in FIG. 9B). The window 202 is etched using a system dry etchant.

Next, as shown in FIGS. 9D and 9E, the layers 42a, 42b, 44 and 48 are formed as described in connection with FIGS. 8C and 8D, and then as described above in connection with FIGS. 8E and 8F. And the process continues.

It should be understood that various changes may be made without departing from the spirit and scope of this disclosure. For example, the metal-semiconductor ohmic contact structure 42 _OC'is , for example, Ta / Al, Ti / Al, Ta / Al / Ta, Ta / Al _1-x Si _x / Ta, Ta / Al / TiN, Ta / Al / Ni. , Ti / Al / Ni, Ta / Al, Ti / Al, Ti / Al / W, Ti / Al / Mo, Ti / Al / Pt, etc., Ta, Ti, TiN, Pt, Ni, Si, AlSi, W , Or may have two or more layers of Al with Mo. Further, the structure shown in FIG. 2J may be removed from the gold-free manufacturing region prior to forming the electrode contact 54, in which case the electrode contact 54 may be gold.

The process for selective deposition of Ni-based gate structures will then be described with reference to FIGS. 11A-11E. Therefore, after forming the openings or windows 46 as shown in FIG. 2F, the nickel oxide (NiO) gate metal layer 128 is selectively deposited through the openings 46, here using the ALD. The NiO layer 128 does not adhere to the SiNx layer 44, but adheres to the AlGaN layer 36 terminated with a natural oxide film that easily forms -OH groups during the NiO ALD deposition process, thereby adhering to the ALD deposition. To support. That is, AlGaN, which is a semiconductor, has some natural oxide film on which NiO adheres in ALD, whereas on the SiNx layer, a significant concentration of -OH groups (for example, SiO 2) to which NiO is bonded (for example, SiO ₂ ). Or, since there is no such as present on an oxide layer such as Al ₂ O ₃ , NiO metal deposition on SiNx is suppressed. This —OH group dependence of the deposit is on the deposited oxide (eg SiO ₂ or Al ₂ O ₃ ), natural oxide film, or oxygen plasma treated surface (eg, oxidized AlGaN surface or SiNx surface). It is the basis of selective gate metal deposition to.

Next, referring to FIG. 11B, the NiO layer 128 is annealed in the reducing agent, and here, for example, the gas having hydrogen is converted into the Ni layer 128'by the reaction of NiO + H ₂ = Ni + H ₂ O. That is, it is reduced to form a gate electrode structure _{14'1-14' 4 as} shown in FIG. 11B.

Next, referring to FIG. 11C, overlying this structure, a dielectric layer 130, for example SiNx, is deposited here, followed by a layer 132, for example silicon dioxide, which is shown in FIG. 11C. Flattened using chemical mechanical polishing (CMP) as shown.

Here, the silicon oxide layer 50 is pierced over the source ohmic contact (S), the drain ohmic contact (D), and the Ni gate metal 128'using, for example, a conventional lithography-etching process using fluorine-based dry etching. The opening 52 is formed. This etching is stopped at the SiNx layer 130. Next, as shown in FIG. 11D, the opening 52 is continued through the SiNx layer 130 by using fluorine-based dry etching, whereby the source ohmic contact (S), the drain ohmic contact (D), and the gate electrode structure are continued. The Ni gate metal _{128'forming 14'1-14'4} is exposed.

Next, with reference to FIG. 11E, copper damascene contacts 541-5411 are formed on the exposed source ohmic contacts (S), drain ohmic contacts (D), and Ni gate metal 128', as shown. .. More specifically, first, the exposed source ohmic contact (S), drain ohmic contact (D), and copper plating on the Ni gate metal _128'of the gate electrode structure _14'1-14'4 can be easily performed. By sputtering a thin metal seed layer (typically Ta / Cu, Ta / TaN / Cu, or TaN / Cu, and ≦ 100 nm), the copper damascene electrode contacts 54 _{1-54 11 are} here. It is formed. The seed layer also functions as a copper diffusion barrier and as an adhesion layer to the dielectric. To complete the FET, excess copper overfill in the opening 52 is then removed by chemical mechanical polishing (CMP), which defines the metal interconnect by leaving only the metal placed in the trench. do. Then, as described in FIG. 2L-2U, the remaining FET processing proceeds.

Next, with reference to FIGS. 12A-12C, another embodiment is shown. Here, after forming the gate metal 128'as shown in FIG. 11B, for example, in order to provide a gamma-shaped gate structure 14 " ₁ to 14" ₄ as shown in FIG. 12A, the gate metal 128'is formed on the gate metal 128'. For example, a top layer or a cap layer 128a such as TiN / W, W, Ta, TaN, Ta / TaN, or Mo is formed.

Then, referring to FIG. 12B, overlying this structure, a dielectric layer 130, for example SiNx, is deposited, followed here, for example, a layer 132, which is silicon dioxide, and it is chemically mechanically polished ( Flattened using CMP).

Next, referring to FIG. 12C, here, using a conventional lithography-etching process using, for example, fluorine-based dry etching, the source ohmic contact (S), the drain ohmic contact (D), and the Ni gate metal 128' An opening 52 is formed above the silicon oxide layer 50 through the silicon oxide layer 50. This etching is stopped at the SiNx layer 130. Next, as shown in FIG. 12C, the opening 52 is continued through the SiNx layer 130 by using fluorine-based dry etching, whereby the source ohmic contact (S), the drain ohmic contact (D), and the gate electrode structure are continued. The Ni gate metal 128'forming 14 " _1-14 " ₄ is exposed. Then, as described above for FIG. 11E (or FIG. 2K) and as described above for FIG. 2L-2U, the rest of the processing proceeds to complete the FET.

Next, referring to FIG. 13A, here, after forming the structure shown in FIG. 2E, here, for example, using an ALD having one or more deposition cycles, on the layer 44 as shown in the figure. Layer 140 of Al ₂ O ₃ is deposited.

Next, with reference to FIG. 13B, as illustrated, using conventional lithography followed by wet and / or dry etching processes such as hydrofluoric acid wet etching or chlorine dry etching or a combination of both. The layer 140 is patterned.

Then referring to FIG. 13C, this process is continued by selectively forming a layer 128 of the ALD NiO material as described above with respect to FIG. 12A on the patterned _{Al2O 3 layer} 140. As described above, the NiO layer 128 does not adhere to the SiNx layer 44 _, but adheres to the patterned _Al2O3 layer 140. This process is then continued as described above for FIG. 11B, where NiO is annealed in a reducing agent, for example a gas having hydrogen, and NiO is converted or reduced to Ni. As mentioned above, the absence of significant concentrations of -OH groups (such as those present on oxide layers such as SiO ₂ or Al ₂ O ₃ ) suppresses NiO metal deposition on SiNx. On the other hand, NiO easily adheres to Al ₂ O ₃ which is an oxide during ALD deposition.

This process is then continued as described above for FIGS. 11C-11E (or FIGS. 2H-K) and by FIG. 2L-2U.

Next, the gate of the metal-insulator-semiconductor FET (MISFET) will be described with reference to FIGS. 14A-14K. Therefore, here, as shown in FIG. 14B, an insulator layer 150, for example, Al ₂ O ₃ , is formed on the AlGaN layer 36 (FIG. 14A). Manufacture then added that the _{Al2O3 layer} 150 in addition to the portion of the SiNx layer 38 needs to be removed in order to form the windows _40'1-40'7 as shown in FIG. _14D . As a requirement, it proceeds in the same manner as in FIG. 2B-2F. _In practice, the fluorinated contact forming dry etching of SiNx is selective for the _Al2O3 layer 150. Removing Al ₂ O ₃ requires rare HF wet etching or chlorine-based dry etching.

As shown in FIG. 14E, the source (S) and drain (D) electrical contact structures _{42 1-427} are formed as described above with respect to FIG. 2D. After forming the electrical contact structure 42 _1-427 as described above in connection with FIG. 2D, this process continues with the dielectric layer 44 as described above with respect to FIG. 2E _- 2F, again in FIG. 14F. As shown, a SiN _x layer is formed.

Next, as shown in FIG. 14G, as described above with respect to FIG. 2F, an opening 46 is formed through the layer 44 and here the passivation layer 38, which is, for example, silicon nitride SiN _x 38. The etching used to form the opening 46 is stopped at the _{Al2O 3 layer} 150 using a timed etching process.

Next, as shown in FIG. 14H, as described above with respect to FIG. 11A, the nickel oxide (NiO) gate metal layer 128 is selectively deposited in the openings using the ALD. Next, with reference to FIG. 14I, as described above with respect to FIG. 11B, here the NiO layer 128 is annealed in a reducing agent, for example a gas having hydrogen, and the NiO layer 128 is converted to the Ni layer 128'. Be reduced. Next, as shown in FIGS. 14J-14K, this process is continued as described above for FIG. 11C-11E, or in lieu, this process is continued as in FIGS. 12A-12C and FIG. 2L-. 2U follows and the FET is completed.

It should no longer be understood that the method of forming the gate structure of a field effect transistor according to the disclosure is to prepare a semiconductor and provide a dielectric layer with an opening over a selected portion of the semiconductor. The gate metal formed on the semiconductor and selectively deposited on the dielectric layer and in the opening using the gate metal deposition process, and the deposited gate metal is said by the gate metal deposition process. Includes not adhering to the dielectric layer. The method may include one or more of the following features, either independently or in combination with other features: chemically reducing the original gate metal; the deposited gate metal , Which does not adhere to the dielectric layer but adheres to the semiconductor by the gate metal deposition process; or comprises forming an insulating layer on the semiconductor, the opening exposing and depositing the insulating layer. The gate metal to be formed does not adhere to the dielectric layer but adheres to the insulating layer by the gate metal deposition process.

It should also be understood that the method of forming the gate structure of an electric field effect transistor according to the disclosure is to prepare a semiconductor and form a non-oxide dielectric layer on the surface of the semiconductor. The non-oxide dielectric layer has openings disposed on selected portions of the surface of the semiconductor, and the non-oxide dielectric layer and the surface of the semiconductor are exposed. The selected portion is subjected to a gate metal deposition process, and the deposited gate metal does not adhere to the non-oxide dielectric layer and is placed on the exposed selected portion of the surface of the semiconductor. Includes adhering to the formed oxides. The method also forms an oxide insulating layer on the surface of the semiconductor, the openings expose the insulating layer of the oxide, and the deposited gate metal is produced by the gate metal deposition process. It may include the feature that it does not adhere to the non-oxide dielectric layer but adheres to the oxide insulating layer.

It should also be understood that the method of forming the gate structure of a field effect transistor according to the disclosure is to prepare a semiconductor and provide a dielectric layer with an opening over a selected portion of the semiconductor. Includes forming on the semiconductor and selectively depositing a gate metal in the opening. The method may include one or more of the following features, either independently or in combination with other features: chemically reducing the original gate metal; forming the original gate metal. Has atomic layer growth; the initial gate metal is a metal oxide; or the chemical reduction has the annealing of the deposited initial gate metal in a reducing agent.

It should also be understood that the method of forming a gate structure on a selected portion of a group III-V semiconductor according to the disclosure has an opening on the selected portion of the semiconductor. A dielectric layer is formed on the semiconductor, nickel oxide is formed on the surface exposed by the openings, and the nickel oxide is annealed in a reducing agent to convert the nickel oxide into nickel. Including that. The method may also include the feature that the initial formation of the nickel oxide has atomic layer growth.

It should also be understood that the method of forming the gate structure of a field effect transistor according to the disclosure is to prepare a semiconductor and provide a dielectric layer with an opening over a selected portion of the semiconductor. , The gate metal is selectively deposited in the opening by forming on the semiconductor and by atomic layer growth, and the deposited gate metal is chemically reduced.

Many embodiments of the present disclosure have been described. Nevertheless, it is understood that various changes can be made without departing from the spirit and scope of this disclosure. For example, the NiO metal 128 does not need to be reduced to the Ni metal 128'in any of the above embodiments, but may only be partially reduced. Therefore, other embodiments are also within the scope of the following claims.

Claims (10)

A method of forming the gate structure of a field effect transistor,
Prepare a semiconductor,
A non-oxide dielectric layer having an opening over a selected portion of the semiconductor is formed on the semiconductor.
The gate metal is selectively deposited on the non-oxide dielectric layer and in the opening using a gate metal deposition process, and the deposited gate metal is nickel oxide, and the gate metal deposition is performed. It does not adhere to the non-oxide dielectric layer by the process,
Chemically reducing the original gate metal,
How to have that. The method according to claim 1, wherein the deposited gate metal does not adhere to the non-oxide dielectric layer by the gate metal deposition process, but adheres to the semiconductor. The method comprises forming an insulating layer on the semiconductor, the opening exposing the insulating layer and the deposited gate metal being the non-oxide dielectric by the gate metal deposition process. The method according to claim 1, wherein the insulating layer is not adhered to the layer but is adhered to the insulating layer. A method of forming the gate structure of a field effect transistor,
Prepare a semiconductor,
An oxide insulating layer is formed on the semiconductor to form an oxide insulating layer.
A non-oxide dielectric layer is formed on the surface of the oxide insulating layer , and the non-oxide dielectric layer is placed on a selected portion of the surface of the oxide insulating layer . Has an opening,
The exposed selected portion of the surface of the non-oxide dielectric layer and the oxide insulating layer is subjected to a gate metal deposition process and the deposited gate metal is nickel oxide and the non-oxide. It does not adhere to the dielectric layer of the oxide, but to the exposed selected portion of the surface of the insulating layer of the oxide.
How to have that. A method of forming the gate structure of a field effect transistor,
Prepare a semiconductor,
A non-oxide dielectric layer having an opening over a selected portion of the semiconductor is formed on the semiconductor.
A gate metal is selectively deposited in the opening, and the gate metal is nickel oxide.
Chemically reducing the original gate metal,
How to have that. The method of claim 5 , wherein the initial formation of the gate metal has atomic layer growth. The method of claim 5 , wherein chemically reducing comprises annealing the initially deposited gate metal in a reducing agent. A method of forming a gate structure on a selected portion of a group III-V semiconductor.
A non-oxide dielectric layer having an opening over a selected portion of the semiconductor is formed on the semiconductor.
Nickel oxide is formed on the surface exposed by the opening and
The nickel oxide is annealed in a reducing agent to convert the nickel oxide into nickel.
How to have that. The method of claim 8 , wherein the initial formation of nickel oxide has atomic layer growth. A method of forming the gate structure of a field effect transistor,
Prepare a semiconductor,
A non-oxide dielectric layer having an opening over a selected portion of the semiconductor is formed on the semiconductor.
Atomic layer growth selectively deposits nickel oxide in the openings.
Chemically reducing the deposited nickel oxide ,
How to have that.

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