JP2007304110A - Contact substrate for semiconductor device test - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a test of an electronic component to be tested having a fine electrode structure while keeping satisfactory electric contact. <P>SOLUTION: This contact substrate includes a contact substrate 5 formed of a gas-permeable insulating material comprising either of liquid crystal polymer containing polytetrafluoroethylene and aramid or polyimide with 70% to 80% aperture ratio of a vacant hole, having an upper face and an under face, and having a plurality of conductive viae penetrating between the upper face and the under face in its inside, and adsorbing the electronic component to be tested 1 by air pressure, and a deformation restraining part 41 for restraining thermal expansion of the contact substrate 5 due to the difference between the thermal expansion coefficient of the electronic component to be tested 1 and the thermal expansion coefficient of the whole contact substrate 5, while the deformation restraining part 41 is projected and arranged from a plane which contacts with the electronic component to be tested so that the periphery of the plurality of the conductive viae may be surrounded. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device testing technique, and more particularly to a semiconductor device testing contact substrate used for reliability testing of a semiconductor device such as burn-in.

  Semiconductor devices need to be tested for their product life in the development and mass production processes, and are usually tested for reliability in various environments. . In a general semiconductor test process, an electrical characteristic test is first performed on a semiconductor wafer on which semiconductor elements constituting an electrical circuit are formed, and semiconductor chips are checked for good / bad. Next, dicing is performed to separate the wafer into chips. Next, assembly is performed in a package state. Next, an electrical property test is performed to select whether the package is good or bad. Next, a burn-in test (high temperature bias test) is performed, and reliability screening is performed. This burn-in test is performed at a temperature of 100 to tens of degrees Celsius for a period of several tens to several tens of hours in order to eliminate initial defects such as gate oxide film breakdown of transistors and wire breaks and shorts of semiconductor elements.

  Next, an electrical property test is performed as a final inspection. In a conventional reliability test of a semiconductor device, a test that requires a long time is performed by assembling a semiconductor chip into a package. In a general semiconductor test process, an unreliable chip assembly cost becomes a problem. Especially when many chips are mounted in one package like MCM (Multi Chip Module) or to supply COB (Chip On Board) bare die, KGD (Known Good Die) technology is used. It is necessary to perform a burn-in test before the assembly process.

  In contrast, as a chip-level burn-in test, each diced chip can be stored in a temporary package and a burn-in test can be performed. However, this method has a problem that the cost, the number of processes, and the process time increase due to KGD.

  Therefore, a wafer level burn-in test has been proposed. As described in Japanese Patent Application Laid-Open No. 10-284556, etc., in a wafer level burn-in test, a wafer is held with an element surface on which an electrode is formed on a base, and is provided on the wafer. A multilayer sheet having a protruding electrode at a position facing the electrode, a flexible member having conductivity at a position facing the electrode, and a burn-in base unit having high flatness in which wiring to the test circuit is formed; A burn-in device having a mechanism for applying pressure is used.

  The conventional semiconductor test apparatus as described above has the following problems. In the wafer level burn-in test, it is necessary to apply a large pressure in order to cover the height variation of the electrode bumps provided on the wafer. Especially, in the case of a thin wafer, the load is partially applied and the wafer is chipped or cracked. There is a risk. In the multilayer sheet, the conductor portion is provided with electrodes having a fine pitch of 100 μm and a length of 50 μm with respect to the electrodes, but this is sufficient when the pitch between the electrodes is reduced and the electrode size is reduced. It is conceivable that the contact area cannot be obtained.

  In particular, if the electrodes of the wafer, which is the electronic component under test, are uneven or the wafer itself is distorted by its own weight, even if the wafer is compressed into a contact substrate with a strong pressure, the contact substrate for each electrode of the wafer The contact areas of the electrodes greatly differ, and stable test results cannot be obtained. At this time, in order to bring all the electrodes on the wafer into contact with each other at a time, in the structure of the conventional burn-in apparatus, the substrate unit is required to have a strict flatness in order to avoid applying a local load. Furthermore, in order to relieve misalignment between electrodes and mechanical stress due to the difference in thermal expansion coefficient between the base material and the wafer, two components, a multilayer sheet and a member, are basically required. Since it is a product, the cost of the member increases.

  The present invention provides a contact substrate for testing a semiconductor device, which can test an electronic device under test having a fine electrode structure while maintaining good electrical contact.

According to the aspect of the present invention , the insulating material is formed of a breathable insulating material made of either polytetrafluoroethylene, a liquid crystalline polymer containing aramid or polyimide, and has an opening ratio of 70% to 80%. A contact board having a hole, an upper surface and a lower surface, a plurality of conductive vias connecting the upper surface and the lower surface, and sucking the electronic device under test through the hole; The surface that adsorbs the test electronic component is placed so as to surround the conductive via in a region other than the region where the conductive via is exposed, and the difference between the thermal expansion coefficient of the electronic device under test and the thermal expansion coefficient of the entire contact substrate There is provided a semiconductor device testing contact substrate including a deformation suppressing unit that suppresses thermal expansion of the contact substrate caused by the above.

  ADVANTAGE OF THE INVENTION According to this invention, the contact substrate for a semiconductor device test which can perform the test of the to-be-tested electronic component which has a fine electrode structure, hold | maintaining favorable electrical contact can be provided.

(First embodiment)
A semiconductor test apparatus and a semiconductor device test contact substrate according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a cross-sectional view of the semiconductor test apparatus according to the first embodiment. A large number of electrodes 2 are provided on the surface of the wafer element surface 3 of the semiconductor wafer 1 which is an electronic component to be tested. A surface opposite to the wafer element surface 3 of the semiconductor wafer 1 is a wafer back surface 4. A contact substrate (contact sheet) 5 is provided under the semiconductor wafer 1. The contact substrate 5 has an upper surface and a lower surface, and vias 6 provided over the upper surface and the lower surface of the contact substrate 5 are electrically and mechanically connected to the electrodes 2 of the semiconductor wafer 1, respectively.

  The contact substrate 5 is provided with a via 6 at the same position as the electrode 2 of the semiconductor wafer 1 of the electronic component to be tested. That is, the via 6 is provided at a position facing the electrode 2 of the semiconductor wafer.

  A multilayer wiring substrate 7 is provided below the contact substrate 5. The multilayer wiring board 7 is provided with wiring 10 on the surface and inside thereof and is electrically connected to the via 6 of the contact board 5. Electrode terminals 8 are provided on the upper surface of the multilayer wiring board 7 at positions facing the vias 6 of the contact substrate 5. A through hole 9 that leads from the upper surface to the lower surface of the multilayer wiring board 7 is provided in a portion where the electrode terminal 8 is not provided. The electrode terminal 8 is connected to the tester 13 by the test signal wiring 12 through the wiring 10. A wiring 10 having a plurality of layer structures is provided in the multilayer wiring board 7, and the wiring 10 is connected one-to-one with the upper and lower wirings 35 penetrating through the multilayer wiring board 7. Yes. The length of the upper and lower wirings 35 is set in accordance with the position of the wiring 10 to be connected.

  The semiconductor wafer 1, the contact substrate 5, and the multilayer wiring substrate 7 are fixed by the suction mechanism 11. That is, these constituent elements are fixed by the suction force passing through the contact substrate 5 and the suction holding force through the through holes 9 penetrating the upper and lower surfaces of the multilayer wiring board 7. That is, this attractive force is shown as a downward arrow in FIG. The envelope 14 surrounds the semiconductor wafer 1, the contact substrate 5, the multilayer wiring substrate 7, and the suction mechanism 11. When the semiconductor test apparatus is a burn-in apparatus, the envelope 14 includes a heating element (not shown) in an atmosphere that supplies heat to the electronic device under test in order to raise the electronic device under test to a desired burn-in temperature. Z)). Alternatively, a heat absorption mechanism (not shown) such as heat generation of the semiconductor wafer and a heat dissipation mechanism (not shown) such as heat generation of the semiconductor wafer are provided.

  Further, the suction mechanism 11 includes a stage on which the multilayer wiring board 7 is mounted as a metal box, and a hole or a groove is provided in the receiving portion of the multilayer wiring board 7 to suck the multilayer wiring board 7. As another example, a porous ceramic plate is placed on the receiving portion of the multilayer wiring board 7 to adsorb the multilayer wiring board 7.

  A top view showing the structure inside the envelope of this semiconductor test apparatus is shown in FIG. Here, the electrode 2 of the semiconductor wafer 1 is shown through. That is, as shown in the cross-sectional view of FIG. 1, the electrode 2 of the semiconductor wafer 1 is provided to face the upper surface of the contact substrate 5 and cannot actually be seen from the upper surface. The same number and the same arrangement of the electrodes 2 of the semiconductor wafer are provided for each of the semiconductor chips 20 provided. Under the contact substrate 5, a multilayer wiring substrate 7 is provided. Here, the contact substrate 5 may have a quadrilateral shape other than the illustrated disk shape, and the outer shape of the contact substrate 5 may be an easy-to-handle shape as long as vias are arranged so as to coincide with the electrodes of the electronic component to be tested. .

  Next, the structure of the contact substrate 5 will be described with reference to FIG. FIG. 3A showing a cross section of the contact substrate 5 shows a state in which a through hole 25 penetrating the upper and lower surfaces is provided between the plurality of vias 6. As shown in a cross-sectional view in FIG. 3B, which is an enlarged view of a portion X in FIG. 3A, the contact substrate 5 is formed of a porous sheet base material 26 having a mesh-like irregular structure. Yes. A large number of holes 27 are provided in the sheet base material 26. The air holes 27 are provided not only in the cross section but over the entire sheet base material 26.

  Here, the via portion 28 is formed with the via 6 in which the hole 27 is filled with a conductive metal, for example, copper. This hole 27 has a portion formed so as to be in contact with each other, in which a via 6 extending from the upper surface to the lower surface of the contact substrate 5 is formed. Adhesion is very good by using an insulating porous (network) sheet such as polytetrafluoroethylene (PTFE), liquid crystalline polymer containing polyimide or aramid for the sheet base material of the contact substrate 5 Gain power. This is because, in addition to good air permeability of the porous sheet, the elasticity of the surface of the contact substrate 5 and the semiconductor wafer 1 can be absorbed by its elasticity.

  Since the contact substrate 5 is provided with holes with an opening ratio of 70% to 80%, for example, a sufficient atmospheric pressure can be transmitted between the upper surface and the lower surface of the contact substrate 5. Further, since the sheet portion other than the via 6 bends during the burn-in heating, the effect of absorbing the difference in the coefficient of thermal expansion from the semiconductor wafer 1 and causing no positional deviation between the electrodes 2 is expected.

  Here, the reason why copper is used as a wiring or via material is that its resistivity is extremely small, and it is also possible to use another conductive material having a low resistivity instead of copper. By using this porous sheet base material 26 as the contact substrate 5, the step of providing an opening in the via portion 28 for forming the via 6 is not necessary. Here, the via shape may be any shape such as a circle, a rectangle, a cone, or a trapezoid. In addition, as a contact substrate, it is also possible to use a sheet having a high aperture ratio by providing a large number of through holes instead of the porous sheet. In the case of a contact substrate that is provided with a large number of holes as shown in FIG. 3B and can be adsorbed, it is not necessary to provide a through hole. In order to provide the versatility of the contact substrate, vias may be provided in excess of the number of electrodes of the electronic device under test so that it can be used for a plurality of types of electronic devices under test.

  In addition, it is preferable for the gas flow that the through hole 9 provided in the multilayer wiring substrate 7 is provided at the same position as the through hole 25 of the contact substrate 5. Such a multilayer wiring board 7 may have any structure as long as gas passes through the openings provided in a number other than the wiring portion used as the wiring, so that the atmospheric pressure can be transmitted between the upper and lower sides. The suction force of the suction mechanism for performing a burn-in test to test the electrical characteristics by applying high temperature to the electronic device under test is to bring the electronic device under test into close contact with the contact substrate and the contact substrate into close contact with the multilayer wiring board, and It is sufficient that the contact area is sufficient to allow a current to flow from the test circuit to the test signal input / output terminal of the electronic device under test with a small resistance.

    According to the first embodiment, even when the number of electrodes of the electronic device under test is large, a wiring substrate is provided under the contact substrate to realize necessary vias and wiring, and uniform pressure is applied to the entire surface by adsorption force. Thus, the electrode of the electronic device under test is brought into contact with the electrode of the contact substrate, and a stable test result can be obtained even when the electronic device under test is large.

  As described above, in the semiconductor test apparatus, the contact substrate used for electrical connection between the semiconductor wafer and the test circuit is made of a porous body, and the suction mechanism is provided on the stage that receives the contact substrate. Even if there is no pressurization control, a uniform load can be applied between the electrodes of the semiconductor wafer and the bumps of the contact substrate, and stable electrical contact can be easily obtained.

  In particular, in the first embodiment, a suction force is used when the electrodes of the semiconductor wafer and the bumps of the contact substrate are brought into contact with each other, so that a uniform force can be applied to the electrodes on the entire surface of the semiconductor wafer. In this way, an even load can be applied to the electrodes on the semiconductor wafer, and even in the case of a thinner and larger semiconductor wafer, the electrodes and bumps can be brought into contact without applying an excessive load to the semiconductor wafer. . Further, since the contact substrate is a porous body, it can be adsorbed from the entire surface of the contact substrate, and sufficient contact can be obtained especially when the number of electrodes is large.

  In the first embodiment, an electronic component to be tested is not limited to a semiconductor wafer, and may be an electronic component such as a semiconductor chip or a semiconductor device mounted on a package.

  As described above, according to the first embodiment, even if the electrode of the semiconductor wafer as the electronic device under test is uneven or the semiconductor wafer itself is distorted by its own weight, the electrode of the semiconductor wafer is not deformed. Since the semiconductor wafer is compressed to the contact substrate with a uniform adsorption force over the entire formed surface, the contact area to the bump of the contact substrate can be prevented for each electrode of the semiconductor wafer, and stable test results can be obtained. Obtainable.

    In addition, the number of manufacturing processes in the test and the number of component materials of the test apparatus can be reduced compared to the conventional burn-in test apparatus at the wafer level.

(Modification of the first embodiment)
In a modification of the first embodiment, a semiconductor test apparatus having a structure as shown in FIG. 4 is provided. Here, the structure of the contact substrate is different from that of the first embodiment, and a multilayer wiring board is not used, but otherwise, it has the same structure as that of the first embodiment. The contact substrate 29 has an upper surface and a lower surface, and wiring 30 is provided on the upper surface and the lower surface of the contact substrate 29. Vias 31 connected to the wirings 30 on a one-to-one basis are provided across the upper and lower surfaces of the contact substrate 29. Of the vias 31, there may be electrode vias 33 that are arranged only on the upper surface of the contact substrate 29 and are not provided to penetrate to the lower surface. The electrode via 33 provided only on the upper surface of the contact substrate 29 is connected to the wiring 30 provided on the upper surface of the contact substrate 29. Each via 31 and electrode via 33 are electrically and mechanically connected to the electrode 2 of the semiconductor wafer 1, respectively. That is, the contact substrate 29 is provided with a via 31 at the same position as the electrode 2 of the semiconductor wafer 1 of the electronic device under test.

  The wiring 30 is connected to the tester 13 by the test signal wiring 12. When the semiconductor wafer 1 and the contact substrate 29 are constituted by through holes or porous bodies penetrating the upper and lower surfaces of the contact substrate 29 by the adsorption mechanism 11, they are fixed by the adsorption holding force through the pores in the porous body. Has been. In this modification as well, when the contact substrate 29 is formed of a porous body, copper is embedded in the holes in the contact substrate 29 to form the vias 31.

  As described above, when the number of electrodes of the electronic device under test is relatively small or when the distance between the electrodes of the electronic device under test is large, wiring is performed above and below the contact substrate 29 as in the modification of the first embodiment. Can be connected to the test signal wiring 12. In this case, a multilayer wiring board is not required as in the first embodiment, and the number of components of the semiconductor test apparatus can be reduced.

(Second Embodiment)
A semiconductor test apparatus and a semiconductor device test contact substrate according to the second embodiment will be described with reference to FIGS. FIG. 5 shows a partial cross section of a semiconductor wafer 50 which is an electronic component under test. A plurality of electrodes 51 and high-load electrodes 52 are provided on the lower surface of the semiconductor wafer 50. The high load electrode 52 is given a larger load on the surface than the other electrodes 51. The high-load electrode 52 is generated when the height is higher than the other electrodes 51, or when the periphery of the high-load electrode 52 protrudes due to distortion of the electronic component under test. When a test is performed by applying the contact substrate of the first embodiment to a semiconductor wafer having such a high-load electrode, impact on the high-load electrode or connection between another electrode and a via of the contact substrate Defects may occur.

  When testing an electronic device under test having such a high load electrode, in the second embodiment, a contact substrate whose cross section is shown in FIG. 6 is used. A contact substrate 53 is provided under the semiconductor wafer 50 which is an electronic component to be tested. The contact substrate 53 has an upper surface and a lower surface, and vias 55 provided over the upper surface and the lower surface are electrically and mechanically connected to the electrodes 51 of the semiconductor wafer 50, respectively. The via 55 has a cylindrical hollow shape. Further, a compressed via 56 whose shape is compressed more than the other vias 55 is electrically and mechanically connected under the high load electrode 52.

  The via 55 and the compressed via 56 are electrically connected to the wiring 30 formed on the lower surface or the upper surface of the contact substrate 53. The contact substrate 53 is provided with a via 55 at the same position as the electrode 51 of the semiconductor wafer 50 of the electronic device under test. The semiconductor wafer 50 and the contact substrate 53 are fixed by an adsorption mechanism 58 by an adsorption holding force through a through hole 59 penetrating the upper and lower surfaces of the contact substrate 53 and a through hole 49 around the wiring 30. This attractive force is shown as a downward arrow in FIG. The semiconductor wafer 50, the electrode 51, and the suction mechanism 58 are accommodated in an envelope (not shown).

  Next, the shape of the via used in the second embodiment will be described with reference to FIGS. 6 and 7 which are sectional views. As shown in FIG. 6, the via 55 formed in the contact substrate 53 is in a state in which the porous portion of the contact substrate 53 is filled with copper by plating. Since the via 55 is hollow, the via 55 itself functions as a compressible spring, and when the stress is applied, the via is easily dented. In this way, stress and impact on the electrode 51 of the semiconductor wafer 50 and the via 55 of the contact substrate 53 can be relaxed.

  When the via is hollow, the shape of the via may be a shape in which the side surface of the cylinder is partially cut away as shown in FIG. That is, the contact surfaces 60 are provided on the upper and lower sides, the contact surfaces 60 are connected by the connecting surface 61, and a cavity 62 is provided in a part of the connecting surface 61.

  Further, as shown in FIG. 7B, a shape in which the side surface of the quadrangular prism is partially cut off may be used. That is, the contact surfaces 63 are provided on the upper and lower sides, the contact surfaces 63 are connected to each other by the connection surface 64, and a cavity 65 is provided in a part of the connection surface 64.

  Further, as shown in FIG. 7C, the rectangular column shown in FIG. 7B is partially cut away, and a slit 66 is further provided in a part of the connecting surface 64. Also good.

  Further, as shown in FIG. 7D, a plating network structure may be used. That is, the contact surfaces 67 are provided on the upper and lower sides, the contact surfaces 67 are connected to each other by a thread-like connecting body 68, and a cavity is provided inside the connecting body 68.

  Further, as shown in FIG. 7E, the connecting body 69 may be in a spring shape and connect the contact surfaces 67 of the upper surface and the lower surface.

  Further, as shown in FIG. 7 (F), the contact surface 67 on the upper surface and the contact surface 67 on the lower surface are displaced in the vertical direction, and the connection surface 64 is partly connected in an S shape therebetween. May be.

  Further, as shown in FIG. 7G, the upper contact surface 67 and the lower contact surface 67 may be partially connected by a columnar connecting surface 64.

  By using the contact substrate configured as described above in the semiconductor device test apparatus according to the second embodiment, the same effects as those of the first embodiment can be obtained.

  Although the contact substrate according to the second embodiment can be applied to a semiconductor test apparatus having an adsorption mechanism as shown in FIG. 1, the contact substrate is placed on a stage and does not have an adsorption mechanism. It can also be applied to a type of semiconductor test equipment.

  Furthermore, according to the semiconductor device testing contact substrate of the second embodiment, the stress relaxation effect on the wafer electrode can be obtained by devising the elasticity and via shape of the contact substrate.

(Third embodiment)
A semiconductor device test contact substrate according to a third embodiment will be described with reference to FIG. PTFE and polyimide, which are considered as materials for the contact substrate used in the first embodiment, have a very large coefficient of thermal expansion as compared with the semiconductor wafer. During the burn-in test, the atmosphere in the semiconductor test apparatus reaches 125 ° C. due to heat generated from the semiconductor wafer, so that the contact substrate is deformed and the positional deviation between the electrodes is concerned. In order to solve such a problem, in the third embodiment, as shown in FIG. 8, a material having a low thermal expansion coefficient such as Ni is partially plated on the contact surface side of the contact substrate 40 with the semiconductor wafer. Thus, the deformation suppressing portion 41 is formed. The deformation suppressing portion 41 is provided in a region other than the region where the via 42 is formed, so that there is no problem in the connection between the semiconductor wafer and the contact substrate.

  By providing the deformation suppressing portion 41, the thermal expansion of the contact substrate 40 can be suppressed and the electrical connection can be maintained. Here, in FIG. 8, the contact substrate 40 is rectangular, but other shapes may be used. Note that the contact substrate is preferably configured to match the overall shape of the electronic device under test.

  The cross-sectional structure of this contact substrate will be described with reference to FIG. In the example shown in FIG. 9A, a deformation suppressing portion 41 is provided through the upper and lower surfaces of the contact substrate 40, and a plurality of vias 42 connect the upper and lower surfaces of the contact substrate 40 between the deformation suppressing portions 41. It is provided through. Further, as shown in FIG. 9B, the deformation suppressing portion 41 may be formed only on the upper surface and the lower surface of the contact substrate 40.

  Next, the shape of the deformation suppressing portion 41 of the contact substrate 40 is not limited to the grid-cut shape shown in FIG. 8, but as long as the shape is integrally connected to each other, as shown in FIG. The deformation suppressing portion 41 may be formed so as to surround the via 42 in a grid pattern, or may be configured in a wave shape as shown in FIG. 9D, and further, as shown in FIG. Thus, it may have a chain structure. That is, a plurality of deformation suppressing portions may be provided so as to surround the periphery of each of several vias and connected to each other. Thus, by increasing the density of the deformation suppressing portion, the effect of suppressing the deformation of the contact substrate is enhanced.

  Here, the deformation suppression portion formed on the contact substrate performs thermal expansion so that the thermal expansion coefficient of the entire contact substrate is ± 6 ppm / K or less with respect to the thermal expansion coefficient of the electronic component to be tested. Forming with the material which suppresses is preferable when suppressing a deformation | transformation of a contact substrate. The deformation suppressing portion can be formed by performing metal plating or resin impregnation on the contact substrate with a low thermal expansion coefficient in accordance with the thermal expansion coefficient of the wafer.

  In addition, the material constituting the deformation suppressing unit may be a metal such as Cu, Au, or Sn other than Ni.

  Furthermore, the material constituting the deformation suppressing portion is a resin that is conventionally used as an insulator of a printed wiring board such as resins instead of Ni, for example, epoxy resin, bismaleimide-triazine resin, PEEK resin, butadiene resin, and the like. Polyolefins such as polyethylene and polypropylene, polydienes such as polybutadiene, polyisoprene and polyvinylethylene, acrylic resins such as polymethyl acrylate and polymethyl methacrylate, polyacrylonitrile derivatives such as polystyrene derivatives, polyacrylonitrile and polymethacrylonitrile Polyacetals such as polyoxymethylene, polyethylene terephthalate, polybutylene terephthalate, etc. and polyesters containing aromatic polyesters, polyarylates, aromatic polymers such as aramid resin Fluorides such as polyamides such as amide and nylon, polyimides, epoxy resins, aromatic polyethers such as poly-p-phenylene ether, polyethersulfones, polysulfones, polysulfides, polytetrafluoroethylene (PTFE) Polymers, polybenzoxazoles, polybenzothiazoles, polyphenylenes such as polyparaphenylene, polyparaphenylene vinylene derivatives, polysiloxane derivatives, novolac resins, melamine resins, urethane resins, polycarbodiimide resins, etc. Also good.

  Furthermore, the material constituting the deformation suppressing unit may be ceramics, for example, metal oxides such as silica, alumina, titania, potassium titanate, and metals such as silicon carbide, silicon nitride, and aluminum nitride.

  By using the contact substrate of the third embodiment in the semiconductor test apparatus of the first embodiment, the same effects as those of the first embodiment can be obtained, and further, the heat of the wafer can be obtained as described above. By performing metal plating or resin impregnation with a low thermal expansion coefficient on the contact substrate in accordance with the expansion coefficient, it is possible to prevent displacement between the electrodes of the contact substrate and the semiconductor wafer that is the electronic device under test due to a temperature rise during the test.

(Fourth embodiment)
In each of the above-described embodiments, bumps, BGA balls, or the like having high heights may be formed on the electrodes of a semiconductor wafer that is an electronic device under test during a test such as burn-in. In this case, the step cannot be absorbed only by the elasticity of the contact substrate, and a sufficient suction force cannot be obtained. That is, a thin contact substrate with a film thickness of about several tens of μm to 100 μm cannot be recessed so as to absorb the convex portion of a high electrode having a height equal to or higher than the thickness of the contact substrate. In that case, pressure leaks from a gap formed between the contact substrate and the semiconductor wafer, and the semiconductor wafer cannot be connected to the electrode of the contact substrate with a sufficient adsorption force. The semiconductor device test contact substrate according to the fourth embodiment suppresses such a phenomenon.

  FIG. 10 is a perspective view of a contact substrate according to the fourth embodiment. The contact substrate 70 is provided with vias 72 extending from the upper surface to the lower surface. A protrusion 73 is provided on the upper surface of the outermost via of the outermost via. The protrusion 73 is made of a material such as resin, ceramic, or metal. The protrusion 73 is provided on the contact substrate 70 to suppress air leakage in accordance with the shape of the semiconductor wafer that is the electronic device under test mounted on the contact substrate 70. In addition, this projection part 73 may be provided in the lower surface.

  In FIG. 11, which shows a cross-section in a state where the electronic device under test is mounted on the contact substrate 70, the protrusion 73 contacts the lower surface of the peripheral portion of the semiconductor wafer 1, and between the semiconductor wafer 1 and the contact substrate 70. Air leakage is prevented. Further, air leakage between the contact substrate 70 and the multilayer wiring substrate 7 is prevented on the multilayer wiring substrate 7 on which the contact substrate 70 is mounted. In FIG. 10, the protrusions 73 are provided only on the outer periphery of the contact substrate 70, but the cross section shown in FIG. 11 shows a structure in which the protrusions 73 are also provided inside the contact substrate at regular intervals. Yes.

  The contact substrate 70 has the same structure as the contact substrate of the first embodiment except that the protrusion 73 is provided.

  Here, it is necessary to provide the protrusion 73 in a shape that completely covers the outer periphery of the semiconductor wafer 1 in order to prevent air leakage. The protrusion 73 is provided outside the region where the via 72 is formed, so that there is no hindrance to the connection between the semiconductor wafer 1 and the contact substrate 70. Here, in FIG. 10, the contact substrate 70 is rectangular, but other shapes may be used. Note that the contact substrate is preferably configured to match the overall shape of the electronic device under test.

  Next, the cross-sectional structure of the contact substrate 70 will be described with reference to FIG. In the example shown in FIG. 12A, protrusions 73 are provided at the same position on both the upper and lower surfaces of the contact substrate 70. In the structure shown in FIG. 12B, an example in which the protrusion 73 is provided only on the upper surface of the contact substrate 70 is shown. In the structure shown in FIG. 12C, an example in which the protrusion 73 is provided only on the lower surface of the contact substrate 70 is shown. As described above, in accordance with the unevenness of the electrodes of the electronic device under test or the multilayer wiring board, the protrusions can be provided on only the upper surface side, only the lower surface side, or both the upper and lower surfaces of the contact substrate.

  Further, the projection 73 having the air leakage prevention function can also be used as the deformation suppressing unit 41 described in the third embodiment. That is, as shown in FIG. 8, since the deformation suppressing portion 41 is formed on the outer periphery of the contact substrate 40, it also functions as an air leakage preventing protrusion. Also in the fourth embodiment, after obtaining the same effect as in the first embodiment, when the height of the convex portion of the electrode of the semiconductor wafer is large, air leakage is prevented and sufficient adsorption power of the semiconductor wafer is obtained. Is obtained.

(Fifth embodiment)
The structure of the semiconductor device test contact substrate of the fifth embodiment will be described with reference to FIG. In the contact substrate 110 whose sectional structure is shown in FIG. 13A, a plurality of vias 111 are provided through the upper and lower surfaces at regular intervals. The via 111 is formed at a position facing the electrode terminal of the electronic device under test and the electrode terminal of the multilayer wiring board.

  In this contact substrate 110, the air hole for fixing the contact substrate 110 is not provided in the adsorption mechanism, and the contact substrate 110 is made of a porous body, and the pores of the porous portion function in the same manner as the through holes. Fulfill. FIG. 13B shows an enlarged view of a Y portion in FIG. The contact substrate 110 is formed of a sheet base material 115 and provided with a large number of holes 113. In the via portion 112, the hole portion is filled with a conductor. Thus, the via 111 and the sheet base material 115 are integrated. As the conductor to be filled, copper or the like can be used. Here, since the adjacent holes 113 are connected to each other, the filled copper continues. Plating can be used as a method for filling the holes 113 with copper.

(Sixth embodiment)
A semiconductor device test method according to the sixth embodiment will be described. First, a semiconductor test apparatus having the structure shown in FIG. 1 described in the first embodiment is prepared. A contact substrate 5 having the above-described configuration is prepared.

  Next, the contact substrate 5 is mounted and connected so that the via 6 is located at a position opposite to the surface of the surface of the semiconductor wafer 1 on which the electrode 2 of the electronic device under test is formed.

  Next, the contact substrate 5 is mounted on the multilayer wiring substrate 7. At this time, alignment is performed so that the electrode terminal 8 of the multilayer wiring board 7 is positioned at a position facing the position of the via 6 of the contact board 5.

  Next, the semiconductor wafer 1, the contact substrate 5, the multilayer wiring substrate 7, and the suction mechanism 11 are sealed in the envelope 14 so as to be confined. The inside of the semiconductor test apparatus surrounded by the envelope 14 is purged with, for example, nitrogen.

  Next, the suction mechanism 11 is operated to perform evacuation, and the contact between the electrode 2 of the semiconductor wafer 1 and the via 6 of the contact substrate 5 is strengthened and bonded. In this way, the semiconductor wafer 1 and the contact substrate 5 are firmly adhered in a state where no positional deviation occurs.

  Next, a temperature control device (not shown) is operated as necessary, and the semiconductor wafer 1 is heated until a temperature necessary for the test is reached. Or depending on the case, it cools to required temperature. The semiconductor test apparatus is insulated from the external environment and can obtain the temperature required for the test.

  Thereafter, the tester 13 is operated to test the semiconductor wafer 1. In this way, all tests can be performed in the wafer state.

  As described above, in the semiconductor test apparatus, the contact substrate used for electrical connection between the semiconductor wafer and the test circuit is made of a porous body, and the suction mechanism is provided on the stage that receives the contact substrate. Even if no pressure control is applied to the semiconductor wafer, a uniform load can be applied between the electrode of the semiconductor wafer and the contact substrate, and it becomes easy to obtain stable electrical contact.

  In particular, in the sixth embodiment, since the adsorption force is used when the electrode of the semiconductor wafer is brought into contact with the contact substrate, a uniform force can be applied to the electrode on the entire surface of the semiconductor wafer. Thus, an even load can be applied to the electrodes on the semiconductor wafer, and even in the case of a thinner and larger semiconductor wafer, the electrodes can be brought into contact with each other without applying an excessive load to the semiconductor wafer. Further, since the contact substrate is a porous body, it can be adsorbed from the entire surface of the contact substrate, and sufficient contact can be obtained especially when the number of electrodes is large.

  In the sixth embodiment, the electronic device under test to be tested is not limited to a semiconductor wafer, but may be an electronic component such as a semiconductor chip or a semiconductor device mounted on a package.

  As described above, according to the sixth embodiment, even if the electrode of the semiconductor wafer as the electronic device under test is uneven or the semiconductor wafer itself is distorted by its own weight, the electrode of the semiconductor wafer is not deformed. Since the semiconductor wafer is compressed to the contact substrate with a uniform adsorption force over the entire formed surface, the contact area to the bump of the contact substrate can be prevented for each electrode of the semiconductor wafer, and stable test results can be obtained. Obtainable. In addition, the number of manufacturing processes in the test and the number of component materials of the test apparatus can be reduced compared to the conventional burn-in test apparatus at the wafer level.

(Modification of the sixth embodiment)
In the modification of the sixth embodiment, a test is performed using a semiconductor test apparatus having a structure shown in FIG. In the semiconductor test apparatus having the structure shown in FIG. 14, the multilayer wiring board 120 is held by a stage 122 instead of the suction mechanism, and the multilayer wiring board 120 is not provided with a through hole. A pressure mechanism 123 is provided so as to compress the semiconductor wafer 1. Other structures are the same as those of the semiconductor test apparatus of FIG. Here, the semiconductor wafer 1 and the contact substrate 5 are connected so that the via 6 of the contact substrate 5 is located at a position facing the electrode 2 of the semiconductor wafer 1. Further, the electrode terminals 121 of the multilayer wiring board 120 and the vias 6 of the contact board 5 are aligned and compressed and fixed by the pressurizing mechanism 123 at positions facing each other.

  A semiconductor wafer test can be performed by executing the semiconductor test apparatus configured as described above except for the step of operating the suction mechanism in the sixth embodiment.

  According to the test method for a semiconductor device according to the modification of the sixth embodiment, even if the electrodes of the semiconductor wafer that is the electronic component under test are uneven or the semiconductor wafer itself is distorted by its own weight. Since the semiconductor wafer is compressed to a contact substrate that expands and contracts in response to the stress with a uniform compressive force over the entire surface of the semiconductor wafer electrode, the contact area to the bump of the contact substrate for each electrode of the semiconductor wafer Can be prevented, and stable test results can be obtained. In addition, by selecting a via having an optimal shape for stress relaxation and using a contact substrate having the via shape having the structure described in the second embodiment, stress relaxation on the electrode of the electronic component to be tested is further achieved. be able to.

(Seventh embodiment)
A method for testing a semiconductor device according to the seventh embodiment will be described with reference to FIG. First, as shown in FIG. 15A, a semiconductor chip 83 having a plurality of solder bumps 85 formed on the lower surface is prepared as an electronic device under test. Further, a contact substrate 80 having a structure similar to that of the contact substrate in the first embodiment is prepared. A plurality of vias 82 are formed in the contact substrate 80. The solder bump 85 may be a gold bump.

  Next, as illustrated in FIG. 15B, the semiconductor chip 83 is connected to the contact substrate 80. At this time, melt bonding is performed after aligning the solder bumps 85 of the semiconductor chip 83 and the vias 82 of the contact substrate 80 so as to face each other.

  Next, the semiconductor chip is tested in the same manner as in the sixth embodiment. That is, the semiconductor chip is tested as an electronic component to be tested instead of the semiconductor wafer in the sixth embodiment.

  Next, as shown in FIG. 15C, the semiconductor chip 83 is peeled off from the contact substrate 80. Here, when the peeled semiconductor chip 83 is confirmed to be a non-defective product, it can be used by being mounted on another substrate.

  Here, the contact substrate 80 has a porous sheet shape with air permeability, and the via 82 is filled into the pores of the porous body by copper plating and integrated with the contact substrate 80. The semiconductor chip 83 can be peeled off with minimal damage to the bumps 85. That is, the via 82 is formed by inserting copper plating into a hole in the contact substrate 80, and when the electronic device under test is joined with solder on the via 82, when the electronic device under test is separated, The copper remains, and the solder is easily separated. Since the electronic device under test can be easily separated from the contact substrate in this way, the electrodes of the electronic device under test are less damaged and can be used as usual.

  Since the electronic device under test and the contact substrate are bonded with solder, if sufficient adhesion strength is obtained, there will be no misalignment even when the test is not performed. The same effect as that of the sixth embodiment can be obtained by performing the same test as the modification of the sixth embodiment using the semiconductor chip and the contact substrate in the seventh embodiment. Furthermore, the same effect as that of the sixth embodiment can be obtained by performing the same test as that of the sixth embodiment by using the semiconductor chip and the contact substrate in the seventh embodiment.

(Eighth embodiment)
A semiconductor device and a manufacturing method thereof according to the eighth embodiment will be described with reference to FIGS. As shown in FIG. 16A, a semiconductor chip 98 having a plurality of solder bumps 95 provided on the lower surface is connected to the contact substrate 91. Here, the contact substrate 91 has the same structure as the contact substrate shown in the first embodiment. The vias 92 of the contact substrate 91 and the solder bumps 95 of the semiconductor chip 98 are aligned and connected at opposite positions. Next, in place of the semiconductor wafer, the semiconductor chip is tested as in the sixth embodiment. That is, after a semiconductor chip is manufactured, it is mounted on a contact substrate having a via that also serves as a CSP substrate and a test is performed.

  As a result of the test, it is confirmed that the semiconductor chip 98 and the contact substrate 91 are connected to each other after the semiconductor chip 98 and the contact substrate 91 are connected. The upper surface is covered. Here, since the contact substrate 91 is formed of a porous sheet, the pores of the porous body are impregnated with the resin 99. In this way, the resin 99 enters the contact substrate 91, the resin 99 and the contact substrate 91 are integrated, and the connection strength between the contact substrate 91 and the semiconductor chip 98 is increased. Here, the optimum physical property value of the resin 99 is a coefficient of thermal expansion and an elastic modulus, and serves as an index for improving the reliability of the package of the semiconductor device. Through simulation, an optimum solution for the thermal expansion coefficient and elastic modulus of the contact substrate is determined depending on the size and thickness of the semiconductor chip, and it is possible to use an optimal resin for resin sealing.

  Next, as shown in FIG. 16B, the solder bumps 100 are connected to the vias 92 on the lower surface of the contact substrate 91 to obtain a semiconductor device. The solder bump 95 of the semiconductor chip 98 and the solder bump 100 of the contact substrate 91 may be gold bumps. In this way, one CSP (Chip Scale Package) type semiconductor device is obtained. Since the electronic device under test and the contact substrate are bonded with solder and resin, if sufficient adhesion strength is obtained, there will be no misalignment when the test is performed without adsorption. Even if it is not used, the eighth embodiment can be implemented.

  Thus, according to the eighth embodiment, a resin having a highly reliable package is selected by selecting a resin having optimum physical properties according to the characteristics of the semiconductor chip and filling the contact substrate with this resin. An apparatus and a manufacturing method thereof can be provided.

  Furthermore, according to the eighth embodiment, the process of separating the contact substrate connected for testing from the semiconductor chip and the process of mounting the semiconductor chip on the CSP substrate are unnecessary, and the number of manufacturing processes can be reduced. it can.

  Each embodiment can be implemented in combination. In each embodiment, the electronic device under test may be a semiconductor chip cut out from a semiconductor wafer in advance. In this case, the semiconductor device can be obtained as it is after the test is completed. In each embodiment, a semiconductor device test apparatus, a test method, and a semiconductor device test contact substrate have been described. However, each embodiment also applies to an electronic component test apparatus, a test method, and an electronic component test contact substrate. Applicable.

1 is a cross-sectional view illustrating a semiconductor test apparatus according to a first embodiment of the present invention. 1 is a top view illustrating a semiconductor test apparatus according to a first embodiment of the present invention. FIG. 3A is a cross-sectional view of the contact substrate according to the first embodiment of the present invention.

FIG. 3B is an enlarged sectional view showing a part of the contact substrate according to the first embodiment of the present invention.
FIG. 4 is a cross-sectional view showing a semiconductor test apparatus according to a modification of the first embodiment of the present invention. It is sectional drawing showing the to-be-tested electronic component which concerns on the 2nd Embodiment of this invention. It is sectional drawing showing the semiconductor test apparatus which concerns on the 2nd Embodiment of this invention. FIG. 7A is a perspective view illustrating an exemplary structure of a via according to the second exemplary embodiment of the present invention.

  FIG. 7B is a perspective view showing another example structure of the via according to the second exemplary embodiment of the present invention.

  FIG. 7C is a perspective view illustrating another example structure of the via according to the second exemplary embodiment of the present invention.

  FIG. 7D is a perspective view illustrating an exemplary structure of a via according to the second exemplary embodiment of the present invention.

  FIG. 7E is a perspective view showing another example structure of the via according to the second exemplary embodiment of the present invention.

  FIG. 7F is a perspective view illustrating another example structure of the via according to the second exemplary embodiment of the present invention.

FIG. 7G is a perspective view illustrating an exemplary structure of a via according to the second exemplary embodiment of the present invention.
It is a perspective view showing the contact substrate which concerns on the 3rd Embodiment of this invention. FIG. 9A is a cross-sectional view illustrating an example of a contact substrate according to the third embodiment of the present invention.

  FIG. 9B is a cross-sectional view illustrating an example of a contact substrate according to the third embodiment of the present invention.

  FIG. 9C is a top view illustrating an example of a contact substrate according to the third embodiment of the present invention.

  FIG. 9D is a top view illustrating an example of a contact substrate according to the third embodiment of the present invention.

FIG. 9E is a top view illustrating an example of a contact substrate according to the third embodiment of the present invention.
It is a perspective view showing the contact substrate which concerns on the 4th Embodiment of this invention. It is sectional drawing showing the semiconductor test apparatus which concerns on the 4th Embodiment of this invention. FIG. 12A is a cross-sectional view illustrating an example of a contact substrate according to the fourth embodiment of the present invention.

  FIG. 12B is a cross-sectional view illustrating an example of a contact substrate according to the fourth embodiment of the present invention.

FIG. 12C is a cross-sectional view illustrating an example of a contact substrate according to the fourth embodiment of the present invention.
FIG. 13A is a cross-sectional view showing a structure of a contact substrate according to the fifth embodiment of the present invention.

FIG. 13B is an enlarged sectional view showing a part of the contact substrate according to the fifth embodiment of the present invention.
FIG. 14 is a cross-sectional view showing a semiconductor test apparatus according to a modification of the sixth embodiment of the present invention. FIG. 15A is a cross-sectional view showing one step in a method for testing a semiconductor device according to the seventh embodiment of the present invention.

  FIG. 15B is a cross-sectional view showing one step in a method for testing a semiconductor device according to the seventh embodiment of the present invention.

FIG. 15C is a cross-sectional view showing one step in the method for testing a semiconductor device according to the seventh embodiment of the present invention.
FIG. 16A is a cross-sectional view illustrating a step of the method of manufacturing a semiconductor device according to the eighth embodiment of the present invention.

  FIG. 16B is a cross-sectional view illustrating a process of the method for manufacturing a semiconductor device according to the eighth embodiment of the invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1,50 ... Semiconductor wafer 2,51 ... Electrode 5,29,40,53,70,80,91,110 ... Contact substrate 6,31,42,55,72,82,92,111 ... Via 7,120 ... Multilayer wiring board 9, 25, 49, 59... Through hole 10, 30... Wire 11, 58... Adsorption mechanism 12... Test signal wiring 13 ... Tester 20, 83, 98 ... Semiconductor chip 26, 115 ... Sheet base material 27, 113 ... Hole 28, 112 ... Via part 35 ... Upper and lower wiring 41 ... Deformation suppression part 52 ... High load electrode 95,100 ... Solder bump

Claims (8)

It is made of a breathable insulating material made of either liquid crystalline polymer containing polytetrafluoroethylene or aramid or polyimide, and pores are provided in the insulating material with an aperture ratio of 70% to 80%. , has an upper surface and a lower surface, have a plurality of conductive vias connecting between the upper surface and the lower surface, and a contact substrate which adsorbs device under test through the holes,
Wherein are arranged to protrude such that the conductive vias in the surface of adsorbing device under test surrounds the conductive vias in a region other than the region to be exposed, the thermal expansion coefficient of the device under test of the contact across the substrate A contact substrate for testing a semiconductor device, comprising: a deformation suppressing unit that suppresses thermal expansion of the contact substrate due to a difference from a thermal expansion coefficient.   2. The semiconductor device testing contact substrate according to claim 1, wherein the deformation suppressing portion is made of a material selected from metal, resins, and ceramics.   The contact substrate for testing a semiconductor device according to claim 1, wherein the deformation suppressing portion is a metal selected from copper, nickel, gold, and tin.   The deformation suppressing part is made of epoxy resin, bismaleimide-triazine resin, PEEK resin, butadiene resin resin, polyethylene or polypropylene polyolefin, polybutadiene, polyisoprene, polyvinylethylene polydienes, polymethyl acrylate, polymethyl methacrylate. Acrylic resins, polystyrene derivatives, polyacrylonitrile, polyacrylonitrile derivatives of polymethacrylonitrile, polyoxymethylene polyacetals, polyethylene terephthalate, polybutylene terephthalate, polyesters including aromatic polyesters, polyarylates, aroma of aramid resin Polyamides of polyamide or nylon, polyimides, epoxy resins, aromatic polyethers of poly p-phenylene ether, polyester Reether sulfones, polysulfones, polysulfides, PTFE fluoropolymers, polybenzoxazoles, polybenzothiazoles, polyparaphenylene polyphenylenes, polyparaphenylene vinylene derivatives, polysiloxane derivatives, novolak resins, melamine resins 2. The contact substrate for testing a semiconductor device according to claim 1, wherein the contact substrate is a material selected from any of resins, urethane resins, and polycarbodiimide resins.   The deformation suppressing unit is a ceramic selected from the group consisting of silica, alumina, titania, and potassium titanate, or a material selected from silicon carbide, silicon nitride, and aluminum nitride. 2. A contact substrate for testing a semiconductor device according to 1.   6. The contact substrate for testing a semiconductor device according to claim 1, wherein the conductive via is formed by plating or filling the hole with a metal.   The semiconductor device testing contact substrate according to claim 1, wherein the conductive via is provided with a cavity, or upper and lower surfaces thereof are connected by a coupling body. . The deformation suppressing portion is formed in a wave shape, a grid shape or a chain shape so as to surround a part of the plurality of conductive vias with respect to a surface in contact with the electronic component to be tested, or the The contact substrate for testing a semiconductor device according to claim 1, wherein the contact substrate is formed in a peripheral portion of the contact substrate so as to surround the plurality of conductive vias.

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