JP2007287126A - Multi-microcontroller system and control method - Google Patents

Abstract

A multi-microcontroller system having an autonomous control capability and a control method are provided.
The present invention discloses a multi-microcontroller system having an autonomous control capability, and a control method, in which any micro-controller core logic directly sets the start address of the insertion program. The program address at the time of interruption received by the controlled microcontroller core logic is temporarily stored in the stack memory indicated by the stack pointer of the microcontroller core logic. After the controlled microcontroller core logic completes the execution of the insertion program, the original program is resumed from this interruption point.
[Selection] Figure 3

Description

  The present invention relates to a multi-microcontroller system and a control method, and more particularly to a multi-microcontroller system having an autonomous control capability and a control method.

Microcontrollers / microprocessors (MCU / MPU), also called single-chip microcomputers, are devices that do not require other auxiliary circuits and can perform operations independently. An integrated circuit that issues a control command. Microcontrollers provide approximately the same functionality as provided by a small computer. In recent years, microcontrollers have been applied to various fields such as household appliances, industrial control devices, medical equipment, and transport control devices. Different microcomputer standards can be applied to different fields, and the peripheral devices to be controlled are also different.

Looking back on the development history of microcontrollers, there are three main targets for development: (1) acceleration of data processing speed, (2) reduction of chip size per unit function, and (3) reduction of power consumption. Under these objectives, increasing the number of processing bits, accelerating the clock frequency, improving computing units, memory management, developing cache technology, submitting pipeline processing structures, application of instruction predecoding and preexecution techniques, multimedia Several important developmental processes have emerged, such as the construction of a new instruction set on demand, a new chip assembly process, and a new packaging technology. However, the various developments described above are due to two important technologies, semiconductor process technology and hardware architecture design technology. One is the development of semiconductor technology, the chip is accommodated in more transistors, the distance between elements is reduced, the function is increased, the voltage is lowered, and the circuit reaction speed is accelerated. In terms of hardware architecture design, super-pipeline architecture, internal cache architecture, super-scalar technology, speculative execution, and microcode tracking technology. Pipeline technology is the technology that has contributed most to the improvement of hardware architecture technology. Pipeline technology performs task distribution, divides tasks into multiple parts, and assigns multiple units. Even if the clock frequency of the microcontroller does not increase, the execution speed of the microcontroller is increased by pipeline technology.

A known multi-microcontroller system and a known hyper-thread microcontroller system for performing task distribution functions are shown in FIGS. 1 (a) and 1 (b). A known multi-microcontroller system (FIG. 1a) mainly comprises multi-microcontrollers 10, 11, and 12, and is connected to a common data memory 13 and a common peripheral device 14 by a bus (indicated by white arrows in the figure). Combined with Since each MCU has program memories 101, 111, and 121 to which the core logics 102, 112, and 122 correspond, the MCU can perform independent work. In FIG. 1 (b), the known hyperthreaded microcontroller system mainly comprises multi-microcontroller core units 15 and 16. Each multi-microcontroller core unit 15, 16 includes MCU core logic 152, 162 and a corresponding dedicated instruction buffer (instruction
buffer) 151 and 161, and is connected to the data memory 18 and the program memory 17 by a bus (indicated by white arrows in the figure). Therefore, the microcontroller core units 15 and 16 execute their own programs in parallel, and the instruction buffers 151 and 161 reduce the reading of the program memory 17 by the microcontroller core units 15 and 16, and different microcontroller core units store the program memory. Reading greatly reduces the probability of mutual interference, and the program is executed effectively.

Even in known multi-microcontroller systems or known hyper-threaded microcontroller systems, the program execution modes that respond when facing an interrupt request are homologous. As shown in FIG. 2, since each microcontroller is executed independently, at the time of an interrupt request, the interrupt request task must wait until one microcontroller detects and responds to the interrupt request. For example, a certain microcontroller core logic 20 detects an interrupt request and responds. When the MCU core logic 20 detects an interrupt request, the MCU core logic 20 first places the contents of the program counter 24 in the stack memory 26, and then acquires the start address of an ISR (Interrupt Service Routine), and then the interrupt task. Execute. As can be seen from the above, in two known multi-microcontroller systems, the microcontroller cannot effectively control the other directly. One microcontroller (not shown in FIG. 2) can set a flag or transmit an interrupt request by simply “notifying” another microcontroller (MCU with core logic 20). To notify the change of the program to be executed. Thereafter, the previous MCU waits for the response of the subsequent MCU. In this case, there is no effective mutual control between the microcontrollers, and the execution time is not accurately controlled even for an immediately executed task. In addition, the function of the multi-microcontroller system is not effectively exhibited because the work is inappropriately distributed to some microcontrollers. Therefore, it is difficult for the above-mentioned system operation mode to satisfy complicated electronic product performance requirements.

Accordingly, the present invention provides a multi-microcontroller system having an autonomous control capability and a control method for the above-described problem, and uses the mutual control characteristics between the micro-controller units of the multi-microcontroller system to insert a program. By placing the start address directly in the controlled microcontroller, the time required for interrupt operation is reduced, and each microcontroller unit achieves optimal performance.

  The problem to be solved is to provide a multi-microcontroller system with autonomous control capability, and by executing several programs in parallel by using several microcontroller core logics, processing multiple programs in parallel, and by software, The objective is to effectively control the operation of each microcontroller core logic to fully demonstrate the maximum functionality of each microcontroller core logic in a multi-microcontroller system.

Further, a multi-microcontroller system having an autonomous control capability and a control method are provided, and a program to be executed by software is controlled by a microcontroller core logic, and a microcontroller core logic in which a program disclosure address of a program to be inserted is controlled Another purpose is to shorten the compatibility processing time between microcontrollers by executing the program inserted immediately by the controlled microcontroller core logic.

  In order to achieve the above object, the present invention provides a multi-microcontroller system having an autonomous control capability, and includes a multi-controller unit, a microcontroller enable register, and at least one memory. The multi-controller unit is connected to a plurality of microcontroller (MCU) functional logics, MCU functional logics, and consists of corresponding program counters that provide program addresses to the MCU functional logic. The microcontroller enable register and the multi-microcontroller unit are electrically connected to enable or disable the microcontroller function logic. The memory is electrically connected to the multi-microcontroller unit and provides a program required by the multi-microcontroller unit. Each microcontroller functional logic can change the contents of any of the above program counters.

In addition, the present invention provides a control method for a multi-microcontroller system having autonomous control capability, and the system corresponds to at least one controller MCU function logic, controlled microcontroller function logic, and controlled microcontroller function logic. The control method includes the following steps. The process comprises the steps of disabling the controlled microcontroller functional logic, freezing the program counter, transmitting the contents of the memory into the program counter, and enabling the controlled microcontroller functional logic. .

Furthermore, the present invention provides a control method for a multi-microcontroller system having autonomous control capability, and the system is a program corresponding to at least one MCU function logic, controlled multi-controller function logic, and controlled multi-controller function logic. It consists of a counter, a program memory, a stack memory, and a stack pointer corresponding to the stack memory. The control method includes the following steps. Invalidating the controlled microcontroller functional logic, freezing the program counter, storing the contents of the memory counter in the first position of the stack memory by the first index of the stack pointer, Storing the address of the program memory for a while in the second position in the stack memory by two positions, storing the contents of the second position in the stack memory in the program counter by the second index of the stack pointer; Enabling the controlled microcontroller function logic, causing the controlled microcontroller function logic to execute a task corresponding to the contents in the program memory address described above, disabling the controlled microcontroller function logic, and stacking memory A step of re-save the contents of the first position into the program counter, at the end, a step of executing the program continues were running originally controlled microcontroller functional logic consists.

  A multi-microcontroller system having an autonomous control capability and a control method according to the present invention can be used to directly control the start address of a program to be inserted by utilizing the mutual control characteristics between the micro-controller units of the multi-microcontroller system. Each microcontroller unit achieves optimal performance by placing it inside and reducing the time required for interrupt operation.

Due to the structure of the multi-microcontroller system of the present invention, each microcontroller core logic has an independent processing capability of the program, and each microcontroller core logic receives the designated program start address in the state in which each program is processed. It transmits in the program counter in the microcontroller core logic of the latter and controls the next task of the latter microcontroller core logic (controlled microcontroller core logic). Thereby, the reaction time of the program change of the controlled microcontroller core logic can be shortened.

A first embodiment of the present invention will be described. In the multi-microcontroller system having the autonomous control capability of the present invention, the method steps of how the system works when the microcontroller core logic wants to execute another unspecified microcontroller core logic are shown. As shown in FIG. 3, first, in a multi-microcontroller system having an autonomous control capability, three microcontroller core logics 30, 31, 32, a microcontroller enable register 35, a program memory 33, and a stack memory 34 are included. . Each of the microcontroller core logics 30, 31, and 32 has microcontroller function logics 301, 311, and 321, program counters 302, 312, and 322, and stack pointers 303, 313, and 323, respectively. The microcontroller core logic 30, 31, 32 is connected to the program memory 33 by the program memory bus 334, and the system program area 330 stored in the program memory 33, the first microcontroller core logic program area 331, the second All instructions and programs in the microcontroller core logic program area 332 and the third microcontroller core logic program area 333 are read. The microcontroller core logic 30, 31, 32 is also connected to the stack memory 34 via the stack memory bus 344, and the first, second, and third microcontroller core logic 30, 31, 32 execute the program. Each time, the contents in the respective first, second, and third program counters 302, 312, 322 are changed to the corresponding first microcontroller core logic stack area 341, second microcontroller core logic stack area 342, And stored in the third microcontroller core logic stack area 343.

The control method of the multi-microcontroller system having the autonomous control capability of the present invention will be described in detail below. Referring to FIG. 3 and FIG. 4, FIG. 4 is a flowchart of the control method of the first embodiment of the present invention. is there. First, in step S01, the three microcontroller core logics 30, 31, and 32 execute their own programs. That is, the first microcontroller function logic 301 in the first microcontroller core logic 30 is executing an instruction at the program address specified by the first program counter 302, and the program address in the program memory 33 is It is assumed that c101. The second microcontroller function logic 311 in the second microcontroller core logic 31 is executing an instruction at the program address specified by the second program counter 312 and the program address in the program memory 33 is c201. Suppose there is. The third microcontroller function logic 321 in the third microcontroller core logic 32 is executing the instruction of the program address specified by the third program counter 322, and this instruction is c301 in the program memory 33. Suppose there is. At this time, the system generates or receives an interrupt request and requests the system to execute one program starting from the program address 00f0. The program address of the inserted program is already in the system program area 330, for example. Saved. This interrupt request needs to cancel the program being executed in the second microcontroller core logic 31 (the program in the second microcontroller core logic program area 322), and is changed to the execution of the insertion program whose start address is 00f0. If the second microcontroller function logic 311 of the second microcontroller core logic 31 does not need to return to the originally executed program, the originally executed program is terminated at the current program address (for example, c202), The second program counter 312 freezes under the state of the corresponding address c202. During step S02, the first microcontroller core logic 30 transmits a disable signal for disabling the second microcontroller core logic 31 through the microcontroller enable register 35, and the second microcontroller core logic 31 corresponds at the same time. The second microcontroller function logic 311 becomes invalid, the execution of the currently executed program is stopped, and the program counter 312 is frozen at the program address c202. During step S03, at this time, the index state of the first stack pointer 303 in the first microcontroller core logic 30 is the stack memory address i, and the second microcontroller function logic of the second microcontroller core logic 31 to be controlled. The insertion program executed by 311 has a program start address of 00f0. The first microcontroller functional logic 301 of the first microcontroller core logic 30 stores 00f0 in the stack memory address i in the stack memory 34. During step S04, the first microcontroller functional logic 301 of the first microcontroller core logic 30 stores the contents (ie, 00f0) in the stack memory address i stored in the stack memory 34 in the second microcontroller core logic 31. To the second program counter 312 and the second microcontroller core logic 31 is re-enabled, and then becomes the program execution address. As the transfer method, for example, a pop command, popPC2 or the like is used. During step S05, the first microcontroller core logic 30 outputs an enable signal to the second microcontroller core logic 31 (and the second microcontroller function logic 311) by the microcontroller enable register 35, and the second microcontroller core. The logic 31 starts from the program address (00f0) designated in the second program counter 312 and executes the insertion program. During step S06, the second program counter 312 in the second microcontroller core logic 31 has already been changed to 00f0, so the states of the three microcontroller core logics 30, 31, 32 are respectively: The first microcontroller function logic 301 of the logic 30 executes the program address in the first program counter 302, and this program address corresponds to the first microcontroller core logic program area 331 in the program memory 33: The second microcontroller function logic 311 of the two microcontroller core logic 31 executes the program address in the second program counter 312 and the program address is programmed. Corresponding to the system program area 330 in the memory 33. The third microcontroller function logic 321 of the third microcontroller core logic 32 executes the program address in the third program counter 322, and this program address is stored in the third microcontroller core logic program area 333 in the program memory 33. Corresponding to

In the first embodiment described above, the inside of the multi-microcontroller system of the present invention is described in detail, and the mutual control method is executed between the MCU core logic (30) and the controlled microcontroller core logic (31). In the embodiment, only the process until the controlled microcontroller core logic changes the program address is described. However, after this insertion program is completed, the controlled microcontroller core logic continues to execute other programs, or returns to the interrupted mode and executes the original program. The second embodiment of the present invention is an extension of the first embodiment, and further, when the controlled microcontroller core logic completes the execution of the insertion program, returns to the interruption program, and the original program needs to be continuously executed. It explains how to execute and the mutual control method between MCU core logic and controlled microcontroller core logic.

3 and 5, FIG. 5 is a flowchart of the control method of the second embodiment of the present invention. The structure of the multi-microcontroller system having autonomous control capability is as described above and will not be described in detail here. The control method of the multi-microcontroller system having the autonomous control capability in the second embodiment is as follows. First, in step S11, the three microcontroller core logics 30, 31, and 32 execute their own programs. That is, the first microcontroller function logic 301 in the first microcontroller core logic 30 is executing an instruction at the program address specified by the first program counter 302, and this instruction is in the first micro memory in the program memory 33. It is located in the controller core logic program area 331. The second microcontroller function logic 311 in the second microcontroller core logic 31 is executing an instruction at the program address specified by the second program counter 312, and this instruction is the second microcontroller core in the program memory 33. Located in the logic program area 332. The third microcontroller function logic 321 in the third microcontroller core logic 32 is executing an instruction at the program address specified by the third program counter 322, and this instruction is the third microcontroller core in the program memory 33. Located in the logic program area 333. At this time, the system generates or receives an interrupt request, requests the system to execute one program starting from the program address 00f0, and the program address of the inserted program is already stored in the system program area 330. ing. Thus, it is necessary for the second microcontroller core logic 31 to terminate the program being executed (the program in the second microcontroller core logic program area 332), and the insertion program with a start address of 00f0 is executed. After completion of the insertion program execution, the second microcontroller core logic 31 recovers the original program execution. During step S12, the first microcontroller core logic 30 transmits a disable signal to the second microcontroller core logic 31 (and the second microcontroller function logic 311) by the microcontroller enable register 35, and the current program. Freeze at address (eg c202). During step S13, at this time, in the first microcontroller core logic 30, the index state of the first stack pointer 303 is the stack memory address i, and the first microcontroller function logic 301 of the first microcontroller core logic 30 is The content of the second program counter 312 in the second microcontroller core logic 31 is stored in the stack memory address i, and the method is, for example, using a push instruction, for example, pushPC2. During step S14, the state of the first stack pointer 303 of the first microcontroller core logic 30 is the stack memory address i + 1, and the program start address of the insertion program executed by the controlled second microcontroller core logic 31 is 00f0. Therefore, the first microcontroller functional logic 301 of the first microcontroller 0 core logic 30 stores 00F0 in the stack memory address i + 1 in the stack memory 34. During step S15, the first microcontroller functional logic 301 of the first microcontroller core logic 30 uses the contents in the stack memory address i + 1 stored in the stack memory 34 (ie, 00f0) in the second microcontroller core logic 31. The data is transmitted to the second program counter 312 and the transmission method is, for example, pop command and popPC2. During step S16, the first microcontroller core logic 30 transmits an enable signal to the second microcontroller core logic 31 (and the second microcontroller function logic 311) by the microcontroller enable register 35, and the second microcontroller The second microcontroller function logic 311 of the core logic 31 is caused to execute the system program with the program start address 00f0 indicated by the second program counter 312. Subsequently, during step S17, the second microcontroller core logic 31 waits for the insertion system program having the program start address 00f0 to be completed, and notifies the first microcontroller core logic 30 of the end of execution of this program. During step S18, the first microcontroller core logic 30 outputs a disable signal through the microcontroller enable register 35, temporarily stops the second microcontroller core logic 31, and stops the currently executed program. In step S19, the content (c202) of the address i stored in the stack memory 34 of the first microcontroller function logic 301 of the first microcontroller core logic 30 is stored in the second program counter 312 in the second microcontroller core logic 31. This operation indicates that the second program counter 312 in the second microcontroller core logic 31 has re-designated the address c202 in the program memory 33. During step S20, the first microcontroller core logic 30 outputs an enable signal from the microcontroller enable register 35 to enable the second microcontroller function logic 311 of the second microcontroller core logic 31, and the second microcontroller core After the logic 31 is re-enabled, the program in the second microcomputer core logic program area 322 is continuously executed in the second program counter 312 by the task before interruption of the program address. Finally, during step S21, the second program counter 312 in the second microcontroller core logic 31 has already been directed to the program memory address c202, and thus the state of the three microcontroller core logics 30, 31, 32 Respectively, the first microcontroller functional logic 301 of the first microcontroller core logic 30 executes the program in the first program counter 302, and the program address is the first microcontroller core in the program memory 33. Located in the logic program area 331: the second microcontroller core logic 31 executes the program of the second program counter 312 and this program address is stored in the second program memory 33 Situated in Lee Black controller core logic program area 332. The third microcontroller core logic 32 executes the program of the third program counter 322, and this program address is located in the third microcontroller core logic program area 333 in the program memory 33.

In the above embodiment, the first microcontroller core logic is depicted as MCU core logic, but any microcontroller core logic can be the controller MCU core logic, and the start address of the insertion program is controlled by the controlled microcontroller. Place in the controller core logic program counter.

In addition, in FIG. 3, the microcontroller core logic is composed of a microcontroller function logic, a program counter, and a stack pointer, but these structures are created to make the present invention easier to understand. The operation between each microcontroller function logic, program counter, and stack pointer is a dynamic correspondence, not a fixed correspondence.

Further, in the above-described embodiment, the program address of the insertion program is stored in the system program area (330). However, as will be understood by those skilled in the art, the program address of the insertion program can be any suitable address. Stored in a location, for example, in a general register. The system program area in the embodiment only shows a kind of embodiment.

In the above embodiment, the program address is transmitted to the controlled microcontroller core logic (31 in the embodiment) using the stack memory and the stack pointer (in the embodiment, the stack pointer of the MCU core logic 30). Or output from there. However, many equivalent methods can achieve this goal, as will be appreciated by those skilled in the art. For example, program addresses can be transferred between different memory locations by using general purpose registers, data memory, or arbitrary memory. Similarly, push and pop instructions are not the only applicable instructions, but other instructions such as a move instruction, a call instruction, a return instruction, or a load table. Alternatively, other methods can be applied to achieve the purpose of transmitting the program address.

As can be seen in comparison with the prior art, the present invention directly modifies the contents of the program counter in the controlled microcontroller core logic. Thus, the MCU microcontroller core logic does not need to set a flag and does not need to wait for the response of the controlled microcontroller core logic. As a result, several or even dozens of timing reaction times can be saved, and the multi-microcontroller system and method having the autonomous control capability of the present invention are simple, effective, and fast in reaction speed. Have

  In the present invention, preferred embodiments have been disclosed as described above. However, the present invention is not limited to the present invention, and any person who is familiar with the technology can use various methods within the spirit and scope of the present invention. Variations and moist colors can be added, so the protection scope of the present invention is based on what is specified in the claims.

It is explanatory drawing which showed the hardware structure of the well-known multimicrocontroller system. It is explanatory drawing which showed the hardware structure of the well-known hyperthreaded microcontroller system. It is a figure which shows operation when the interruption request | requirement of a well-known microcontroller system arises. It is a figure which shows the structure of the multimicrocontroller system which has the autonomous control capability of this invention. It is a flowchart of the 1st example of the present invention. It is a flowchart of the 2nd example of the present invention.

Explanation of symbols

10, 11, 12 microcontroller
101, 111, 121 Program memory
102, 112, 122 Microcontroller core logic
13 Data memory
14 Peripheral elements
15, 16 Microcontroller core unit
151, 161 instruction buffer
152, 162 Microcontroller core logic
17 Program memory
18 Data memory
20 Microcontroller core logic
24 program counter
26 Stack memory
30 First microcontroller core logic
31 Second microcontroller core logic
32 Third microcontroller core logic
301 First microcontroller functional logic
311 Second microcontroller functional logic
321 Third Microcontroller Functional Logic
302 First program counter
312 Second program counter
322 Third program counter
303 First stack pointer
313 Second stack pointer
323 Third stack pointer
33 Program memory
330 System program area
331 First Microcontroller Core Logic Program Area
332 Second Microcontroller Core Logic Program Area
333 Third Microcontroller Core Logic Program Area
334 Program memory bus
34 Stack memory
341 1st Microcontroller Core Logic Stack Area
342 Second Microcontroller Core Logic Stack Area
343 Third Microcontroller Core Logic Stack Area
344 Stacked memory bus
35 Microcontroller enable register

Claims (20)

A multi-microcontroller system,
A multi-controller unit comprising a plurality of microcontroller function logics and a plurality of program counters, each program counter being coupled to one microcontroller function logic and providing a program address to the microcontroller function logic;
A microcontroller enable register connected to the multi-microcontroller unit to disable and enable the microcontroller function logic;
At least one memory connected to the multi-microcontroller unit and storing a program required by the multi-microcontroller unit;
A multi-microcontroller system, wherein each of the microcontroller functional logics can change the contents of any of the above-mentioned program counters. 2. Each of the microcontroller functional logics independently executes at least one program and simultaneously executes one instruction to control another microcontroller functional logic. Multi-microcontroller system as described in The command is one of the following several commands:
Enable the other microcontroller function logic described above:
Disable the other microcontroller function logic described above:
Transfer the program address into the other microcontroller function logic and corresponding program counter:
3. The multi-microcontroller system according to claim 2, wherein the contents of the program counter corresponding to the other microcontroller function logic are transferred to at least one memory. The at least one memory is
At least one program memory connected to the multi-microcontroller unit by a program memory bus, having a plurality of program memory addresses, and storing at least one program;
A plurality of stack memory addresses connected to the multi-microcontroller unit by a stack memory bus, and comprising at least one stack memory storing at least one program address of a program executed by the multi-microcontroller unit; and,
The multi-microcontroller unit further includes:
A plurality of stack pointers each connected to the microcontroller functional logic and providing a stack memory address;
The multi-microcontroller system according to claim 1, comprising: The instruction of "Transfer Program Address into Program Counter Corresponding to the Another Microcontroller Functional Logic" is either a push instruction or a move instruction. Multi microcontroller system. The instruction "transfer program address to the program counter corresponding to the other microcontroller function logic" is one of a move instruction, a call instruction, a return instruction, or a load table instruction. The multi-microcontroller system according to claim 3. A push control method applied in a multi-microcontroller system, wherein the multi-microcontroller system corresponds to at least one controller MCU function logic, a controlled microcontroller function logic, and the controlled microcontroller function logic The control method comprises a program counter and a memory.
The controlled microcontroller functional logic issuing a push command;
The system stores the contents of a program counter corresponding to the controlled microcontroller functional logic in the memory location;
A control method comprising: A pop control method applied in a multi-microcontroller system, wherein the multi-microcontroller system corresponds to at least one controller MCU function logic, a controlled microcontroller function logic, and the controlled microcontroller function logic The control method comprises a program counter and a memory.
The microcontroller functional logic issuing a pop command;
The system inserts a program address into the program counter of the controlled controller functional logic;
A control method comprising: A control method applied in a multi-microcontroller system, wherein the multi-microcontroller system includes at least one controller MCU function logic, a controlled microcontroller function logic, a program counter corresponding to the controlled microcontroller function logic, and , Memory, and the control method is:
Disabling the controlled microcontroller functional logic;
Freezing the program counter;
Transmitting the contents of the first location in the memory into the program counter;
Enabling the controlled microcontroller functional logic;
A control method comprising: The control method according to claim 9, wherein the invalidation step and the validity step are achieved by a microcontroller enable register. The control method according to claim 9, further comprising a step of storing the contents of the program counter in a second location of the memory before the transfer step. Further, after enabling the controlled microcontroller function logic, the task corresponding to the contents of the first position in the memory is waited for completion, and the contents of the second position in the memory are stored again in the program counter. The control method according to claim 11, further comprising the step of: The control according to claim 9, wherein the step of “transferring the contents in the first position in the memory into the program counter” is one of a move instruction, a call instruction, and a load table instruction. Method. 12. The control method according to claim 11, wherein the step of “saving the contents in the program counter in the second position of the memory” is a push command or a movement command. 13. The step of “storing the contents of the second location in the memory again in the program counter” is one of a move instruction, a call instruction, a return instruction, and a load table instruction. The control method described in 1. The control method according to claim 9, wherein the first position of the memory is a position in a program memory. The control method according to claim 11, wherein the second position in the memory is a position in a stack memory. The system further includes a stack pointer corresponding to the stack memory, and the step of “saving the contents of the program counter in a second location in the memory” includes:
18. The control method according to claim 17, further comprising the step of storing the contents of the program counter in a location of the stack memory according to the index of the stack pointer. The system further comprises a stack pointer corresponding to the stack memory, and the step of “transferring the contents in the first location in the memory into the program counter” comprises:
Temporarily storing the contents of the first location of the memory in a location of the stack memory by a first index of the stack pointer;
Storing the contents of the location of the stack memory in the program counter by a second index of the stack pointer;
The control method according to claim 16, further comprising: A control method applied to a multi-microcontroller system, wherein the multi-microcontroller system includes at least one MCU function logic, a controlled multi-controller function logic, a program counter corresponding to the controlled multi-controller function logic, and a program memory , A stack memory, and a stack pointer corresponding to the stack memory, and the control method includes:
Disabling the controlled microcontroller functional logic;
Freezing the program counter;
Storing the contents of the memory counter in a first location of the stack memory by a first index of the stack pointer;
Temporarily storing one address of the program memory in a second position in the stack memory by a second position of the stack pointer;
Storing the contents of the second location in the stack memory in the program counter by a second index of the stack pointer;
Enabling the controlled microcontroller functional logic and causing the controlled microcontroller functional logic to perform a task corresponding to the content in the program memory address;
Disabling the controlled microcontroller functional logic;
Restoring the contents of the first location of the stack memory into the program counter;
And a step of causing the controlled microcontroller function logic to continuously execute a program that was originally being executed.