FR2911415A1 - MULTIPLE INDEPENDENT MICROCONTROLLER SYSTEM AND METHOD OF CONTROLLING THE SAME - Google Patents

Abstract

The present invention describes an autonomous multi-microcontroller system and a control method thereof, wherein any MCU central logic (30, 31, 32) of the multiple microcontroller system can directly set the starting address of a program inserted into the program counter (302, 312, 322) of a controlled central MCU logic. The interrupted program address of the controlled MCU central logic (30, 31, 32) is temporarily stored in the stack memory (34) according to the index of the stack pointer (303, 313, 323) of the central logic. of the MCU (30, 31, 32) so that the central MCU logic controlled (30, 31, 32) can resume execution of the interrupted program after it has completed execution of the inserted program.

Description

MULTIPLE SELF-CONTAINED MICROCONTROLLER SYSTEM AND METHOD OF CONTROLLING

  The present invention relates to a multi-microcontroller system and the control method thereof, particularly to a multi-autonomous microcontroller system and to the control method thereof. A microcontroller / microprocessor (MCU / MPU), which is also called a single chip microcomputer, is an integrated circuit that establishes control instructions in a system. It can operate without the help of any other auxiliary circuit. A microcontroller provides functions almost equivalent to those provided by a miniature computer. In recent years, microcontrollers have been widely applied in many fields, such as consumer electronics, industrial controllers, medical equipment, vehicle controllers, and so on. Depending on the domain to which it is applied, a microcontroller may have a different specification and may cooperate with different peripheral devices.

  The history of microcontroller development is a story of continuous improvement of three targets: (1) acceleration of data processing speed, (2) miniaturization of chip size by unit function, and (3) reduction of the size of the chip. power consumption. Many important advances of the microcontrollers have thus been realized, including: an increase in the number of bits processed, a faster clock frequency, an improvement of the arithmetic units, a better management of the memory, a cache technology, architectures of pipeline processing, pre-decoding and prefetching of instructions, new sets of instructions for multimedia, new manufacturing processes and new enclosure technologies. Nevertheless, all the successes mentioned above are attributed to the improvement of two key technologies: semiconductor processing technology and hardware architecture development technology. Advances in semiconductor processing technology increase the number of transistors per chip and reduce the distances between devices, so that the operating voltage can be lowered, the operating speed can be increased and more advanced functions can be insured. Advances in hardware architecture development include: super-pipeline architecture, internal cache architecture, super-scalar technology, predictive-execution technology, and microcode trace technology. Among the above, pipeline technology is the largest contributor to improving hardware architecture debugging technology. Pipeline technology performs a task partition, which divides a task into multiple parts and assigns them to multiple units. Even though the clock rate of a microcontroller can not be increased, the execution speed of a microcontroller can still be increased due to such pipeline technology. A conventional multi-microcontroller system and a conventional Hyper-Flot (Hyperthread) microcontroller system performing a task partitioning function are shown in the block diagrams of Figure 1 (a) and Figure 1 (b). The conventional multi-microcontroller system (FIG. 1 (a)) essentially comprises multiple microcontrollers 10, 11 and 12, which are coupled to a common data memory 13 and to common peripheral devices 14 via buses (illustrated by FIG. the double hollow arrows). Each of the MCUs (microcontroller unit) comprises a central logic 102, 112 and 122 which cooperates respectively with a corresponding program memory 101, 111 and 121. The MCUs operate mutually independently. The conventional Hyperthread microcontroller system (Fig. 1 (b)) essentially comprises multiple microcontroller central units 15 and 16. Each of the microcontroller central units 15 and 16 comprises a central MCU logic (152 and 162) and a buffer. corresponding dedicated instructions (151 and 161).

  The MCU CPUs 15 and 16 are respectively coupled to a data memory 18 and a program memory 17 via buses (represented by the double hollow arrows). By this arrangement of the instruction buffers, the microcontroller units can run in parallel and separately corresponding programs, so that each MCU has less access to the program memory 17. Thus, the probability that the CPUs will Microcontroller interfere with each other during access to program memory 17 is greatly reduced and programs can be run more efficiently. Whether it be multiple conventional microcontrollers for the microcontroller system or for the conventional Hyperthread system, their program execution operation in response to an interrupt request is identical. Referring to Figure 2, it can be seen that since each microcontroller operates independently of any other MCU, when an interrupt occurs, the interrupt task must wait until one MCUs are able to detect and respond to the interruption. It is assumed that an MCU having a central logic of MCU 20 is the MCU responding to the interrupt. When the central logic 20 of MCU detects an interrupt request, the central logic 20 of MCU will first put the contents of its own program counter 24 in a stack memory 26 and then obtain the starting address of an Interrupt Service Routine Routine Interrupt Service Routine to perform the interrupt task. As can be seen from the foregoing, in these two conventional multi-microcontroller systems, microcontrollers can not control each other in a direct and efficient manner. A microcontroller (not shown in FIG. 2) can only inform another microcontroller (such as the MCU having the central logic 20) by activating a flag or sending an interrupt request to the latter. , that the program that it runs should be changed. Then the first MCU must wait for the last MCU to respond. In such a case, the tasks may be inappropriately distributed to the microcontrollers, and the overall performance of the multiple microcontroller system as a whole may be degraded. In addition to the inability to direct and efficient cross-control, the interrupt action also takes time in such a mode of operation. Therefore, it is difficult for such conventional technology to meet the higher and more complex requirements of advanced electronic products. Accordingly, the present invention provides an autonomous multi-microcontroller system and a control method thereof for overcoming the above-mentioned problems, the microcontroller units of a multi-microcontroller system being able to control each other effectively, and starting address of the interrupt (inserted) program that can be directly placed in the controlled microcontroller unit, so that the time required for the interrupt action can be shortened, and each microcontroller unit can thus reach the best performance possible.

  The main objective of the present invention is to provide an autonomous multi-microcontroller system, in which multiple central MCU logic (microcontroller units) are used to run multiple programs in parallel, and the operation of each MCU core logic. is precisely and efficiently controlled via software, so that each central MCU logic of the multiple microcontroller system can achieve the best possible efficiency. Another object of the present invention is to provide a system with multiple independent microcontrollers and a control method thereof, wherein, according to the instruction from a central control MCU logic, the starting address of an inserted program is sent to the program counter of a controlled central MCU logic, so that the centralized MCU logic can instantly execute the inserted program, and thus the required interaction time between the microcontrollers is made minimal. To achieve the above-mentioned objectives, the present invention provides an autonomous multi-microcontroller system, comprising: a multi-microcontroller unit, comprising a plurality of MCU (Microcontroller Unit) functional logic and a corresponding plurality of program counters respectively coupled to said MCU functional logic for providing a program address to said MCU functional logic; a microcontroller activation register, coupled to said multimicrocontroller unit, for enabling or disabling said MCU functional logic; and at least one memory, coupled to said multi-microcontroller unit, for storing a program required by said multi-microcontroller unit; each of said functional logic of MCU being capable of changing the contents of any one of said program counters.

  Each of said MCU functional logic can be arranged to independently run at least one program and simultaneously execute an instruction to control another of said MCU functional logic. Said instruction may be an instruction selected from the group consisting of: activating said other MCU functional logic; disabling said other functional logic of MCU; transferring a program address in a program counter corresponding to said other MCU functional logic; and transferring the contents of a program counter corresponding to said other MCU functional logic to said one or more memories. Said memory or memories may comprise at least one program memory, coupled to said multi-microcontroller unit via a program memory bus, and having a plurality of program memory addresses for storing at least one program ; and at least one stack memory, coupled to said multi-microcontroller unit via a stack memory bus, and having a plurality of stack memory addresses for storing at least one program address of a program executed by said multimicrocontroller unit; and said multi-microcontroller unit further comprises a plurality of stack pointers respectively coupled to said MCU functional logic to provide a stack memory address. Said instruction for transferring the contents of a program counter corresponding to said other MCU functional logic to said one or more memories may be an instruction selected from the group consisting of a Push instruction and a Move instruction. ). Said instruction for transferring a program address in a program counter corresponding to said other MCU functional logic may be an instruction selected from the group consisting of a Pop instruction, a Move instruction, a Cali_ (Call) statement, a Return statement, and a Load Table operation. The present invention also provides a method of push command control for a multiple microcontroller system having at least one control MCU (Control Microcontroller Unit) functional unit, a controlled MCU functional logic, a program counter corresponding to said controlled MCU and a memory location, the method comprising the steps of: said control MCU functional logic issues a push instruction; and said system stores the contents of said program counter corresponding to said controlled MCU functional logic in a memory location.

  The present invention further relates to a Pop instruction control method for a multi-microcontroller system having at least one control MCU (Microcontroller Unit) functional logic, a controlled MCU functional logic, a program counter corresponding to said controlled MCU and a memory location, the method comprising the steps of: said control MCU functional logic issues a Pop instruction; and said system interposes a program address in said program counter corresponding to said controlled MCU functional logic. In addition, the present invention also provides a control method for an autonomous multi-microcontroller system, the system having at least one control MCU (Microcontroller Unit) functional logic, a controlled MCU functional logic, a corresponding program counter said controlled MCU and a memory, the method comprising the steps of: deactivating said controlled MCU functional logic; freeze said program counter; transferring the content to a location of said memory in said program counter; and activate said controlled MCU functional logic. Said steps of activating and deactivating said controlled MCU functional logic can be performed by means of a microcontroller activation register. The method may further include the step of, prior to transferring the contents to a first location of said memory in said program counter, storing the contents of said program counter in a second location of said memory. The method may further include the step of, after activation of said controlled MCU functional, whereby said MCU functional logic terminates the task corresponding to the content in said first location of said memory, restoring the content in said second memory location. location of said memory in said program counter. Said step of transferring the content in a first location of said memory into said program counter may be an instruction selected from the group consisting of a Pop instruction, a Move instruction, a Call instruction, and a Load Table operation.

  Said step of storing the contents of said program counter in a second location of said memory may be an instruction selected from the group consisting of a push instruction and a move instruction.

  Said step of restoring the content in said second location of said memory in said program counter may be an instruction selected from the group consisting of a Pop instruction, a Move instruction, a Call statement, a Return statement, and a Load Table operation. . Said first location of said memory may be a location in a program memory.

  Said second location of said memory may be a location in a stack memory. The system may further include a stack pointer corresponding to said stack memory, and wherein said step of storing the contents of said program counter in a second location of said memory may include the step of storing the contents of said counter program in a location of said stack memory according to the index of said stack pointer. The system may further include a stack memory and a stack pointer corresponding to said stack memory, and wherein said step of transferring the contents to a first location of said memory in said program counter may include the step of temporarily storing the contents in a first location of said memory in a location of said stack memory according to a first index of said stack pointer; and storing the contents in said location of said stack memory in said program counter according to a second index of said stack pointer. In addition, the present invention also provides a control method for an autonomous multi-microcontroller system, the system having at least one control MCU (Microcontroller Unit) functional logic, a controlled MCU functional logic, a corresponding program counter said controlled MCU, a program memory, a stack memory, and a stack pointer corresponding to said stack memory, the method comprising the steps of: disabling said controlled MCU functional logic; freeze said program counter; storing the contents of said program counter in a first location of said stack memory according to a first index of said stack pointer; temporarily storing an address of said program memory in a second location of said stack memory according to a second index of said stack pointer; storing the contents in said second location of said stack memory in said program counter according to said second index of said stack pointer; enabling said controlled MCU functional logic, whereby said MCU functional logic terminates the task corresponding to the content in said address of said program memory; disabling said controlled MCU functional logic; restoring the contents in said second location of said stack memory in said program counter; and enabling said controlled MCU functional logic, whereby said controlled MCU functional logic resumes its original task. For a better understanding of the purposes, technical contents, features and effectiveness of the present invention, the present invention will be described below in detail by illustrative embodiments, with reference to the accompanying drawings.

On the drawings:

  Figure 1 (a) is a block diagram schematically showing the architecture of the conventional multi-microcontroller system; Figure 1 (b) is a block diagram schematically showing the architecture of the conventional Hyperthread microcontroller system;

  Figure 2 is a block diagram schematically showing the architecture of the conventional microcontroller system for operation when an interrupt request occurs;

  Figure 3 is a block diagram schematically showing the architecture of the multi-autonomous microcontroller system according to this invention;

  Figure 4 is a flowchart according to a first embodiment of the present invention;

  Figure 5 is a flowchart according to a second embodiment of the present invention.

  The present invention is based on the architecture of a multiple microcontroller system in which each central logic of the MCU (Microcontroller Unit) can independently execute its program. According to the present invention, during the execution of its respective program, each central logic of MCU can enter the starting address of a program assigned to the program counter of another central logic of MCU to determine the next task for this central logic of MCU (central logic of MCU 20 ordered). In this way, the time required to change programs of the central logic of MCU is made minimal. As an example, a first embodiment of the present invention will be described to explain how the system and method operate when an MCU core logic of the standalone multiple microcontroller system aims to control an unspecified MCU core logic (c that is, any other central logic) of the same system. Referring to Figure 3, it can be seen that the multiple autonomous microcontroller system of the present invention comprises: three central logic of MCUs 30, 31 and 32; a microcontroller activation register 35; a program memory 33; and a stack memory 34. The central logic of MCU 30, 31 and 32 respectively comprise functional logic 301, 311 and 321; program counters 302, 312 and 322; and stack pointers 303, 313 and 323.

  The central logic of MCU 30, 31 and 32 are related to program memory 33 via a program memory bus 334; in this way, the central logic of MCU 30, 31 and 32 can access program memory 33 to retrieve programs and instructions stored in system program block 330 and in the first, second and third program blocks 331 , 332 and 333 of MCU Central Logic. The central logic of MCUs 30, 31 and 32 are also related to the stack memory 34 via a stack memory bus 344; in this way, when the central logic of MCU 30, 31, and 32 execute programs, the contents of the first, second, and third program counters 302, 312, and 322 may be temporarily stored separately in the first, second, and third stack blocks 341, 342 and 343 of corresponding MCU central logic. The control method of the multi-autonomous microcontroller system of the present invention will be described in detail below. Referring to Figure 3 and Figure 4, Figure 4 is a flowchart of the control method according to the first embodiment of the present invention. First, in Step S01, the three central logic of MCU 30, 31 and 32 respectively execute their own programs. To be more illustrative, it is assumed that the functional logic 301 of the first MCU central logic 30 is executing the instruction in the program address pointed by the first program counter 302, and the program address is c101 of the program memory 33; the functional logic 311 of the second central logic of MCU 31 executes the instruction in the program address pointed by the second program counter 312, and the program address is c201 of the program memory 33; and the functional logic 321 of the third MCU central logic 32 executes the instruction in the program address pointed by the third program counter 322, and the program address is c301 of the program memory 33. interrupt occurs, which requires the system to run a program starting at the 00fO program address. The program addresses of this inserted program have been stored, for example, in the system program block 330. The interrupt requires the second central logic of MCU 31 to stop its current program of the second program block 332 of central logic of MCU, and execute the inserted system program with starting address 00fO. Assuming that the functional logic 311 of the second central logic of MCU 31 is not necessary to resume execution of its initial program, the initial program will be stopped at its current program address (for example c202), and the second counter program 312 will be correspondingly frozen at address c202. In Step S02, the first central logic of MCU 30 cooperates with the microcontroller activation register 35 to send a deactivation signal to the second central logic of MCU 31 (and thus to its functional logic 311), stopping the executing the program in progress and freezing the program counter 312 to the program address c202. In Step S03, as the index of the first stack pointer 303 of the first central logic unit 30 of MCU is at address i of the stack memory, and that the starting address of the program inserted, which must be executed by the functional logic 311 of the second centralized MCU logic 31 is 00f0, the functional logic 301 of the first MCU central logic 30 stores 00f0 in the address i of the stack memory 34. At step SO4 , the functional logic 301 of the first central logic of MCU 30 transfers (for example, by a Pop instruction such as pop PC2) the contents of the stack memory address i of the stack memory 34 (ie say 00fO) to the second program counter 312 of the second MCU 31; thus, when the second central logic of MCU 31 is activated later, it will execute the program from the address 00f0. In Step S05, the first central logic of MCU 30 cooperates with the microcontroller activation register 35 to send an activation signal to the second central logic of MCU 31 (and thus to its functional logic 311), such that so that the functional logic 311 of the second central logic of MCU 31 can begin to execute the inserted program with the start program address 00f0 pointed by the second program counter 312. In Step S06, since the content the second program counter 312 of the second MCU 31 has been changed to 00f0, the state of the three central logic of MCU 30, 31 and 32 is as follows: the functional logic 301 of the first central logic of MCU 30 always executes the program in the program address pointed by the first program counter 302, and the program address is in the first MCU central logic program block 331 of the program memory 33; the functional logic 311 of the second central logic 31 of the MCU executes the program in the program address pointed by the second program counter 312, but the program address is in the system program block 330 of the program memory 33; and the functional logic 321 of the third MCU central logic 32 always executes the program in the program address pointed by the third program counter 322, and the program address is in the third MCU central logic program block 333 of the program memory 33.

  The first embodiment mentioned above explained in detail the reciprocal control method for the control MCU central logic and the controlled MCU central logic 31. In this first embodiment, after the centralized MCU logic completes the execution of the inserted program, the centralized MCU logic may begin executing a new program or resume execution of the interrupted program. The second embodiment of the present invention further describes how the system operates when the centralized MCU logic needs to resume execution of the interrupted program after it has completed execution of the inserted program. Referring to Figure 3 and Figure 5, Figure 5 is a flowchart of the control method according to the second embodiment of the present invention.

  The architecture of the multi-autonomous microcontroller system of the present invention has been described above and is not repeated here. The control method of the multiple microcontroller system according to the second embodiment of the present invention will now be described in detail below. Firstly, in Step S11, the three central logic units of MCU 30, 31 and 32 respectively execute their own programs, i.e., the functional logic 301 of the first central logic of MCU 30 executes the program. instruction at the program address pointed by the first program counter 302, and the instruction is at the first program block 331 of the MCU central logic of the program memory 33; the functional logic 311 of the second MCU central logic 31 executes the instruction at the program address pointed to by the second program counter 312, and the instruction is at the second MCU central logic program block 332 of the program memory 33; and the functional logic 321 of the third MCU central logic 32 executes the instruction in the program address pointed by the third program counter 322, and the instruction is in the third MCU central logic program block 333. program memory 33. Next, an interrupt occurs, which requires the system to execute a program starting from the program address 00f0 which is now stored in the system program block 330. This requires that the second logic MCU central station 31 stops its current program from the second MCU central logic program block 332, and executes the inserted system program with start address 00f0; furthermore, the second central logic of MCU 31 will have to resume execution of its initial program after completion of the inserted system program. In Step S12, the first central logic of MCU 30 cooperates with the microcontroller activation register 35 to send a deactivation signal to the second central logic of MCU 31 (and thus to its functional logic 311), stopping the executing the current program and freezing the program counter 312 to the current program address (for example c202). In Step S13, as the index of the first stack pointer 303 of the first central logic of MCU 30 is at the stack memory address i, the functional logic 301 of the first central logic of MCU 30 stores (by for example, by a push instruction such as Push PC2) the contents of the second program counter 312 of the second central logic MCU 311 in the stack memory address i. In Step S14, as the index of the first stack pointer 303 of the first central logic of MCU 30 is now at the address i + 1 of stack memory, and that the starting address of the program inserted, which must be executed by the second centralized MCU logic 31, is 00f0, the functional logic 301 of the first central logic of MCU 30 stores 00fO in the i + 1 address of the stack memory 34 of the stack memory. Step S15, the functional logic 301 of the first central logic of MCU 30 transfers (for example, by a Pop instruction such as Pop PC2) the contents of the i + 1 address of the stack memory of the stack memory 34 ( i.e. 00fO) to the second program counter 312 of the second central logic of MCU 31. In Step S16, the first central logic of MCU 30 cooperates with the microcontroller activation register 35 to send a activation signal to the central logic second MCU 31 (and thus its logic functi onnel 311), so that the functional logic 311 of the second central logic of MCU 31 can begin to execute the inserted system program with the start address 00f0 pointed by the second program counter 312. At step S17 after completing the execution of the program inserted with the start address 00f0, the second central logic of MCU 31 informs the first central logic of MCU 30 that execution of the inserted program has been completed. In Step S18, in cooperation with the microcontroller activation register 35, the first central logic of MCU 30 sends a deactivation signal for the second central logic of MCU 31 to pause and stop its execution of the current program. . In Step S19, according to the index of the first stack pointer 303 of the first central logic of MCU 30, the functional logic 301 of the first central logic of MCU 30 restores (for example, by a Pop instruction such as Pop PC2 ) the content (i.e., c202) of the stack memory address i of the stack memory 34 to the second program counter 312 of the second central logic of MCU 31, and this means that the second program Counter 312 of the second central logic of MCU 31 is now again pointing to the program memory address c202 of the program memory 33. In Step S20, the first central logic of MCU 30 cooperates with the program register. activation of microcontroller 35 for sending an activation signal to the second central logic of MCU 31, activating the functional logic 311 of the second central logic of MCU 31 to resume the interrupted program stored in the second central logic program block 332 ofMCU according to the program address pointed by the second program counter 312. Finally, in Step S21, as the second program counter 312 of the second central logic of MCU 31 pointed back to the memory address of program c202 of program memory 33, the state of the three central logic of MCU 30, 31 and 32 is as follows: the functional logic 301 of the first central logic of MCU 30 always executes the program in the program address pointed by the first program counter 302, and the program address is at the first MCU central logic program block 331 of the program memory 33; the functional logic 311 of the second central logic of MCU 31 has resumed the execution of its initial program, that is to say the program at the program address pointed by the second program counter 312, and the address program is at the second MCU central logic program block 332 of the program memory 33; and the functional logic 321 of the third MCU central logic 32 always executes the program in the program address pointed by the third program counter 322, and the program address is at the third MCU central logic program block 333 of program memory 33. It should be noted that in the previous embodiments, the first central logic of MCU is described as the central control MCU logic; however, any of the central MCU logic may act as a control MCU central logic to set the start address of a program inserted into the program counter of a controlled MCU central logic. And, although it is shown in Figure 3 that an MCU functional logic, a program counter, and a stack pointer together constitute a core MCU logic, this is only for a better understanding of the architecture of the MCU. present invention. In fact, each of the functional logic of the MCU can have a dynamic match with one of the program counters and one of the stack pointers. Moreover, in the previous embodiments, the program addresses of the inserted program are stored in the system program block 330. However, as one skilled in the art can readily understand, the program addresses of the inserted program may be stored in any convenient location, such as in a general registry. The system program block 330 described here is only an example. In addition, in the previous embodiments, the program addresses are transferred from and to the centralized MCU logic (the second central logic of MCU 31 in the embodiments) by means of a stack memory, together with the use of the stack pointer of the central control MCU logic (the first central logic of MCU 30). However, those skilled in the art can easily think of many equivalent approaches to achieve the same goal. For example, the program addresses may be transferred from and to any other memory location, such as a general register, a data memory, or any other memory. Similarly, using a push instruction or a pop instruction is not the only way to transfer program addresses between memory locations; there are many equivalent ways to do this, such as using a Move statement, a Call statement, a Return statement, Load Table operation, and so on. Compared with conventional technology, the present invention directly changes the content of the program counter of the controlled MCU, and therefore it is not necessary for the control MCU to activate a flag and wait until the MCU ordered answers; the loss of several or even several tens of clock cycles of time can thus be saved. Therefore, what the present invention describes is a simple, efficient and fast response autonomous multiple microcontroller system and a control method thereof.

  The embodiments described above are by way of illustration only, so that those skilled in the art understand the present invention. The embodiments are in no way intended to limit the scope of the present invention. Any modification and variation within the spirit of the present invention should be within the scope of the present invention.

Claims (8)

  1 - Multi-autonomous microcontroller system characterized in that it comprises: a multi-microcontroller unit, comprising a plurality of MCU (Microcontroller Unit) functional logic (301, 311, 321) and a corresponding plurality of counter meters; program (302, 312, 322) respectively coupled to said MCU functional logic (301, 311, 321) for providing a program address to said MCU functional logic (301, 311, 321); a microcontroller activation register (35), coupled to said multi-microcontroller unit, for activating or deactivating said MCU functional logic (301, 311, 321); and - at least one memory, coupled to said multi-microcontroller unit, for storing a program required by said multi-microcontroller unit; each of said MCU functional logic (301, 311, 321) being capable of changing the contents of any one of said program counters (302, 312, 322).   2 - System with multiple autonomous microcontrollers according to claim 1, characterized in that each of said functional logic MCU (301, 311, 321) is arranged to be able to independently run at least one program and simultaneously execute an instruction to control another of said functional logic of MCU (301, 311, 321).   3 - autonomous multi-microcontroller system according to claim 2, characterized in that said instruction is an instruction selected from the group consisting of the operations of: -activate said other MCU functional logic (301, 311, 321); disabling said other MCU functional logic (301, 311, 321); transferring a program address in a program counter (302, 312, 322) corresponding to said other MCU functional logic (301, 311, 321); and - transferring the contents of a program counter (302, 312, 322) corresponding to said other MCU functional logic (301, 311, 321) to said one or more memories.   4 - System with multiple autonomous microcontrollers according to claim 1, characterized in that said one or more memories comprise: - at least one program memory (33), coupled to said multi-microcontroller unit via a bus program memory (334), and having a plurality of program memory addresses for storing at least one program; and - at least one stack memory (34), coupled to said multi-microcontroller unit via a stack memory bus (344), and having a plurality of stack memory addresses for storing at least a program address of a program executed by said multi-microcontroller unit; and said multi-microcontroller unit further comprising: - a plurality of stack pointers (303, 313, 323) respectively coupled to said MCU functional logic (301, 311, 321) for providing a stack memory address.   5 - autonomous multi-microcontroller system according to claim 3, characterized in that said instruction for transferring the contents of a program counter (302, 312, 322) corresponding to said other functional logic of the MCU (301, 311, 321) to said one or more memories is an instruction selected from the group consisting of: a Push instruction (Put in the Stack) and a Move instruction (Move). 35   6 - System with multiple independent microcontrollers according to claim 3, characterized in that said instruction to transfer a program address in a program counter (302, 312, 322) corresponding to said other functional logic MCU (301, 311 , 321) is an instruction selected from the group consisting of: a Pop instruction (Pile Extraction), a Move instruction, a Cali_ (Call) instruction, a Return statement, and a Load Table operation. Loading Table).   A method of push command control for a multi-microcontroller system according to any one of claims 1 to 6, having at least one operating unit of MCU (Microcontroller Unit) control (301, 311, 321), a controlled MCU functional logic (301, 311, 321), a program counter (302, 312, 322) corresponding to said controlled MCU and a memory location, characterized in that it comprises the following steps: said functional logic MCU command issues a push instruction; and said system stores the contents of said program counter (302, 312, 322) corresponding to said controlled MCU functional logic in a memory location. A pop instruction control method for a multi-microcontroller system according to any one of claims 1 to 6, having at least one control MCU (Control Microcontroller Unit) functional logic (301, 311, 321), logic controlled MCU functional unit (301, 311, 321), a program counter (302, 312, 322) corresponding to said controlled MCU and a memory location, characterized in that it comprises the following steps. said control MCU functional logic issues a Pop instruction; and said system interposes a program address in said program counter (302, 312, 322) corresponding to said controlled MCU functional logic. 9 - Control method for a multiple microcontroller system according to any one of claims 1 to 6, having at least one control MCU (Microcontroller Unit) functional logic, a controlled MCU functional logic, a program counter (302, 312, 322) corresponding to said controlled MCU and a memory, characterized in that it comprises the following steps: - deactivating said controlled MCU functional logic; freezing said program counter (302, 312, 322); -transferring the contents to a first location of said memory in said program counter (302, 312, 322); and - activate said controlled MCU functional logic. 10 - Control method according to claim 9, characterized in that said steps of activating and deactivating said controlled MCU functional logic are performed by means of a microcontroller activation register (35). 11 - Control method according to claim 9, characterized in that it further comprises the step of: - before transferring the contents to a first location of said memory in said program counter (302, 312, 322), storing the contents of said program counter in a second location of said memory. 12 - control method according to claim 11, characterized in that it further comprises the step of: - after activation of said controlled MCU functional logic, whereby said command MCU functional logic completes the task corresponding to the contents in said first location of said memory, restoring the contents in said second location of said memory in said program counter (302, 312, 322). 13 - control method according to claim 9, characterized in that said step of transferring the content in a first location of said memory in said program counter (302, 312, 322) is an instruction selected from the group consisting of : a Pop instruction, a Move statement, a Call statement, and a Load Table operation. 14 - control method according to claim 11, characterized in that said step of storing the contents of said program counter (302, 312, 322) in a second location of said memory is an instruction selected from the group consisting of: a push statement and a move statement. Control method according to claim 12, characterized in that said step of restoring the content in said second location of said memory in said program counter (302, 312, 322) is an instruction selected from the group consisting of : a Pop instruction, a Move statement, a Call statement, a Return statement, and a Load Table operation. 16 - Control method according to claim 9, characterized in that said first location of said memory is a location in a program memory (33). 17 - Control method according to claim 11, characterized in that said second location of said memory is a location in a stack memory (34). 18. The control method as claimed in claim 17, characterized in that said system further comprises a stack pointer (303, 313, 323) corresponding to said stack memory (34), and wherein said step of storing the content of said program counter (302, 312, 322) in a second location of said memory (34) comprises the step of: - storing the contents of said program counter (302, 312, 322) in a location of said stack memory (34) according to the index of said stack pointer (303, 313, 323). 19 - control method according to claim 16, characterized in that said system further comprises a stack memory (34) and a stack pointer (303, 313, 323) corresponding to said stack memory (34), and wherein said step of transferring the contents to a first location of said memory in said program counter (302, 312, 322) comprises the step of: - temporarily storing the contents in a first location of said memory in a location of said stack memory (34) according to a first index of said stack pointer (303, 313, 323); and storing the contents in said location of said stack memory (34) in said program counter (302, 312, 322) according to a second index of said stack pointer (303, 313, 323). Control method for a multi-microcontroller system according to any of claims 1 to 6, having at least one control MCU (Microcontroller Unit) functional logic, a controlled MCU functional logic, a program counter ( 302, 312, 322) corresponding to said controlled MCU, a program memory (33), a stack memory (34) and a stack pointer (303, 313, 323) corresponding to said stack memory (34), characterized in that it comprises the steps of: - disabling said controlled MCU functional logic - freezing said program counter (302, 312, 322); Storing the contents of said program counter (302, 312, 322) in a first location of said staple memory (34) according to a first index of said stack pointer (303, 313, 323); temporarily storing an address of said program memory (33) in a second location of said stack memory (34) according to a second index of said stack pointer (303, 313, 323); storing the contents in said second location of said stack memory (34) in said program counter (302, 312, 322) according to said second index of said stack pointer (303, 313, 323); enabling said controlled MCU functional logic, whereby said MCU functional logic terminates the task corresponding to the content in said address of said program memory (33); - disabling said controlled MCU functional logic - restoring the contents in said second location of said stack memory (34) in said program counter (302, 312, 322); and - activating said controlled MCU functional logic, whereby said controlled MCU functional logic resumes its original task.