JP2007281289A - Electronic component and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of an electronic component which suppresses the generation of a notch in forming a through-hole. <P>SOLUTION: This manufacturing method of the electronic component is sequentially provided with at least a step of forming a conductive notch preventing layer on one part of one surface of a semiconductor substrate; second process of forming a first insulating resin layer, so as to cover the semiconductor substrate and the notch preventing layer; third step of forming an electrode layer on a position corresponding to the notch preventing layer on the first insulating resin layer; fourth step of forming a through-hole formed so that the electrode layer is exposed from the other main surface side of the semiconductor substrate, and formed to be left so that the one part of the notch preventing layer formes one part on an internal peripheral surface and to surround the through hole; fifth step of forming a second insulating resin layer on the internal wall surface of the through hole; and sixth step of forming a conductor in the through-hole so as to cover the second insulating resin layer, and electrically connecting the conductor to the electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic component having a through electrode and a method for manufacturing the same. More specifically, the present invention relates to an electronic component that suppresses generation of a notch during formation of a through hole and a manufacturing method thereof.

  Recently, a wafer level package using a through electrode for connection to an element has been proposed instead of wire bonding that has been used for a package of an optical element such as an image sensor. In order to form a through electrode on a Si substrate on which a device such as an image element has been formed, holes are formed in the Si substrate up to the electrode pad on the device formation surface. As a general method for forming holes in the Si substrate, dry etching is performed.

As shown in FIG. 5, when the substrate is Si, the insulating layer is SiO _2, and Si etching is performed using a gas centered on SF ₆ or the like, the etching rate of the insulating layer is the etching rate of the substrate. Since it is much slower than that, Si etching stops. (Hereinafter, stopping the etching is called etching stop. Further, the insulating layer at this time is called the etching stop layer.)

  However, when etching is stopped at the insulating layer, when Si etching reaches the stop layer, side etching occurs at the tip of the hole, and there is a problem that the diameter is wider than the original shape (this side etching is The expanded part is hereinafter referred to as a notch). Since the insulating layer and the wiring layer cannot be formed well in the notch portion, problems such as poor insulation of the through electrode and poor contact occur.

As a prior art which does not make such a notch, there is Patent Document 1. In this method, a charge is prevented from accumulating in the etching stop layer during etching by providing a conductive layer and an electrode under the conductive layer in the etching stop layer.
In addition, it is basically known that notch generation can be suppressed only by providing a conductive layer in the etching stop layer, even if the electrode provided in the lower portion is not in contact with the conductive layer on the etching stop side.

  As another notch countermeasure method, there is one having a function of suppressing notch generation on the side of an etching apparatus used when etching using an insulating layer as an etching stop. In principle, a low-frequency power source is provided on the side opposite to the electrode on which the sample substrate is placed, and the charge accumulated in the insulating layer is released to the opening side of the hole to suppress the generation of notches.

  As described above, there are two methods for suppressing the generation of notches: a charge suppression layer is provided on the sample side, and a function for suppressing notches is provided on the device side.

  In the method described in Patent Document 1, it is considered that the use of a conductive layer as an etching stop layer is very good for generating a notch. However, in a case where a through electrode is formed at a wafer level on a device-formed substrate. Since the conductive layer side is a surface on which a device or the like is formed, it is impossible to peel off the conductive layer on this surface after forming the hole and perform a process such as forming an insulating layer.

Basically, the surface on the device forming side is formed with a cover or the like for protecting the device, so that the processes that can be performed are limited. Therefore, it is impossible to form a conductive layer on this side and form holes, then peel off the conductive layer, and re-form the insulating layer.
JP 2004-152967 A

  The present invention has been devised in view of such conventional circumstances, and has as its first object to provide an electronic component that has no insulation failure or contact failure and has improved the reliability of the through electrode. To do. The second object of the present invention is to provide a method of manufacturing an electronic component that suppresses the generation of notches when forming a through hole.

An electronic component according to claim 1 of the present invention is provided so as to cover a conductive notch prevention layer provided on a part of one main surface of a semiconductor substrate, and the semiconductor substrate and the notch prevention layer. The first insulating resin layer, the electrode layer on the first insulating resin layer and provided at a position corresponding to the notch prevention layer, and the electrode layer exposed from the other main surface side of the semiconductor substrate And a part of the notch prevention layer constitutes a part of the inner peripheral surface, the through hole left to circulate, and the second insulating resin layer provided on the inner wall surface of the through hole And a conductor provided in the through hole so as to cover the second insulating resin layer and electrically connected to the electrode.
The telegraph component according to claim 2 of the present invention is characterized in that, in claim 1, the notch prevention layer is made of a metal or a semiconductor material.
The electronic component according to claim 3 of the present invention is the electronic component according to claim 2, wherein the notch prevention layer is any one selected from Al, Ti, TiN, Cr, Al-Si, Al-Si-Cu, and TiW. It consists of multiple species.
According to a fourth aspect of the present invention, in the electronic component according to the first aspect, the functional element is formed on the semiconductor substrate, and the functional element and the electrode layer are electrically connected. Features.
According to a fifth aspect of the present invention, there is provided a method for manufacturing an electronic component comprising: a first step of forming a conductive notch prevention layer on a part of one main surface of a semiconductor substrate; and the semiconductor substrate and the notch prevention layer. A second step of forming a first insulating resin layer so as to cover; a third step of forming an electrode layer on the first insulating resin layer at a position corresponding to the notch prevention layer; and A fourth step in which the electrode layer is exposed from the other main surface side, and a part of the notch prevention layer constitutes a part of the inner peripheral surface to form a through hole left to circulate; A fifth step of forming a second insulating resin layer on the inner wall surface of the through hole; and a conductor is formed so as to cover the second insulating resin layer in the through hole, and the conductor is electrically connected to the electrode. And a sixth step of connecting, at least in order.

  In the present invention, a conductive layer (notch prevention layer) having abundant free electrons is provided on or on the same surface of the insulating layer as an etching stop layer when forming a hole by etching. By electrically neutralizing the charge of the ionic species having the following charge and preventing the charge from accumulating, it is possible to provide a method of manufacturing an electronic component that suppresses the generation of notches during hole formation.

  Further, according to the present invention, it is possible to provide an electronic component in which the generation of notches is suppressed, there is no insulation failure or contact failure, and the reliability of the through electrode is improved.

  Hereinafter, an embodiment of an electronic component according to the present invention will be described with reference to the drawings.

FIG. 1 is a cross-sectional view showing an example of an electronic component of the present invention.
The electronic component 1 includes a semiconductor substrate 2, a first insulating layer 3 provided on one main surface of the semiconductor substrate 2, and a conductive notch prevention layer 4 provided on a part of the first insulating layer 3. And a second insulating layer 5 (first insulating resin layer) provided so as to cover the first insulating layer 3 and the notch prevention layer 4, and on the second insulating layer 5 and corresponding to the notch prevention layer 4. The electrode layer 6 provided at the position, the protective cover 7 attached over the entire surface of the second insulating layer 5 so as to cover the electrode layer 6, and the third provided on the other main surface of the semiconductor substrate 2. An insulating layer 8; a through hole 9 provided so that the electrode layer 6 is exposed from the other main surface side of the semiconductor substrate 2; and a fourth insulating layer 10 (second insulation) provided on the inner wall surface of the through hole 9. Resin layer) and a conductive layer provided in the through hole 9 so as to cover the fourth insulating layer 10 and electrically connected to the electrode layer 6. It includes a body 11, a.

  A through hole 9 is formed from one surface of the semiconductor substrate 2 to the other surface, and a conductor 11 is formed in the through hole 9 to form a through electrode. In the through hole 9, a part of the notch prevention layer 4 constitutes a part of the inner peripheral surface and is left so as to go around.

  Since the electronic component 1 of the present invention is manufactured by a method as described later, generation of a notch is suppressed when the through hole 9 is formed, so the fourth insulating layer 10 is formed on the inner wall surface of the through hole 9. In this case, the insulating performance of the through electrode is improved. Moreover, since it becomes advantageous also when forming the conductor 11 in the through-hole 9, the high resistance defect by a disconnection defect, an insulation defect, etc. is improved. As a result, the through electrode is excellent in reliability.

  And the manufacturing method of the electronic component 1 of this invention is the 1st process of forming the electroconductive notch prevention layer 4 in a part on one main surface of a semiconductor substrate, the said semiconductor substrate 2 and the said notch prevention layer 4 A second step of forming a second insulating layer 5 (first insulating resin layer) so as to cover the electrode layer 6 is formed on the second insulating layer 5 at a position corresponding to the notch prevention layer 4. In the third step, the electrode layer 6 is exposed from the other main surface side of the semiconductor substrate 2, and a part of the notch prevention layer 4 constitutes a part of the inner peripheral surface and is left so as to go around. A fourth step of forming the through hole 9, a fifth step of forming a third insulating layer 8 (second insulating resin layer) on the inner wall surface of the through hole 9, and the third insulation in the through hole 9. Forming a conductor 11 so as to cover the layer 8 and electrically connecting the conductor 11 to the electrode; Characterized in that it comprises the Kutomo order.

  In the present invention, a conductive layer (notch) having abundant free electrons on the upper surface or the same surface of the insulating layer (second insulating layer 5) to be an etching stop layer when the through hole 9 is formed by etching. A prevention layer 4) is provided. Thereby, the charge of the ion species having a positive charge can be electrically neutralized so that the charge is not accumulated. As a result, side etching during etching can be suppressed, and generation of a notch on the bottom side of the through hole 9 can be suppressed.

The manufacturing method of the electronic component 1 of this invention is demonstrated using FIGS.
First, as shown in FIG. 2A, a semiconductor substrate 2 is prepared, and a first insulating layer 3 is formed on one main surface (lower surface) thereof.
The semiconductor substrate 2 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip obtained by cutting (dicing) the semiconductor wafer into chip dimensions. When the semiconductor substrate 2 is a semiconductor chip, first, a plurality of semiconductor elements, ICs, functional elements, etc. are formed on a semiconductor wafer and then cut into chip dimensions to obtain a plurality of semiconductor chips. Can do.

For example, silicon oxide (SiO ₂ ) can be used as the first insulating layer 3. When the substrate 1 is made of silicon, the silicon oxide insulating layer is advantageous because it can be easily and inexpensively formed by a thermal oxidation method.

  Next, as shown in FIG. 2B, an opening 3 b is formed in a part of the first insulating layer 3. Such an opening 3b can be formed by etching, for example.

Next, as shown in FIG. 2C, a conductive notch prevention layer 4 is formed so as to fill the opening.
The notch prevention layer 4 can be made of a general material used in a semiconductor process having good adhesion with Si, SiO ₂ or the like, and can be manufactured by a general method such as sputtering, CVD, or photolithography. it can.

The notch prevention layer 4 is preferably made of a metal or semiconductor material having a relatively large number of free electrons.
As such a metal or semiconductor material, for example, one or a plurality of materials selected from Al, Ti, TiN, Cr, Al—Si, Al—Si—Cu, and TiW are used. These materials are excellent in resistance to etching species in plasma and excellent in adhesion to Si and SiO ₂ .

  The notch prevention layer 4 may be formed either before or after the formation of the functional element in consideration of resistance to each process of the functional element or the like.

Next, as shown in FIG. 2D, a second insulating layer 5 is formed so as to cover the first insulating layer 3 and the notch prevention layer 4.
The second insulating layer 5 is made of, for example, polyimide resin, epoxy resin, silicone resin, or the like, and can be formed by, for example, spin coating, printing, laminating, or the like.

Next, as shown in FIG. 3A, an electrode layer 6 is formed on the second insulating layer 5 at a position corresponding to the notch prevention layer 4.
As the electrode layer 6, for example, an Al pad is used.

Next, as shown in FIG. 3B, a protective cover 7 is attached over the entire surface of the second insulating layer 5 so as to cover the electrode layer 6.
The protective cover 7 is not particularly limited, and may be the same substrate as the device-side substrate, such as a Si substrate, in addition to a glass substrate.
Such a protective cover 7 is bonded onto the second insulating layer 5 by, for example, anodic bonding or an adhesive.

  Next, as shown in FIG. 3C, the semiconductor substrate 2 is thinned by polishing or etching the other main surface (upper surface) of the semiconductor substrate 2.

Next, as shown in FIG. 3D, the third insulating layer 8 is formed on the upper surface of the semiconductor substrate 2, and the opening 8a is formed at the position where the through electrode is formed.
As the third insulating layer 8, for example, SiO ₂ is formed by plasma CVD or the like.
The opening 8a can be formed by patterning using a photolithography technique, for example.

First, as shown in FIG. 4A, the through hole 9 is formed in the semiconductor substrate 2.
The through hole 9 is formed so that the electrode layer 6 is exposed from the upper surface side of the semiconductor substrate 2. At this time, a part of the notch prevention layer 4 constitutes a part of the inner peripheral surface of the through hole 9 and is left so as to go around.
Dry etching or the like can be used to form the through holes 9.

As described above, in the prior art, as soon as Si etching reaches the insulating layer, which is an etching stop layer, a charge centered on the ion species drawn to the cathode side of the etching apparatus accumulates in the insulating layer. Along with this, reactive species with Si also gather at the bottom of the through hole, so that a notch is formed at the bottom of the through hole (see FIG. 4).
Therefore, in order to suppress the generation of the notch, it is necessary to release the charge accumulated at the bottom of the through hole when the Si etching reaches the etching stop layer.

  In the present invention, a conductive film (notch) having abundant free electrons on the upper surface or the same surface of the insulating layer (second insulating layer 5) to be an etching stop layer when the through hole 9 is formed by etching. A prevention layer 4) is provided. Thereby, the charge of the ion species having a positive charge can be electrically neutralized so that the charge is not accumulated. As a result, side etching during etching can be suppressed, and generation of a notch on the bottom side of the through hole 9 can be suppressed.

Next, as shown in FIG. 4B, a third insulating layer 8 is formed on the inner wall surface of the through hole 9.
The third insulating layer 8 is made of, for example, polyimide resin, epoxy resin, silicone resin or the like, and can be formed by, for example, spin coating, printing, laminating, or the like.

  At this time, in the notch prevention layer 4, since a portion where the through electrode is formed is opened, insulation can be performed when the insulating layer (third insulating layer 8) is formed on the inner wall surface of the through hole 9. Therefore, it is not necessary to remove this notch prevention layer 4.

  Next, as shown in FIG. 4C, the third insulating layer 8 formed on the bottom surface of the through hole 9 is removed.

Next, as shown in FIG. 4 (d), a conductor 11 is formed in the through hole 9 so as to cover the third insulating layer 8, and the conductor 11 is electrically connected to the electrode layer 6. Connect to.
The conductor 11 can be formed by sputtering, CVD, plating, filling with molten metal, filling with metal paste, or the like. Thereby, the electronic component 1 is produced.
If necessary, a rewiring layer, a stress relaxation layer, a bump, and the like may be further formed.

  As described above, according to the present invention, abundant free electrons are provided on the upper surface or the same surface of the insulating layer (second insulating layer 5) which becomes an etching stop layer when the through hole 9 is formed by etching. A conductive film (notch prevention layer 4) is provided. Thereby, the charge of the ion species having a positive charge can be electrically neutralized so that the charge is not accumulated. As a result, side etching during etching can be suppressed, and generation of a notch on the bottom side of the through hole 9 can be suppressed.

  In particular, since the notch prevention layer 4 is provided, over-etching can be sufficiently performed after reaching the etching stop layer (second insulating layer 5) during etching of the Si substrate. Thereby, even in a portion where the etching rate is slow due to the in-plane distribution during dry etching, the etching time can be taken, so that all the in-plane portions can be reliably etched.

  Further, since the generation of notches is suppressed, it is advantageous when an insulating layer is formed on the inner wall surface of the through-hole 9, and the insulating performance is improved. In addition, since it is advantageous when a conductor is formed in the through hole 9, a high resistance failure due to a disconnection failure or an insulation failure is improved. As a result, the obtained electronic component 1 is excellent in the reliability of the through electrode.

  In the electronic component 1, a functional element is formed on a semiconductor substrate 2, and the functional element and the electrode layer 6 are electrically connected. However, the notch prevention layer 4 is electrically independent from the functional element and the through electrode (not conductive).

  Since the notch prevention layer 4 provided in the present invention is opened in the same manner as the through-hole 9 to be formed, an insulating layer (third insulating layer 8) is formed on the inner wall surface of the through-hole 9 in a later step. , And can be electrically independent of the through electrode. Moreover, it is not necessary to remove like the prior art.

  As mentioned above, although the manufacturing method of the wiring board of this invention has been demonstrated, this invention is not limited to said example, It can change suitably as needed.

The present invention can be applied to a bonded substrate or the like regardless of the presence or absence of a functional element. This method can also be applied to a substrate without bonding.
In particular, in this method, it is possible to effectively perform the process in the case where the functional element is formed first and the functional element surface is protected.

  The present invention is widely applicable to an electronic component having a through electrode and a method for manufacturing the same.

It is sectional drawing which shows an example of the electronic component which concerns on this invention. FIG. 3 is a cross-sectional view sequentially illustrating an example of a manufacturing process of the electronic component illustrated in FIG. 1. FIG. 3 is a cross-sectional view sequentially illustrating an example of a manufacturing process following the process illustrated in FIG. 2. FIG. 4 is a cross-sectional view sequentially illustrating an example of a manufacturing process following the process illustrated in FIG. 3. It is sectional drawing which shows the state in which the notch was formed in the conventional electronic component.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Electronic component, 2 Semiconductor substrate, 3 1st insulating layer, 3a opening part, 4 Notch prevention layer, 5 2nd insulating layer, 6 Electrode layer, 7 Protective cover, 8 3rd insulating layer, 8a Opening part, 9 Through-hole 10, fourth insulating layer, 11 conductor.

Claims (5)

A conductive notch prevention layer provided on a part of one main surface of the semiconductor substrate;
A first insulating resin layer provided to cover the semiconductor substrate and the notch prevention layer;
On the first insulating resin layer, an electrode layer provided at a position corresponding to the notch prevention layer;
A through-hole that is provided so that the electrode layer is exposed from the other main surface side of the semiconductor substrate, and a part of the notch prevention layer constitutes a part of an inner peripheral surface, and is left to circulate; ,
A second insulating resin layer provided on the inner wall surface of the through hole;
An electronic component comprising at least a conductor provided in the through hole so as to cover the second insulating resin layer and electrically connected to the electrode.   The electronic component according to claim 1, wherein the notch prevention layer is made of a metal or a semiconductor material.   3. The electronic component according to claim 2, wherein the notch prevention layer is made of one or a plurality selected from Al, Ti, TiN, Cr, Al—Si, Al—Si—Cu, and TiW.   The electronic component according to claim 1, wherein a functional element is formed on the semiconductor substrate, and the functional element and the electrode layer are electrically connected. A first step of forming a conductive notch prevention layer on a part of one main surface of the semiconductor substrate;
A second step of forming a first insulating resin layer so as to cover the semiconductor substrate and the notch prevention layer;
A third step of forming an electrode layer on the first insulating resin layer at a position corresponding to the notch prevention layer;
The electrode layer is exposed from the other main surface side of the semiconductor substrate, and a part of the notch prevention layer constitutes a part of the inner peripheral surface, and a fourth through hole that is left to circulate is formed. Process,
A fifth step of forming a second insulating resin layer on the inner wall surface of the through hole;
Forming a conductor so as to cover the second insulating resin layer in the through hole, and electrically connecting the conductor to the electrode;
At least in order. The manufacturing method of the electronic component characterized by the above-mentioned.

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