JP2007273886A - Variable capacitance diode and manufacturing method thereof - Google Patents

Abstract

The present invention provides a variable capacitance diode that can be manufactured without decreasing the epitaxial impurity concentration even when the capacitance change ratio is increased, without increasing the series resistance, and having good CV linearity.
An outward from the center of the anode region composed of P ⁺ semiconductor region (or the center from the outside of the P ⁺ anode region) have a structure in which a trench spacing spreads the anode region composed of stepwise P ⁺ semiconductor region The depletion layer is connected in order from the P ⁺ anode region of the central trench structure to the outside (or from the P ⁺ semiconductor region of the outer trench structure to the center). Reduce capacity.
[Selection] Figure 2

Description

  The present invention relates to a variable capacitance diode and a method for manufacturing the same, and more particularly to a variable capacitance diode having a low series resistance and good CV linearity.

  In recent years, variable capacitance diodes are frequently used as tuning variable capacitors in tuners such as VCO modules, radio receivers, and television receivers in electronic devices such as mobile phones. When the variable capacitance diode is mounted as a chip component in these devices, further increase in capacitance change ratio, reduction in series resistance, and improvement in CV linearity are required.

For example, as an example of a conventional variable capacitance diode, there is a variable capacitance diode having a rectangular junction surface (Patent Document 1). This variable capacitance diode having a quadrangular junction area includes a low concentration N-type epitaxial layer 2 and a silicon oxide film on the surface of a high concentration N ⁺ type semiconductor substrate 1 as shown in a cross-sectional explanatory view in FIG. 12 and a plan view in FIG. 3 and a P-type impurity is introduced from a window formed in the silicon oxide film 3 to form a high-concentration P ⁺ -type semiconductor layer 7 to form a PN junction. At that time, although not shown, an N-type impurity is implanted near the PN junction of the N-type epitaxial layer 2 to increase the impurity concentration, and an impurity concentration gradient is formed in the N-type epitaxial layer 2. ing. Then, the anode electrode 8 is formed on the P ⁺ type semiconductor layer 7 side, the passivation film 9 is formed, and finally the cathode electrode 10 is formed on the substrate side, thereby completing the variable capacitance diode. In this configuration, an N-type impurity is implanted in the vicinity of the PN junction of the N-type epitaxial layer 2 to increase its impurity concentration, and an impurity concentration gradient is formed in the N-type epitaxial layer 2 to thereby form a super-step PN junction. The capacitance change becomes steep by adjusting the elongation of the depletion layer with respect to the applied voltage. Although FIG. 13 shows a variable capacitance diode having a rectangular junction surface, the junction surface may be circular as shown in FIG.

  In order to increase the capacitance change ratio, a trench is formed on the substrate surface and a PN junction is formed along the inner wall of the trench, thereby increasing the junction area and increasing the maximum capacitance, thereby increasing the capacitance change ratio. There has also been proposed a method (Patent Document 2).

Japanese Patent Laid-Open No. 5-167088 JP 2001-102599 A

  However, in the variable capacitance diode of Patent Document 1 shown in FIGS. 12, 13, and 14, the impurity concentration in the low-concentration side impurity region in the vicinity of the PN junction, that is, the N-type epitaxial layer 2 is relatively reduced. In this case, an impurity concentration gradient is provided in the N-type epitaxial layer 2 to increase the capacitance change ratio. In this case, the decrease in the average impurity concentration of the N-type epitaxial layer 2 is caused by the series connection of the variable capacitance diodes. There may be an increase in resistance. In addition, the impurity concentration gradient becomes too steep and the CV linearity is deteriorated.

  Further, in the configuration of Patent Document 2 in which the capacity change ratio is increased, the depletion layer extends to change the capacity, but the depletion layer extending from the adjacent recess contacts and is connected. Occurs instantaneously in each region, and there is a problem that the CV linearity is further deteriorated in the vicinity of the contact region.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a variable capacitance diode having good CV linearity without increasing the series resistance even when the capacitance change ratio is increased.

Therefore, the present invention forms a plurality of trenches at a predetermined interval on the surface of the substrate having the semiconductor region of the first conductivity type, and a second having a conductivity type opposite to that of the semiconductor region along the outer wall of the trench. Forming a PN junction, and controlling the magnitude of the electric field applied to the PN junction, thereby changing the extension of the depletion layer, The distance between the PN junction surfaces is changed so that the contact with the adjacent depletion layer occurs stepwise by the extension of the depletion layer.
With this configuration, when the magnitude of the electric field applied to the PN junction is increased, adjacent depletion layers are gradually closed and connected. Accordingly, since the capacitance changes without causing a sudden capacitance change as in the case of connection at a time, CV linearity can be obtained.

The present invention also includes the variable capacitance diode formed so that the interval between the trenches is different.
With this configuration, if the trenches are formed to have different spacings, the spacing between the PN junction surfaces will be different. Therefore, when the magnitude of the electric field applied to the PN junction is increased, the adjacent depletion layers are gradually plugged and connected. Thus, the capacitance changes without causing a sudden capacitance change as in the case of connection at a time, so that CV linearity can be obtained.

The present invention includes the variable capacitance diode, wherein the trench is formed to be perpendicular to the substrate surface.
With this configuration, the PN junction surface can be maximized.

According to the present invention, in the above variable capacitance diode, the trench is formed such that the interval gradually increases from the center of the substrate toward the outside.
With this configuration, since the depletion layer is gradually connected from the center, the capacitance is changed without causing a sudden change in capacitance as in the case of being connected at one time, so that CV linearity can be obtained. It becomes possible.

According to the present invention, in the above variable capacitance diode, the trench is formed such that the interval gradually increases from the outside to the inside of the substrate.
With this configuration, since the capacitance changes without causing a sudden change in capacitance as it is connected from the outside to the inside of the substrate at once, CV linearity can be obtained.

In the variable capacitance diode according to the present invention, the PN junction surface formed along the inner wall of the trench is gradually opened from the anode side constituting the P-type semiconductor region toward the cathode side constituting the N-type semiconductor region. Including a tapered surface.
With this configuration, the depletion layer is gradually connected along the taper surface, so that the capacity is changed stepwise without causing a sudden capacity change as in the case of being connected at once. -V linearity can be obtained.

In the variable capacitance diode according to the present invention, the trench is formed to have an inner wall having a predetermined angle with respect to the substrate surface, and a PN junction surface formed along the inner wall of the trench. Includes a taper surface opening from the anode side constituting the P-type semiconductor region toward the cathode side constituting the N-type semiconductor region.
With this configuration, it is possible to easily form a device having a desired pattern accuracy with controllability by introducing impurities along the inner wall of the trench.

  According to the present invention, in the above variable capacitance diode, an anode electrode disposed so as to contact the P-type semiconductor region having a high impurity concentration, and a high-concentration contact region in the N-type semiconductor region having a low impurity concentration. Including a cathode electrode provided so as to be in contact with each other.

The present invention also includes a step of forming a plurality of trenches at a predetermined interval on a substrate surface having a semiconductor region of the first conductivity type, and a second conductivity type containing impurities of a second conductivity type in the trench. Forming a semiconductor layer and forming a PN junction surface with the semiconductor region of the first conductivity type; and each of the semiconductor region of the first conductivity type and the semiconductor layer of the second conductivity type, And a step of forming an electrode, wherein the contact between the PN junction surface and the adjacent depletion layer is stepwise due to the extension of the depletion layer formed on the surface of the semiconductor region. As described above, the interval between the PN junction surfaces is adjusted.
With this configuration, the interval between the PN junction surfaces is adjusted so that the contact between the PN junction surface and the adjacent depletion layer occurs stepwise due to the extension of the depletion layer formed on the surface of the semiconductor region. Therefore, it is possible to form a variable capacitance diode having excellent CV linearity without requiring a special device with only a slight shape change.

According to the present invention, in the method of manufacturing a variable capacitance diode, the step of forming the trench is formed such that an interval between the trenches is different so that an inner wall of the trench is perpendicular to the substrate surface. Including a step of forming by anisotropic etching through a resist pattern.
This configuration enables highly accurate shape processing.

In the variable capacitance diode manufacturing method, the step of forming the trench includes a step of performing isotropic etching so that an inner wall of the trench has a tapered surface with respect to the surface of the substrate. .
With this configuration, it is possible to easily form a desired variable capacitance diode with good controllability.

According to the present invention, in the method for manufacturing a variable capacitance diode, in the step of forming the PN junction surface, the trench is filled with a first conductivity type high concentration impurity, and the trench inner wall is filled with the first conductivity type high concentration impurity. A step of diffusing the concentration impurity, and a step of removing the high-concentration impurity of the first conductivity type, forming the semiconductor layer of the second conductivity type in the trench again, and forming a PN junction surface.
With this configuration, a super staircase junction is easily formed.

For example, the present invention has a structure in which the trench interval of the anode region gradually increases from the center of the anode region made of the P ⁺ semiconductor region to the outside (or from the outside to the center of the anode region). By depleting layers connected in order from the anode region of the P ⁺ semiconductor region to the outside thereof (or from the anode region of the outer trench structure to the center thereof), the PN junction capacitance area is reduced, The above problems are solved.

  As described above, according to the present invention, the depletion layer is formed so as to be gradually connected. Therefore, even if the capacitance change ratio is increased, the series resistance is not increased, and the CV linearity is good. A variable capacitance diode can be provided.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Embodiment 1)
In this embodiment, as shown in FIG. 1 and FIG. 2, respectively, a cross sectional view and a plan view form a trench structure with a circular junction surface, and P is formed stepwise from the center of the anode region made of P ⁺ semiconductor region to the outside. ⁺ Shows a variable capacitance diode configured such that the interval between the trenches 4 of the anode region 7 made of a semiconductor region increases. 1 is a cross-sectional view taken along line AA of FIG. FIG. 3 is an enlarged cross-sectional view showing a detailed description of the present embodiment, and FIG. 4 is an enlarged cross-sectional view of a main part. That is, in the present embodiment, an N type epitaxial growth layer 2 is formed as a first conductivity type semiconductor region on the surface of an N ⁺ type silicon substrate 1, and a gap L is formed on the surface of the epitaxial growth layer 2 of this type. A plurality of trenches 4 are formed so as to increase in size, and an anode region 7 made of a P ⁺ semiconductor region is formed as a second conductivity type semiconductor region along the outer wall of the trench 4 to form a PN junction Is formed. Here, the first conductivity type impurity is diffused at a high concentration on the outer wall of the trench, and a high concentration N ⁺ semiconductor region 6 is formed to constitute a super step junction. Here, the trench 4 is formed so as to be perpendicular to the substrate surface.

An anode electrode 8 is formed in a window opened in the protective film made of the silicon oxide film 9 in the anode region 7 made of the P ⁺ semiconductor region. On the other hand, a cathode electrode 10 is formed on the back side of the silicon substrate 1, and the voltage applied between the cathode electrode 10 and the anode electrode 8 is controlled to increase the magnitude of the electric field applied to the PN junction. Adjacent depletion layers are gradually plugged and connected.

That is, the trench interval anode region 7 consisting of stepwise ^{P +} semiconductor region from the center of the anode region 7 of ^{P +} semiconductor region outwardly, spreading the L1 <L2 <L3 <L4 < L5 <···· Ln It has a structure that goes on. The PN junction area is significantly larger than that in the case of not having a trench structure of an anode region made of a P ⁺ semiconductor region. When the applied voltage is low, the depletion layer spreads small as shown in FIG. 6 and the entire depletion layer exists along the trench structure, so that the junction capacitance increases.

  On the other hand, as the applied voltage is increased, the depletion layer expands. As shown in FIG. 7, the depletion layers adjacent to each other are gradually connected in order from L1 → L3 → L4 → L5 → Ln, which are narrowly spaced from each other between adjacent trench structures. As a result, the effect of the trench structure is gradually reduced, and the junction capacitance is reduced to the same extent as in the case without the trench structure.

  In this way, since the capacitance gradually changes without causing a sudden capacitance change as in the case where all the trenches are connected at once, CV linearity can be obtained. Since the trench is formed so as to be perpendicular to the substrate surface, the PN junction surface can be maximized. Therefore, the capacitance change is larger than that without the trench structure. For this reason, it is not necessary to reduce the average impurity concentration of the N-type epitaxial layer 2 and increase the capacitance, and the series resistance of the variable capacitance diode is not increased. In addition, since the depletion layers are connected step by step in the order of narrow spacing between the trench structures, the inconvenience that the CV linearity is lowered due to the steep impurity concentration gradient.

Next, a method for manufacturing the variable capacitance diode of the present invention will be described.
FIGS. 5A to 5D are process cross-sectional views showing a process for mounting the variable capacitance diode of the present invention.
First, as shown in FIG. 5A, a low concentration N type epitaxial layer 2 is formed on a high concentration N ⁺ type semiconductor substrate 1, and a silicon oxide film 3 is formed. Thereafter, a resist pattern is formed by photolithography, and the trench 4 is formed. At this time, the epitaxial growth layer 2 formed on the surface of the silicon substrate 1 is etched using the resist pattern as a mask to form a trench. Alternatively, the trench 4 may be formed by dry etching (anisotropic etching) using the silicon oxide film 2 as a hard mask. At this time, the trench 4 is formed from the center of the element region to the outside (or from the outside to the center of the element region).

  Next, a phosphorus-doped polysilicon layer 5 is deposited in the vicinity of the PN junction along the surface of the trench 4 formed on the surface of the N-type epitaxial layer 2, and phosphorus is diffused from the doped polysilicon layer 5 to reduce the impurity concentration. The N + type impurity region 6 is formed to increase the impurity concentration gradient in the N type epitaxial layer 2. Next, the phosphorus-doped polysilicon 5 in the previous step is etched by dry etching to expose the trench 4 again by photolithography.

Thereafter, high-concentration boron-doped silicon is formed in the anode region by a CVD method, a P ⁺ type semiconductor layer is formed, and a PN junction is formed. Next, the anode electrode 8 is formed, the passivation 9 is formed, and finally the cathode electrode 10 is formed.

In this way, the variable capacitance diode of the first embodiment is formed.
According to the method of the present embodiment, it is possible to provide a variable capacitance diode with high dimensional accuracy and excellent CV linearity.

(Embodiment 2)
In this embodiment, the capacitance change accompanying the extension of the depletion layer is changed stepwise by changing the trench interval. However, in this embodiment, the trench interval is constant and the vertical trenches are changed. The shape of this is a taper surface, and the capacitance change due to the extension of the depletion layer is changed stepwise. As shown respectively sectional and plan views in FIGS. 8 and 9, so as to form a concentric circle from the center to the outside of the anode region composed of P ⁺ semiconductor region that forms a trench structure of the junction surface circular, P at the same interval ^{+ A} trench 4 is provided which becomes an anode region 7 made of a semiconductor region. The PN junction surface formed along the inner wall of the trench forms a tapered surface that gradually opens from the anode side constituting the P-type semiconductor region toward the cathode side constituting the N-type semiconductor region. The trench is formed so as to have an inner wall having a predetermined angle with respect to the substrate surface, and a PN junction surface formed along the inner wall of the trench is an anode constituting a P-type semiconductor region. A tapered surface opening from the side toward the cathode side constituting the N-type semiconductor region is formed.
Therefore, as the electric field between the anode and cathode increases, the depletion layer gradually connects along the taper surface, so that the capacitance changes without causing a sudden change in capacitance as in the case of connection at once. And CV linearity can be obtained.

  In manufacturing, the trench is formed by isotropic etching, and a tapered surface is formed. The other differences are the same as in the first embodiment except that the trench is formed.

Note that an anode electrode 8 is formed in a window opened in the protective film made of the silicon oxide film 9 in the anode region 7 made of a P ⁺ type semiconductor region. On the other hand, a cathode electrode 10 is formed on the back side of the silicon substrate 1, and the voltage applied between the cathode electrode 10 and the anode electrode 8 is controlled to increase the magnitude of the electric field applied to the PN junction. Adjacent depletion layers are gradually blocked in the vertical direction and connected. As a result, the capacity can be changed very smoothly and the CV linearity is higher.

  As shown in FIGS. 10 and 11, the planar shape of the trench can be appropriately changed such as a square shape with rounded corners or a stripe shape.

  In the above embodiment, the position of the PN junction surface is adjusted by adjusting the shape of the trench, but the impurity concentration profile is adjusted to adjust the position of the PN junction surface while maintaining the shape of the trench. Thus, the PN junction surface may be substantially adjusted.

  Furthermore, in the above-described embodiment, phosphorus diffusion is performed to form a super step junction, but it goes without saying that the present invention can also be applied to a variable capacitance diode having a normal PN junction.

  The variable capacitance diode and the manufacturing method of the present invention can be manufactured without decreasing the epitaxial impurity concentration even when the capacitance change ratio is increased, and therefore, the series resistance is not increased, and the CV straight line can be obtained. It is useful as a variable capacitance diode with good characteristics.

The figure which shows sectional drawing of the variable capacitance diode which concerns on Embodiment 1 of this invention. The figure which shows the top view of the variable capacitance diode which concerns on Embodiment 1 of this invention. Illustration of the variable capacitance diode The principal part expanded sectional view of the variable capacitance diode The figure which shows the manufacturing process of the variable capacitance diode Explanatory diagram showing the operation of the variable capacitance diode Explanatory diagram showing the operation of the variable capacitance diode The figure which shows sectional drawing of the variable capacitance diode which concerns on Embodiment 2 of this invention. The figure which shows the top view of the variable capacitance diode which concerns on Embodiment 2 of this invention. The top view which shows the modification of the variable capacitance diode of embodiment of this invention The top view which shows the modification of the variable capacitance diode of embodiment of this invention The figure which shows sectional drawing of the variable capacity diode of a prior art example The figure which shows the top view of the variable capacitance diode of a prior art example The figure which shows the top view of the variable capacitance diode of a prior art example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 High concentration N ⁺ type semiconductor substrate 2 N type epitaxial layer 3 Silicon oxide film 4 Trench 5 Phosphorus doped polysilicon layer 6 Trench (structure)
7 High concentration P ⁺ type semiconductor layer (anode region)
8 Anode electrode 9 Passivation 10 Cathode electrode

Claims (13)

A plurality of trenches are formed at predetermined intervals on a substrate surface having a semiconductor region of the first conductivity type, and a second conductivity type semiconductor having a conductivity type opposite to that of the semiconductor region along the outer wall of the trench Forming a region, forming a PN junction, and controlling a magnitude of an electric field applied to the PN junction, thereby changing a depletion layer extension;
A variable capacitance diode in which a distance between PN junction surfaces is changed so that contact with an adjacent depletion layer occurs stepwise due to elongation of the depletion layer. The variable capacitance diode according to claim 1,
Variable capacitance diodes including those formed so that the intervals between the trenches are different. The variable capacitance diode according to claim 2,
The variable capacitance diode is formed so that the trench is perpendicular to the substrate surface. The variable capacitance diode according to claim 2 or 3,
The trench is a variable-capacitance diode formed such that the interval gradually increases from the center of the substrate toward the outside. The variable capacitance diode according to claim 2 or 3,
The trench is a variable capacitance diode formed such that the interval gradually increases from the outside to the inside of the substrate. The variable capacitance diode according to claim 1,
A variable capacitance diode in which a PN junction surface formed along an inner wall of the trench forms a tapered surface that gradually opens from an anode side constituting a P-type semiconductor region toward a cathode side constituting an N-type semiconductor region. The variable capacitance diode according to claim 1,
The trench is formed so as to have an inner wall having a predetermined angle with respect to the substrate surface, and a PN junction surface formed along the inner wall of the trench is an anode side forming a P-type semiconductor region A variable capacitance diode that forms a tapered surface that opens from the cathode toward the cathode that forms the N-type semiconductor region. The variable capacitance diode according to any one of claims 1 to 7,
An anode electrode disposed in contact with the P-type semiconductor region having a high impurity concentration;
A variable capacitance diode in which a cathode electrode is provided so as to contact the N-type semiconductor region having a low impurity concentration through a contact region having a high concentration. The variable capacitance diode according to any one of claims 1 to 8,
A variable capacitance diode in which the PN junction surface forms a super step junction. Forming a plurality of trenches at a predetermined interval on a substrate surface having a semiconductor region of a first conductivity type;
Forming a second conductive type semiconductor layer containing an impurity of the second conductive type in the trench and forming a PN junction surface with the first conductive type semiconductor region;
A method of manufacturing a variable capacitance diode, comprising: forming electrodes on the first conductive type semiconductor region and the second conductive type semiconductor layer, respectively.
A variable in which the interval between the PN junction surfaces is changed so that the contact between the PN junction surface and the adjacent depletion layer occurs stepwise by the extension of the depletion layer formed on the surface of the semiconductor region. A method for manufacturing a capacitive diode. It is a manufacturing method of the variable capacity diode according to claim 10,
In the step of forming the trench, anisotropic etching is performed through a resist pattern formed so that the interval between the trenches is different so that the inner wall of the trench is perpendicular to the substrate surface. A manufacturing method of a variable capacitance diode which is a process. It is a manufacturing method of the variable capacity diode according to claim 10,
The step of forming the trench includes a step of performing isotropic etching so that an inner wall of the trench has a tapered surface with respect to the surface of the substrate. A method of manufacturing a variable capacitance diode according to any one of claims 10 to 12,
The step of forming the PN junction surface includes:
Filling the trench with a first conductivity type high concentration impurity and diffusing the first conductivity type high concentration impurity in the trench inner wall;
A method of manufacturing a variable capacitance diode, comprising: removing a high-concentration impurity of the first conductivity type; and forming a second conductivity type semiconductor layer in the trench again to form a PN junction surface.

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