JP2007258360A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

An object of the present invention is to reduce the on-resistance of a field effect transistor using a heterojunction.
A hetero semiconductor region that forms a heterojunction with a drain region formed on a substrate region, and a gate insulating film adjacent to a junction end between the hetero semiconductor region and the drain region. In the field effect transistor semiconductor device having the gate electrode 11 disposed in the trench, a trench whose bottom is a heterojunction interface between the drain region 2 and the hetero semiconductor region 8 is formed on the drain region 2. Is formed in a sidewall shape on the sidewall of the groove by anisotropic etching, and a transistor drive point is formed in a region where the gate insulating film 9, the hetero semiconductor region 8, and the drain region 2 are in contact with each other.
[Selection] Figure 1

Description

  The present invention relates to a field effect transistor semiconductor device having a heterojunction and a method of manufacturing the same.

  Conventionally, as this kind of technology, for example, one described in Document 1 shown below is known (see Patent Document 1). In the technique described in this document 1, a heterojunction is formed by a silicon carbide (SiC) substrate and polycrystalline silicon, and the thickness of the barrier at the heterointerface is controlled by the voltage applied to the gate electrode, thereby providing a field effect transistor. When the (FET) is turned on, carriers are passed by a tunnel current. Such FETs do not have a channel region like MOS type FETs, and have a device structure that is not easily affected by high channel resistance, and have a high breakdown voltage and low on-resistance power semiconductor switch. Can be provided.

In such an FET, in order to further improve the off characteristics of the transistor, as described in Document 2 (see Patent Document 1) shown below, a hetero semiconductor region that forms a heterojunction with a silicon carbide substrate The main P-type conductive region and the N-type conductive region, which is very narrow in cross-sectional shape as compared with the P-type conductive region, are required to be accurately created.
JP 2003-318398 A JP 2005-259796

  In the technique described in Document 2, after forming a P-type polycrystalline silicon layer that forms a heterojunction with a silicon carbide substrate, the N-type is applied to the P-type polycrystalline silicon in an atmosphere containing N-type impurities. By doping this impurity, an N-type polycrystalline silicon layer was formed adjacent to the P-type polycrystalline silicon layer. In such a formation method, it has been extremely difficult in the manufacturing process to accurately introduce an impurity into a very narrow region as compared with a P-type polycrystalline silicon region.

  Accordingly, the present invention has been made in view of the above, and an object of the present invention is to provide a semiconductor device in which the on-resistance of a field effect transistor using a heterojunction is reduced, and a method for manufacturing the same.

  In order to achieve the above object, means for solving the problems of the present invention includes a semiconductor substrate, a hetero semiconductor region in contact with the first main surface of the semiconductor substrate and forming a heterojunction with the semiconductor substrate, and the hetero A gate electrode disposed via a gate insulating film adjacent to a junction end between the semiconductor region and the semiconductor substrate, a source electrode connected to the hetero semiconductor region, and a drain electrode connected to the semiconductor substrate In the semiconductor device, a groove is formed on the semiconductor substrate, the bottom of which forms a heterojunction interface between the semiconductor substrate and the hetero semiconductor region, and the hetero semiconductor region is formed on a sidewall of the groove by anisotropic etching. The driving point of the semiconductor device is formed in a region where the gate insulating film, the hetero semiconductor region, and the semiconductor substrate are in contact with each other. And said that you are.

  According to the present invention, the reverse leakage current of a field effect transistor of a semiconductor device is reduced by forming a hetero semiconductor region that forms a driving point by forming a heterojunction with a semiconductor substrate in a very narrow shape by self-alignment. In addition, the transistor can be miniaturized and the on-resistance of the transistor can be reduced.

  DESCRIPTION OF THE PREFERRED EMBODIMENTS The best embodiment for carrying out the present invention will be described below with reference to the drawings.

  FIG. 1 is a cross-sectional view showing a configuration of a semiconductor device according to Embodiment 1 of the present invention. FIG. 1 shows a cross section in which two unit cells of a field effect transistor, which is a semiconductor device of the present invention, are arranged facing each other. In practice, a plurality of these unit cells are arranged and connected in parallel to form one transistor. In the following embodiment, this sectional structure will be representatively described.

In FIG. 1, a drain region 2 made of N-type low concentration (N ⁻ ) SiC is formed on the surface of a substrate region 1 made of N-type high concentration (N ⁺ ) SiC (silicon carbide). The drain region 2 is composed of an epitaxial layer grown on the substrate region 1, and the drain region 2 and the substrate region 1 constitute a semiconductor substrate.

  There are several polytypes (crystal polymorphs) of SiC, but here, it will be described as representative 4H—SiC. In FIG. 1, the concept of the thickness of the substrate region 1 and the drain region 2 is omitted. Actually, the substrate region 1 has a thickness of about several hundred μm, and the drain region 2 has a thickness of about several μm to several tens of μm.

  On the surface side of the drain region 2, a well region 3 made of P-type SiC corresponding to each cell is formed. Further, on the surface side of the well region 3, a hetero semiconductor region 4 made of polycrystalline silicon that forms a heterojunction with SiC corresponding to each cell is formed.

SiC and polycrystalline silicon have different band gaps and different electron affinities. A heterojunction is formed at the junction interface between SiC and the hetero semiconductor region 4 made of polycrystalline silicon. A groove is formed between the P-type well region 3 from the surface side of the P-type well region 3 to the junction interface between the drain region 2 and the well region 3, and an N ⁺ type made of polycrystalline silicon is formed on the sidewall of the groove. The hetero semiconductor region 8 is formed.

Here, the N ⁺ -type hetero semiconductor region 8 is formed in a sidewall shape on the side wall of the groove, and the portion (heterojunction interface) in contact with the drain region 2 at the bottom of the groove is much larger than the P-type well region 3. It is narrowly formed. A gate electrode 11 is formed through a gate insulating film 9 adjacent to the junction between the drain region 2 and the N ⁺ type hetero semiconductor region 8.

The hetero semiconductor region 4 formed on the P-type well region 3 is formed at least on the surface side in an N ⁺ type and is electrically connected to the N ⁺ type hetero semiconductor region 8 with a low resistance. Further, a source electrode 14 is formed on the hetero semiconductor region 4 and directly connected thereto. A part of the hetero semiconductor region 4 is P ⁺ type in the entire thickness direction, and connects the P type well region 3 and the source electrode 14 with low resistance. The bottom surface portion of the hetero semiconductor region 4 is formed in, for example, a P ⁺ type.

  A drain electrode 13 is electrically ohmically connected to the back surface of the substrate region 1 with a low resistance. The gate electrode 11 is insulated from the source electrode 14 by the interlayer insulating film 12. In FIG. 1, the trench between the well region 3 of each cell and the hetero semiconductor region 4 stacked thereon is formed to the depth of the junction interface between the well region 3 and the drain region 2. However, it may reach the inside of the drain region 2.

  The cross section of the basic cell structure is as described, and at the outermost peripheral portion of the chip in which a plurality of basic cells are connected in parallel, the electric field concentration at the periphery when the field effect transistor is off is alleviated to achieve a high breakdown voltage. For this purpose, a termination structure (not shown) such as a guard ring is employed, but a general termination structure used in the field of power devices can be applied, and the description thereof is omitted.

  The basic operation of the transistor having the structure shown in FIG. 1 is the same as that described in the above documents 1 and 2, and different operations and effects will be described.

The well region 3 is fixed to the potential of the source electrode 14 through the P ⁺ type region of the hetero semiconductor region 4. In this state, when the voltage applied to the gate electrode 11 is 0V, the potential of the source electrode 14 is 0V, and a positive voltage is applied to the drain electrode 13, the field effect transistor is turned off. In this state, an electric field is applied to the PN junction between the well region 3 and the N-type drain region 2, and a depletion layer extends in SiC. Thus, a field effect transistor having reverse characteristics of a SiC PN junction is realized.

  In the first embodiment, the SiC PN junction is present at a position adjacent to the groove portion, so that the electric field applied to the gate insulating film 9 is relieved by the depletion layer that extends when the field effect transistor is turned off. As a result, it is possible to reduce the stress applied to the gate insulating film 9, and it is possible to realize a highly reliable field effect transistor that is less likely to deteriorate with time such as characteristic variation of the field effect transistor.

Further, since the heterojunction between the N ⁺ -type hetero semiconductor region 8 and the drain region 2 has a relatively low potential barrier, a leak current is likely to be generated when the field effect transistor is turned off. However, in the present invention, since the heterojunction between the hetero semiconductor region 8 and the drain region 2 is very narrow, the reverse leakage current can be suppressed as compared with the conventional case.

When a voltage higher than a predetermined threshold is applied to the gate electrode 11, the field effect transistor is turned on. The on-time operation is basically the same as the conventional device operation. That is, the width of the potential barrier at the heterojunction interface formed by the hetero semiconductor region 8 and the drain region 2 is reduced by the electric field from the gate electrode 11, and the drain region 2, the hetero semiconductor region 8 and the gate insulating film 9 are reduced. A tunnel current flows at the driving point in contact. At this time, the electron current is generated from the source electrode 14 to the N ⁺ -type region on the surface of the hetero semiconductor region 4, the side wall-like hetero semiconductor region 8 formed on the side wall of the groove, the driving point of the transistor, the drain described above The region 2 flows in the order of the substrate region 1 and the drain electrode 13.

  Providing a field effect transistor having such characteristics greatly contributes to the realization of miniaturization, weight reduction, and cost reduction in the field of power electronics systems including in-vehicle use.

  Next, the manufacturing method of the apparatus shown in FIG. 1 will be described with reference to the manufacturing process sectional views shown in FIGS.

First, a drain region 2 made of N ⁻ -type SiC is formed on a substrate region 1 made of N ⁺ -type SiC by epitaxial growth or the like (FIG. 2-A (a)).

Subsequently, a P ⁻ -type well region 3 is stacked on the surface side of the drain region 2. This can be realized by introducing impurities such as Al and B from the SiC surface by high-temperature ion implantation and activating the impurities by high-temperature annealing (FIG. 2-A (b)).

  Subsequently, a hetero semiconductor region 4 made of polycrystalline silicon is further deposited on the surface side to form a stacked layer. The hetero semiconductor region 4 is formed to have a desired impurity distribution using ion implantation or a stacked structure. A resist 5 as a mask material is applied thereon. In addition, an oxide film or a nitride film may be used as the mask material (FIG. 2-A (c)).

  Thereafter, the resist 5 is selectively removed and patterned (FIG. 2A (d)), and the hetero semiconductor region 4 and the well region 3 are simultaneously removed by etching using the patterned resist 5 as a mask to form the groove 6. Form. This etching process can be performed with good controllability by dry etching using, for example, ions or plasma so as to cope with a fine pattern. Here, the bottom of the trench 6 is dug up to the junction interface between the well region 3 and the drain region 2, but may be dug into the drain region 2 (FIG. 2-B (e)).

  Next, after removing the resist 5 which is a mask material (FIG. 2-B (f)), a polycrystalline silicon 7 is again deposited over the entire surface including the groove 6 (FIG. 2-B (g)). .

  Subsequently, the entire surface side is etched by highly anisotropic etching such as dry etching. In this anisotropic etching process, since the thickness of the polycrystalline silicon differs between the planar region where the two polycrystalline silicons overlap and the bottom of the groove 6, even if the polycrystalline silicon at the bottom of the groove 6 is completely removed. Polycrystalline silicon still remains on the planar portion, and polycrystalline silicon remains on the side wall of the groove 6 in the form of a sidewall. Thereby, a hetero semiconductor region 8 made of polycrystalline silicon is formed in a sidewall shape on the side wall of the groove 6. Here, the width of the sidewall-like hetero semiconductor region 8 can be controlled and adjusted by the thickness of the polycrystalline silicon deposited in the step shown in FIG. -B (g)).

  Next, after depositing the gate insulating film 9 over the entire surface by CVD or the like and performing a desired annealing treatment (FIG. 2-C (i)), a polycrystalline silicon 10 is deposited over the entire surface of the gate insulating film 9 to form a desired one. Are introduced from the surface (FIG. 2-C (j)).

  Subsequently, after the polycrystalline silicon 10 is patterned into a desired shape and a gate electrode 11 is formed (FIG. 2-C (k)), an interlayer insulating film 12 is deposited and formed thereon (FIG. 2-C ( l)).

  Subsequently, after removing the polycrystalline silicon adhering to the back surface side, a metal drain electrode 13 is formed so as to be in contact with the substrate region 1 so that the drain electrode 13 and the substrate region 1 are ohmically connected with low resistance. Heat treatment for alloying is performed (FIG. 2-D (m)).

  Finally, after patterning the interlayer insulating film 12 on the surface into a desired shape (FIG. 2-D (n)), a metal source electrode 14 is formed so as to be in contact with the hetero semiconductor region 4 through the contact hole. The semiconductor device of Example 1 shown is completed (FIG. 2-D (o)).

  In the semiconductor device of the first embodiment formed by adopting such a manufacturing method, the hetero semiconductor region 8 constituting the driving point of the field effect transistor can be formed in a very narrow shape by self-alignment. Become. As a result, the reverse leakage current of the field effect transistor can be drastically reduced, the field effect transistor can be miniaturized, and a field effect transistor with low on-resistance can be realized as the cell density increases. It becomes possible.

  In addition, since the well region 3 can be formed in the vicinity of the gate electrode 11 by self-alignment, it is possible to further improve the off characteristics of the field effect transistor, and the gate insulating film 9 when the field effect transistor is off. It is possible to effectively reduce the electric field. Thereby, a field effect transistor with high reliability can be realized.

FIG. 3 is a sectional view showing a configuration of the semiconductor device according to the first embodiment of the present invention. The feature of the second embodiment shown in FIG. 3 is that the bottom of the groove formed in the drain region 2 reaches the drain region 2 as compared with the first embodiment shown in FIG. 3 is deleted, and accordingly, the bottom of the hetero semiconductor region 4 is formed in a P ⁺ -type, and the others are the same as in the first embodiment. The bottom of the groove may be a junction interface between the drain region 2 and the hetero semiconductor region 4 without reaching the drain region 2.

  The manufacturing method of such a device can be easily manufactured by using the same method as in the first embodiment, and has a P-type well region as compared with the manufacturing method of the first embodiment. Therefore, steps such as high temperature ion implantation and high temperature annealing can be omitted.

  In such a configuration, the heterojunction interface between the drain region 2 and the hetero semiconductor region 4 has a relatively high potential barrier. As a result, when the field effect transistor is turned off, the depletion layer extends from the heterojunction interface to the drain region 2 side, so that a high breakdown voltage can be obtained.

  Further, as in the first embodiment, the region of the hetero semiconductor region 8 is narrow, and the gate electrode 11 can be formed in a self-aligned manner with good controllability. Both the reduction of the on-resistance and the reduction of the reverse leakage current can be satisfied.

  In the second embodiment, in addition to the above-described effects, a heterojunction diode can be used as a reverse breakdown voltage holding mechanism of the transistor. As a result, the diode parasitic in parallel between the drain and source of the field effect transistor can be a heterojunction diode.

  A diode with a heterojunction has a monopolar operation in which carrier injection from the P-type region to the N-type region does not occur during forward operation. For this reason, when used in a circuit configuration that actively utilizes a heterojunction diode, there is little reverse recovery charge of the diode, making it possible to construct a system with excellent switching characteristics. An effect can be obtained.

  In Examples 1 and 2, the semiconductor substrate may be made of gallium nitride or diamond in addition to silicon carbide, and the hetero semiconductor region is made of single crystal silicon or amorphous silicon in addition to polycrystalline silicon. May be.

It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the process of the manufacturing method of the semiconductor device which concerns on Example 1 of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on Example 2 of this invention.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Substrate region 2 ... Drain region 3 ... Well region 4, 8 ... Hetero semiconductor region 5 ... Resist 6 ... Groove 7, 10 ... Polycrystalline silicon 9 ... Gate insulating film 11 ... Gate electrode 12 ... Interlayer insulating film 13 ... Drain electrode 14 ... Source electrode

Claims (11)

A semiconductor substrate;
A hetero semiconductor region in contact with the first main surface of the semiconductor substrate to form a hetero junction with the semiconductor substrate;
A gate electrode disposed via a gate insulating film adjacent to a junction end between the hetero semiconductor region and the semiconductor substrate;
A source electrode connected to the hetero semiconductor region;
In a semiconductor device having a drain electrode connected to the semiconductor substrate,
A groove whose bottom is a heterojunction interface between the semiconductor substrate and the hetero semiconductor region is formed on the semiconductor substrate, and the hetero semiconductor region is formed in a sidewall shape on the sidewall of the groove by anisotropic etching. A driving point of the semiconductor device is formed in a region where the gate insulating film, the hetero semiconductor region, and the semiconductor substrate are in contact with each other. A semiconductor substrate;
A hetero semiconductor region in contact with the first main surface of the semiconductor substrate to form a hetero junction with the semiconductor substrate;
A gate electrode disposed via a gate insulating film adjacent to a junction end between the hetero semiconductor region and the semiconductor substrate;
A source electrode connected to the hetero semiconductor region;
In a semiconductor device having a drain electrode connected to the semiconductor substrate,
A groove having a bottom extending into the semiconductor substrate is formed on the semiconductor substrate, and the hetero semiconductor region is formed in a sidewall shape on a sidewall of the groove by anisotropic etching, and the gate insulating film and the hetero semiconductor are formed. A driving point of the semiconductor device is formed in a region where the region and the semiconductor substrate are in contact with each other. 3. The semiconductor substrate according to claim 1, wherein the semiconductor substrate is of a first conductivity type, and has a second conductivity type well region in contact with the first main surface of the semiconductor substrate and in the vicinity of the driving point. Semiconductor device. The semiconductor device according to claim 1, wherein the hetero semiconductor region has a region having the same conductivity type as the semiconductor substrate. The semiconductor device according to claim 1, wherein the semiconductor substrate is made of any one of silicon carbide, gallium nitride, and diamond. 6. The semiconductor device according to claim 1, wherein the hetero semiconductor region is made of any one of single crystal silicon, polycrystalline silicon, and amorphous silicon. In a method of manufacturing a field effect transistor semiconductor device having a heterojunction,
A first step of forming a second conductivity type well region on the first main surface of the first conductivity type semiconductor substrate;
A second step of forming a first hetero semiconductor region on the well region;
A third step of selectively removing the well region and the first hetero semiconductor region, and forming a groove whose bottom is a bonding interface between the well region and the semiconductor substrate;
A fourth step of forming a second hetero semiconductor region over the entire first main surface side of the semiconductor substrate;
A fifth step of selectively removing at least the second hetero semiconductor region formed at the bottom of the trench by anisotropic etching to form a sidewall-like second hetero semiconductor region on the sidewall of the trench; A method for manufacturing a semiconductor device, comprising: In a method of manufacturing a field effect transistor semiconductor device having a heterojunction,
A first step of forming a second conductivity type well region on the first main surface of the first conductivity type semiconductor substrate;
A second step of forming a first hetero semiconductor region on the well region;
A third step of selectively removing the well region, the first hetero semiconductor region, and the semiconductor substrate, and forming a groove whose bottom reaches the semiconductor substrate;
A fourth step of forming a second hetero semiconductor region over the entire first main surface side of the semiconductor substrate;
A fifth step of selectively removing at least the second hetero semiconductor region formed at the bottom of the trench by anisotropic etching to form a sidewall-like second hetero semiconductor region on the sidewall of the trench; A method for manufacturing a semiconductor device, comprising: In a method of manufacturing a field effect transistor semiconductor device having a heterojunction,
A first step of forming a first hetero semiconductor region on a semiconductor substrate;
A second step of selectively removing the first hetero semiconductor region and forming a groove whose bottom portion serves as a junction interface between the semiconductor substrate and the first hetero semiconductor region;
A third step of forming a second hetero semiconductor region over the entire first main surface side of the semiconductor substrate;
A fourth step of selectively removing at least the second hetero semiconductor region formed at the bottom of the groove by anisotropic etching to form a sidewall-like second hetero semiconductor region on the side wall of the groove; A method for manufacturing a semiconductor device, comprising: In a method of manufacturing a field effect transistor semiconductor device having a heterojunction,
A first step of forming a first hetero semiconductor region on a semiconductor substrate;
A second step of selectively removing the first hetero semiconductor region and the semiconductor substrate, and forming a groove having a bottom portion extending into the semiconductor substrate;
A third step of forming a second hetero semiconductor region over the entire first main surface side of the semiconductor substrate;
A fourth step of selectively removing at least the second hetero semiconductor region formed at the bottom of the groove by anisotropic etching to form a sidewall-like second hetero semiconductor region on the side wall of the groove; A method for manufacturing a semiconductor device, comprising: The semiconductor substrate and a second hetero semiconductor region formed on a side wall of the groove are of a first conductivity type, and a part of the first hetero semiconductor region is of a second conductivity type. Item 11. The method for manufacturing a semiconductor device according to any one of Items 7 to 10.

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