JP2007251543A - DISPLAY CONTROL DEVICE, ITS CONTROL METHOD, INFORMATION REPRODUCTION DEVICE, AND ELECTRONIC DEVICE - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a display control device capable of reducing the capacity of a buffer provided before input to a decoder, a control method therefor, an information reproducing device and an electronic device.
A display control apparatus 10 refers to image data in first to Nth reference frame buffers REF1 to REFN for storing image data for which a display time is set, and first to Nth reference frame buffers. A decoder 20 that performs decoding processing, an image data transfer instruction unit 42 that instructs to transfer image data, and an image data transfer control unit that performs control to transfer the image data of the first to Nth reference frame buffers to the display unit 44. The image data transfer instruction unit 42 instructs to transfer image data whose display time has arrived, and when the decoding process for the image data of the current frame is completed and the first to Nth reference frame buffers are full, An instruction to transfer the oldest image data in the first to Nth reference frame buffers is issued.
[Selection] Figure 1

Description

  The present invention relates to a display control device, a control method therefor, an information reproduction device, and an electronic apparatus.

  In terrestrial digital broadcasting that appears in place of analog terrestrial broadcasting, there are expectations for the provision of various new services in addition to improving the quality of images and audio. One of the services newly provided by the introduction of terrestrial digital broadcasting is so-called “one-segment broadcasting” as a service for mobile terminals. In “1-segment broadcasting”, digital modulated waves modulated by the QPSK (Quadrature Phase Shift Keying) modulation method are multiplexed by the OFDM (Orthogonal Frequency Division Multiplexing) modulation method, so that stable broadcast reception is possible even when the mobile terminal is moving. Is possible.

An example of such a mobile terminal is a mobile phone. When a reception function of “1-segment broadcasting” is added to a cellular phone, a separation process of a transport stream in which video data and audio data after compression processing are multiplexed and data decoding processing after the separation processing are performed. Then, the video data and audio data of the decoding process are reproduced while being synchronized.
JP 2004-140506 A

  By the way, in “1-segment broadcasting”, a model called a coded picture buffer (hereinafter abbreviated as CPB) for buffering a bit stream is defined before a video decoder that performs video data decoder processing. . The capacity of this CPB is defined according to the level, for example, 125 kilobytes or 150 kilobytes.

  However, when the capacity of CPB is not considered as in Patent Document 1, for example, the capacity of a memory of 125 kilobytes or 150 kilobytes must be secured as the capacity of CPB. For this reason, it is difficult to reduce the cost, reduce the power consumption, and reduce the size of the mobile phone to which the technology of Patent Document 1 is applied. Therefore, it is desirable to reduce the CPB capacity as much as possible without breaking the original decoding process.

  The present invention has been made in view of the technical problems as described above, and an object of the present invention is to provide a display control apparatus capable of reducing the capacity of a buffer provided before being input to a decoder, its control method, and information. To provide a playback device and an electronic device.

In order to solve the above problems, the present invention
Each reference frame buffer stores first to Nth (N is a natural number) reference frame buffers for storing image data for one frame for which a display time is set;
A decoder that performs decoding processing to generate image data of a current frame with reference to image data of at least one frame stored in the first to Nth reference frame buffers;
An image data transfer instruction unit for instructing transfer of image data;
An image data transfer control unit that performs control to transfer image data for one frame from any of the first to Nth reference frame buffers to a display unit based on a transfer instruction from the image data transfer instruction unit. ,
The image data transfer instruction unit
Instructing transfer of image data whose display time has arrived during decoding of the current frame,
When the decoding process for the image data of the current frame is completed and the first to Nth reference frame buffers are full, the image data stored in the first to Nth reference frame buffers is set. The present invention relates to a display control apparatus that issues an instruction to transfer the oldest image data among the image data stored in the first to Nth reference frame buffers regardless of the display time.

  According to the present invention, it is possible to transfer the image data after the decoding process in which the display time is set to the display unit according to the display time, and the first to Nth references even though the decoding process by the decoder is completed. Since all the frame buffers are full, it is possible to avoid a situation in which image data after decoding cannot be stored in the reference frame buffer. Therefore, according to the present invention, the capacity of the so-called CPB arranged before the decoder can be reduced.

In the display control device according to the present invention,
The image data transfer instruction unit
Based on the display time table in which the display time data corresponding to the display time and the storage location of the image data corresponding to the display time data are stored for each image data, the transfer instruction of the image data can be performed. .

  According to the present invention, whether or not image data transfer control is possible can be determined based on whether or not the display time is represented by the display time data set in the display time table. For this reason, for example, even when the time interval at which an image is generated differs from frame to frame, the management of the image of each frame is facilitated, and the flexibility of display control such as changing the display interval time is improved. Will be able to. In addition, it is not necessary to buffer a large number of images unnecessarily, and it is possible to contribute to cost reduction of a device to which the display control device is applied.

In the display control device according to the present invention,
Includes a timer part that generates an interrupt at a set time,
The image data transfer instruction unit
After the display time data is set in the timer unit, when an interrupt from the timer unit is received, the transfer instruction can be issued to the image data transfer control unit.

In the display control device according to the present invention,
Includes a timer section that keeps time,
The image data transfer instruction unit
After setting the display time data in the timer unit, the timer unit is polled to determine whether or not the display time represented by the display time data has elapsed, and the time of the timer unit has passed the display time When it is determined that the transfer has been performed, the transfer instruction can be issued to the image data transfer control unit.

  According to any one of the above inventions, it is possible to instruct image data transfer at a display time with a simple configuration.

In the display control device according to the present invention,
N may be 3.

  According to the present invention, it is possible to apply the present invention to an apparatus that reproduces “one-segment broadcasting” with a minimum configuration.

The present invention also provides
First to Nth (N is a natural number) reference frame buffer for storing each frame of image data for which a display time is set;
A decoder that performs decoding processing to generate image data of a current frame with reference to image data of at least one frame stored in the first to Nth reference frame buffers;
A display control apparatus control method including an image data transfer control unit that performs control to transfer image data for one frame from any of the first to Nth reference frame buffers to a display unit,
Instructing the image data transfer control unit to transfer image data whose display time has arrived during decoding of the current frame,
When the decoding process for the image data of the current frame is completed and the first to Nth reference frame buffers are full, the image data stored in the first to Nth reference frame buffers is set. Regardless of the display time, the image data transfer control unit is related to the control method of the display control apparatus that instructs the image data transfer control unit to transfer the oldest image data among the image data stored in the first to Nth reference frame buffers. To do.

In the control method of the display control device according to the present invention,
Based on the display time table in which the display time data corresponding to the display time and the storage location of the image data corresponding to the display time data are stored for each image data, the transfer instruction of the image data can be performed. .

  According to any one of the above-described inventions, the image data after the decoding process in which the display time is set can be transferred to the display unit according to the display time, and the first to the first data are obtained despite the completion of the decoding process by the decoder. Since all the Nth reference frame buffers are full, it is possible to avoid a situation in which the decoded image data cannot be stored in the reference frame buffer. Therefore, according to the present invention, the capacity of the so-called CPB arranged before the decoder can be reduced.

The present invention also provides
An information reproducing apparatus for reproducing at least one of video data and audio data,
Transport a first TS (Transport Stream) packet for generating video data, a second TS packet for generating audio data, and a third TS packet other than the first and second TS packets. A separation processing unit for extracting from the stream;
A first storage area for storing the first TS packet; a second storage area for storing the second TS packet; and a third storage area for storing the third TS packet; A memory having a reference frame image data storage area for storing first to Nth (N is a natural number) reference frame image data;
A video decoding process for generating the video data based on the first TS packet read from the first storage area is performed, and the data after the video decoding process is used as the first to Nth reference frame image data. A video decoder for storing in a reference frame storage area of the memory as one of
An audio decoder for performing audio decoding processing for generating the audio data based on the second TS packet read from the second storage area;
An image data transfer control unit that controls transfer of one of the first to Nth reference frame image data as image data from a reference frame image data storage area of the memory;
The video decoder reads the first TS packet from the first storage area independently of the audio decoder, performs the video decoding process based on the first TS packet,
The audio decoder reads the second TS packet from the second storage area independently of the video decoder, performs the audio decoding process based on the second TS packet,
The image data transfer control unit is
While transferring the image data whose display time has arrived during the decoding process of the current frame,
When the decoding process for the image data of the current frame is completed and all the storage areas in which the first to Nth reference frame image data are stored are full, the first to Nth reference frames Regardless of the display time set in the image data, the present invention relates to an information reproducing apparatus that controls transfer of the oldest image data among the image data stored in the reference frame image data storage area.

In the information reproducing apparatus according to the present invention,
Based on the display time table in which the display time data corresponding to the display time and the storage location of the image data corresponding to the display time data are stored for each image data, the transfer instruction of the image data can be performed. .

  According to any one of the above-described inventions, it is possible to reduce the storage area of the memory functioning as a so-called CPB, and thus it is possible to reduce the cost of the information reproducing apparatus that performs reproduction processing of video data and audio data.

The present invention also provides
An information reproducing apparatus as described above;
The present invention relates to an electronic apparatus including a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

The present invention also provides
Tuner,
The information reproducing apparatus as described above, wherein a transport stream from the tuner is supplied;
The present invention relates to an electronic apparatus including a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

  According to any one of the above-described inventions, it is possible to provide an electronic apparatus to which an information reproducing apparatus for reducing the storage area of a memory functioning as a so-called CPB and performing reproduction processing of video data and audio data is applied.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Display Control Device FIG. 1 is a block diagram showing a configuration example of a display control device according to this embodiment.

  The display control apparatus 10 performs display control of the display unit 50 by controlling transfer of image data generated from stream data including continuous packet data to the display unit 50. Here, the display unit 50 drives, for example, a liquid crystal display (hereinafter abbreviated as LCD) panel (not shown) as an electro-optical device, and a plurality of scanning lines and a plurality of data lines of the LCD panel. Driving circuit (not shown). The driving circuit drives the plurality of data lines of the LCD panel based on the image data while scanning the plurality of scanning lines of the LCD panel. In this case, the display control device 10 transfers the image data to the drive circuit of the display unit 50.

  The stream data input to the display control device 10 is temporarily stored in a coded picture buffer (CPB) 60 and then output in order to maintain a predetermined bit rate. Such stream data includes one or more packet data. Each packet data includes header information and a payload portion. Then, control is performed for causing the display unit 50 to display one or a plurality of image data generated based on the data in the payload portion at a display time specified by the packet data.

  Such a display control apparatus 10 includes a decoder 20, a buffer unit 40, an image data transfer instruction unit 42, and an image data transfer control unit 44.

  The buffer unit 40 includes first to Nth (N is a natural number) reference frame buffers REF1 to REFN. In each of the first to Nth reference frame buffers REF <b> 1 to REFN, image data for one frame after the decoding process by the decoder 20, in which a display time is set, is stored.

  The decoder 20 performs a decoding process on image data extracted from packet data constituting stream data. The decoder 20 refers to at least one frame of image data stored in the first to Nth reference frame buffers REF1 to REFN of the buffer unit 40 and performs a decoding process for generating image data of the current frame. Then, the decoder 20 stores the image data for one frame after the decoding processing in any one of the first to Nth reference frame buffers REF1 to REFN. Such a decoder 20 is, for example, H.264. H.264 / AVC standard compliant decoding processing can be performed. For example, when starting the decoding process, the decoder 20 can temporarily store the image data to be processed in the decoding frame buffer 46 and perform the decoding process using the decoding frame buffer 46 as a work area.

  The image data transfer instruction unit 42 instructs the image data transfer control unit 44 to transfer image data for one frame to the display unit 50. More specifically, the image data transfer instruction unit 42 instructs transfer of image data whose display time has arrived during the decoding process of the current frame. Further, when the decoding process for the image data of the current frame by the decoder 20 is completed and all of the first to Nth reference frame buffers REF1 to REFN are full, the image data transfer instruction unit 42 Regardless of the display time set for the image data stored in each of the reference frame buffers REF1 to REFN of the N reference frame buffers, most of the image data stored in the first to Nth reference frame buffers REF1 to REFN. Instructs transfer of old image data.

  The image data transfer control unit 44 transfers image data for one frame from any one of the first to Nth reference frame buffers REF <b> 1 to REFN to the display unit 50 based on a transfer instruction from the image data transfer instruction unit 42. Control.

  According to the display control device 10 as described above, the image data is transferred to the display unit 50 on the condition that the display time arrives, while the first to N-th items when the decoding process by the decoder 20 is completed. When all of the reference frame buffers REF1 to REFN are full, the image data is transferred from any one of the first to Nth reference frame buffers REF1 to REFN regardless of the display time set for the image data. Data can be forcibly transferred to the display unit 50.

  Generally, when the internal processing of the display control device to which data to be decoded is sequentially input as stream data is stagnated, the capacity of the CPB for buffering the stream data input to the display control device must be increased. Disappear. However, according to the present embodiment, since the first to Nth reference frame buffers REF1 to REFN are all full even though the decoding process by the decoder 20 is completed, the image data after the decoding process is referred to. It is possible to avoid the situation where it cannot be stored in the frame buffer. Therefore, according to the present embodiment, the capacity of CPB can be reduced.

  Here, in “1-segment broadcasting”, H.264 is used. Since H.264 / AVC is employed and the number of reference frames is limited to a maximum of three frames, N is preferably 3. In this way, it is possible to apply to a device that performs “1-segment broadcast” playback or the like with a minimum configuration.

  FIG. 2 is an explanatory diagram showing an example of the operation of the display control apparatus 10 in the present embodiment.

  In FIG. 2, it is assumed that N is 3, image data of each frame is F0, F1, F2, and F3, and F0 is the oldest image data (oldest image data). FIG. 2 schematically shows the buffering status of the decoding frame buffer 46 and the first to third reference frame buffers REF1 to REF3.

  First, it is assumed that the first to third reference frame buffers REF1 to REF3 are all in an empty state as an initial state.

  Here, when decoding of the image data F0 is completed at time T0, the decoded image data F0 is stored in the first reference frame buffer REF1, and the image data F1 of the next frame is stored in the decoding frame buffer 46. Is stored.

  Next, when the decoding of the image data F1 is completed at time T1 after time T0, the image data F0 is transferred to the second reference frame buffer REF2, and the image after decoding processing is performed to the first reference frame buffer REF1. Data F1 is stored, and the image data F2 of the next frame is stored in the decoding frame buffer 46.

  Then, when the display time set in the image data F0 comes at time T10 after the time T1 and before the decoding processing of the image data F2 is completed, the image data transfer instruction unit 42 receives the second reference frame buffer. An instruction to transfer the image data F0 stored in REF2 is issued, and the image data transfer control unit 44 controls to transfer the image data F0 to the display unit 50. As a result, the second reference frame buffer REF2 becomes empty.

  Thereafter, when the decoding of the image data F2 is completed at time T2, the image data F1 is transferred to the second reference frame buffer REF2, and the decoded image data F2 is stored in the first reference frame buffer REF1. The decoding frame buffer 46 stores the image data F3 of the next frame.

  As described above, the image data transfer instruction unit 42 can instruct transfer of the image data F0 whose display time has arrived during the decoding process of the image data F2.

  FIG. 3 is an explanatory diagram of another example of the operation of the display control apparatus 10 in the present embodiment.

  Also in FIG. 3, it is assumed that N is 3, image data of each frame is F0, F1, F2, F3, and F4, and F0 is the oldest image data (oldest image data). FIG. 3 schematically shows the buffering status of the decoding frame buffer 46 and the first to third reference frame buffers REF1 to REF3.

  First, it is assumed that the first to third reference frame buffers REF1 to REF3 are all in an empty state as an initial state.

  Here, when the decoding of the image data F0 is completed at time T20, the decoded image data F0 is stored in the first reference frame buffer REF1, and the image data F1 of the next frame is stored in the decoding frame buffer 46. Is stored.

  Next, when decoding of the image data F1 is completed at time T21 after time T20, the image data F0 is transferred to the second reference frame buffer REF2, and the image after decoding processing is performed to the first reference frame buffer REF1. Data F1 is stored, and the image data F2 of the next frame is stored in the decoding frame buffer 46.

  Further, when decoding of the image data F2 is completed at time T22 after time T21, the image data F0 is transferred to the third reference frame buffer REF3, and the image data F1 is transferred to the second reference frame buffer REF2. The decoded image data F2 is stored in the first reference frame buffer REF1, and the image data F3 of the next frame is stored in the decoding frame buffer 46.

  Assume that the decoding of the image data F3 is completed at time T23 after time T22. At this time, since the first to third reference frame buffers REF1 to REF3 are all full, the image data transfer instructing unit 42 receives the image data F2 stored in the first to third reference frame buffers REF1 to REF3. Regardless of the display time set in F1, F0, F1 instructs transfer of the oldest image data F0 among the image data F2, F1, F0 stored in the first to third reference frame buffers REF1-REF3.

  Subsequently, the image data F1 is transferred to the third reference frame buffer REF3, the image data F2 is transferred to the second reference frame buffer REF2, the image data F1 is transferred to the first reference frame buffer REF1, The decoding frame buffer 46 stores the image data F4 of the next frame.

  Thereafter, even when the display time set in the image data F0 comes at time T30 after time T23, the transfer instruction of the image data F0 is no longer performed.

  Thus, the image data transfer instruction unit 42 completes the first to third reference frame buffers REF1 to REF3 when the decoding process for the image data F3 is completed and the first to third reference frame buffers are full. Regardless of the display time set for the image data stored in, the transfer instruction of the oldest image data stored in the first to third reference frame buffers REF1 to REF3 can be issued.

  Such a display control device 10 is based on a display time table in which display time data corresponding to a display time and a storage destination of image data corresponding to the display time data are stored for each image data. It is desirable to give a transfer instruction.

  Therefore, the display control device 10 can further include a header analysis unit 48. The header analysis unit 48 detects display time information included in header information of packet data constituting stream data. Then, the image data transfer instruction unit 42 refers to the display time table obtained by tabulating the display time data, which is obtained using at least the display time information detected by the header analysis unit 48, and instructs the image data transfer for each frame. I do.

  FIG. 4 is an explanatory diagram of a display time table in the present embodiment.

  In the display time table in the present embodiment, display time data is set in units of frames in order from the table number “0”. For example, the frame number, display time data, and reference frame buffer address are set corresponding to the table number.

  The display time data is obtained based on the display time information of the header information of the packet data, or is obtained based on the display time information and the payload portion of the packet data. Then, an EOT (End Of Table) code which is a predetermined end code is set as the display time data of the last table number of the display time table. When referring to the display time data in the display time table in order, it is determined whether or not all the display time data in the display time table has been read out by determining whether or not the display time data is an EOT code. Can be done.

  When the decoded image data is stored in any of the first to Nth reference frame buffers REF1 to REFN, the display time table includes a head of the reference frame buffer serving as the storage destination of the image data. An address is set corresponding to the display time of the image data. Therefore, the image data transfer instruction unit 42 can easily implement an image data transfer instruction to the image data transfer control unit 44 by referring to the display time table.

  The display time data corresponding to the table number set in the display time table and the address of the reference frame buffer are specified by the display pointer DisP. By incrementing the display pointer DisP every time an image data transfer instruction is given, the image data transfer instruction can be given in order of display time.

  By configuring the display control device 10 as described above and generating a display time table, an image is displayed depending on whether or not the display time (reproduction time) is represented by the display time data set in the display time table. Whether or not data transfer control is possible can be determined. For this reason, for example, even when the time interval at which an image is generated differs from frame to frame, the management of the image of each frame is facilitated, and the flexibility of display control such as changing the display interval time is improved. Will be able to. In addition, it is not necessary to buffer a lot of images unnecessarily, and it is possible to contribute to the cost reduction of a device to which the display control device 10 is applied.

  Further, in FIG. 1, the display control device 10 can further include a timer unit 70. The timer unit 70 generates an interrupt at the time set by the image data transfer instruction unit 42. Then, the image data transfer instruction unit 42 sets one of the display time data of the display time table in the timer unit 70, and then receives the interrupt from the timer unit 70 as a condition. An image data transfer instruction can be issued.

  Next, the main part of the display control apparatus 10 in the present embodiment will be described.

1.1 Decoder FIG. 5 shows a block diagram of a configuration example of the decoder 20 of FIG.

  In FIG. 5, the same parts as those in FIG.

  The decoder 20 includes a context adaptive variable length coding (Context-Adaptive Variable Length Coding) (hereinafter abbreviated as CAVLC) unit 22, an inverse quantization unit 24, and an inverse discrete cosine transform (hereinafter abbreviated as DCT). A calculation unit 26, an addition unit 28, a deblocking filter 30, a motion compensation unit 32, a motion prediction unit 34, and a parameter analysis unit 36 are included. The motion prediction unit 34 includes an intra-screen prediction unit 37 and a weighted prediction unit 38.

  The CAVLC unit 22 performs a process of decoding the bitstream encoded by the entropy encoding method. That is, the CAVLC unit 22 performs a CAVLC calculation process for decoding data encoded by CAVLC. About this CAVLC calculation, for example, the well-known H.264. The detailed description is omitted because it is defined by H.264 / AVC.

  The inverse quantization unit 24 performs inverse quantization on the data decoded by the CAVLC unit 22. Thereafter, the inverse DCT operation unit 26 performs an inverse DCT operation on the inversely quantized data. The adder 28 adds the output of the inverse DCT calculator 26 and the output of the motion predictor 34 to generate image data after motion prediction and motion compensation. The deblocking filter 30 performs processing for reducing block noise in the image generated by the adding unit 28. The output of the deblocking filter 30 is stored as output image data of the decoder 20 in any of the first to Nth reference frame buffers REF <b> 1 to REFN of the buffer unit 40.

  On the other hand, the parameter analysis unit 36 analyzes the header information of the bit stream, extracts parameters necessary for the intra-screen prediction process performed in the intra-screen prediction unit 37, and performs the weighted prediction performed in the weighted prediction unit 38. Extract parameters required for processing.

  The parameter analysis unit 36 that analyzes the header information of the bit stream can determine whether to perform intra prediction or inter frame prediction. When performing intra prediction, the intra prediction unit 37 of the motion prediction unit 34 performs a known intra prediction process within the frame based on the output result of the addition unit 28. When performing inter-frame prediction, the weighted prediction unit 38 of the motion prediction unit 34 uses the image data after motion compensation of the motion compensation unit 32 to perform H.264 prediction. A known weighted prediction defined in the H.264 / AVC standard is performed.

  The motion compensation unit 32 is a reference frame buffer designated as a result of the analysis of the parameter analysis unit 36 from the image data of one or more reference frames stored in the first to Nth reference frame buffers REF1 to REFN. Using one or more image data. A known motion compensation process defined by the H.264 / AVC standard is performed.

  The data subjected to motion prediction or motion compensation in this way is added to the data after the inverse DCT calculation in the adding unit 28.

  When such decoding processing is completed and the decoded image data is stored in any of the first to Nth reference frame buffers REF1 to REFN of the buffer unit 40, the decoder 20 is located outside or inside the decoder 20. A provided decode completion flag (not shown) is set. This decoding completion flag is reset when the decoding completion flag is accessed.

  Each part of the decoder 20 performs a decoding process using the decoding frame buffer 46 as a work area.

1.2 Normal Image Data Transfer Control In this embodiment, the timer unit 70 is used to recognize the arrival of the display time. When the arrival of the display time is recognized, the image data transfer instruction unit 42 instructs the image data transfer control unit 44 to transfer image data.

  FIG. 6 shows a block diagram of a configuration example of the timer unit 70 of FIG.

  The timer unit 70 can include a display time setting register 72, a counter 74, a comparator 76, and an interrupt generation unit 78. In the display time setting register 72, one of the display time data of the display time table is set from the image data transfer instruction unit. The counter 74 counts the count number of a given reference clock and outputs the count value to the comparator 76 as a count value. The comparator 76 compares the count value of the counter 74 with the set value of the display time setting register 72, and outputs a coincidence detection pulse to the interrupt generator 78 when the two values match. The interrupt generator 78 outputs an interrupt signal when the coincidence detection pulse is input. This interrupt signal is input to the image data transfer instruction unit 42.

  Then, the image data transfer instruction unit 42 instructs the image data transfer control unit 44 to transfer image data on condition that the interrupt from the timer unit 70 has been received. Thereafter, the image data transfer instruction unit 42 sets the next display time data of the display time table in the display time setting register 72 of the timer unit 70, and waits for reception of the next interrupt signal.

  FIG. 7 shows a flowchart of a processing example of the image data transfer instruction unit 42.

  For example, the display control device 10 has a central processing unit (CPU) and a memory (not shown), and a CPU that executes processing according to a program stored in the memory has the function of the image data transfer instruction unit 42. Can be realized. At this time, the flow of FIG. 7 can be executed as an interrupt handler when an interrupt signal from the timer unit 70 is received.

  First, the image data transfer instruction unit 42 (CPU not shown) determines whether or not the decoding completion flag set by the decoder 20 is on (set state) (step S100). When it is determined that the decode completion flag is on (step S100: Y), the image data transfer instruction unit 42 sets the address of the reference frame buffer in which the image data of the frame number indicated by the display pointer DisP is stored. A transfer command is issued to the image data transfer control unit 44 to instruct image data transfer (step S101).

  Thereafter, the image data transfer instruction unit 42 increments the display pointer DisP that designates the table number of the display time table, and designates the next display time data (step S102). Then, the display time data of the table number pointed to by the display pointer DisP incremented in step S102 is set in the display time setting register 72 of the timer unit 70 (step S103), and the series of processing ends (end).

  On the other hand, when it is determined in step S100 that the decode completion flag is not on (step S100: N), the image data transfer instruction unit 42 sets a predetermined timer value to the timer unit in order to wait for reception of the next interrupt signal. 70 is set in the display time setting register 72 (step S104), and a series of processing ends (end).

  In this way, the image data transfer instruction unit 42 can issue an image data transfer instruction according to the display time table tabulated in the display time table.

  6 and 7, the image data transfer instruction unit 42 recognizes the arrival of the display time by the interrupt notification from the timer unit 70, but the present invention is not limited to this. For example, the image data transfer instruction unit 42 may poll the timer unit 70 to recognize the arrival of the display time.

  FIG. 8 shows a block diagram of another configuration example of the timer unit 70 of the present embodiment.

  In FIG. 8, the same parts as those of FIG. 8 is different from FIG. 6 in that a data register 79 is provided in place of the interrupt generation unit 78.

  That is, the comparator 76 compares the count value of the counter 74 with the set value of the display time setting register 72 and outputs a coincidence detection pulse to the data register 79 when the two values match. The data register 79 sets a display time arrival flag by the coincidence detection pulse from the comparator 76. The display time arrival flag is reset when display time data is set in the display time setting register 72 or when read access to the data register 79 is performed.

  Then, the image data transfer instructing unit 42 notifies the image data transfer control unit 44 on condition that, as a result of polling the timer unit 70, it is detected that the display time arrival flag of the data register 79 is set. Instructs transfer of image data. Thereafter, the image data transfer instruction unit 42 sets the next display time data in the display time table in the display time setting register 72 of the timer unit 70, and performs the next polling operation.

  That is, the timer unit 70 measures time. Then, after the image data transfer instruction unit 42 sets one of the display time data in the display time table in the timer unit 70, the timer unit 70 is polled to display the display time represented by the display time data in the display time table. Whether or not the time has elapsed is determined, and the image data transfer control unit 44 is instructed to transfer image data on the condition that the time of the timer unit 70 has been determined to have passed the display time.

1.3 Forcible Image Data Transfer Control In this embodiment, when all of the first to Nth reference frame buffers REF1 to REFN are full and the decoding process of the decoder 20 is completed, the image data transfer instruction unit 42 However, it instructs to transfer the image data stored in the first to Nth reference frame buffers REF1 to REFN to the display unit 50 regardless of the display time set for the image data.

  FIG. 9 shows a flowchart of a processing example of forced image data transfer control performed by the image data transfer instruction unit 42.

  For example, the display control apparatus 10 has a CPU and a memory (not shown), and a CPU that executes processing according to a program stored in the memory realizes the function of the image data transfer instruction unit 42 and executes the processing shown in FIG. can do. In FIG. 9, it is assumed that N is 3.

  Here, the image data transfer instruction unit 42 uses a decode pointer DecP that specifies a frame number of image data to be decoded in the decoder 20.

  First, the image data transfer instruction unit 42 (a CPU (not shown)) monitors whether the decoding completion flag set by the decoder 20 is on (set state) (step S120: N). When it is determined that the decode completion flag is on (step S120: Y), the image data transfer instruction unit 42 sets the address of the reference frame buffer in which the image data of the frame number indicated by the decode pointer DecP is stored. Then, it is set in the display time table (step S121). As a result, the address of the reference frame buffer in the display time table shown in FIG. 4 is set.

  Next, the image data transfer instruction unit 42 determines the difference between the frame number (F (DisP) specified by the display pointer DisP and the frame number F (DecP) specified by the decode pointer DecP (for example, | F (DisP) −F It is determined whether (DecP) |) is equal to or greater than 3 (= N), which is the number of frames that can be stored in the reference frame buffer (step S122), whereby the first to third reference frame buffers REF1 to REF1. It is determined whether or not all of REF3 are full.

  If it is determined in step S122 that | F (DisP) −F (DecP) | is 3 or more (step S122: Y), the image data transfer instruction unit 42 transfers the frame image data indicated by the display pointer DisP. An instruction is given (step S123), and the display pointer DisP is incremented (step S124).

  After step S124 or when it is determined in step S122 that | F (DisP) -F (DecP) | is not 3 or more (step S122: N), the decode pointer DecP is incremented (step S125), End the processing of (end).

  As described above, when all of the first to Nth reference frame buffers REF1 to REFN are full and the decoding process of the decoder 20 is completed, the image data transfer instruction unit 42 performs the first to Nth reference frame buffers. The image data stored in the reference frame buffers REF1 to REFN can be instructed to be transferred to the display unit 50 regardless of the display time set for the image data.

1.4 Display Time Table Generation Processing Next, display time table generation processing in the present embodiment will be described in detail. In the following, it is assumed that the packet data is PES (Packetized Elementary Stream) packet data, and the display time information is PTS (Presentation Time Stamp).

  FIG. 10A and FIG. 10B are explanatory diagrams of PES packets.

  Here, one PES packet is described as including one access unit (AU), which is a data unit on which decoding processing is performed, for example, but one PES packet includes two or more AUs. Also good.

  FIG. 10A shows a configuration example of a PES packet including an IDR (Instantaneous Decoding Refresh) picture, and FIG. 10B shows a configuration example of a PES packet not including an IDR picture. As shown in FIGS. 10A and 10B, the PES packet includes a PES header (PES Header: PESH) (header information in a broad sense) and a payload portion. PESH includes PTS.

  In FIG. 10A, the payload portion includes SPS (Sequence Parameter Set), PPS (Picture Parameter Set), SEI (Supplemental Enhancement Information), bit data portion, and EOS (End Of Sequence). On the other hand, in FIG. 10B, the payload portion includes PPS, SEI, bit data portion, and EOS.

  In the SPS, parameters of the entire sequence with a plurality of consecutive pictures as a unit are set. The SPS includes a VUI (Video Usability Information) parameter as video display information, and a display time control parameter and the like are set. Examples of display time control parameters set in such a VUI include num_units_in_tick, time_scale, and fixed_frame_rate_flag. num_units_in_tick is the number of time units at the clock operating frequency, time_scale is the number of time units per second, and fixed_frame_rate_flag is a flag indicating whether the frame rate is a fixed frame rate or a variable frame rate.

  The PPS is a parameter set for each picture, and is always set for a PES packet packet including an IDR picture.

  The SEI includes a buffering period SEI, a picture timing SEI, a pan scan rectangle SEI, and a filler payload SEI. The AU including the IDR picture is set with the above four types of SEI, and the AU not including the IDR picture is set to the picture timing SEI, Filler payload SEI is set. As a display time control parameter set in the picture timing SEI, there is cpb_removal_delay. cpb_removal_delay corresponds to a delay time until the AU is decoded on the basis of the decoding time for the AU to which the immediately preceding buffering period SEI is given.

  A bit stream for generating image data is set in the bit data portion. For example, image data can be generated by performing decoding processing of this bit stream.

  EOS is a code indicating the end of the sequence.

  Therefore, the display time data can be generated based on the PSH of the PESH, the PTS, the VUI, and the SEI. Then, a display time table is generated according to the flow shown below.

  FIG. 11 shows a flowchart of a display time table generation processing example in the present embodiment.

  For example, the display control apparatus 10 includes a CPU and a memory (not shown), and a CPU that executes processing according to a program stored in the memory can realize the function of the header analysis unit 48 or the image data transfer instruction unit 42. . Then, the CPU functioning as the header analysis unit 48 or the image data transfer instruction unit 42 can generate a display time table according to the following processing.

  First, the header analysis unit 48 or the image data transfer instruction unit 42 (CPU not shown) detects the PTS of PESH from the stream data (step S150). When the PTS of PESH is detected (step S150: Y), the header analysis unit 12 sets display time data corresponding to the PTS together with the frame number at the head of the display time table (step S152). Then, the header analysis unit 48 or the image data transfer instruction unit 42 increments the pointer that specifies the table number of the display time table (step S153), and ends the series of processing (end).

  On the other hand, when the PSH of PESH is not detected in step S150 (step S150: N), the header analysis unit 48 or the image data transfer instruction unit 42 determines whether the fixed_frame_rate_flag of the VUI is 0 (step S154). When it is determined that the fixed_frame_rate_flag is 0 (step S154: Y), the header analysis unit 48 or the image data transfer instruction unit 42 determines that the AU has a variable frame rate, and this AU includes an IDR picture AU (IDR_AU). ) Is determined (step S155).

  When it is determined in step S155 that the AU is IDR_AU (step S155: Y), the header analysis unit 48 or the image data transfer instruction unit 42 displays the display time data CTime that can be set by the 90 kHz counter using the following formula: (Step S156).

CTime = PTS + (Cn × num_units_in_tick / time_scale × 90000) (1)
In equation (1), PTS is the value of the PSH of the PESH, Cn is the value of the cpb_removal_delay set in the n (n is a natural number) AU picture timing SEI included in the PES packet, and num_units_in_tick and time_scale are set to VUI Is the value of the controlled parameter.

  When it is determined in step S155 that the AU is IDR_AU (step S155: Y), the header analysis unit 12 obtains the display time data CTime as shown in the following equation (step S157).

CTime = PTS + (Cn-C1) × num_units_in_tick / time_scale × 90000 (2)
In Expression (2), C1 is the value of cpb_removal_delay set in the picture timing SEI of the first AU included in the PES packet, and Cn (where n is an integer of 2 or more) is the nth included in the PES packet. This is the value of cpb_removal_delay set in the picture timing SEI of the AU.

  Further, when it is determined in step S154 that fixed_frame_rate_flag is 1 (step S154: N), the header analysis unit 12 determines that the frame rate is a fixed frame rate, and displays the display time data CTime as the following equation: Obtained (step S158).

CTime = PTS + (N-1) × num_units_in_tick / time_scale (3)
In Expression (3), N is a parameter indicating that it is the Nth AU included in the PES packet.

  When the display time data CTime is obtained in any one of steps S156, S157, and S158, the header analysis unit 48 or the image data transfer instruction unit 42 sets the display time data CTime together with the frame number in the display time table ( Step S159). After step S159, the process proceeds to step S153, where the header analysis unit 48 or the image data transfer instruction unit 42 increments a pointer that specifies the table number of the display time table (step S153), and ends the series of processing. (End).

  When the stream data is input, the header analysis unit 48 or the image data transfer instruction unit 42 sets the display time data in the display time table for each AU by performing the processing as described above, as shown in FIG. A display time table can be generated. Note that it is desirable to insert an EOT code as an end code by a known process as the display time data of the last table number of the display time table.

2. Information Reproducing Device Next, an information reproducing device to which the display control device in the present embodiment is applied will be described. The information reproducing apparatus according to the present embodiment enables reproduction of terrestrial digital broadcasting. Video data encoded according to the H.264 / AVC standard can be decoded.

2.1 Overview of 1-segment broadcasting In terrestrial digital broadcasting that appears in place of terrestrial analog broadcasting, there are high expectations for the provision of various new services in addition to improving the quality of images and audio.

  FIG. 12 is an explanatory diagram of the concept of digital terrestrial broadcasting segments.

  In digital terrestrial broadcasting, a pre-assigned frequency band is divided into 14 segments, and broadcasting is performed using 13 segments SEG1 to SEG13. The remaining one segment is used as a guard band. Then, one segment SEGm out of 13 segments for broadcasting is allocated to the frequency band of broadcasting for mobile terminals.

  In one-segment broadcasting, a transport stream (Transport Stream: TS) in which video data, audio data, and other data (control data) encoded (compressed) are multiplexed is transmitted. More specifically, a Reed-Solomon error correction code is added to each packet of the TS, and then divided into layers, and convolutional coding and carrier modulation are performed in each layer. After layer synthesis, frequency interleaving and time interleaving are performed, and a pilot signal necessary for the receiving side is added to form an OFDM segment frame. The OFDM segment frame is subjected to inverse Fourier transform operation and transmitted as an OFDM signal.

  FIG. 13 is an explanatory diagram of TS.

  The TS is composed of a plurality of TS packet sequences as shown in FIG. The length of each TS packet is fixed to 188 bytes. Each TS packet has header information called a 4-byte TS header (TS header) added thereto, and includes a PID (Packet Identifier) serving as an identifier of the TS packet. One segment broadcast program is specified by PID.

The TS packet includes an adaptation field, and is embedded with PCR (Program Clock Reference) and dummy data which are time information serving as a reference for synchronous reproduction of video data, audio data, and the like. The payload includes data for generating a PES (Packetized Elementary Stream) packet or section.

  FIG. 14 is an explanatory diagram of PES packets and sections.

  Each of the PES packet and the section is configured by the payload of each TS packet of one or a plurality of TS packets. The PES packet includes a PES header and a payload, and video data, audio data, or caption data is set as ES (Elementary Stream) data in the payload. In the section, program information such as video data set in the PES packet is set.

  Therefore, when a TS is received, first, it is necessary to analyze program information included in the section and specify a PID corresponding to the broadcast program. Then, video data and audio data corresponding to the PID are extracted from the TS, and the extracted video data and audio data are reproduced.

2.2 Mobile terminal A mobile terminal having a 1-segment broadcast reception function requires processing such as packet analysis as described above. That is, such a mobile terminal is required to have a high processing capacity. Therefore, when a one-segment broadcast receiving function is added to a conventional mobile phone as a mobile terminal (electronic device in a broad sense), it is necessary to further add a processor or the like having a high processing capability.

  FIG. 15 shows a block diagram of a configuration example of a mobile phone including a multimedia processing CPU in a comparative example of the present embodiment.

  In this cellular phone 900, the received signal received via the antenna 910 is demodulated, the telephone CPU 920 performs the incoming call processing, and the signal processed by the telephone CPU 920 is modulated and transmitted via the antenna 910. Sent. The telephone CPU 920 can read a program stored in the memory 922 and perform incoming call processing and outgoing call processing.

  When a desired signal is extracted from the received signal received via the antenna 930 via the tuner 940, a TS is generated by using the desired signal as an OFDM signal in the reverse procedure. The multimedia processing CPU 950 analyzes the TS packet from the generated TS, determines the PES packet and the section, and decodes video data and audio data from the TS packet of the desired program. The multimedia processing CPU 950 can read the program stored in the memory 952 and perform the above-described packet analysis processing and decoding processing. The display panel 960 performs display output based on the decoded video data, and the speaker 970 performs audio output based on the decoded audio data.

  In this way, the multimedia processing CPU 950 requires a very high processing capability. In general, a processor having a high processing capability has a high operating frequency and a large circuit scale.

  By the way, considering the bit rate of 1-segment broadcasting, most of the bandwidth is considered to be the bandwidth for video data and audio data, and the bandwidth for data broadcasting itself is narrowed. Accordingly, among the processes that can be realized by the multimedia processing CPU, it is necessary to always operate the multimedia processing CPU even though only the reproduction processing of video data and audio data may be required, resulting in an increase in power consumption. .

  Therefore, in this embodiment, a video decoder that performs video data decoding processing and an audio decoder that performs audio data decoding processing are provided independently, and the decoding processing is performed independently, thereby reducing the processing capability of each. You can adopt things. Furthermore, it is possible to flexibly reduce power consumption by appropriately stopping one of the operations of the video decoder and the audio data.

  Furthermore, since the video decoder and the audio decoder can be operated in parallel, the processing capability of each decoder can be reduced, and lower power consumption and cost can be realized.

  FIG. 16 shows a block diagram of a configuration example of a mobile phone including the information reproducing apparatus in the present embodiment. In FIG. 16, the same parts as those in FIG. 15 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The cellular phone 100 includes a host CPU (host in a broad sense) 110, a RAM (Random Access Memory) 120, a ROM (Read Only Memory) 130, a display driver 140, a DAC (Digital-to-Analog Converter) 150, an image processing IC ( Integrated Circuit) (information reproducing apparatus in a broad sense) 200 can be included. Further, the cellular phone 100 includes antennas 910 and 930, a tuner 940, a display panel 960, and a speaker 970.

  The host CPU 110 has a function of controlling the image processing IC 200 as well as the function of the telephone CPU 920 in FIG. The host CPU 110 reads a program stored in the RAM 120 or the ROM 130, and performs processing of the telephone CPU 920 in FIG. 15 and processing of controlling the image processing IC 200. At this time, the host CPU 110 can use the RAM 120 as a work area.

  The image processing IC 200 receives, from the TS from the tuner 940, a video TS packet (first TS packet) for generating video data and an audio TS packet (second TS packet) for generating audio data. Extract and buffer in a shared memory (not shown). The image processing IC 200 includes a video decoder and an audio decoder (not shown) capable of controlling the operation stop independently of each other. The video decoder and the audio decoder decode the video TS packet and the audio TS packet, respectively. Video data and audio data are generated. The video data and the audio data are supplied to the display driver 140 and the DAC 150, respectively, while being synchronized. The host CPU 110 can instruct the image processing IC 200 to start the video decoding process and the audio decoding process. The host CPU 110 may instruct the image processing IC 200 to start at least one of video decoding processing and audio decoding processing.

  A display driver (driving circuit in a broad sense) 140 drives a display panel (electro-optical device in a broad sense) 960 based on video data. More specifically, the display panel 960 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels, each pixel being specified by each scanning line and each data line. Crystal Display panel can be used. The display driver 140 has a function of a scanning driver that scans a plurality of scanning lines and a function of a data driver that drives a plurality of data lines based on the video data.

  The DAC 150 converts audio data that is a digital signal into an analog signal and supplies the analog signal to the speaker 970. The speaker 970 outputs sound corresponding to the analog signal from the DAC 150.

2.3 Information Reproducing Device FIG. 17 shows a block diagram of a configuration example of the image processing IC 200 of FIG. 16 as the information reproducing device of the present embodiment.

  The image processing IC 200 includes a TS separation unit (separation processing unit) 210, a memory (shared memory) 220, a video decoder 230, and an audio decoder 240. The image processing IC 200 further includes an image data transfer control unit 250, a tuner I / F (Interface) 260, a host I / F 270, a driver I / F 280, and an audio I / F 290.

  The TS separation unit 210 includes a video TS packet (first TS packet) for generating video data, an audio TS packet (second TS packet) for generating audio data, a video TS packet, and audio. Packets other than the TS packet for use (third TS packet) are extracted from the TS. The TS separation unit 210 can extract the first and second TS packets based on the analysis result of the host CPU 110 that analyzes the third TS packet once extracted from the TS.

  The video decoder 230 reads a video TS packet from a storage area dedicated to the video TS packet in the storage area of the memory 220 and performs video decoding processing for generating video data based on the video TS packet.

  The audio decoder 240 reads the audio TS packet from the storage area dedicated to the audio TS packet in the storage area of the memory 220 and performs audio decoding processing for generating audio data based on the audio TS packet.

  The image data transfer control unit 250 performs a rotation process for rotating the orientation of the image represented by the video data read from the memory 220 and a resizing process for reducing or enlarging the size of the image. The data after the rotation processing and the data after the resizing processing are supplied to the driver I / F 280.

  The tuner I / F 260 performs an interface process with the tuner 940. More specifically, the tuner I / F 260 performs control to receive a TS from the tuner 940. Tuner I / F 260 is connected to TS separator 210.

  The host I / F 270 performs interface processing with the host CPU 110. More specifically, the host I / F 270 controls data transmission / reception with the host CPU 110. The host I / F 270 is connected to the TS separator 210, the memory 220, the image data transfer controller 250, and the audio I / F 290.

  The driver I / F 280 reads video data from the memory 220 at a predetermined cycle via the image data transfer control unit 250 and supplies the video data to the display driver 140. The driver I / F 280 performs interface processing for transmitting video data to the display driver 140.

  The audio I / F 290 reads audio data from the memory 220 at a predetermined cycle and supplies the audio data to the DAC 150. The audio I / F 290 performs interface processing for transmitting audio data to the DAC 150.

  In such an image processing IC 200, the TS packet is extracted from the TS from the tuner 940 by the TS separator 210. The TS packet is stored in a pre-allocated storage area of the memory 220 as a shared memory. Then, the video decoder 230 and the audio decoder 240 respectively read out TS packets from dedicated storage areas allocated to the memory 220, generate video data and audio data, and display the synchronized video data and audio data with the display driver 140. And to the DAC 150.

  FIG. 18 is a diagram for explaining the operation of the image processing IC 200 shown in FIG.

  In FIG. 18, the same parts as those in FIG. 17 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  The memory 220 has first to eighth storage areas AR1 to AR8, and each storage area is assigned in advance.

  The first storage area AR1 stores the video TS packet (first TS packet) extracted by the TS separation unit 210 as a storage area dedicated to the video TS packet. The second storage area AR2 stores the voice TS packet (second TS packet) extracted by the TS separation unit 210 as a storage area dedicated to the voice TS packet. In the third storage area AR3, TS packets (third TS packets) excluding video TS packets and audio TS packets among the TS packets extracted by the TS separator 210 are stored.

  The fourth storage area AR4 stores the video ES data generated by the video decoder 230 as a storage area dedicated to the video ES data. The fifth storage area AR5 stores the audio ES data generated by the audio decoder 240 as a storage area dedicated to the audio ES data.

  In the sixth storage area AR6, a TS generated by the host CPU 110 is stored as TSRAW data. TSRAW data is set by the host CPU 110 instead of the TS from the tuner 940. Then, the TS separation unit 210 extracts a video TS packet, an audio TS packet, and other TS packets from the TS set as TSRAW data.

  The seventh storage area AR7 (reference frame image data storage area in a broad sense) stores video data after decoding by the video decoder 230. The video data stored in the seventh storage area AR7 is read by the image data transfer control unit 250 and used for video output by the display panel 960. The eighth storage area AR8 stores the audio data after the decoding process by the audio decoder 240. The audio data stored in the eighth storage area AR8 is provided for audio output by the speaker 970.

  The video decoder 230 includes a header analysis unit 232 and a video decoding processing unit 234. The header analysis unit 232 reads the video TS packet from the first storage area AR1, analyzes the TS header of the video TS packet, generates a PES packet (first PES packet), and then displays the PES header. The deletion process is performed, and the payload portion is stored in the fourth storage area AR4 of the memory 220 as video ES data. The fourth storage area AR4 of the memory 220 functions as a CPB.

  And the header analysis part 232 produces | generates the display time table in this embodiment as mentioned above. Then, the video decoder 230 including the header analysis unit 232 instructs the image data transfer control unit 250 to transfer image data according to the display time table. That is, the video decoder 230 implements the functions of the header analysis unit 48 and the image data transfer instruction unit 42 in the present embodiment.

  The video decoding processing unit 234 reads video ES data from the fourth storage area AR4, Video data generated by performing decoding processing (video decoding processing in a broad sense) according to the H.264 / AVC (Advanced Video Coding) standard is written in the seventh storage area AR7 (reference frame image data storage area). The video decoding processing unit 234 realizes the function of the decoder 20 in the present embodiment. Then, the video decoding processing unit 234 performs video decoding processing for generating video data based on the first TS packet read from the first storage area AR1, and the data after the video decoding processing is first to first data One of the N reference frame image data is stored in the seventh storage area AR7 (reference frame storage area). That is, the seventh storage area AR7 functions as the buffer unit 40 including the first to Nth reference frame buffers REF1 to REFN in the present embodiment.

The audio decoder 240 includes a header deletion processing unit 242 and an audio decoding processing unit 244. The header deletion processing unit 242 reads the audio TS packet from the second storage area AR2, analyzes the TS header of the audio TS packet, generates a PES packet (second PES packet), and then generates the PES header. The payload portion is stored as audio ES data in the fifth storage area AR5 of the memory 220. The audio decoding processing unit 244 reads audio ES data from the fifth storage area AR5, and performs decoding processing (audio decoding processing in a broad sense) in accordance with the MPEG-2 AAC (Advanced Audio Coding) standard.
Is written in the eighth storage area AR8.

  Then, the video decoder 230 reads the video TS packet (first TS packet) from the first storage area AR1, independently of the audio decoder 240, and performs the video decoding process based on the video TS packet. I do. Also, the audio decoder 240 reads the audio TS packet (second TS packet) from the second storage area AR2 independently of the video decoder 230, and performs the above audio decoding process based on the audio TS packet. Do. In this way, the video decoder 230 and the audio decoder 240 can be operated when the video and audio are output in synchronism, while only the video decoder 230 is operated and output when only the video is output. The operation of the decoder 240 can be stopped. When outputting only audio, only the audio decoder 240 can be operated to stop the operation of the video decoder 230.

  The host CPU 110 reads another TS packet (third TS packet) stored in the third storage area AR3, and generates a section from the TS packet. Then, various table information included in the section is analyzed. The host CPU 110 sets the analysis result in a predetermined storage area of the memory 220 and specifies it as control information for the TS separation unit 210. Thereafter, the TS separation unit 210 extracts TS packets from the tuner 940 according to the control information. On the other hand, the host CPU 110 can issue activation commands to the video decoder 230 and the audio decoder 240 separately. The video decoder 230 and the audio decoder 240 independently access the memory 220, read the analysis result of the host CPU 110, and perform a decoding process corresponding to the analysis result.

  In FIG. 18, the TS separation unit 210 can include a timer unit 70. The image data transfer control unit 250 implements the function of the image data transfer control unit 44 in the present embodiment.

2.3.1 Reproduction Operation Next, an operation in the case of reproducing video data or audio data multiplexed on a TS in the image processing IC 200 as an information reproduction apparatus in the present embodiment will be described.

  FIG. 19 shows a flowchart of an operation example of the reproduction processing by the host CPU 110. The host CPU 110 can perform the process shown in FIG. 19 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 performs broadcast reception start processing (step S10). Thereby, video data or audio data of a desired program among a plurality of programs received as a TS can be extracted from the TS. Then, the host CPU 110 activates at least one of the video decoder 230 and the audio decoder 240 of the image processing IC 200.

  Thereafter, the host CPU 110 causes the video decoder 230 and the audio decoder 240 to perform decoding processing when reproducing video and audio. Alternatively, the host CPU 110 stops the operation of the audio decoder 240 and causes the video decoder 230 to perform decoding processing when reproducing only the video. Alternatively, when reproducing only audio, the host CPU 110 stops the operation of the video decoder 230 and causes the audio decoder 240 to perform decoding processing (step S11).

  Next, the host CPU 110 performs broadcast reception end processing (step S12), and ends a series of processing (end). As a result, the host CPU 110 stops the operation of each unit of the image processing IC 200.

2.3.1.1 Broadcast Reception Start Process Next, a process example of the broadcast reception start process shown in FIG. 19 will be described. Here, a case where video and audio are reproduced will be described.

  FIG. 20 shows a flowchart of an operation example of the broadcast reception start process of FIG. The host CPU 110 can perform the process shown in FIG. 20 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 activates the video decoder 230 and the audio decoder 240 of the image processing IC 200 (step S20). Thereafter, the host CPU 110 initializes the tuner 940 and sets given operation information (step S21). Then, the host CPU 110 also initializes the DAC 150 and sets given operation information (step S22).

  Thereafter, the host CPU 110 monitors reception of TS (step S23: N). When reception of the TS is started, in the image processing IC 200, the TS separation unit 210 separates the TS from the TS into the video TS packet, the audio TS packet, and the other TS packets as described above, and the separated TS packet. Is stored in a storage area of a memory 220 provided for exclusive use. For example, the host CPU 110 can detect reception of a TS by an interrupt signal generated on the condition that a TS packet is stored in the third storage area AR3 in the memory 220 of the image processing IC 200. Alternatively, the host CPU 110 can periodically determine whether the TS packet has been written by accessing the third storage area AR3 of the memory 220, thereby determining the reception of the TS.

When reception of a TS is detected in this way (step S23: Y), the host CPU 110 reads a TS packet stored in the third storage area AR3 and generates a section. Then, PSI (Program Specific Information) / SI (Service Information: program arrangement information) included in the section is analyzed (step S24).
This PSI / SI is defined by the MPEG-2 system (ISO / IEC 13818-1).

PSI / SI is NIT (Network Information Table)
And PMT (Program Map Table). The NIT includes, for example, a network identifier for specifying which broadcasting station the TS is from, a service identifier for specifying the PMT, a service type identifier indicating the type of broadcast, and the like. In the PMT, for example, the PID of the video TS packet multiplexed in the TS and the PID of the audio TS packet are set.

  Therefore, the host CPU 110 extracts a service identifier for specifying the PMT from the PSI / SI, and can specify the PID of the received video TS packet and audio TS packet based on the service identifier (step S25). . Then, a predetermined storage in the memory 220 is provided so that the host CPU 110 can refer to the video decoder 230 and the audio decoder 240 for the PID corresponding to the program selected by the user of the mobile terminal or the PID corresponding to the predetermined program. An area (for example, the third storage area AR3) is set (step S26), and a series of processing ends (end).

  In this way, the video decoder 230 and the audio decoder 240 can perform decoding processing on the video TS packet and the audio TS packet while referring to the PID set in the memory 220.

  The host CPU 110 sets information corresponding to, for example, a service identifier for specifying the PMT in the TS separation unit 210 of the image processing IC 200. In this way, the TS separation unit 210 determines a section periodically received at a predetermined time interval, analyzes the PMT corresponding to the service identifier, and identifies the video TS specified by the PMT. Packets and TS packets for voice and other TS packets are extracted and stored in the memory 220.

  FIG. 21 is a diagram for explaining the operation in the broadcast reception start process of the image processing IC 200 shown in FIGS. In FIG. 21, the same parts as those in FIG. 17 or FIG.

  In FIG. 21, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, when TS is input from the tuner 940 (SQ1), the TS separation unit 210 stores a TS packet including PSI / SI in the memory 220 (SQ2). At this time, the TS separation unit 210 can extract the PSI / SI itself of the TS packet and store it in the memory 220. Further, the TS separation unit 210 can extract the NIT from the PSI / SI and store it in the memory 220.

  The host CPU 110 reads PSI / SI, NIT, and PMT (SQ3), analyzes them, and identifies the PID corresponding to the program to be decoded. Then, the host CPU 110 sets information corresponding to the service identifier or PID corresponding to the program to be decoded in the TS separation unit 210 (SQ4). The host CPU 110 also sets the PID in a predetermined storage area of the memory 220 and refers to it during decoding processing by the video decoder 230 and the audio decoder 240.

  The TS separation unit 210 extracts video TS packets and audio TS packets from the TS based on the set PID, and writes them to the first and second storage areas AR1 and AR2, respectively (SQ5).

  Thereafter, the video decoder 230 and the audio decoder 240 activated by the host CPU 110 sequentially read the video TS packet and the audio TS packet from the first and second storage areas AR1 and AR2 (SQ6), and perform video decoding processing and Perform audio decoding.

2.3.1.2 Broadcast Reception End Process Next, an operation example of the broadcast reception end process shown in FIG. 19 will be described. Here, a case where video and audio are reproduced will be described.

  FIG. 22 shows a flowchart of a processing example of the broadcast reception end processing of FIG. The host CPU 110 can perform the process shown in FIG. 22 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 stops the video decoder 230 and the audio decoder 240 of the image processing IC 200 (step S30). For example, the host CPU 110 can issue a control command to the image processing IC 200, and the image processing IC 200 can stop the video decoder 230 and the audio decoder 240 using the decoding result of the control command.

  Thereafter, the host CPU 110 similarly stops the TS separation unit 210 (step S31). Then, the host CPU 110 stops the tuner 940 (step S32).

  FIG. 23 shows an operation explanatory diagram of the broadcast reception end process of the image processing IC 200 of FIGS. 17 and 18. In FIG. 23, the same parts as those in FIG.

  First, the host CPU 110 performs control to stop the operation of the image data transfer control unit 250, and stops the supply of video data to the display driver 140 (SQ10). Next, the host CPU 110 stops the operations of the video decoder 230 and the audio decoder 240 (SQ11), and then stops the operations in the order of the TS separation unit 210 and the tuner 940 (SQ12, SQ13).

2.3.1.3 Reproduction Process Next, an operation example of the video decoder 230 that performs the reproduction process of the video data will be described.

  FIG. 24 shows a flowchart of an operation example of the video decoder 230.

  When the video decoder 230 is activated by the host CPU 110, for example, the video decoder 230 reads the program stored in a predetermined storage area of the memory 220, and can execute the processing shown in FIG. 24 by executing processing corresponding to the program. It is like that. That is, the video decoder 230 includes a CPU (Central Processing Unit), and after initialization processing of the image processing IC 200 (information reproduction device), a program for realizing video decoding processing is read from the outside of the image processing IC 200 to the CPU. Thus, the CPU can realize the video decoding process. Note that at least a part of the processing of the video decoder 230 may be performed by hardware such as a combinational circuit or a logic circuit.

  Note that at least one of the video decoder 230 and the audio decoder 240 includes a CPU, and after initialization processing of the image processing IC 200, a program for realizing each decoding process is read into the CPU from the outside of the image processing IC 200. It may be.

  First, the video decoder 230 determines whether or not the first storage area AR1 provided as the video TS buffer is in an empty state (step S30). When there is no video TS packet to be read from the first storage area AR1, the state becomes empty.

  When it is determined in step S30 that the first storage area AR1 that is the video TS buffer is not empty (step S30: N), the video decoder 230 further includes a fourth storage area provided as a video ES buffer. It is determined whether or not AR4 is full (step S31). When no more video ES data can be stored in the fourth storage area AR4, the full state is entered.

  When it is determined in step S31 that the fourth storage area AR4 that is the video ES buffer is not full (step S31: N), the video decoder 230 reads the video TS packet from the first storage area AR1, It is detected whether or not the PID (designated PID) specified by the host CPU 110 in step S26 of FIG. 20 (step S32).

  In step S32, when it is detected that the PID of the video TS packet is the designated PID (step S32: Y), the video decoder 230 analyzes the TS header and the PES header (step S33), and the video ES data Are stored in a fourth storage area AR4 provided as a video ES buffer (step S34).

  Thereafter, the video decoder 230 updates the read pointer for specifying the read address of the first storage area AR1, which is a video TS buffer (step S35), and returns to step S30 (return).

  When it is detected in step S32 that the PID of the video TS packet is not the designated PID (step S32: N), the process proceeds to step S35. When it is determined in step S30 that the first storage area AR1 that is the video TS buffer is in an empty state (step S30: Y), or in step S31, the fourth storage area AR4 that is the video ES buffer. Is determined to be full (step S31: Y), the process returns to step S30 (return).

  The video ES data stored in the fourth storage area AR4 in this way is sent to the H.264 by the video decoder 230. A decoding process according to the H.264 / AVC standard is performed and written as video data in the seventh storage area AR7 (see FIG. 18).

  FIG. 25 is a diagram for explaining the operation of the video decoder of the image processing IC 200 shown in FIGS. In FIG. 25, the same parts as those in FIG.

  In FIG. 25, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, as shown in FIG. 20, the host CPU 110 sets the PID corresponding to the program to be decoded in the TS separator 210 (SQ20). When a TS is input from the tuner 940 (SQ21), the TS separation unit 210 separates the video TS packet, audio TS packet, and other TS packets from the TS from the tuner 940 (SQ22). The video TS packet separated by the TS separation unit 210 is stored in the first storage area AR1. The audio TS packet separated by the TS separation unit 210 is stored in the second storage area AR2. TS packets other than the video TS packet and audio TS packet separated by the TS separation unit 210 are stored in the third storage area AR3 as PSI / SI. At this time, the TS separation unit 210 extracts NIT and PMT in the PSI / SI and stores them in the third storage area AR3.

  Next, the video decoder 230 activated by the host CPU 110 reads the video TS packet from the first storage area AR1 (SQ23), generates video ES data, and stores the video ES data in the fourth storage area AR4. (SQ24).

  After that, the video decoder 230 reads the video ES data from the fourth storage area AR4 (SQ25). The decoding process according to the H.264 / AVC standard is performed. In FIG. 25, the decoded video data is directly supplied to the image data transfer control unit 250 (SQ26). For example, the decoded video data is temporarily written back to a predetermined storage area of the memory 220, Thereafter, it is desirable to supply the image data transfer control unit 250 while synchronizing with the output timing of the audio data.

  The display driver 140 drives the display panel based on the video data thus supplied to the image data transfer control unit 250 (SQ27).

  Next, an operation example of the audio decoder 240 that performs audio data reproduction processing will be described.

  FIG. 26 shows a flowchart of an operation example of the audio decoder 240.

  When the audio decoder 240 is activated by the host CPU 110, for example, the audio decoder 240 reads out a program stored in a predetermined storage area of the memory 220, and can execute the processing shown in FIG. 26 by executing processing corresponding to the program. It is like that. That is, the audio decoder 240 includes a CPU (central processing unit), and after initialization processing of the image processing IC 200 (information reproduction device), a program for realizing audio decoding processing is read into the CPU from outside the image processing IC 200. Thus, the CPU can realize the audio decoding process. Note that at least a part of the processing of the audio decoder 240 may be performed by hardware such as a combinational circuit or a logic circuit.

  First, the audio decoder 240 determines whether or not the second storage area AR2 provided as the audio TS buffer is in an empty state (step S40). When there is no audio TS packet to be read from the second storage area AR2, the state becomes empty.

  When it is determined in step S40 that the second storage area AR2 that is the audio TS buffer is not empty (step S40: N), the audio decoder 240 further includes a fifth storage area provided as an audio ES buffer. It is determined whether or not AR5 is full (step S41). When no more audio ES data can be stored in the fifth storage area AR5, the full state is entered.

  When it is determined in step S41 that the fifth storage area AR5, which is the audio ES buffer, is not full (step S41: N), the audio decoder 240 reads the audio TS packet from the second storage area AR2, It is detected whether or not the PID (specified PID) specified by the host CPU 110 in step S26 of FIG. 20 (step S42).

  When it is detected in step S42 that the PID of the audio TS packet is the designated PID (step S42: Y), the audio decoder 240 analyzes the TS header and the PES header (step S43), and the audio ES data Are stored in a fifth storage area AR5 provided as an audio ES buffer (step S34).

  Thereafter, the audio decoder 240 updates the read pointer for specifying the read address of the second storage area AR2 which is the audio TS buffer (step S45), and returns to step S40 (return).

  In step S42, when it is detected that the PID of the voice TS packet is not the designated PID (step S42: N), the process proceeds to step S45. When it is determined in step S40 that the second storage area AR2 that is the audio TS buffer is in an empty state (step S40: Y), or in step S41, the fifth storage area AR5 that is the audio ES buffer. Is determined to be full (step S41: Y), the process returns to step S40 (return).

  The audio ES data stored in the fifth storage area AR5 in this way is decoded by the audio decoder 240 in accordance with the MPEG-2 AAC standard, and is used as audio data in the eighth storage area AR8 (see FIG. 18). ).

  FIG. 27 is a diagram for explaining the operation of the audio decoder of the image processing IC 200 shown in FIGS. In FIG. 27, the same portions as those in FIG. 21 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 27, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, as shown in FIG. 20, the host CPU 110 sets the PID corresponding to the program to be decoded in the TS separator 210 (SQ30). When a TS is input from the tuner 940 (SQ31), the TS separation unit 210 separates the video TS packet, the audio TS packet, and the other TS packets from the TS from the tuner 940 (SQ32). The video TS packet separated by the TS separation unit 210 is stored in the first storage area AR1. The audio TS packet separated by the TS separation unit 210 is stored in the second storage area AR2. TS packets other than the video TS packet and audio TS packet separated by the TS separation unit 210 are stored in the third storage area AR3 as PSI / SI. Furthermore, the TS separation unit 210 can extract NIT and PMT in the PSI / SI and write them in a predetermined storage area of the third storage area AR3.

  Next, the audio decoder 240 activated by the host CPU 110 reads the audio TS packet from the second storage area AR2 (SQ33), generates audio ES data, and stores the audio ES data in the fifth storage area AR5. (SQ34).

  Thereafter, the audio decoder 240 reads audio ES data from the fifth storage area AR5 (SQ35), and performs a decoding process according to the MPEG-2 AAC standard. In FIG. 27, the decoded audio data is directly supplied to the DAC 150 (SQ36). For example, the decoded audio data is temporarily written back to a predetermined storage area of the memory 220, and then the video data It is desirable to supply to the DAC 150 in synchronization with the output timing.

  The operation of the audio decoder 240 as described above is performed independently of the operation of the video decoder 230.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. In the above embodiment or its modification, an example applicable to terrestrial digital broadcasting has been described. However, the present invention is not limited to one applicable to terrestrial digital broadcasting.

  In the present embodiment, mainly H.264 is used. Although the case where the present invention is applied to decoding processing conforming to H.264 / AVC has been described, the present invention is not limited to this, and other standards, It goes without saying that the present invention can be applied to decoding processing based on a standard developed from the H.264 / AVC standard.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The block diagram of the structural example of the display control apparatus in this embodiment. Explanatory drawing of an example of operation | movement of the display control apparatus in this embodiment. Explanatory drawing of the other example of operation | movement of the display control apparatus in this embodiment. Explanatory drawing of the display time table in this embodiment. FIG. 2 is a block diagram of a configuration example of a decoder in FIG. 1. The block diagram of the structural example of the timer part of FIG. The flowchart of the example of a process of the image data transfer instruction | indication part in this embodiment. The block diagram of the other structural example of the timer part of FIG. FIG. 6 is a flowchart of a processing example of forced image data transfer control performed by an image data transfer instruction unit according to the present embodiment. FIGS. 10A and 10B are explanatory diagrams of PES packets. The flowchart of the example of a production | generation process of the display time table in this embodiment. Explanatory drawing of the concept of the segment of digital terrestrial broadcasting. Explanatory drawing of TS. Explanatory drawing of a PES packet and a section. The block diagram of the structural example of the mobile telephone containing the multimedia processing CPU in the comparative example of this embodiment. The block diagram of the structural example of the mobile telephone containing the information reproducing | regenerating apparatus in this embodiment. The block diagram of the structural example of the image processing IC of FIG. 16 as an information reproduction | regeneration apparatus of this embodiment. FIG. 18 is an operation explanatory diagram of the image processing IC of FIG. The flowchart of the operation example of the reproduction | regeneration processing by host CPU. The flowchart of the operation example of the broadcast reception start process of FIG. FIG. 19 is an operation explanatory diagram of broadcast reception start processing of the image processing IC of FIGS. 17 and 18. The flowchart of the process example of the broadcast reception end process of FIG. Operation | movement explanatory drawing in the broadcast reception end process of the image processing IC of FIG.17 and FIG.18. The flowchart of the operation example of a video decoder. FIG. 19 is an operation explanatory diagram of a video decoder of the image processing IC in FIGS. 17 and 18. The flowchart of the operation example of an audio | voice decoder. FIG. 19 is an operation explanatory diagram of the audio decoder of the image processing IC of FIGS. 17 and 18.

Explanation of symbols

10 display control device, 20 decoder, 22 CAVLC unit, 24 inverse quantization unit,
26 inverse DCT calculation unit, 28 addition unit, 30 deblocking filter,
32 motion compensator, 34 motion predictor, 36 parameter analyzer,
37 intra prediction unit, 38 weighted prediction unit, 40 buffer unit,
42 image data transfer instruction unit, 44, 250 image data transfer control unit,
46 Decoding frame buffer, 48 Header analysis section, 50 Display section,
60 CPB, 70 Timer section, 72 Display time register, 74 Counter,
76 Comparator, 78 Interrupt generator, 79 Status register,
110 host CPU, 200 image processing IC, 210 TS separation unit,
220 memory, 230 video decoder, 232 header analysis unit,
234 video decoding processing unit, 240 audio decoder, 242 header deletion processing unit,
244 audio decoding processing unit, 260 tuner I / F, 270 host I / F,
280 Driver I / F, 290 Audio I / F, 940 Tuner

Claims (11)

Each reference frame buffer stores first to Nth (N is a natural number) reference frame buffers for storing image data for one frame for which a display time is set;
A decoder that performs decoding processing to generate image data of a current frame with reference to image data of at least one frame stored in the first to Nth reference frame buffers;
An image data transfer instruction unit for instructing transfer of image data;
An image data transfer control unit that performs control to transfer image data for one frame from any of the first to Nth reference frame buffers to a display unit based on a transfer instruction from the image data transfer instruction unit. ,
The image data transfer instruction unit
Instructing transfer of image data whose display time has arrived during decoding of the current frame,
When the decoding process for the image data of the current frame is completed and the first to Nth reference frame buffers are full, the image data stored in the first to Nth reference frame buffers is set. A display control apparatus for instructing transfer of the oldest image data among the image data stored in the first to Nth reference frame buffers regardless of a display time. In claim 1,
The image data transfer instruction unit
The display time data corresponding to the display time and the storage location of the image data corresponding to the display time data are instructed to transfer the image data based on a display time table stored for each image data. A display control device. In claim 1 or 2,
Includes a timer part that generates an interrupt at a set time,
The image data transfer instruction unit
A display control apparatus, wherein after the display time data is set in the timer unit, when the interrupt from the timer unit is received, the transfer instruction is given to the image data transfer control unit. In claim 1 or 2,
Includes a timer section that keeps time,
The image data transfer instruction unit
After setting the display time data in the timer unit, the timer unit is polled to determine whether or not the display time represented by the display time data has elapsed, and the time of the timer unit has passed the display time When it is determined that the image data has been transferred, the image data transfer control unit is instructed to transfer the display. In any one of Claims 1 thru | or 4,
A display control apparatus, wherein N is 3. First to Nth (N is a natural number) reference frame buffer for storing each frame of image data for which a display time is set;
A decoder that performs decoding processing to generate image data of a current frame with reference to image data of at least one frame stored in the first to Nth reference frame buffers;
A display control apparatus control method including an image data transfer control unit that performs control to transfer image data for one frame from any of the first to Nth reference frame buffers to a display unit,
Instructing the image data transfer control unit to transfer image data whose display time has arrived during decoding of the current frame,
When the decoding process for the image data of the current frame is completed and the first to Nth reference frame buffers are full, the image data stored in the first to Nth reference frame buffers is set. Regardless of display time, the image data transfer control unit is instructed to transfer the oldest image data among the image data stored in the first to Nth reference frame buffers. Control method. In claim 6,
The display time data corresponding to the display time and the storage location of the image data corresponding to the display time data are instructed to transfer the image data based on a display time table stored for each image data. Display control method. An information reproducing apparatus for reproducing at least one of video data and audio data,
Transport a first TS (Transport Stream) packet for generating video data, a second TS packet for generating audio data, and a third TS packet other than the first and second TS packets. A separation processing unit for extracting from the stream;
A first storage area for storing the first TS packet; a second storage area for storing the second TS packet; and a third storage area for storing the third TS packet; A memory having a reference frame image data storage area for storing first to Nth (N is a natural number) reference frame image data;
A video decoding process for generating the video data based on the first TS packet read from the first storage area is performed, and the data after the video decoding process is used as the first to Nth reference frame image data. A video decoder for storing in a reference frame storage area of the memory as one of
An audio decoder for performing audio decoding processing for generating the audio data based on the second TS packet read from the second storage area;
An image data transfer control unit that controls transfer of one of the first to Nth reference frame image data as image data from a reference frame image data storage area of the memory;
The video decoder reads the first TS packet from the first storage area independently of the audio decoder, performs the video decoding process based on the first TS packet,
The audio decoder reads the second TS packet from the second storage area independently of the video decoder, performs the audio decoding process based on the second TS packet,
The image data transfer control unit is
While transferring the image data whose display time has arrived during the decoding process of the current frame,
When the decoding process for the image data of the current frame is completed and all the storage areas in which the first to Nth reference frame image data are stored are full, the first to Nth reference frames An information reproducing apparatus for performing transfer control of the oldest image data among the image data stored in the reference frame image data storage area regardless of a display time set for the image data. In claim 8,
The display time data corresponding to the display time and the storage location of the image data corresponding to the display time data are instructed to transfer the image data based on a display time table stored for each image data. Information reproducing apparatus. An information reproducing apparatus according to claim 8 or 9,
An electronic apparatus comprising: a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process. Tuner,
The information reproduction apparatus according to claim 8 or 9, wherein a transport stream from the tuner is supplied;
An electronic apparatus comprising: a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

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