JP2007243763A - Decoding device, control method therefor, information reproducing device, and electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a decoder even with a low processing capability for realizing decode processing with a heavy processing load at high speed by cutting waste in its circuit, and to provide a control method thereof and an information reproducing apparatus and an electronic apparatus. <P>SOLUTION: The decoder 40 includes: a sequencer section 50 for applying inverse discrete cosine transform to data obtained by decoding stream data coded by an entropy coding system and then performing dequantization of the resultant and generating image data resulting from motion prediction or motion compensation applied to the data after the inverse discrete cosine transform; and a filter section 60 for applying processing of reducing a block noise to the image data subjected to the motion prediction or motion compensation in the unit of a prescribed data block. Each of the sequence section 50 and the filter section 60 is started so as to be in parallel operations in the unit of a prescribed data block. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a decoding device, a control method thereof, an information reproducing device, and an electronic apparatus.

  MPEG-4 (Moving Picture Experts Group Phase 4) and H.264 are general-purpose encoding methods for moving image data. H.264 / AVC (Advanced Video Coding) is standardized. In particular, H.C. H.264 / AVC uses conventional encoding such as MPEG-4 by reducing the processing unit of motion compensation images, increasing the number of reference frames, devising entropy coding, employing a deblocking filter, and the like. High compression encoding efficiency is achieved compared to the system. Moreover, H.C. H.264 / AVC has been defined as a compression encoding method for moving image data in digital terrestrial broadcasting. H.264 / AVC is becoming even more important.

  This terrestrial digital broadcast is a broadcast performed in place of the conventional terrestrial analog broadcast. Among these broadcasts, there is a so-called “one-segment broadcast” as a service for mobile terminals. In “1-segment broadcasting”, digital modulated waves modulated by the QPSK (Quadrature Phase Shift Keying) modulation method are multiplexed by the OFDM (Orthogonal Frequency Division Multiplexing) modulation method, so that stable broadcast reception is possible even when the mobile terminal is moving. Is possible. Thus, in a battery-powered mobile phone, H. H.264 / AVC processing is required and high processing capability is required. It is essential to realize H.264 / AVC processing with low power consumption.

H. For example, Patent Document 1 discloses a configuration that performs MPEG-2 (Moving Picture Experts Group Phase 2) standard decoding processing, which has a lighter processing load than H.264 / AVC. In this Patent Document 1, MPEG-2 standard decoding processing is performed by a plurality of processors with low processing capacity provided in parallel. In other words, a video signal encoded according to the MPEG-2 standard is separated into a plurality of bit streams, and variable length decoding processing and motion compensation processing are performed on each bit stream, and the processing capability of the processor that realizes each processing Even if it is low, high processing capacity is realized as a whole.
JP-A-8-130745

  However, in Patent Document 1, each block performs decoding processing of each data block in parallel. That is, the data of each data block obtained by dividing the input stream data is distributed in each block, thereby performing a parallel operation. This increases the circuit scale of the decoding system. In particular, since the processing load of the decoding process varies greatly depending on the data content of the data block, when the configuration disclosed in Patent Document 1 is adopted, processing is performed depending on the type of data content of the data block. In many cases, there is no useless circuit portion.

  The present invention has been made in view of the technical problems as described above. The object of the present invention is to realize a high-speed decoding process with a heavy processing load even with a low processing capability, eliminating waste of circuits. It is an object of the present invention to provide a decoding device, a control method thereof, an information reproducing device, and an electronic apparatus.

In order to solve the above problems, the present invention
A decoding device for decoding stream data,
An image obtained by performing inverse discrete cosine transform on data that has been subjected to inverse quantization after decoding stream data encoded by the entropy encoding method, and performing motion prediction or motion compensation on the data after the inverse discrete cosine transform A sequencer section for generating data;
A filter unit that performs processing for reducing block noise of the image data subjected to the motion prediction or motion compensation in a predetermined data block unit,
Each of the sequencer unit and the filter unit is related to a decoding device that is activated to operate in parallel in a given data block unit.

In the decoding device according to the present invention,
In the second period following the first period,
The filter unit performs a process of reducing block noise of image data after motion prediction or motion compensation generated by the sequencer unit in the first period,
The sequencer unit performs inverse discrete cosine transform on the data inversely quantized in the first period, and generates image data obtained by performing motion prediction or motion compensation on the data after the inverse discrete cosine transform. Can do.

  According to any one of the above-described inventions, when performing decoding processing of stream data, the sequencer unit and the filter unit are divided so that each unit can be activated. The processing load of the filter unit is particularly heavy, and the sequencer unit processing and filter unit processing can be operated in parallel, so even if the processing capacity of each unit is low, decoding processing with heavy processing load can be performed at high speed. It becomes possible to execute.

In the decoding device according to the present invention,
The sequencer section is
A first operation completion flag set on condition that the motion prediction or motion compensated image data is generated after the sequencer unit is activated;
The filter unit is
A second operation completion flag that is set on the condition that processing for reducing block noise of the image data after motion prediction or motion compensation has been completed after activation of the filter unit;
Each unit of the sequencer unit and the filter unit may be activated based on the monitoring result of the set state of the first and second operation completion flags.

In the decoding device according to the present invention,
When processing the first to third data blocks in order from the first data block,
Inverse quantization for the third data block is completed, and the first operation completion flag from the sequencer unit is set for the second data block, and the first data block The sequencer unit and the filter unit may be activated on condition that the second operation completion flag from the filter unit is set to the data block.

  According to any one of the above-described inventions, parallel operation control can be realized simply by performing a polling operation on the first and second operation completion flags.

In the decoding device according to the present invention,
When starting to operate the sequencer unit and the filter unit in parallel,
The sequencer unit may be activated after the filter unit is activated.

  According to the present invention, even when the sequencer unit is not activated in the decoding process, the operation of the filter unit can be started quickly, which can contribute to the speeding up of the decoding process.

In the decoding device according to the present invention,
The data block is
Of the image generated based on the stream data, it may be data for one macroblock having a given number of pixels in the horizontal direction and a given number of lines in the vertical direction as a unit.

In the decoding device according to the present invention,
The decoding processing control unit that performs inverse quantization after decoding the stream data, the sequencer unit, and the filter unit may be activated to operate in parallel in units of given data blocks.

In the decoding device according to the present invention,
Including a central processing unit,
A program for decoding the stream data and realizing the function of starting the sequencer unit and the filter unit is read, and the stream data encoded by the entropy encoding method is decoded according to the program, and then inverse quantization is performed. While executing the processing, each unit can be activated so that the sequencer unit and the filter unit operate in parallel in a given data block unit.

  According to any one of the above-described inventions, when the decoding process of the stream data is performed, the decoding process control unit, the sequencer unit, and the filter unit are divided so that each unit can be activated. The processing load of the filter unit is particularly heavy, and the sequencer unit processing and filter unit processing can be operated in parallel, so even if the processing capacity of each unit is low, decoding processing with heavy processing load can be performed at high speed. It becomes possible to execute. In particular, since the processing block for accessing the stream data is limited to the decoding processing control unit, the decoding processing control unit can be realized by software processing by a central processing unit having low processing capability.

The present invention also provides
Image data obtained by performing inverse discrete cosine transform on the inversely quantized data after decoding the stream data encoded by the entropy encoding method and performing motion prediction or motion compensation on the data after the inverse discrete cosine transform A sequencer section to generate,
A control method of a decoding device including a filter unit that performs processing for reducing block noise of image data after motion prediction or motion compensation in units of predetermined data blocks,
Among the images generated based on the stream data, the sequencer unit and the filter in units of data of one macroblock having a given number of pixels in the horizontal direction and a given number of lines in the vertical direction as units. The present invention relates to a control method of a decoding device that activates each unit so that the units operate in parallel.

In the decoding device control method according to the present invention,
In the second period following the first period,
The filter unit performs a process of reducing block noise of image data after motion prediction or motion compensation generated by the sequencer unit in the first period,
The sequencer unit may be activated to perform inverse discrete cosine transform on the inversely quantized data and perform motion prediction or motion compensation on the data after the inverse discrete cosine transform in the first period. it can.

In the decoding device control method according to the present invention,
When operating the sequencer unit and the filter unit in parallel,
The sequencer unit may be activated after the filter unit is activated.

In the decoding device control method according to the present invention,
Each of the decoding processing control unit that performs inverse quantization after decoding the stream data, the sequencer unit, and the filter unit can be activated to operate in parallel in units of a given data block.

The present invention also provides
An information reproducing apparatus for reproducing at least one of video data and audio data,
Transport a first TS (Transport Stream) packet for generating video data, a second TS packet for generating audio data, and a third TS packet other than the first and second TS packets. A separation processing unit for extracting from the stream;
A first storage area for storing the first TS packet; a second storage area for storing the second TS packet; and a third storage area for storing the third TS packet; A memory having
The decoding device according to any one of the above, which performs video decoding processing for generating the video data based on the first TS packet read from the first storage area;
An audio decoder that performs audio decoding processing for generating the audio data based on the second TS packet read from the second storage area;
The decoding device reads the first TS packet from the first storage area independently of the audio decoder, performs the video decoding process based on the first TS packet,
Related to an information reproducing apparatus in which the audio decoder reads the second TS packet from the second storage area independently of the video decoder and performs the audio decoding process based on the second TS packet To do.

  ADVANTAGE OF THE INVENTION According to this invention, the information reproducing | regenerating apparatus which implement | achieves a decoding process with a heavy processing load with low power consumption using a processing circuit with low processing capability can be provided.

In the information reproducing apparatus according to the present invention,
When reproducing only the video data of the video data and audio data, stop the operation of the audio decoder,
When only the audio data among the video data and audio data is reproduced, the operation of the decoding device may be stopped.

  According to the present invention, further reduction in power consumption of the information reproducing apparatus can be realized.

The present invention also provides
An information reproducing apparatus as described above;
The present invention relates to an electronic apparatus including a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

The present invention also provides
Tuner,
The information reproducing apparatus as described above, wherein a transport stream from the tuner is supplied;
The present invention relates to an electronic apparatus including a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

  According to any one of the above-described inventions, it is possible to provide an electronic device that can realize the reproduction processing of one-segment broadcasting with heavy processing load with low power consumption.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. The embodiments described below do not unduly limit the contents of the present invention described in the claims. Also, not all of the configurations described below are essential constituent requirements of the present invention.

1. Decoding Device FIG. 1 shows a block diagram of a configuration example of a decoding system in the present embodiment.

  The decoding system 10 includes a decoding processing control unit 20 and a decoding device 40. In the decoding system 10, the decoding process control unit 20 and the decoding device 40 are used to generate an H.264 signal. The stream data encoded according to the H.264 / AVC standard is decoded. Here, the stream data is data encoded by an entropy encoding method.

  In the present embodiment, H is performed on data in units of data blocks corresponding to one macroblock (MB) having a given number of pixels in the horizontal direction and a given number of lines in the vertical direction as units. . The H.264 / AVC standard series of decoding processes are divided into a plurality of processing blocks, and each processing block is operated in parallel. H.264 / AVC standard decoding processing is realized. Therefore, in this embodiment, the decoding process control unit 20 and the decoding device 40 are operated in parallel for each MB.

  The decode processing control unit 20 is configured to transmit the H.264 data. In accordance with the H.264 / AVC standard, stream data encoded by the entropy encoding method is decoded, and then dequantized data is generated. More specifically, the decoding processing control unit 20 includes a context adaptive variable length coding (Context-Adaptive Variable Length Coding: hereinafter abbreviated as CAVLC) unit 22, an inverse quantization unit 24, and a parameter analysis unit 26. And a parallel operation control unit 30. The parameter analysis unit 26 includes an intra parameter analysis unit 27 and an inter parameter analysis unit 28.

  On the other hand, the decoding device 40 includes a sequencer unit 50 and a filter unit 60. The sequencer unit 50 is an H.264. In accordance with the H.264 / AVC standard, data from the decoding processing control unit 20 is subjected to inverse discrete cosine transform (hereinafter abbreviated as DCT), and motion prediction or motion compensation is performed on the data after the inverse discrete cosine transform. Generated image data. The filter unit 60 performs a process of reducing block noise of image data after motion prediction or motion compensation in units of predetermined data blocks. Therefore, the sequencer unit 50 includes an inverse DCT calculation unit 52, an addition unit 53, a motion compensation unit 54, and a motion prediction unit 56. The motion prediction unit 56 includes a weighted prediction unit 57 and an in-screen prediction unit 58. In FIG. 1, the function of the motion compensation unit 54 includes the functions of the addition unit 53 and the motion prediction unit 56 and can be called motion compensation.

  The filter unit 60 includes a deblock filter 62.

  Thus, the data after the block noise reduction is output as the image data of the output image. The image data of the output image is accumulated in the output image buffer 70 of the decoding system 10, and the image data in the output image buffer 70 is used for motion compensation processing and motion prediction processing for generating image data of the next image. .

  In this way, the function of the decoding process control unit 20 and the function of the decoding device 40 are separated from each other. Processing blocks that access stream data encoded according to the H.264 / AVC standard can be limited to the decoding processing control unit 20. This is because when analyzing the contents of stream data, it is necessary to read and process the data in order from the front, so it is desirable that the number of processing blocks for processing stream data is limited to one. As a result, while the decoding processing control unit 20 accesses the stream data, the decoding device 40 provided in the subsequent stage can perform inverse DCT operation or the like on the data of another MB.

  That is, the decoding processing control unit 20 reads out the predetermined data unit from the stream data encoded by the entropy encoding method, calculates the number of bits to be read in order to analyze the read data and analyze the next parameter, The process of accessing the stream data again is repeated to obtain bit data for generating image data, parameters (motion vector information) necessary for motion prediction, and the like. In this way, the decoding device 40 only needs to execute a series of iterative processes for generating image data.

  The processing of the decoding processing control unit 20 in the present embodiment is desirably realized by so-called software. This is because it is necessary to repeatedly read and process the bit stream as described above. This is because CAVLC adopted as an entropy encoding method of the H.264 / AVC standard is realized by a hardware circuit, thereby increasing the circuit scale. Therefore, the decoding process control unit 20 includes a central processing unit (CPU), and implements a process of decoding stream data encoded by the entropy encoding method and performing inverse quantization after decoding. The CPU can implement the processing of the decoding processing control unit 20 described above.

  In the present embodiment, in consideration of the processing time of the decoding processing control unit 20 and the processing time of the decoding device 40, the processing of the sequencer unit 50 and the processing of the filter unit 60 are further operated in parallel in the decoding device 40. That is, paying attention to the heavy processing load of the deblocking filter processing in the filter unit 60, the sequencer unit 50 and the filter unit 60 are activated separately to divide the processing of each unit. As a result, the processing time of the deblocking filter process and the processing time of the sequencer unit 50 can be made substantially the same. Therefore, in the decoding system 10 in the present embodiment, the decoding processing control unit 20, the sequencer unit 50, and the filter unit 60 operate in parallel. The parallel operation is started by the parallel operation control unit 30 of the decode processing control unit 20.

  FIG. 2 is a flowchart showing an outline of the processing flow of the decoding system 10 in this embodiment.

  For example, the decoding process control unit 20 can read a program for executing the process shown in FIG. 2 and realize the process shown in FIG.

  In the decoding system 10, first, the decoding process control unit 20 detects the head of an IDR (Instantaneous Decoding Refresh) block (step S10). The IDR block is a block for decoding without referring to past pictures in order to realize a random access function.

  Next, the decoding process control unit 20 reads out a predetermined data unit from the stream data, performs parameter analysis necessary for the decoding process, and is necessary for extraction of bit data for generating image data, motion prediction, and the like. Parameters (motion vector information) and the like are obtained (step S11).

  Thereafter, the decoding process control unit 20 performs a CAVLC process to decode the stream data encoded by the entropy encoding method (step S12).

  The sequencer unit 50 then performs inverse DCT operation on the data decoded by the decoding process control unit 20 to generate image data that has undergone motion prediction or motion compensation (step S13).

  The image data generated by the sequencer unit 50 is subjected to processing for reducing block noise in the filter unit 60 and is output as image data of an output image (step S14).

  Then, it is determined whether or not it is the final MB obtained by dividing the image (step S15). When it is determined that the image is the final MB (step S15: Y), a series of processing ends, and it is determined that it is not the final MB. When it is done (step S15: N), the process returns to step S11.

  Here, the head detection, parameter analysis, and CAVLC processing of the IDR block are performed by the decoding processing control unit 20. The sequencer process is performed by the sequencer unit 50. The deblocking filter process is performed by the filter unit 60. The decoding process control unit 20 starts the processing of the sequencer unit 50 and the processing of the filter unit 60. More specifically, the decoding process control unit 20 activates the sequencer unit 50 and the filter unit 60 so that the sequencer process and the deblocking filter process operate in parallel with respect to continuous MB data. In this way, H. The decoding process conforming to the H.264 / AVC standard can be executed at high speed.

  FIG. 3 shows a schematic diagram of a bit stream in MB extracted from the stream data. Here, it is assumed that the bit stream data extracted from the stream data is divided into MB units, and MB1 (first data block), MB2 (second data block), MB3 (first data block) in the order of input of each MB. 3 data blocks).

  FIG. 4 shows a timing chart of an operation example of the decoding system in the comparative example of the present embodiment.

  In the arrangement order of MBs as shown in FIG. 3, in the comparative example, first, a processing block that realizes the function of the decoding processing control unit in the present embodiment decodes entropy-encoded data for MB1, and then performs reverse processing. Quantization processing is performed (TG1). After that, the processing block that realizes the function of the sequencer unit in the present embodiment performs inverse discrete cosine transform on the data after inverse quantization performed on the data of MB1, and the data after the inverse discrete cosine transform Image data subjected to motion prediction or motion compensation is generated (TG2). Then, the processing block that realizes the function of the filter unit in the present embodiment performs processing to reduce block noise on the image data after motion prediction or motion compensation performed on the data of MB1 (TG3). .

  When a series of decoding processes for MB1 is completed, the processing block that realizes the function of the decoding process control unit in the present embodiment decodes the entropy-encoded data for MB2, and then reverses the process. Quantization processing is performed (TG4). After that, the processing block that realizes the function of the sequencer unit in the present embodiment performs inverse discrete cosine transform on the data after inverse quantization performed on the data of MB2, and the data after the inverse discrete cosine transform is performed. Image data subjected to motion prediction or motion compensation is generated (TG5). Then, the processing block that realizes the function of the filter unit in the present embodiment performs a process of reducing block noise on the image data after motion prediction or motion compensation performed on the data of MB2 (TG6). . Thereafter, the decoding process is similarly performed in MB units.

  As shown in FIG. 3, processing time PT1 is required for the decoding process for 1 MB data.

  On the other hand, in the present embodiment, decoding processing can be realized by the decoding processing control unit 20, the sequencer unit 50, and the filter unit 60 performing a parallel operation (more specifically, a pipeline operation).

  FIG. 5 shows a timing chart of an operation example of the decoding system in the present embodiment.

  Here, it is assumed that the second period T2 is a period following the first period T1. In the present embodiment, in the second period T2, the filter unit 60 causes block noise of image data (MB1 data in FIG. 5) after motion prediction or motion compensation generated by the sequencer unit 50 in the first period T1. (TG10) is performed. In the second period T2, the sequencer unit 50 performs inverse discrete cosine on the inversely quantized data (MB2 data in FIG. 5) performed in the decoding process control unit 20 in the first period T1. Image data obtained by performing motion prediction or motion compensation is generated on the data that has been transformed and subjected to the inverse discrete cosine transform (TG11).

  Therefore, in the second period T2, the decoding processing control unit 20 generates data that has been subjected to dequantization processing after decoding entropy-encoded data with respect to MB3 data following MB1 and MB2. (TG12).

  As a result, although the processing time of the decoding process for MB1 is not different from that in FIG. 4, the processing time of the decoding process for MB2 and MB3 is greatly reduced. That is, when compared with FIG. 4, high-speed decoding processing can be performed on data having the same number of MBs.

  In addition, the processing of the decoding processing control unit 20 advantageous for software processing is performed by the CPU, and the processing of the sequencer unit 50 and the processing of the filter unit 60 which are other repetitive processing are performed by the hardware circuit. A decoding system that can use a low CPU and suppresses an increase in circuit scale can be provided.

  Hereinafter, processing of each unit of the decoding system 10 in the present embodiment will be described.

1.1 Decoding Process Control Unit The decoding process control unit 20 according to the present embodiment includes a header analysis process for extracting parameters from stream data, and a CAVLC process for decoding data extracted from stream data encoded by the entropy encoding method. Inverse quantization processing is performed.

  FIG. 6 shows a flowchart of an example of the header analysis process performed in the decoding process control unit 20.

  When the stream data is input, the decoding process control unit 20 reads data having a predetermined number of bits from the stream data stored in, for example, a buffer (step S20). The intra parameter analysis unit 27 of the parameter analysis unit 26 determines whether or not the data read in step S20 is an intra parameter, and the inter parameter analysis unit 28 determines that the data read in step S20 is the inter parameter. It is discriminate | determined whether it is (step S21). As a result, when it is determined that the parameter is an intra parameter or an inter parameter (step S21: Y), an intra parameter or an inter parameter is obtained (step S22).

  When it is determined in step S21 that the parameter is not an intra parameter or an inter parameter (step S21: N), or when an intra parameter or an inter parameter is obtained, the bit position of the next parameter is obtained (step S23). This means that parameter types, data sizes, etc. are defined, and stream data must be analyzed in order from the front.

  Thus, when the next bit position is specified, when the header analysis is finished (step S24: Y), a series of processing is finished, and when the header analysis is continued (step S24: N), the process returns to step S20. Then, the next predetermined number of bits of data is read from the stream data.

  For example, in the detection processing of the head of the IDR block in FIG. 2 and the parameter analysis processing after the detection processing, each processing is performed while accessing the stream data as described above.

  When the header analysis as described above is performed, the bit position of the image data to be decoded can be specified, and the decoding process in the CAVLC unit 22 is started.

  FIG. 7 shows a flowchart of an example of processing of the CAVLC unit 22.

  Similar to FIG. 6, the CAVCL unit 22 reads data of a predetermined number of bits from, for example, stream data stored in a buffer (step S30). Then, the CAVLC unit 22 determines whether or not the data read in step S30 is CAVLC data (step S31). Here, the CAVLC data is data encoded by CAVLC.

  When it is determined that the data is CAVLC data (step S31: Y), CAVLC calculation is performed using the parameters obtained by the header analysis of FIG. 6 (step S32), and a series of processing ends (end).

  In step S31, when it is determined that the data is not CAVLC data (step S31: N), the series of processing ends (end).

  FIG. 8A, FIG. 8B, and FIG. 8C are explanatory diagrams of CAVLC calculation.

8A shows quantized DCT coefficient values ED ₁₁ , ED ₁₂ , ED ₁₃ ,..., ED ₄₄ of data blocks for four pixels in the horizontal direction of the image and four lines in the vertical direction of the image. Show. On the encoding side of the stream data, the data is made one-dimensional in the order shown in FIG. 8A, and a data string as shown in FIG. 8B is once generated. Then, stream data is generated by encoding the data sequence shown in FIG. 8B by the entropy encoding method.

  More specifically, encoding is performed by sequentially storing the parameter values shown in FIG. In FIG. 8C, TotalCoeff indicates “the number of non-zero coefficients” of the data string in FIG. TrailingOnes indicates “the number of coefficients having the absolute value 1 that is continuous last” in the data string of FIG. Trailing_ones_sign_flag indicates “the sign of the coefficient having the absolute value 1 that is continuous last” in the data string in FIG. Level indicates the “quantized DCT coefficient value” of the data string in FIG. total_zeros indicates “the number of zero coefficients before the last non-zero coefficient” in FIG. run_before indicates “the number of consecutive 0s before the coefficient value” in FIG.

  By the way, the data decoded by the CAVLC unit 22 as described above is further encoded by a Golomb code. Therefore, the CAVLC unit 22 can further decode the Golomb encoded data.

  9A, 9B, and 9C are explanatory diagrams of Golomb codes.

  The Golomb code is an H.264 code similar to CAVLC. This is an encoding method adopted in the H.264 / AVC standard. As shown in FIG. 9A, the Golomb code includes a prefix (PX) part PX and a suffix (Suffix) part SX with the separator SPR “1” as a boundary. A predetermined number of “0” s are continued in the prefix part PX, and the same number of “0” or “1” as the prefix part PX is entered in the suffix part SX depending on the data to be encoded. Here, the Golomb code shown in FIG. 9A is assigned to a code number according to the table shown in FIG. Furthermore, the code numbers shown in FIG. 9B are assigned to the syntax element values according to the table shown in FIG.

  Then, the CAVLC unit 22 analyzes the parameterized numerical values as shown in FIG. 8C and converts them into a data string shown in FIG. 8B. Then, the CAVLC unit 22 can generate a quantized DCT coefficient value group as shown in FIG. At this time, the CAVLC unit 22 decodes the decoded data based on the Golomb code determined according to the table shown in FIG. 9C and the table shown in FIG. 9B.

  As described above, when the stream data encoded by the entropy encoding method is decoded, the decoded data is input to the inverse quantization unit 24.

  FIG. 10 shows an explanatory diagram of processing of the inverse quantization unit 24.

  The above-mentioned DCT coefficient value is a value obtained by rounding the result obtained by dividing in the quantization step to an integer value. Therefore, the inverse quantization unit 24 generates data to be supplied to the inverse DCT calculation unit 52 by multiplying the DCT coefficient value obtained as a result of the above decoding by a quantization step.

  At this time, it is desirable to obtain the quantization step according to the characteristics shown in FIG. In FIG. 10, when the quantization parameter is shown on the horizontal axis and the quantization step is shown on the vertical axis, the quantization parameter and the quantization step have nonlinearity. More specifically, when a quantization parameter is given as a DCT coefficient value, a quantization step is obtained according to the characteristics shown in FIG. More specifically, the quantization step is derived so that the logarithm of the quantization parameter and the quantization step is proportional.

  Then, data supplied to the inverse DCT calculation unit 52 is generated using the quantization step and the quantization parameter.

1.2 Sequencer Unit As shown in FIG. 1, the sequencer unit 50 includes a start flag SF1 and an operation completion flag EF1 (first operation completion flag). The activation flag SF1 and the operation completion flag EF1 are accessed by the decoding process control unit 20 (parallel operation control unit 30). That is, when the activation flag SF1 is set by the parallel operation control unit 30, the sequencer unit 50 performs the inverse DCT operation on the data in MB units from the decode processing control unit 20, and the data after the inverse DCT operation Image data subjected to motion prediction or motion compensation is generated. Then, when the generation of the image data subjected to motion prediction or motion compensation is completed, the operation completion flag EF1 is set. Accordingly, the operation completion flag EF1 is set on condition that image data after motion prediction or motion compensation is generated after the sequencer unit 50 is started by the parallel operation control unit 30.

  The status of the operation completion flag EF1 is monitored by the parallel operation control unit 30, and the operation completion flag EF1 is reset when the parallel operation control unit 30 reads the status of the operation completion flag EF1.

  In such a sequencer unit 50, when the activation flag SF1 is set, the inverse DCT calculation unit 52 performs the H.264 operation. A known inverse DCT operation defined in the H.264 / AVC standard is performed. At this time, the parameter analysis unit 26 of the decoding process control unit 20 has already finished analyzing the intra parameters or the inter parameters for the MB data. Therefore, the motion prediction unit 56 is designated according to the analysis result of the parameter analysis unit 26 whether to perform intra-frame prediction or inter-frame prediction.

  When performing intra prediction, the intra prediction unit 58 of the motion prediction unit 56 performs known intra prediction processing within the frame based on the output result of the addition unit 53.

  On the other hand, the motion compensation unit 54 uses the reference frame of the frame analyzed by the inter parameter analysis unit 28 out of the plurality of reference frames stored in the output image buffer 70, and outputs the H.264. A known motion compensation process defined by the H.264 / AVC standard is performed. When performing inter-frame prediction based on the analysis result of the parameter analysis unit 26, the weighted prediction unit 57 of the motion prediction unit 56 is A known weighted prediction defined in the H.264 / AVC standard is performed.

  The data subjected to motion prediction or motion compensation in this manner is added to the data after inverse DCT calculation in the adding unit 53. Thereafter, the operation completion flag EF1 is set.

1.3 Filter Unit As shown in FIG. 1, the filter unit 60 includes a start flag SF2 and an operation completion flag EF2 (second operation completion flag). The activation flag SF2 and the operation completion flag EF2 are accessed by the decoding process control unit 20 (parallel operation control unit 30). That is, when the activation flag SF2 is set by the parallel operation control unit 30, the filter unit 60 performs processing (decoding) for reducing block noise of image data subjected to motion prediction or motion compensation in the sequencer unit 50 in units of MB. Block filter processing). When the deblocking filter process is completed, the operation completion flag EF2 is set. Therefore, the operation completion flag EF2 is set on the condition that the processing for reducing the block noise of the image data after motion prediction or motion compensation is completed after the parallel operation control unit 30 starts the filter unit 60.

  The status of the operation completion flag EF2 is monitored by the parallel operation control unit 30, and the operation completion flag EF2 is reset when the parallel operation control unit 30 reads the status of the operation completion flag EF2.

  In such a filter unit 60, when the activation flag SF2 is set, the deblocking filter 62 can perform a process of reducing block noise of at least one of the block boundary and the macroblock boundary. This process is described in H.264. A known deblocking filter process defined in the H.264 / AVC standard can be employed.

  Thus, when the deblock filter processing is completed, the operation completion flag EF2 is set. Note that the data after the deblocking filter processing is output as image data of an output image. This image data is stored in the output image buffer 70.

  By such a deblocking filter process, the decoding process is not performed using the reference image with a lot of block noise, and the propagation of the block noise can be reduced and the image quality of the decoded image can be improved.

1.4 Parallel Operation The processes of the decoding process control unit 20, the sequencer unit 50, and the filter unit 60 described above are controlled in parallel by the parallel operation control unit 30 of the decoding process control unit 20. The function of the parallel operation control unit 30 can also be realized by software processing executed by the CPU that realizes the function of the decoding process control unit 20.

  11 and 12 are flowcharts of processing examples of the parallel operation control unit 30.

  First, the parallel operation control unit 30 polls and monitors the operation completion flags EF1 and EF2 (step S40). When detecting that the operation completion flags EF1 and EF2 have changed, the parallel operation control unit 30 reads and stores the status of the operation completion flag EF1 of the sequencer unit 50 (step S41). Subsequently, the parallel operation control unit 30 reads and stores the status of the operation completion flag EF2 of the filter unit 60 (step S42).

  Then, the parallel operation control unit 30 monitors whether or not the stream data access process of FIG. 6, the CAVLC process of FIG. 7, and the inverse quantization process of FIG. (Step S43). When it is detected that the process up to the inverse quantization process in FIG. 10 is completed in MB units (step S43: Y), the parallel operation control unit 30 determines whether or not the operation completion flag EF1 is “1” (step S43: Y). Step S45). Here, when the operation completion flag EF1 is “1”, this indicates that the processing of the MB in the sequencer unit 50 has been completed, and when the operation completion flag EF1 is “0”, the processing of the MB in the sequencer unit 50 has not been completed. Indicates completion.

  When it is detected in step S43 that the inverse quantization process of FIG. 10 has not been completed in MB units (step S43: N), the parallel operation control unit 30 monitors the timeout again (step S44: N). . And when timeout is detected (step S44: Y), it returns to step S43.

  In step S45, when it is detected that the operation completion flag EF1 is “0” (step S45: N), the parallel operation control unit 30 monitors the timeout again (step S46: N). When a time-out is detected (step S46: Y), the status of the operation completion flag EF1 of the sequencer unit 50 is read and stored as in step S41 (step S47). Thereafter, the process returns to step S45.

  On the other hand, when it is detected in step S45 that the operation completion flag EF1 is “1” (step S45: Y), the parallel operation control unit 30 determines whether or not the operation completion flag EF2 is “1”. It discriminate | determines (step S48). Here, when the operation completion flag EF2 is “1”, it indicates that the processing of the MB in the filter unit 60 is completed, and when the operation completion flag EF2 is “0”, the processing of the MB in the filter unit 60 is not yet performed. Indicates completion.

  In step S48, when it is detected that the operation completion flag EF2 is “0” (step S48: N), the parallel operation control unit 30 monitors the timeout again (step S49: N). When a time-out is detected (step S49: Y), the status of the operation completion flag EF2 of the filter unit 60 is read out and stored (step S50) as in step S42. Thereafter, the process returns to step S48.

  When it is detected in step S48 that the operation completion flag EF2 is “1” (step S48: Y), the parallel operation control unit 30 performs the stream data of FIG. A series of processes of the access process, the CAVLC process of FIG. 7, and the inverse quantization process of FIG. 10 are activated, the activation flag SF1 of the sequencer unit 50 is set, and the activation flag SF2 of the filter unit 60 is set (step S51). When the sequencer unit 50 and the filter unit 60 are activated to operate in parallel, it is desirable that the sequencer unit 50 is activated after the filter unit 60 is activated. By doing so, even if the sequencer unit 50 is not activated in the decoding process, the operation of the filter unit 60 can be started quickly, which can contribute to the speeding up of the decoding process.

  Thereafter, the parallel operation control unit 30 clears the read values of the operation completion flags EF1 and EF2 (step S52) and returns to step S40.

  Thus, for example, when MB1 to MB3 (first to third data blocks) are sequentially decoded from MB1, the inverse quantization for MB3 (third data block) ends, and MB2 The operation completion flag EF1 from the sequencer unit 50 is set for (second data block), and the operation completion flag EF2 from the filter unit 60 is set for MB1 (first data block). The sequencer unit 50 and the filter unit 60 are activated on the condition that this is done.

  As a result, the parallel operation control unit 30 only needs to perform the polling operation on the operation completion flags EF1 and EF2 at a predetermined cycle, and the parallel operation control can be realized with a simple configuration and control.

  In FIG. 1, the function of the inverse quantization unit 24 has been described as being realized by the decoding process control unit 20, but the present invention is not limited to this, and the sequencer unit 50 of the decoding device 40 may be A function may be realized.

2. Information Reproducing Device Next, an information reproducing device to which the decoding system in the present embodiment is applied will be described. The information reproducing apparatus according to the present embodiment enables reproduction of terrestrial digital broadcasting. Video data encoded according to the H.264 / AVC standard can be decoded.

2.1 Overview of 1-segment broadcasting In terrestrial digital broadcasting that appears in place of terrestrial analog broadcasting, there are high expectations for the provision of various new services in addition to improving the quality of images and audio.

  FIG. 13 is an explanatory diagram of the concept of digital terrestrial broadcast segments.

  In digital terrestrial broadcasting, a pre-assigned frequency band is divided into 14 segments, and broadcasting is performed using 13 segments SEG1 to SEG13. The remaining one segment is used as a guard band. Then, one segment SEGm out of 13 segments for broadcasting is allocated to the frequency band of broadcasting for mobile terminals.

  In one-segment broadcasting, a transport stream (Transport Stream: TS) in which video data, audio data, and other data (control data) encoded (compressed) are multiplexed is transmitted. More specifically, a Reed-Solomon error correction code is added to each packet of the TS, and then divided into layers, and convolutional coding and carrier modulation are performed in each layer. After layer synthesis, frequency interleaving and time interleaving are performed, and a pilot signal necessary for the receiving side is added to form an OFDM segment frame. The OFDM segment frame is subjected to inverse Fourier transform operation and transmitted as an OFDM signal.

  FIG. 14 is an explanatory diagram of TS.

  The TS is composed of a plurality of TS packet sequences as shown in FIG. The length of each TS packet is fixed to 188 bytes. Each TS packet has header information called a 4-byte TS header (TS header) added thereto, and includes a PID (Packet Identifier) serving as an identifier of the TS packet. One segment broadcast program is specified by PID.

The TS packet includes an adaptation field, and is embedded with PCR (Program Clock Reference) and dummy data which are time information serving as a reference for synchronous reproduction of video data, audio data, and the like. The payload includes data for generating a PES (Packetized Elementary Stream) packet or section.

  FIG. 15 is an explanatory diagram of PES packets and sections.

  Each of the PES packet and the section is configured by the payload of each TS packet of one or a plurality of TS packets. The PES packet includes a PES header and a payload, and video data, audio data, or caption data is set as ES (Elementary Stream) data in the payload. In the section, program information such as video data set in the PES packet is set.

  Therefore, when a TS is received, first, it is necessary to analyze program information included in the section and specify a PID corresponding to the broadcast program. Then, video data and audio data corresponding to the PID are extracted from the TS, and the extracted video data and audio data are reproduced.

2.2 Mobile terminal A mobile terminal having a 1-segment broadcast reception function requires processing such as packet analysis as described above. That is, such a mobile terminal is required to have a high processing capacity. Therefore, when a one-segment broadcast receiving function is added to a conventional mobile phone as a mobile terminal (electronic device in a broad sense), it is necessary to further add a processor or the like having a high processing capability.

  FIG. 16 shows a block diagram of a configuration example of a mobile phone including a multimedia processing CPU in a comparative example of the present embodiment.

  In this cellular phone 900, the received signal received via the antenna 910 is demodulated, the telephone CPU 920 performs the incoming call processing, and the signal processed by the telephone CPU 920 is modulated and transmitted via the antenna 910. Sent. The telephone CPU 920 can read a program stored in the memory 922 and perform incoming call processing and outgoing call processing.

  When a desired signal is extracted from the received signal received via the antenna 930 via the tuner 940, a TS is generated by using the desired signal as an OFDM signal in the reverse procedure. The multimedia processing CPU 950 analyzes the TS packet from the generated TS, determines the PES packet and the section, and decodes video data and audio data from the TS packet of the desired program. The multimedia processing CPU 950 can read the program stored in the memory 952 and perform the above-described packet analysis processing and decoding processing. The display panel 960 performs display output based on the decoded video data, and the speaker 970 performs audio output based on the decoded audio data.

  In this way, the multimedia processing CPU 950 requires a very high processing capability. In general, a processor having a high processing capability has a high operating frequency and a large circuit scale.

  By the way, considering the bit rate of 1-segment broadcasting, most of the bandwidth is considered to be the bandwidth for video data and audio data, and the bandwidth for data broadcasting itself is narrowed. Accordingly, among the processes that can be realized by the multimedia processing CPU, it is necessary to always operate the multimedia processing CPU even though only the reproduction processing of video data and audio data may be required, resulting in an increase in power consumption. .

  Therefore, in this embodiment, a video decoder that performs video data decoding processing and an audio decoder that performs audio data decoding processing are provided independently, and the decoding processing is performed independently, thereby reducing the processing capability of each. You can adopt things. Furthermore, it is possible to flexibly reduce power consumption by appropriately stopping one of the operations of the video decoder and the audio data.

  Furthermore, since the video decoder and the audio decoder can be operated in parallel, the processing capability of each decoder can be reduced, and lower power consumption and cost can be realized.

  FIG. 17 shows a block diagram of a configuration example of a mobile phone including the information reproducing apparatus in the present embodiment. In FIG. 17, the same parts as those in FIG. 16 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  A cellular phone (electronic device in a broad sense) 100 includes a host CPU (host in a broad sense) 110, a RAM (Random Access Memory) 120, a ROM (Read Only Memory) 130, a display driver 140, a DAC (Digital-to-Analog Converter). ) 150, and an image processing IC (Integrated Circuit) (information reproducing apparatus in a broad sense) 200. Further, the cellular phone 100 includes antennas 910 and 930, a tuner 940, a display panel 960, and a speaker 970.

  The host CPU 110 has a function of controlling the image processing IC 200 as well as the function of the telephone CPU 920 of FIG. The host CPU 110 reads a program stored in the RAM 120 or the ROM 130, and performs processing of the telephone CPU 920 in FIG. 16 and processing of controlling the image processing IC 200. At this time, the host CPU 110 can use the RAM 120 as a work area.

  The image processing IC 200 receives, from the TS from the tuner 940, a video TS packet (first TS packet) for generating video data and an audio TS packet (second TS packet) for generating audio data. Extract and buffer in a shared memory (not shown). The image processing IC 200 includes a video decoder and an audio decoder (not shown) capable of controlling the operation stop independently of each other. The video decoder and the audio decoder decode the video TS packet and the audio TS packet, respectively. Video data and audio data are generated. The video data and the audio data are supplied to the display driver 140 and the DAC 150, respectively, while being synchronized. The host CPU 110 can instruct the image processing IC 200 to start the video decoding process and the audio decoding process. The host CPU 110 may instruct the image processing IC 200 to start at least one of video decoding processing and audio decoding processing.

  A display driver (driving circuit in a broad sense) 140 drives a display panel (electro-optical device in a broad sense) 960 based on video data. More specifically, the display panel 960 includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels, each pixel being specified by each scanning line and each data line. Crystal Display panel can be used. The display driver 140 has a function of a scanning driver that scans a plurality of scanning lines and a function of a data driver that drives a plurality of data lines based on the video data.

  The DAC 150 converts audio data that is a digital signal into an analog signal and supplies the analog signal to the speaker 970. The speaker 970 outputs sound corresponding to the analog signal from the DAC 150.

2.3 Information Reproducing Device FIG. 18 is a block diagram showing a configuration example of the image processing IC 200 shown in FIG. 17 as the information reproducing device of this embodiment.

The image processing IC 200 includes a TS separation unit (separation processing unit) 210, a memory (shared memory) 220, a video decoder 230, and an audio decoder 240. The image processing IC 200 further includes a display control unit 250, a tuner I / F (Interface) 260, and a host I / F.
270, a driver I / F 280, and an audio I / F 290.

  Here, the video decoder 230 includes a CPU (not shown), and the function of the video decoder 230 is realized by the CPU and the decoding device 40 that perform the function of the decoding processing control unit 20 in the present embodiment.

  The TS separation unit 210 includes a video TS packet (first TS packet) for generating video data, an audio TS packet (second TS packet) for generating audio data, a video TS packet, and audio. Packets other than the TS packet for use (third TS packet) are extracted from the TS. The TS separation unit 210 can extract the first and second TS packets based on the analysis result of the host CPU 110 that analyzes the third TS packet once extracted from the TS.

  The memory 220 has a plurality of storage areas in which the start address and end address of each storage area are determined in advance. Then, each of the video TS packet, audio TS packet, and other TS packets separated by the TS separation unit 210 is stored in a storage area dedicated to each TS packet.

  The video decoder 230 reads a video TS packet from a storage area dedicated to the video TS packet in the storage area of the memory 220 and performs video decoding processing for generating video data based on the video TS packet. More specifically, in the video decoding process, the process performed by the decoding process control unit 20 in FIG. 1, the process performed by the sequencer unit 50, and the process performed by the filter unit 60 are executed in parallel.

  The audio decoder 240 reads the audio TS packet from the storage area dedicated to the audio TS packet in the storage area of the memory 220 and performs audio decoding processing for generating audio data based on the audio TS packet.

  The display control unit 250 performs a rotation process for rotating the orientation of the image represented by the video data read from the memory 220 and a resizing process for reducing or enlarging the size of the image. The data after the rotation processing and the data after the resizing processing are supplied to the driver I / F 280.

  The tuner I / F 260 performs an interface process with the tuner 940. More specifically, the tuner I / F 260 performs control to receive a TS from the tuner 940. Tuner I / F 260 is connected to TS separator 210.

  The host I / F 270 performs interface processing with the host CPU 110. More specifically, the host I / F 270 controls data transmission / reception with the host CPU 110. The host I / F 270 is connected to the TS separation unit 210, the memory 220, the display control unit 250, and the audio I / F 290.

  The driver I / F 280 reads video data from the memory 220 via the display control unit 250 at a predetermined cycle, and supplies the video data to the display driver 140. The driver I / F 280 performs interface processing for transmitting video data to the display driver 140.

  The audio I / F 290 reads audio data from the memory 220 at a predetermined cycle and supplies the audio data to the DAC 150. The audio I / F 290 performs interface processing for transmitting audio data to the DAC 150.

  In such an image processing IC 200, the TS packet is extracted from the TS from the tuner 940 by the TS separator 210. The TS packet is stored in a pre-allocated storage area of the memory 220 as a shared memory. Then, the video decoder 230 and the audio decoder 240 respectively read out TS packets from dedicated storage areas allocated to the memory 220, generate video data and audio data, and display the synchronized video data and audio data with the display driver 140. And to the DAC 150.

  FIG. 19 shows an operation explanatory diagram of the image processing IC 200 of FIG.

  19, the same parts as those in FIG. 18 are denoted by the same reference numerals, and the description thereof will be omitted as appropriate.

  The memory 220 has first to eighth storage areas AR1 to AR8, and each storage area is assigned in advance.

  The first storage area AR1 stores the video TS packet (first TS packet) extracted by the TS separation unit 210 as a storage area dedicated to the video TS packet. The second storage area AR2 stores the voice TS packet (second TS packet) extracted by the TS separation unit 210 as a storage area dedicated to the voice TS packet. In the third storage area AR3, TS packets (third TS packets) excluding video TS packets and audio TS packets among the TS packets extracted by the TS separator 210 are stored.

  The fourth storage area AR4 stores the video ES data generated by the video decoder 230 as a storage area dedicated to the video ES data. The fifth storage area AR5 stores the audio ES data generated by the audio decoder 240 as a storage area dedicated to the audio ES data.

  In the sixth storage area AR6, a TS generated by the host CPU 110 is stored as TSRAW data. TSRAW data is set by the host CPU 110 instead of the TS from the tuner 940. Then, the TS separation unit 210 extracts a video TS packet, an audio TS packet, and other TS packets from the TS set as TSRAW data.

  In the seventh storage area AR7, video data after decoding by the video decoder 230 is stored. The video data stored in the seventh storage area AR7 is read by the display control unit 250 and used for video output by the display panel 960. The eighth storage area AR8 stores the audio data after the decoding process by the audio decoder 240. The audio data stored in the eighth storage area AR8 is provided for audio output by the speaker 970.

The video decoder 230 includes a header deletion processing unit 232 and a video decoding processing unit 234. The header deletion processing unit 232 reads the video TS packet from the first storage area AR1, analyzes the TS header of the video TS packet, generates a PES packet (first PES packet), and then generates the PES header. The payload portion is stored in the fourth storage area AR4 of the memory 220 as video ES data. The video decoding processing unit 234 reads video ES data from the fourth storage area AR4, H.264 / AVC (Advanced Video Coding) standard decoding process (video decoding process in a broad sense)
Are written in the seventh storage area AR7.

The audio decoder 240 includes a header deletion processing unit 242 and an audio decoding processing unit 244. The header deletion processing unit 242 reads the audio TS packet from the second storage area AR2, analyzes the TS header of the audio TS packet, generates a PES packet (second PES packet), and then generates the PES header. The payload portion is stored as audio ES data in the fifth storage area AR5 of the memory 220. The audio decoding processing unit 244 reads audio ES data from the fifth storage area AR5, and performs decoding processing (audio decoding processing in a broad sense) in accordance with the MPEG-2 AAC (Advanced Audio Coding) standard.
Is written in the eighth storage area AR8.

  Then, the video decoder 230 reads the video TS packet (first TS packet) from the first storage area AR1, independently of the audio decoder 240, and performs the video decoding process based on the video TS packet. I do. Also, the audio decoder 240 reads the audio TS packet (second TS packet) from the second storage area AR2 independently of the video decoder 230, and performs the above audio decoding process based on the audio TS packet. Do. In this way, the video decoder 230 and the audio decoder 240 can be operated when the video and audio are output in synchronism, while only the video decoder 230 is operated and output when only the video is output. The operation of the decoder 240 can be stopped. When outputting only audio, only the audio decoder 240 can be operated to stop the operation of the video decoder 230.

  The host CPU 110 reads another TS packet (third TS packet) stored in the third storage area AR3, and generates a section from the TS packet. Then, various table information included in the section is analyzed. The host CPU 110 sets the analysis result in a predetermined storage area of the memory 220 and specifies it as control information for the TS separation unit 210. Thereafter, the TS separation unit 210 extracts TS packets from the tuner 940 according to the control information. On the other hand, the host CPU 110 can issue activation commands to the video decoder 230 and the audio decoder 240 separately. The video decoder 230 and the audio decoder 240 independently access the memory 220, read the analysis result of the host CPU 110, and perform a decoding process corresponding to the analysis result.

2.3.1 Reproduction Operation Next, an operation in the case of reproducing video data or audio data multiplexed on a TS in the image processing IC 200 as an information reproduction apparatus in the present embodiment will be described.

  FIG. 20 shows a flowchart of an operation example of reproduction processing by the host CPU 110. The host CPU 110 can perform the process shown in FIG. 20 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 performs a broadcast reception start process (step S100). Thereby, video data or audio data of a desired program among a plurality of programs received as a TS can be extracted from the TS. Then, the host CPU 110 activates at least one of the video decoder 230 and the audio decoder 240 of the image processing IC 200.

  Thereafter, the host CPU 110 causes the video decoder 230 and the audio decoder 240 to perform decoding processing when reproducing video and audio. Alternatively, the host CPU 110 stops the operation of the audio decoder 240 and causes the video decoder 230 to perform decoding processing when reproducing only the video. Alternatively, when reproducing only audio, the host CPU 110 stops the operation of the video decoder 230 and causes the audio decoder 240 to perform decoding processing (step S101).

  Next, the host CPU 110 performs broadcast reception end processing (step S102), and ends a series of processing (end). As a result, the host CPU 110 stops the operation of each unit of the image processing IC 200.

2.3.1.1 Broadcast Reception Start Process Next, a process example of the broadcast reception start process shown in FIG. 20 will be described. Here, a case where video and audio are reproduced will be described.

  FIG. 21 shows a flowchart of an operation example of the broadcast reception start process of FIG. The host CPU 110 can perform the process shown in FIG. 21 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 activates the video decoder 230 and the audio decoder 240 of the image processing IC 200 (step S110). Thereafter, the host CPU 110 initializes the tuner 940 and sets given operation information (step S111). Then, the host CPU 110 also initializes the DAC 150 and sets given operation information (step S112).

  Thereafter, the host CPU 110 monitors reception of TS (step S113: N). When reception of the TS is started, in the image processing IC 200, the TS separation unit 210 separates the TS from the TS into the video TS packet, the audio TS packet, and the other TS packets as described above, and the separated TS packet. Is stored in a storage area of a memory 220 provided for exclusive use. For example, the host CPU 110 can detect reception of a TS by an interrupt signal generated on the condition that a TS packet is stored in the third storage area AR3 in the memory 220 of the image processing IC 200. Alternatively, the host CPU 110 can periodically determine whether the TS packet has been written by accessing the third storage area AR3 of the memory 220, thereby determining the reception of the TS.

  When reception of a TS is detected in this way (step S113: Y), the host CPU 110 reads a TS packet stored in the third storage area AR3 and generates a section. Then, PSI (Program Specific Information) / SI (Service Information: program arrangement information) included in the section is analyzed (step S114). This PSI / SI is defined by the MPEG-2 system (ISO / IEC 13818-1).

PSI / SI is NIT (Network Information Table)
And PMT (Program Map Table). The NIT includes, for example, a network identifier for specifying which broadcasting station the TS is from, a service identifier for specifying the PMT, a service type identifier indicating the type of broadcast, and the like. In the PMT, for example, the PID of the video TS packet multiplexed in the TS and the PID of the audio TS packet are set.

  Therefore, the host CPU 110 extracts a service identifier for specifying the PMT from the PSI / SI, and can specify the PID of the received video TS packet and audio TS packet based on the service identifier (step S115). . Then, a predetermined storage in the memory 220 is provided so that the host CPU 110 can refer to the video decoder 230 and the audio decoder 240 for the PID corresponding to the program selected by the user of the mobile terminal or the PID corresponding to the predetermined program. An area (for example, the third storage area AR3) is set (step S116), and a series of processing ends (end).

  In this way, the video decoder 230 and the audio decoder 240 can perform decoding processing on the video TS packet and the audio TS packet while referring to the PID set in the memory 220.

  The host CPU 110 sets information corresponding to, for example, a service identifier for specifying the PMT in the TS separation unit 210 of the image processing IC 200. In this way, the TS separation unit 210 determines a section periodically received at a predetermined time interval, analyzes the PMT corresponding to the service identifier, and identifies the video TS specified by the PMT. Packets and TS packets for voice and other TS packets are extracted and stored in the memory 220.

  FIG. 22 is an operation explanatory diagram of the broadcast reception start process of the image processing IC 200 of FIGS. 18 and 19. In FIG. 22, the same parts as those in FIG. 18 or FIG.

  In FIG. 22, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, when TS is input from the tuner 940 (SQ1), the TS separation unit 210 stores a TS packet including PSI / SI in the memory 220 (SQ2). At this time, the TS separation unit 210 can extract the PSI / SI itself of the TS packet and store it in the memory 220. Further, the TS separation unit 210 can extract the NIT from the PSI / SI and store it in the memory 220.

  The host CPU 110 reads PSI / SI, NIT, and PMT (SQ3), analyzes them, and identifies the PID corresponding to the program to be decoded. Then, the host CPU 110 sets information corresponding to the service identifier or PID corresponding to the program to be decoded in the TS separation unit 210 (SQ4). The host CPU 110 also sets the PID in a predetermined storage area of the memory 220 and refers to it during decoding processing by the video decoder 230 and the audio decoder 240.

  The TS separation unit 210 extracts video TS packets and audio TS packets from the TS based on the set PID, and writes them to the first and second storage areas AR1 and AR2, respectively (SQ5).

  Thereafter, the video decoder 230 and the audio decoder 240 activated by the host CPU 110 sequentially read the video TS packet and the audio TS packet from the first and second storage areas AR1 and AR2 (SQ6), and perform video decoding processing and Perform audio decoding.

2.3.1.2 Broadcast Reception End Process Next, an operation example of the broadcast reception end process shown in FIG. 20 will be described. Here, a case where video and audio are reproduced will be described.

  FIG. 23 shows a flowchart of a processing example of the broadcast reception end processing of FIG. The host CPU 110 can perform the process shown in FIG. 23 by reading a program stored in the RAM 120 or the ROM 130 and executing a process corresponding to the program.

  First, the host CPU 110 stops the video decoder 230 and the audio decoder 240 of the image processing IC 200 (step S120). For example, the host CPU 110 can issue a control command to the image processing IC 200, and the image processing IC 200 can stop the video decoder 230 and the audio decoder 240 using the decoding result of the control command.

  Thereafter, the host CPU 110 similarly stops the TS separation unit 210 (step S121). Then, the host CPU 110 stops the tuner 940 (step S122).

  FIG. 24 is a diagram for explaining the operation in the broadcast reception end process of the image processing IC 200 shown in FIGS. In FIG. 24, the same parts as those in FIG. 22 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  First, the host CPU 110 performs control to stop the operation of the display control unit 250, and stops the supply of video data to the display driver 140 (SQ10). Next, the host CPU 110 stops the operations of the video decoder 230 and the audio decoder 240 (SQ11), and then stops the operations in the order of the TS separation unit 210 and the tuner 940 (SQ12, SQ13).

2.3.1.3 Reproduction Process Next, an operation example of the video decoder 230 that performs the reproduction process of the video data will be described.

  FIG. 25 shows a flowchart of an operation example of the video decoder 230.

  When the video decoder 230 is activated by the host CPU 110, for example, the video decoder 230 reads out a program stored in a predetermined storage area of the memory 220 and can execute the processing shown in FIG. 25 by executing processing corresponding to the program. It is like that.

  First, the video decoder 230 determines whether or not the first storage area AR1 provided as the video TS buffer is in an empty state (step S140). When there is no video TS packet to be read from the first storage area AR1, the state becomes empty.

  When it is determined in step S140 that the first storage area AR1 that is the video TS buffer is not empty (step S140: N), the video decoder 230 further includes a fourth storage area provided as a video ES buffer. It is determined whether or not AR4 is full (step S141). When no more video ES data can be stored in the fourth storage area AR4, the full state is entered.

  When it is determined in step S141 that the fourth storage area AR4 that is the video ES buffer is not full (step S141: N), the video decoder 230 reads the video TS packet from the first storage area AR1, It is detected whether or not the PID (designated PID) specified by the host CPU 110 in step S116 in FIG. 21 (step S142).

  When it is detected in step S142 that the PID of the video TS packet is the designated PID (step S142: Y), the video decoder 230 analyzes the TS header and the PES header (step S143), and the video ES data Are stored in a fourth storage area AR4 provided as a video ES buffer (step S144).

  Thereafter, the video decoder 230 updates the read pointer for specifying the read address of the first storage area AR1, which is a video TS buffer (step S145), and returns to step S140 (return).

  When it is detected in step S142 that the PID of the video TS packet is not the designated PID (step S142: N), the process proceeds to step S145. When it is determined in step S140 that the first storage area AR1 that is the video TS buffer is in an empty state (step S140: Y), or in step S141, the fourth storage area AR4 that is the video ES buffer. Is determined to be full (step S141: Y), the process returns to step S140 (return).

  The video ES data stored in the fourth storage area AR4 in this way is sent to the H.264 by the video decoder 230 as described above. A decoding process according to the H.264 / AVC standard is performed and written as video data in the seventh storage area AR7 (see FIG. 19).

  FIG. 26 is a diagram for explaining the operation of the audio decoder of the image processing IC 200 shown in FIGS. In FIG. 26, the same parts as those in FIG. 22 are denoted by the same reference numerals, and description thereof will be omitted as appropriate.

  In FIG. 26, the seventh storage area AR7 is shared with the fourth storage area AR4, and the eighth storage area AR8 is shared with the fifth storage area AR5. In addition, PSI / SI, NIT, and PMT are stored in a predetermined storage area in the third storage area AR3.

  First, as shown in FIG. 21, the host CPU 110 sets the PID corresponding to the program to be decoded in the TS separator 210 (SQ20). When a TS is input from the tuner 940 (SQ21), the TS separation unit 210 separates the video TS packet, audio TS packet, and other TS packets from the TS from the tuner 940 (SQ22). The video TS packet separated by the TS separation unit 210 is stored in the first storage area AR1. The audio TS packet separated by the TS separation unit 210 is stored in the second storage area AR2. TS packets other than the video TS packet and audio TS packet separated by the TS separation unit 210 are stored in the third storage area AR3 as PSI / SI. At this time, the TS separation unit 210 extracts NIT and PMT in the PSI / SI and stores them in the third storage area AR3.

  Next, the video decoder 230 activated by the host CPU 110 reads the video TS packet from the first storage area AR1 (SQ23), generates video ES data, and stores the video ES data in the fourth storage area AR4. (SQ24).

  After that, the video decoder 230 reads the video ES data from the fourth storage area AR4 (SQ25). The decoding process according to the H.264 / AVC standard is performed. Here, as described above, the parallel operation in the present embodiment is performed. In FIG. 26, the video data after the decoding process is directly supplied to the display control unit 250 (SQ26). For example, the video data after the decoding process is once written back to a predetermined storage area of the memory 220, and then It is desirable to supply the display control unit 250 while synchronizing with the output timing of the audio data.

  Based on the video data thus supplied to the display control unit 250, the display driver 140 drives the display panel (SQ27).

  Similarly, the audio decoder 240 that performs the audio data reproduction process reads the audio TS packet from the second storage area AR2 provided as the audio TS buffer, analyzes the TS header and the PES header, The audio ES data is stored in a fifth storage area AR5 provided as an audio ES buffer.

  The audio ES data stored in the fifth storage area AR5 in this way is decoded by the audio decoder 240 in accordance with the MPEG-2 AAC standard, and is used as audio data in the eighth storage area AR8 (see FIG. 19). ).

  The operation of the audio decoder 240 as described above is performed independently of the operation of the video decoder 230.

  The present invention is not limited to the above-described embodiment, and various modifications can be made within the scope of the gist of the present invention. In the above embodiment or its modification, an example applicable to terrestrial digital broadcasting has been described. However, the present invention is not limited to one applicable to terrestrial digital broadcasting.

  Note that the decoding system and decoding apparatus in this embodiment are H.264. Although the case where the present invention is applied to decoding processing conforming to H.264 / AVC has been described, the present invention is not limited to this, and other standards, It goes without saying that the present invention can be applied to decoding processing based on a standard developed from the H.264 / AVC standard.

  In the invention according to the dependent claims of the present invention, a part of the constituent features of the dependent claims can be omitted. Moreover, the principal part of the invention according to one independent claim of the present invention can be made dependent on another independent claim.

The block diagram of the structural example of the decoding system in this embodiment. The flowchart of the outline | summary of the flow of a process of the decoding system in this embodiment. The schematic diagram of the bit stream of MB unit extracted from the stream data. The timing diagram of the operation example of the decoding system in the comparative example of this embodiment. The timing diagram of the example of operation | movement of the decoding system in this embodiment. The flowchart of an example of the header analysis process performed in a decoding process control part. The flowchart of an example of a process of a CAVLC part. 8A, 8B, and 8C are explanatory diagrams of CAVLC calculation. FIGS. 9A, 9B, and 9C are explanatory diagrams of Golomb codes. Explanatory drawing of a process of an inverse quantization part. The flowchart of the example of a process of a parallel operation control part. The flowchart of the example of a process of a parallel operation control part. Explanatory drawing of the concept of the segment of digital terrestrial broadcasting. Explanatory drawing of TS. Explanatory drawing of a PES packet and a section. The block diagram of the structural example of the mobile telephone containing the multimedia processing CPU in the comparative example of this embodiment. The block diagram of the structural example of the mobile telephone containing the information reproduction apparatus of this embodiment. Block diagram of a configuration example of the image processing IC of FIG. FIG. 19 is an operation explanatory diagram of the image processing IC in FIG. 18. The flowchart of the operation example of the reproduction | regeneration processing by host CPU. The flowchart of the process example of the broadcast reception start process of FIG. Operation | movement explanatory drawing in the broadcast reception start process of the image processing IC of FIG.18 and FIG.19. The flowchart of the process example of the broadcast reception end process of FIG. Operation | movement explanatory drawing in the broadcast reception end process of the image processing IC of FIG.18 and FIG.19. The flowchart of the operation example of a video decoder. FIG. 20 is an operation explanatory diagram of the audio decoder of the image processing IC in FIGS. 18 and 19.

Explanation of symbols

10 decoding system, 20 decoding processing control unit, 22 CAVLC unit,
24 Inverse quantization unit, 26 Parameter analysis unit, 27 Intra parameter analysis unit,
28 Inter parameter analysis unit, 30 parallel operation control unit, 40 decoding device,
50 sequencer section, 52 inverse DCT calculation section, 53 addition section, 54 motion compensation section,
56 motion prediction units, 57 weighted prediction units, 58 intra-screen prediction units,
60 filter section, 62 deblock filter, 70 output image buffer,
EF1, EF2 operation completion flag, SF1, SF2 start flag

Claims (16)

A decoding device for decoding stream data,
An image obtained by performing inverse discrete cosine transform on data that has been subjected to inverse quantization after decoding stream data encoded by the entropy encoding method, and performing motion prediction or motion compensation on the data after the inverse discrete cosine transform A sequencer section for generating data;
A filter unit that performs processing for reducing block noise of the image data subjected to the motion prediction or motion compensation in a predetermined data block unit,
A decoding apparatus, wherein each of the sequencer unit and the filter unit is activated so as to operate in parallel in a given data block unit. In claim 1,
In the second period following the first period,
The filter unit performs a process of reducing block noise of image data after motion prediction or motion compensation generated by the sequencer unit in the first period,
The sequencer unit performs inverse discrete cosine transform on the data inversely quantized in the first period, and generates image data obtained by performing motion prediction or motion compensation on the data after the inverse discrete cosine transform. A decoding device characterized by the above. In claim 1 or 2,
The sequencer section is
A first operation completion flag set on condition that the motion prediction or motion compensated image data is generated after the sequencer unit is activated;
The filter unit is
A second operation completion flag that is set on the condition that processing for reducing block noise of the image data after motion prediction or motion compensation has been completed after activation of the filter unit;
6. A decoding apparatus according to claim 1, wherein each of the sequencer unit and the filter unit is activated based on a monitoring result of the set states of the first and second operation completion flags. In claim 3,
When processing the first to third data blocks in order from the first data block,
Inverse quantization for the third data block is completed, and the first operation completion flag from the sequencer unit is set for the second data block, and the first data block The decoding apparatus, wherein the sequencer unit and the filter unit are activated on condition that the second operation completion flag from the filter unit is set to a data block. In any one of Claims 1 thru | or 4,
When starting to operate the sequencer unit and the filter unit in parallel,
The decoding apparatus, wherein the sequencer unit is activated after the filter unit is activated. In any one of Claims 1 thru | or 5,
The data block is
The decoding apparatus according to claim 1, wherein the decoding apparatus is data for one macroblock having a given number of pixels in the horizontal direction and a given number of lines in the vertical direction as a unit among images generated based on the stream data. In any one of Claims 1 thru | or 6.
A decoding apparatus comprising: a decoding processing control unit that performs inverse quantization after decoding the stream data, the sequencer unit, and the filter unit are activated to operate in parallel in units of a given data block . In any one of Claims 1 thru | or 7,
Including a central processing unit,
A program for decoding the stream data and realizing the function of starting the sequencer unit and the filter unit is read, and the stream data encoded by the entropy encoding method is decoded according to the program, and then inverse quantization is performed. A decoding apparatus characterized by executing processing and activating each unit so that the sequencer unit and the filter unit operate in parallel in a given data block unit. Image data obtained by performing inverse discrete cosine transform on the inversely quantized data after decoding the stream data encoded by the entropy encoding method and performing motion prediction or motion compensation on the data after the inverse discrete cosine transform A sequencer section to generate,
A control method of a decoding device including a filter unit that performs processing for reducing block noise of image data after motion prediction or motion compensation in units of predetermined data blocks,
Among the images generated based on the stream data, the sequencer unit and the filter in units of data of one macroblock having a given number of pixels in the horizontal direction and a given number of lines in the vertical direction as units. A control method of a decoding device, wherein each unit is activated so that the units operate in parallel. In claim 9,
In the second period following the first period,
The filter unit performs a process of reducing block noise of image data after motion prediction or motion compensation generated by the sequencer unit in the first period,
Starting the sequencer unit to perform inverse discrete cosine transform on the inversely quantized data and to perform motion prediction or motion compensation on the data after the inverse discrete cosine transform in the first period. A control method for a decoding apparatus, which is characterized. In claim 9 or 10,
When operating the sequencer unit and the filter unit in parallel,
A control method for a decoding apparatus, wherein the sequencer unit is activated after the filter unit is activated. In any of claims 9 to 11,
A decoding processing control unit that performs inverse quantization after decoding the stream data, the sequencer unit, and the filter unit are activated so as to operate in parallel in a given data block unit. Control method. An information reproducing apparatus for reproducing at least one of video data and audio data,
Transport a first TS (Transport Stream) packet for generating video data, a second TS packet for generating audio data, and a third TS packet other than the first and second TS packets. A separation processing unit for extracting from the stream;
A first storage area for storing the first TS packet; a second storage area for storing the second TS packet; and a third storage area for storing the third TS packet; A memory having
The decoding device according to any one of claims 1 to 8, wherein a video decoding process for generating the video data based on the first TS packet read from the first storage area is performed.
An audio decoder that performs audio decoding processing for generating the audio data based on the second TS packet read from the second storage area;
The decoding device reads the first TS packet from the first storage area independently of the audio decoder, performs the video decoding process based on the first TS packet,
The audio decoder reads the second TS packet from the second storage area independently of the video decoder, and performs the audio decoding process based on the second TS packet. Information playback device. In claim 13,
When reproducing only the video data of the video data and audio data, stop the operation of the audio decoder,
An information reproducing apparatus characterized by stopping the operation of the decoding apparatus when reproducing only the audio data of the video data and audio data. An information reproducing apparatus according to claim 13 or 14,
An electronic apparatus comprising: a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process. Tuner,
The information reproducing apparatus according to claim 13 or 14, wherein a transport stream from the tuner is supplied;
An electronic apparatus comprising: a host that instructs the information reproduction apparatus to start at least one of the video decoding process and the audio decoding process.

Images