JP2007228043A - Digital dll circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a digital DLL circuit with a simple configuration capable of easily obtaining a delay feedback value without using a phase comparator or the like and easily executing complicated control. <P>SOLUTION: The digital DLL circuit includes: a register 11 for holding a delay target value; a ring oscillator 12; a first counter 13 for counting an external reference clock RCLK for determining a measurement period; a second counter 14 for counting an oscillated output clock CLK of the ring oscillator 12 by each measurement period depending on the first counter 13; a digital control variable delay circuit 15; and a control circuit 16 that performs control of resetting, starting, and stopping as required of the first and second counters 13, 14 on the basis of control signals CTL1, CTL2, digitally calculates a count C2 of the second counter 14 and the delay target value DV of the register 11, and provides a result of the arithmetic operation to the variable delay circuit 15 as a delay control variable DCV on the basis of a count value C1 of the first counter 13. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a digital DLL (Delay locked loop) circuit applicable to an interface circuit of a memory such as a DRAM.

The circuit delay inside the LSI varies depending on the power supply voltage, temperature, and process variations during manufacturing.
A DLL (Delay lock loop) circuit is used to suppress the fluctuation and realize a desired stable delay.

DLL is a technique that can adjust a delay amount (time difference) generated between a clock signal from the outside of a chip and an internal clock signal in a circuit to realize a high-speed clock access time and a high operating frequency. The DLL circuit is used for a DRAM interface circuit or the like.
Various circuits have been proposed as this type of DLL circuit (see, for example, Patent Document 1 and Patent Document 2).

In the DLL circuits described in Patent Document 1 and Patent Document 2, a delay or phase determination for delay control is performed by a phase comparison circuit.
1 and 8 of Japanese Patent Laid-Open No. 2005-142859 Fig. 1 and Fig. 3 of JP-T 2004-531981

As described above, the existing DLL circuit uses the phase comparison circuit to determine the delay or phase for delay control.
In many cases, the output of the phase comparison circuit is converted into an analog voltage by a charge pump and used as a control signal for the analog control variable delay circuit.

In the case of the analog system, it is difficult to perform complicated control such as dynamically adapting the feedback control system in accordance with the passage of time after reset release and the fluctuation state of the delay.
In order to set the delay targets of the plurality of variable delay circuits to different values, it is necessary to have a plurality of control systems such as a phase comparison circuit.
When a digitally controlled variable delay circuit is used, the output of the phase comparison circuit is handled as a binary precision value, or an analog / digital (A / D) conversion circuit is added to obtain a multivalued digital value. Need to be converted.

  It is an object of the present invention to provide a digital DLL circuit that can easily obtain a delay feedback value with a simple configuration without using a phase comparison circuit or the like and can easily perform complicated control.

  A digital DLL circuit according to a first aspect of the present invention includes a register that holds a delay target value, an oscillator, a first counter that counts an external reference clock or an oscillation output of the oscillator in order to determine a measurement period, Based on the count value of the first counter, the second counter that counts the oscillation output of the oscillator or the external reference clock for each measurement period determined by the first counter, the digitally controlled variable delay circuit, and the first counter. The counter and the second counter are reset, started, and stopped if necessary, and the count value of the second counter and the delay target value of the register are digitally calculated, and the calculation result is output to the variable delay circuit. And a control circuit for giving a delay control value.

  Preferably, there are a plurality of registers for holding the delay target values, a plurality of the digitally controlled variable delay circuits, and the control circuit reads the delay target values of the plurality of registers, and the delay control values corresponding to each of them. Is supplied to the plurality of variable delay circuits.

  According to the present invention, a delay feedback value can be easily obtained with a simple configuration without using a phase comparison circuit or the like, and complicated control can be easily performed.

  Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.

<First Embodiment>
FIG. 1 is a block diagram showing a digital DLL circuit according to the first embodiment of the present invention.
The digital DLL circuit of the first embodiment can easily obtain a delay feedback value with a simple configuration without using a PLL (phase comparison circuit), and can easily perform complicated control. It is configured.

  As shown in FIG. 1, the digital DLL circuit 10 includes a register 11, a ring oscillator (oscillator) 12, a first counter 13, a second counter 14, a digitally controlled variable delay circuit 15, and a control circuit 16.

  The register 11 holds a delay target value set in advance.

  The ring oscillator 12 oscillates a clock CLK having a predetermined frequency and outputs it to the second counter 14.

  The first counter 13 counts the reference clock RCLK outside the IC and determines the measurement period, and outputs the count value C1 to the control circuit 16.

  The second counter 14 counts the oscillation output clock CLK of the ring oscillator 12 every measurement period determined by the first counter 13 and outputs a count value C2 to the control circuit 16.

  The digitally controlled variable delay circuit 15 delays the input data IN by a delay amount corresponding to the delay control value given from the control circuit 16 to obtain a delay output DOUT.

FIG. 2 is a diagram conceptually illustrating a configuration example of the digitally controlled variable delay circuit 15.
The variable delay circuit 15 of FIG. 2 includes a plurality of delay elements 151-1 to 151-n cascaded to the input IN, and delay elements 151-1 to 151-1 in accordance with a delay control value DCV supplied from the control circuit 16. The selector 152 selects one of the outputs 151-n to obtain the delayed output DOUT.

  Based on the count value C1 of the first counter 13, the control circuit 16 resets and activates the first counter 13 and the second counter 14, and further controls the stop as necessary based on the control signals CTL1 and CTL2. The count value C2 of the second counter 14 and the delay target value DV of the register are digitally calculated, and the calculation result is given to the variable delay circuit 15 as the delay control value DCV.

In the digital DLL circuit 10 having the above configuration, the ring oscillator 12 and the variable delay circuit 15 are arranged close to each other in the same LSI, and the delay gates in the ring oscillator 12 and the variable delay circuit 15 are configured to be similar. The influence of the power supply voltage and temperature inside the LSI on the delay of process variations determined at the time of manufacture is almost the same between the ring oscillator 12 and the variable delay circuit 15.
Therefore, the ratio between the oscillation period of the ring oscillator 12 and the delay amount of the variable delay circuit 15 is always substantially constant.
Therefore, if the oscillation frequency of the ring oscillator 12 or the reciprocal thereof is measured, the delay value of the variable delay circuit 15 can be found by proportional calculation.
The delay control value (feedback amount) DCV to be given to the variable delay circuit 15 can be calculated from the target delay value DV and the current delay value of the variable delay circuit 15.
In the first embodiment, the first counter 13 and the second counter 14 are used for measuring the oscillation period or the oscillation frequency of the ring oscillator 12.

  Next, the operation of the digital DLL circuit 10 according to the embodiment will be described with reference to the flowchart of FIG.

First, a measurement loop is started (ST10), and the first counter 13 and the second counter 14 are initialized by the control signals CTL1 and CTL2 (ST11).
Next, the first counter 13 starts counting the external reference clock RCLK, and the second counter 14 starts counting the oscillation output clock CLK of the ring oscillator 12 (ST12).
Next, it is determined whether or not the count value C1 of the first counter 13 has reached the maximum value (max) (ST13). If it is determined that the count value C1 has reached, the count operation of the first counter 13 and the second counter 14 is performed. Stop (ST14).
Then, the count C2 of the second counter 14 is read (ST15).

Next, the delay control value (feedback amount) DCV calculation process is started (ST20), and the delay target value DV and the second count value C2 of the register 11 are fetched (ST21).
Then, the fetched delay target value DV and the second count value C2 are digitally calculated to obtain the delay control value DCV of the variable delay circuit 15 (ST22), and this delay control value DCV is set (given) to the variable delay circuit 15. .

If the measurement cycle is determined by the count value C1 of the first counter 13 in accordance with the operation flow of FIG. The period or frequency ratio of 12 oscillation clocks CLK can be found.
The period or frequency of the oscillation clock CLK of the ring oscillator 12 is determined from the ratio and the period or frequency of the reference clock RCLK.
Since the ratio of the period of the oscillation clock CLK of the ring oscillator 12 and the delay of the variable delay circuit can be found by delay analysis at the time of LSI design, the delay of the variable delay circuit 15 can be found as a result.

As described above, according to the first embodiment, the register 11 that holds a preset delay target value, the ring oscillator 12 that oscillates the clock CLK having a predetermined frequency, and the external cycle to determine the measurement cycle. The first counter 13 that counts the reference clock RCLK and obtains the count value C1, the second counter 14 that counts the oscillation output clock CLK of the ring oscillator 12 for each measurement period determined by the first counter 13, and obtains the count value C2. The first counter 13 and the second counter are based on the digitally controlled variable delay circuit 15 that obtains the delay output DOUT by delaying the input data IN by a delay amount corresponding to the control value DCV, and the count value C1 of the first counter 13. 14 reset, start, and if necessary stop control control signals CTL1, CT 2 and the control circuit 16 which digitally calculates the count value C2 of the second counter 14 and the delay target value DV of the register and gives the calculation result to the variable delay circuit 15 as the delay control value DCV. The following effects can be obtained.
By comparing the current delay value of the variable delay circuit 15 with the delay target and applying feedback by digital calculation in the control circuit 16, the delay of the variable delay circuit 15 is always kept in the vicinity of the target delay. Functions as a high DLL.
In other words, a delay feedback value can be easily obtained with a simple configuration without using a phase comparison circuit or the like, and complicated control can be easily performed.

In order to improve the accuracy of delay control, the clock frequency used for measurement may be increased or the count value may be increased by extending one measurement period.
In order to increase the response speed, the accuracy may be constant and the clock frequency may be increased, or the clock frequency may be the same and the accuracy reduced.

Second Embodiment
FIG. 4 is a block diagram showing a digital DLL circuit according to the second embodiment of the present invention.

  The digital DLL circuit 10A according to the second embodiment is different from the digital DLL circuit 10 according to the first embodiment in that it has a plurality of (n) registers 11 that hold delay target values, and is digitally controlled. The purpose is to have a plurality of (for example, n) variable delay circuits 15.

  In this case, the control circuit 16A reads the delay target values DV1 to DVn of the plurality of registers 11-1 to 11-n, calculates the delay control values DCV1 to DCVn corresponding to each, and calculates the plurality of variable delay circuits 15-1. ~ 15-n.

  That is, as in the second embodiment, when there are a plurality of registers and variable delay circuits that hold delay targets, feedback control by digital calculation for bringing the delay of each variable delay circuit closer to each delay target is performed. It is done individually.

The above digital operations may be processed in parallel using a plurality of circuits.
More preferably, it is possible to reduce the scale of the digital arithmetic circuit by applying time division processing and pipeline processing generally used in the digital arithmetic circuit.

  Other configurations are the same as those of the first embodiment, and the same effects as those of the first embodiment can be obtained.

<Third Embodiment>
FIG. 5 is a block diagram showing a digital DLL circuit according to the third embodiment of the present invention.

The digital DLL circuit 10B of the third embodiment is different from the digital DLL circuit 10A of the second embodiment in that the inputs of the two counters 13B and 14B are switched.
In this case, the output count value C2 of the second counter 14B is not a frequency of the clock to be measured but a value proportional to the cycle.

  Other configurations are the same as those of the second embodiment, and the same effects as those of the first and second embodiments can be obtained.

The digital DLL circuits 10, 10A and 10B having the above-described features can be used as an interface circuit of a DDR (Double Data Rate) DRAM as shown in FIG. 6, for example.
In FIG. 6, reference numeral 30 denotes a DDR synchronous DRAM (SDRAN), and 20 denotes a predetermined LSI. 21 and 22 are D-type flip-flops, and 23 is an inverter.
In FIG. 6, the power supply system is omitted.

  7A to 7D are timing charts for explaining the operation of the DLL functioning as a DDR interface.

When data is read from the DDR SDRAM 30, a signal DQS * indicating the change timing of the read data is output for each group (for example, every 8 bits) of the read data DQ *.
In order to latch the read data inside the LSI 20, it is necessary to delay the signal DQS * by about 1/4 of the clock period and use it as a fetch clock.
The digital DLL circuit 10A generates a stable delayed signal DQS for this purpose.

  As described above, it can be applied as a DDR interface, and a stable clock signal with little delay oscillation can be generated.

  According to each embodiment described above, the following effects can be obtained.

That is, since the delay or frequency is detected by the counter without using the phase comparison circuit or the charge pump, the output is a multi-bit digital value representing the absolute value of the delay or frequency. Therefore, it becomes easy to digitally calculate the delay feedback value of the DLL.
In addition, if it is a digital operation, process porting that is required for changing generations of processes becomes easier than an analog circuit.
In addition, more complex control is facilitated as compared with an analog filter or the like used for feedback to an analog type variable delay circuit.
Further, when a plurality of slave delay circuits are provided, it is easy to set different delay target values by digital calculation.
Delay measurement and feedback accuracy can be improved easily by increasing the clock frequency or extending the measurement period.

In recent years, high-speed serial interfaces instead of high-speed memory interfaces and buses have been frequently used, and therefore, a digital DLL circuit like this embodiment is required for sending and receiving data.
Compared to analog, the area of a digital circuit is steadily shrinking as generations of semiconductor process technology change. As the speed of LSI operations increases as process technology changes, the frequency of the reference clock used there will also increase. Therefore, it can be expected that the response speed and accuracy of the digital DLL circuit of this embodiment will be improved and the merit will be increased.

1 is a block diagram showing a digital DLL circuit according to a first embodiment of the present invention. It is a figure which shows notionally the structural example of the digital control variable delay circuit which concerns on embodiment. 4 is a flowchart for explaining a control operation of the digital DLL circuit according to the embodiment. It is a block diagram which shows the digital DLL circuit which concerns on the 2nd Embodiment of this invention. It is a block diagram which shows the digital DLL circuit which concerns on the 3rd Embodiment of this invention. It is a figure for demonstrating a DDR interface. 6 is a timing chart for explaining an operation of a DLL functioning as a DDR interface.

Explanation of symbols

10, 10A, 10B ... digital DLL circuit, 11, 11-1 to 11-n ... register, 12, 12B ... ring oscillator, 13, 13B ... first counter, 14 ... first 2 counters, 15, 15-1 to 15-n... Variable delay circuit, 16, 16A.

Claims (4)

A register holding the delay target value;
An oscillator,
A first counter for counting an external reference clock or an oscillation output of the oscillator to determine a measurement period;
A second counter that counts the oscillation output of the oscillator or an external reference clock every measurement period determined by the first counter;
A digitally controlled variable delay circuit;
Based on the count value of the first counter, the first counter and the second counter are reset, started, and stopped as necessary. The count value of the second counter and the delay target value of the register are controlled. A digital DLL circuit comprising: a control circuit that performs a digital operation on the signal and provides the result of the operation to the variable delay circuit as a delay control value. A plurality of registers for holding the delay target value;
Having a plurality of the above-mentioned digitally controlled variable delay circuits,
2. The digital DLL circuit according to claim 1, wherein the control circuit reads delay target values of a plurality of registers, calculates a delay control value corresponding to each of the plurality of registers, and supplies the delay control value to the plurality of variable delay circuits. The digital DLL circuit according to claim 1, wherein the oscillator is a ring oscillator. The digital DLL circuit according to claim 2, wherein the oscillator is a ring oscillator.

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