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JP2007227712A - Multilayer printed wiring board - Google Patents

Multilayer printed wiring board Download PDF

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Publication number
JP2007227712A
JP2007227712A JP2006048005A JP2006048005A JP2007227712A JP 2007227712 A JP2007227712 A JP 2007227712A JP 2006048005 A JP2006048005 A JP 2006048005A JP 2006048005 A JP2006048005 A JP 2006048005A JP 2007227712 A JP2007227712 A JP 2007227712A
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substrate
conductor
printed wiring
multilayer printed
wiring board
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Kunihiko Inoue
邦彦 井上
Satoru Nakao
知 中尾
Koji Tsurusaki
幸司 鶴崎
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Fujikura Ltd
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Fujikura Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a multilayer printed wiring board in which solder heat resistance can be enhanced by preventing a substrate from swelling owing to gas produced at the time of soldering. <P>SOLUTION: In at least one conductor layer, out-gas diffusion regions 14 from where conductors 13 on an insulating substrate 12 are removed regularly at a pitch of 11 mm or less are provided in a region other than a circuit forming portion. When a nonconductor 14 is square, for example, the conductors are arranged regularly at pitches P<SB>11</SB>and P<SB>12</SB>of 11 mm or less in both longitudinal and lateral directions. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

本発明は、多層プリント配線板に関し、部品実装時に行う半田付け工程で発生するアウトガスをコントロールすることによって基板の膨れを防止する技術に関する。   The present invention relates to a multilayer printed wiring board, and relates to a technique for preventing a board from swelling by controlling an outgas generated in a soldering process performed during component mounting.

多層プリント配線板に部品を実装して、その部品と外層回路の配線パターンとを電気的かつ機械的に接合するために半田付けの工程に通される。量産時によく用いられる代表的な自動半田付け方法の一つとして、半田ペースト印刷等により予め基板上に必要量のはんだを付与しておき、遠赤外線や熱風循環方式等のリフロー炉内に基板を通過させることにより基板上の半田を加熱して溶融させる方法が知られている。この方法では、多層プリント配線板は半田融点以上の温度に耐える半田耐熱性が要求される。   A component is mounted on the multilayer printed wiring board, and is passed through a soldering process in order to electrically and mechanically join the component and the wiring pattern of the outer layer circuit. As one of the typical automatic soldering methods often used in mass production, a necessary amount of solder is applied to the substrate in advance by solder paste printing or the like, and the substrate is placed in a reflow furnace such as a far infrared ray or hot air circulation method. A method is known in which the solder on the substrate is heated and melted by passing it through. In this method, the multilayer printed wiring board is required to have solder heat resistance that can withstand a temperature higher than the solder melting point.

しかし、導体層間に用いられる絶縁性基材や接着材によっては半田耐熱性が劣るものがあり、半田付け工程の加熱の際にアウトガスの発生によって層間膨れ等の異常が出やすい傾向がある。特に、アースやシールド、その他各種補強用などとして、回路形成部以外に、連続して広い面積に導体層が形成されている領域(本発明ではこれを「回路未形成領域」という場合がある。)において膨れによる層間剥離が生じやすい。これは半田付け時における基板材料の加熱による分解ガスが発生することや、絶縁性基材や接着材に接している導体層の界面に吸着されていたガスが加熱により放出されること等が原因と考えられている。このようにして発生したガスの拡散が導体層に遮られるため、絶縁性基材、層間接着材、導体層の界面や層間接着材の内部で膨れが発生し、基板の異常や破壊の原因となるのである。   However, some insulating base materials and adhesives used between conductor layers have poor solder heat resistance, and there is a tendency that abnormalities such as expansion of the interlayer are likely to occur due to outgassing during heating in the soldering process. In particular, for grounding, shielding, and other various reinforcements, in addition to the circuit forming portion, a region where a conductor layer is continuously formed in a large area (in the present invention, this may be referred to as a “circuit non-forming region”). ) Is likely to cause delamination due to swelling. This is because decomposition gas is generated due to heating of the substrate material during soldering, or gas adsorbed on the interface of the conductor layer in contact with the insulating base material or adhesive is released by heating. It is believed that. Since the diffusion of the gas generated in this way is blocked by the conductor layer, the insulating base material, the interlayer adhesive, the interface of the conductor layer and the inside of the interlayer adhesive will swell, causing abnormalities and destruction of the substrate. It becomes.

このような膨れ、層間剥離を防止するために従来様々な対策が講じられており、従来技術としては例えば以下のようなものがある。
特許文献1には、内層及び外層に広い面積にわたって連続した状態で設けられた導体層の領域において、ピッチが0.1〜10mmの密集状態で点状、筋状、格子状の層間連結部を形成し、これらの層間連結部により、内層に設けられた内層べた導体層と外層に設けられた外層べた導体層とを一体的に結合することによって、半田付けの加熱時に発生するガスに対して層間の強固な結合状態を維持し、層間剥離を防止する方法が示されている。
特許文献2には、熱硬化性樹脂を含浸した合成樹脂繊維不織布の層を加熱加圧成形した積層板において、積層板の水分拡散係数を小さくする、具体的には1.3×10−8cm/秒以下とすることによって、リフロー炉内の熱で基板の層間剥離が起こらないようにする手法が示されている。
特開平11−214845号公報 特許第3339357号公報
Conventionally, various measures have been taken to prevent such swelling and delamination. Examples of conventional techniques include the following.
In Patent Document 1, in a region of a conductor layer provided in a continuous state over a large area on an inner layer and an outer layer, dot-like, streaky, and lattice-like interlayer coupling portions are formed in a dense state with a pitch of 0.1 to 10 mm. By forming and integrally connecting the inner solid conductor layer provided in the inner layer and the outer solid conductor layer provided in the outer layer by these interlayer connection portions, the gas generated during the heating of soldering can be prevented. A method for maintaining a strong bonded state between layers and preventing delamination is shown.
Patent Document 2 discloses that in a laminated plate obtained by heating and press-molding a synthetic resin fiber nonwoven fabric layer impregnated with a thermosetting resin, the moisture diffusion coefficient of the laminated plate is reduced, specifically 1.3 × 10 −8. A method is shown in which delamination of the substrate does not occur due to heat in the reflow furnace by setting it to cm 2 / sec or less.
JP-A-11-214845 Japanese Patent No. 3339357

しかし、特許文献1に示された手法によれば、層間連結部の形成は、内層べた導体層の上に、コーティングまたはラミネートによって外層の絶縁性樹脂を積層し、この積層した絶縁性樹脂の加工により絶縁性樹脂を貫通するバイアホール又はグルーブを多数形成し、これらバイアホール又はグルーブの内壁面に、外層べた導体層と共に導体層を形成して内層べた導体層と接続するという、複数の加工工程が必要である。このため、製造コストの大幅な増加が否めない上、絶縁性樹脂に対して導体層は、内層及び外層のべた導体層として形成されるため、半田付け時に発生するガスが絶縁性基材、層間接着材、導体層の界面や層間接着材の内部に滞留するという根本的な問題を解決するものではない。
また、特許文献2に示された手法によれば、使用できる絶縁材料が著しく限定されるため、応用範囲が限られており、また材料コストの増加も懸念される。
However, according to the technique disclosed in Patent Document 1, the interlayer connection portion is formed by laminating an insulating resin of the outer layer on the inner solid conductor layer by coating or laminating, and processing the laminated insulating resin. A plurality of via holes or grooves penetrating the insulating resin, and forming a conductor layer together with an outer solid conductor layer on the inner wall surface of these via holes or grooves and connecting to the inner solid conductor layer. is required. For this reason, a significant increase in manufacturing cost cannot be denied, and since the conductor layer is formed as a solid conductor layer of the inner layer and the outer layer with respect to the insulating resin, the gas generated during soldering is reduced to the insulating base material, the interlayer It does not solve the fundamental problem of staying at the interface between the adhesive and the conductor layer or inside the interlayer adhesive.
Further, according to the technique disclosed in Patent Document 2, since usable insulating materials are remarkably limited, the application range is limited, and there is a concern about an increase in material cost.

本発明は、上記事情に鑑みてなされたものであり、半田付け時に発生するガスに対して基板の膨れを防止し、半田耐熱性を向上させることが可能な多層プリント配線板を提供することを課題とする。   The present invention has been made in view of the above circumstances, and provides a multilayer printed wiring board capable of preventing swelling of a substrate against gas generated during soldering and improving solder heat resistance. Let it be an issue.

前記課題を解決するため、本発明は、少なくとも一層の導体層において、回路形成部以外の領域に、絶縁性基材上の導体が11mm以下のピッチで規則的に除去されたアウトガス拡散部を有することを特徴とする多層プリント配線板を提供する。
前記アウトガス拡散部の例としては、縦方向及び横方向の両方向について11mm以下のピッチで導体が規則的に除去された正方形の非導体部からなるもの、11mm以下のピッチで導体が規則的に除去された平行な筋状の非導体部からなるものが挙げられる。
In order to solve the above-mentioned problems, the present invention has an outgas diffusion portion in which conductors on an insulating substrate are regularly removed at a pitch of 11 mm or less in a region other than a circuit formation portion in at least one conductor layer. A multilayer printed wiring board is provided.
Examples of the outgas diffusion portion include a square non-conductor portion in which conductors are regularly removed at a pitch of 11 mm or less in both the vertical direction and the horizontal direction, and conductors are regularly removed at a pitch of 11 mm or less. And those composed of parallel, striped non-conductor portions.

本発明の多層プリント配線板は、少なくとも一層の導体層において、回路形成部以外の領域に、絶縁性基材上の導体が11mm以下のピッチで規則的に除去されたアウトガス拡散部を有するので、このアウトガス拡散部を通じてアウトガスを逃がすことができ、半田付け時に発生するガスが絶縁性基材、層間接着材、導体層の界面や層間接着材の内部に滞留して膨れの原因となるという根本的な問題を解決して、基板の膨れを確実に防止し、半田耐熱性を大幅に向上させることができる。   Since the multilayer printed wiring board of the present invention has an outgas diffusion portion in which the conductor on the insulating substrate is regularly removed at a pitch of 11 mm or less in a region other than the circuit formation portion in at least one conductor layer. The outgas can be released through this outgas diffusion part, and the gas generated during soldering stays in the insulating base material, interlayer adhesive, conductor layer interface and inside the interlayer adhesive and causes the swell. Therefore, it is possible to reliably prevent the substrate from swelling and to greatly improve the soldering heat resistance.

以下、最良の形態に基づいて本発明を説明する。
本発明は、絶縁層と導体層とが積層されて成る多層プリント配線板において、アースやシールド、その他各種補強用などとして、回路形成部以外に、連続して広い面積に導体層が形成されている領域(本発明ではこれを「回路未形成領域」という場合がある。)における基板の膨れを防止するため、回路未形成領域内に絶縁性基材上の導体が不存在とされた非導体部を11mm以下のピッチで規則的に形成してアウトガス拡散部を構成したことを特徴とする。
The present invention will be described below based on the best mode.
In the multilayer printed wiring board formed by laminating an insulating layer and a conductor layer, the present invention has a conductor layer formed continuously over a wide area in addition to a circuit forming portion for grounding, shielding, and other various reinforcements. In order to prevent the expansion of the substrate in the area where the circuit is present (in the present invention, this may be referred to as “circuit non-formation area”), the non-conductor in which the conductor on the insulating base material is not present in the circuit non-formation area The outgas diffusion part is configured by regularly forming the part with a pitch of 11 mm or less.

一般に銅箔等の導体層は気体透過性が低いため、連続して広い面積に導体層が存在すると、その領域においてアウトガスの拡散が阻止される。このため、絶縁性基材、層間接着材、導体層の界面や層間接着材の内部にアウトガスが滞留して膨れが発生し、基板の異常や破壊の原因となっていたのである。   In general, since a conductor layer such as a copper foil has low gas permeability, if a conductor layer exists continuously over a wide area, diffusion of outgas is prevented in that region. For this reason, the outgas stays in the interface of the insulating base material, the interlayer adhesive, and the conductor layer, and inside the interlayer adhesive, resulting in swelling and causing abnormalities and destruction of the substrate.

そこで本発明では、上述のように非導体部を規則的に形成したので、半田付け時に絶縁性基材等の樹脂層や接着材から発生するガスが樹脂層や接着材中を透過して拡散するとき、導体層を迂回して非導体部を通り抜け、最終的には多層プリント配線板の外部まで到達することができる。このように樹脂層や接着材の内部で発生したアウトガスの脱気が導体層で阻止されることがなく、ガスを自然に基板の外部へ放出させることができるので、基板に膨れを生じることがない。このように、アウトガスが絶縁性基材、層間接着材、導体層の界面や層間接着材の内部に滞留して膨れの原因となるという根本的な問題を解決して、基板の膨れを確実に防止し、半田耐熱性を大幅に向上させることができる。   Therefore, in the present invention, since the non-conductor portion is regularly formed as described above, the gas generated from the resin layer and the adhesive material such as the insulating base material permeates and diffuses through the resin layer and the adhesive material during soldering. When doing so, it can bypass the conductor layer, pass through the non-conductor portion, and finally reach the outside of the multilayer printed wiring board. In this way, the degassing of the outgas generated inside the resin layer or the adhesive is not blocked by the conductor layer, and the gas can be released naturally to the outside of the substrate, which may cause the substrate to swell. Absent. In this way, the fundamental problem that outgas stays in the insulating base material, interlayer adhesive, conductor layer interface and inside the interlayer adhesive and causes the swelling is solved, and the swelling of the substrate is ensured. And can greatly improve solder heat resistance.

本発明で用いられる基板材料には特に制限はない。銅張積層板(CCL)としては、絶縁性樹脂層に銅箔が直接積層された2層材のCCL、絶縁性樹脂層と銅箔とが接着材を介して接着された3層材のCCLのいずれでも使用することができる。絶縁性基材の材料としては、例えばポリイミド、ポリエステル、液晶ポリマー等の絶縁性樹脂が挙げられるが、特にこれらに限定されるものではない。
非導体部の形成方法は特に限定されないが、基板を回路形成するとき、回路形成と同時に、回路未形成領域となる領域の導体を部分的に除去して絶縁層を露出させた箇所を非導体部とする方法が好ましい。この手法によれば、加工工程の増加がなく、製造コストの増加が小さく済むという利点がある。
本発明の多層プリント配線板では、アウトガス拡散部は回路未形成領域に設けられるものであり、回路形成部については、特に制限するものではない。多層プリント配線板は2層以上の導体層を有するものである。本発明ではこれら導体層のうち、少なくとも一層の導体層において回路未形成領域にアウトガス拡散部が形成されていればよく、回路未形成領域が存在しないか、その面積が比較的小さい導体層については、アウトガス拡散部を設けなくとも良い。アウトガスの滞留を可能な限り抑制するため、好ましくは、すべての導体層において回路未形成領域にアウトガス拡散部を設けることが望ましい。
There is no restriction | limiting in particular in the board | substrate material used by this invention. As the copper clad laminate (CCL), a two-layer CCL in which a copper foil is directly laminated on an insulating resin layer, and a three-layer CCL in which the insulating resin layer and the copper foil are bonded via an adhesive. Any of these can be used. Examples of the material for the insulating substrate include insulating resins such as polyimide, polyester, and liquid crystal polymer, but are not particularly limited thereto.
The method of forming the non-conductor portion is not particularly limited, but when the circuit is formed on the substrate, at the same time as the circuit is formed, the conductor in the region that becomes the circuit non-formation region is partially removed to expose the insulating layer. The method of making parts is preferred. According to this method, there is an advantage that there is no increase in processing steps and an increase in manufacturing cost is small.
In the multilayer printed wiring board of the present invention, the outgas diffusion part is provided in the circuit non-formation region, and the circuit formation part is not particularly limited. A multilayer printed wiring board has two or more conductor layers. In the present invention, it is sufficient that an outgas diffusion portion is formed in a circuit non-formation region in at least one of the conductor layers, and there is no circuit non-formation region or a conductor layer having a relatively small area. It is not necessary to provide an outgas diffusion part. In order to suppress the outgas stagnation as much as possible, it is preferable to provide an outgas diffusion portion in a circuit non-formation region in all the conductor layers.

回路未形成領域に設けられるアウトガス拡散部の構成について、図1及び図2を参照して説明する。図1及び図2は、多層プリント配線板において、回路未形成領域にアウトガス拡散部が設けられた導体層における回路未形成領域のみを部分的に拡大して示した図面である。図1(a)及び図2(a)は、アウトガス拡散部を形成する前の基板材料であって、絶縁性基材12、22上に導体層13、23を有する片面CCL11、21を示す断面図である。   The configuration of the outgas diffusion portion provided in the circuit non-formation region will be described with reference to FIGS. FIG. 1 and FIG. 2 are drawings in which only a circuit non-formation region in a conductor layer in which an outgas diffusion portion is provided in a circuit non-formation region is partially enlarged in a multilayer printed wiring board. FIG. 1A and FIG. 2A are cross-sectional views showing single-sided CCLs 11 and 21 having conductor layers 13 and 23 on insulating base materials 12 and 22 as substrate materials before forming an outgas diffusion portion. FIG.

回路未形成領域に形成されるアウトガス拡散部の構成の一例としては、図1(b)及び図1(c)に示すように、多層プリント配線板10を構成する各基板11の回路未形成領域において絶縁性基材12上の導体層13を除去して、基板面に沿う互いに垂直な2方向(図1(b)では縦方向及び横方向の2方向)に正方形の非導体部14、14、…を多数配列した構成が挙げられる。この場合、導体層13によるガスの滞留を避けるため、非導体部14、14、…の縦方向のピッチP11と横方向のピッチP12の両方を11mm以下とすることが望ましい。これにより、導体の浮きや基板の膨れ(層間剥離)を防止する効果が優れた構成となる。
図1(b)において、縦方向のピッチP11とは、隣接する2つの非導体部14、14についての縦方向の中心間距離であり、横方向のピッチP12とは、隣接する2つの非導体部14、14についての横方向の中心間距離である。
As an example of the configuration of the outgas diffusion part formed in the circuit non-formation region, as shown in FIGS. 1B and 1C, the circuit non-formation region of each substrate 11 constituting the multilayer printed wiring board 10 In FIG. 1, the conductive layer 13 on the insulating base 12 is removed, and the non-conductor portions 14 and 14 that are square in two directions perpendicular to each other along the substrate surface (two directions in the vertical direction and the horizontal direction in FIG. 1B). ,... Are arranged in a large number. In this case, to avoid accumulation of gas by the conductor layer 13, the non-conductor portion 14, 14, it is desirable to ... both longitudinal pitch P 11 and lateral pitch P 12 and 11mm below. Thereby, it becomes the structure excellent in the effect which prevents the floating of a conductor and the swelling (delamination) of a board | substrate.
In FIG. 1B, the vertical pitch P 11 is the distance between the centers of the two adjacent non-conductor portions 14, 14, and the horizontal pitch P 12 is the two adjacent pitches P 12 . The distance between the centers of the non-conductor portions 14 and 14 in the horizontal direction.

回路未形成領域に形成されるアウトガス拡散部の構成の別の例としては、図2(b)及び図2(c)に示すように、多層プリント配線板20を構成する各基板21の回路未形成領域において絶縁性基材22上の導体層23に平行な筋状の非導体部24、24、…を形成した構成が挙げられる。この場合、導体層23によるガスの滞留を避けるため、非導体部24、24、…のピッチPを11mm以下とすることが望ましい。これにより、導体の浮きや基板の膨れ(層間剥離)を防止する効果が優れた構成となる。
ここで、平行な筋状の非導体部24、24、…のピッチPとは、隣接する2つの非導体部24、24の中心間距離である。
As another example of the configuration of the outgas diffusion portion formed in the circuit non-formation region, as shown in FIGS. 2B and 2C, the circuit of each substrate 21 constituting the multilayer printed wiring board 20 is not formed. The structure which formed the stripe-like nonconductor parts 24, 24, ... parallel to the conductor layer 23 on the insulating base material 22 in the formation area is mentioned. In this case, to avoid accumulation of gas by the conductor layer 23, it is desirable to non-conductive area 24, 24, ... of the pitch P 2 of 11mm or less. Thereby, it becomes the structure excellent in the effect which prevents the floating of a conductor and the swelling (delamination) of a board | substrate.
Here, parallel streaks of the non-conductor portion 24, 24, ... and the pitch P 2 of a distance between the centers of two adjacent non-conductive area 24, 24.

なお、本発明における非導体部の形状は、正方形状や平行な筋状に限定されるものではなく、正方形状を変形した形状、平行な筋状を変形した形状などを採用することも可能である。   In addition, the shape of the non-conductor portion in the present invention is not limited to a square shape or a parallel stripe shape, and a shape obtained by deforming a square shape, a shape obtained by deforming a parallel stripe shape, or the like can also be adopted. is there.

回路未形成領域に規則的に非導体部を設けた片面基板11、21の積層方法は特に限定されないが、例えば図1(d)、図2(d)に示すように、接着材15、25を挟み込んで熱及び圧力で積層一体化することにより、図1(e)、図2(e)に示す多層プリント配線板10、20を製造することができる。本発明の多層プリント配線板10、20において基板11、21を積層する枚数や、回路の層数などは特に限定されない。   The method of laminating the single-sided substrates 11 and 21 in which non-conductor portions are regularly provided in the circuit non-formation region is not particularly limited. For example, as shown in FIGS. 1 (d) and 2 (d), the adhesives 15 and 25 The multilayer printed wiring boards 10 and 20 shown in FIG. 1 (e) and FIG. 2 (e) can be manufactured by stacking and integrating them with heat and pressure. In the multilayer printed wiring boards 10 and 20 of the present invention, the number of stacked substrates 11 and 21 and the number of circuit layers are not particularly limited.

本実施例では、図5に示すように、回路形成部1a及び回路未形成領域1bを有する第1の基板1と、回路形成部2a及び回路未形成領域2bを有する第2の基板2を作製し(図5の上部参照)、これらの基板1、2を位置合わせして積層し、回路形成部2aにおいては回路が層間導通(図示省略)された2層の多層プリント配線板3を作製した(図5の下部参照)。各基板1、2において、回路形成部1a、2aと回路未形成領域1b、2bとの間は、短絡防止のため銅箔除去部1c、2cにより所定以上の導体間隙が確保されている。   In this embodiment, as shown in FIG. 5, a first substrate 1 having a circuit formation portion 1a and a circuit non-formation region 1b and a second substrate 2 having a circuit formation portion 2a and a circuit non-formation region 2b are produced. (See the upper part of FIG. 5), these substrates 1 and 2 are aligned and laminated, and in the circuit forming portion 2a, a two-layered multilayer printed wiring board 3 in which the circuit is interlayer-conductive (not shown) is produced. (See the lower part of FIG. 5). In each of the substrates 1 and 2, between the circuit forming portions 1a and 2a and the circuit non-forming regions 1b and 2b, a predetermined or larger conductor gap is secured by the copper foil removing portions 1c and 2c to prevent a short circuit.

(実施例1)
以下に、回路未形成領域が格子状となるように等ピッチで正方形状の非導体部を設けた例を示す(回路未形成領域については、図1参照)。
Example 1
In the following, an example is shown in which square non-conductor portions are provided at equal pitches so that the circuit non-formation region has a lattice shape (see FIG. 1 for the circuit non-formation region).

・基板構成(片面基板/接着シート/片面基板)
片面CCL11:ポリイミド12の厚さ25μm、片面銅箔13の厚さ25μm
接着シート15:アクリル系接着シート、シート厚25μm(デュポン株式会社製、商品名:パイララックスLF)
非導体部14のピッチ:縦方向P11及び横方向P12;0.1mm、0.5mm、1mm、1.5mm、2mm、2.5mm、3mm、3.5mm、4mm、4.5mm、5mm、5.5mm、6mm、6.5mm、7mm、7.5mm、8mm、8.5mm、9mm、9.5mm、10mm、10.5mm、11mm、11.5mm、12mm、12.5mm、13mm、13.5mm、14mm、14.5mm、15mm
・ Substrate configuration (single-sided substrate / adhesive sheet / single-sided substrate)
Single-sided CCL11: polyimide 12 thickness 25 μm, single-sided copper foil 13 thickness 25 μm
Adhesive sheet 15: acrylic adhesive sheet, sheet thickness 25 μm (manufactured by DuPont, trade name: Piralux LF)
Pitch of non-conductor portion 14: longitudinal direction P 11 and transverse direction P 12 ; 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm 5.5 mm, 6 mm, 6.5 mm, 7 mm, 7.5 mm, 8 mm, 8.5 mm, 9 mm, 9.5 mm, 10 mm, 10.5 mm, 11 mm, 11.5 mm, 12 mm, 12.5 mm, 13 mm, 13 .5mm, 14mm, 14.5mm, 15mm

・基板作製手順
(1) 図1(a)に示すように、ポリイミド12及び片面銅箔13より構成される片面CCL11を用意する。
(2) 上記片面CCL11をパターン形成して、回路形成部に回路を形成すると同時に、回路未形成領域が格子状になるように、ポリイミド12上の片面銅箔13に等ピッチでアウトガス拡散部となる正方形の非導体部14、14、…を規則的に形成する(P11=P12)。図1(b)は回路未形成領域の部分拡大平面図、図1(c)は図1(b)に示す基板をA−A線に沿って切断した場合の断面図である。
(3) 上の(1)〜(2)と全く同様の方法で回路及びアウトガス拡散部を形成した別の片面基板11を用意し、一方の片面基板11のポリイミド12面と他方の片面基板11の導体13面とを対向させ、接着シート15を挟んで積層し、実施例1に係る多層プリント配線板10を得る(図1(d)、(e)参照)。
-Board | substrate preparation procedure (1) As shown to Fig.1 (a), single-sided CCL11 comprised from the polyimide 12 and the single-sided copper foil 13 is prepared.
(2) The single-sided CCL 11 is patterned to form a circuit in the circuit-forming portion, and at the same time, the out-gas diffusion portion and the single-sided copper foil 13 on the polyimide 12 are arranged at an equal pitch so that the circuit-unformed region has a lattice shape. Are formed regularly (P 11 = P 12 ). FIG. 1B is a partially enlarged plan view of a circuit non-formed region, and FIG. 1C is a cross-sectional view of the substrate shown in FIG. 1B cut along the line AA.
(3) Another single-sided substrate 11 having a circuit and an outgas diffusion portion formed thereon is prepared in the same manner as (1) and (2) above, and the polyimide 12 side of one single-sided substrate 11 and the other single-sided substrate 11 are prepared. The multi-layer printed wiring board 10 according to the first embodiment is obtained (see FIGS. 1D and 1E).

(実施例2)
以下に、回路未形成領域に一方向に沿って平行な筋状の非導体部を設けた例を示す(回路未形成領域については、図2参照)。
(Example 2)
In the following, an example is shown in which a line-shaped non-conductor portion parallel to one direction is provided in a circuit non-formation region (see FIG. 2 for the circuit non-formation region).

・基板構成(片面基板/接着シート/片面基板)
片面CCL21:ポリイミド22の厚さ25μm、片面銅箔23の厚さ25μm
接着シート25:アクリル系接着シート、シート厚25μm(デュポン株式会社製、商品名:パイララックスLF)
非導体部24のピッチP:0.1mm、0.5mm、1mm、1.5mm、2mm、2.5mm、3mm、3.5mm、4mm、4.5mm、5mm、5.5mm、6mm、6.5mm、7mm、7.5mm、8mm、8.5mm、9mm、9.5mm、10mm、10.5mm、11mm、11.5mm、12mm、12.5mm、13mm、13.5mm、14mm、14.5mm、15mm
・ Substrate configuration (single-sided substrate / adhesive sheet / single-sided substrate)
Single-sided CCL21: polyimide 22 thickness 25 μm, single-sided copper foil 23 thickness 25 μm
Adhesive sheet 25: acrylic adhesive sheet, sheet thickness 25 μm (manufactured by DuPont, trade name: Piralux LF)
Pitch P 2 of non-conductor portion 24: 0.1 mm, 0.5 mm, 1 mm, 1.5 mm, 2 mm, 2.5 mm, 3 mm, 3.5 mm, 4 mm, 4.5 mm, 5 mm, 5.5 mm, 6 mm, 6 .5mm, 7mm, 7.5mm, 8mm, 8.5mm, 9mm, 9.5mm, 10mm, 10.5mm, 11mm, 11.5mm, 12mm, 12.5mm, 13mm, 13.5mm, 14mm, 14.5mm , 15mm

・基板作製手順
(1) 図2(a)に示すように、ポリイミド22及び片面銅箔23より構成される片面CCL21を用意する。
(2) 上記片面CCL21をパターン形成して、回路形成部に回路を形成すると同時に、回路未形成領域において、一方向に沿って平行な筋状のアウトガス拡散部となる非導体部14、14、…を規則的に形成する。図2(b)は回路未形成領域の部分拡大平面図、図2(c)は図2(b)に示す基板をB−B線に沿って切断した場合の断面図である。
(3) 上の(1)〜(2)と全く同様の方法で回路及びアウトガス拡散部を形成した別の片面基板21を用意し、一方の片面基板21のポリイミド22面と他方の片面基板21の導体23面とを対向させ、接着シート25を挟んで積層し、実施例2に係る多層プリント配線板20を得る(図2(d)、(e)参照)。
-Board | substrate preparation procedure (1) As shown to Fig.2 (a), the single-sided CCL21 comprised from the polyimide 22 and the single-sided copper foil 23 is prepared.
(2) A pattern is formed on the one-sided CCL 21 to form a circuit in the circuit forming portion, and at the same time, in the non-circuit forming region, non-conductor portions 14 and 14 that become parallel streaky outgas diffusion portions along one direction. ... are regularly formed. 2B is a partially enlarged plan view of a circuit non-formation region, and FIG. 2C is a cross-sectional view of the substrate shown in FIG. 2B cut along the line BB.
(3) Another single-sided substrate 21 in which a circuit and an outgas diffusion portion are formed in the same manner as in (1) and (2) above is prepared, and the polyimide 22 surface of one single-sided substrate 21 and the other single-sided substrate 21 The multilayer printed wiring board 20 according to the second embodiment is obtained (see FIGS. 2D and 2E).

(試験例)
上記の実施例1、2で作製した多層プリント配線板10、20について半田耐熱特性を調べるために吸湿リフロー試験を行った。試験条件は、JEDECの吸湿リフロー規格LEVEL3に準拠するものとした。
実施例1、2の基板を、温度30℃/相対湿度60%の条件下で192時間湿熱槽に静置した後、湿熱槽から取り出して15分後に260℃ピーク/20秒間の条件で遠赤外線リフロー炉に投入し、基板の膨れ箇所の数をカウントした。その結果をそれぞれ図3、図4に示す。
(Test example)
A moisture absorption reflow test was performed on the multilayer printed wiring boards 10 and 20 produced in Examples 1 and 2 in order to examine the solder heat resistance characteristics. The test conditions were based on JEDEC's moisture absorption reflow standard LEVEL3.
The substrates of Examples 1 and 2 were left in a wet heat bath at a temperature of 30 ° C./relative humidity of 60% for 192 hours, then taken out from the wet heat bath, and after 15 minutes, far infrared rays were applied at a peak of 260 ° C./20 seconds. The substrate was put into a reflow furnace, and the number of swelled portions of the substrate was counted. The results are shown in FIGS. 3 and 4, respectively.

実施例1の場合、図3に示すように、非導体部のピッチが12.5mm以上になると、リフロー後に基板の膨れが見られた。非導体部のピッチが0.1〜12mmの範囲では、リフロー後の基板の膨れが発生しなかった。
実施例2の場合、図4に示すように、非導体部のピッチが11.5mm以上になると、リフロー後に基板の膨れが見られた。非導体部のピッチが0.1〜11mmの範囲では、リフロー後の基板の膨れが発生しなかった。
以上の結果から、リフロー後に基板の膨れが発生せず、半田耐熱性に優れた基板とするためには、非導体部によるアウトガス拡散部のピッチを11mm以下にする必要がある。
In the case of Example 1, as shown in FIG. 3, when the pitch of the non-conductor portions was 12.5 mm or more, the substrate was swollen after reflow. When the pitch of the non-conductor portion is in the range of 0.1 to 12 mm, the substrate does not swell after reflow.
In the case of Example 2, as shown in FIG. 4, when the pitch of the non-conductor portions was 11.5 mm or more, the substrate was swollen after reflow. When the pitch of the non-conductor portion is in the range of 0.1 to 11 mm, the substrate does not swell after reflow.
From the above results, it is necessary to set the pitch of the outgas diffusion portion by the non-conductor portion to 11 mm or less in order to obtain a substrate that does not swell after reflow and has excellent solder heat resistance.

本発明の多層プリント配線板は、各種電気機器、電子機器などに利用することができる。   The multilayer printed wiring board of the present invention can be used for various electric devices, electronic devices and the like.

本発明の実施例1に係る多層プリント配線板の製造方法を工程順に示す図であり、(a)は基板材料となる銅張積層板を示す断面図、(b)は正方形の非導体部が形成された領域を示す基板の回路未形成領域の部分拡大平面図、(c)は(b)に示す基板のA−A線に沿う断面図、(d)は非導体部が形成された基板間に接着材を挟み込む状態を示す回路未形成領域における断面図、(e)は多層プリント配線板を示す回路未形成領域における断面図である。It is a figure which shows the manufacturing method of the multilayer printed wiring board which concerns on Example 1 of this invention in order of a process, (a) is sectional drawing which shows the copper clad laminated board used as a board | substrate material, (b) is a square nonconductor part. The partial enlarged plan view of the circuit non-formation area | region of the board | substrate which shows the formed area | region, (c) is sectional drawing which follows the AA line of the board | substrate shown in (b), (d) is a board | substrate with which the nonconductor part was formed Sectional drawing in the circuit non-formation area | region which shows the state which pinches | interposes an adhesive material in between, (e) is sectional drawing in the circuit non-formation area | region which shows a multilayer printed wiring board. 本発明の実施例2に係る多層プリント配線板の製造方法を工程順に示す図であり、(a)は基板材料となる銅張積層板を示す断面図、(b)は平行な筋状の非導体部が形成された領域を示す基板の回路未形成領域の部分拡大平面図、(c)は(b)に示す基板のB−B線に沿う断面図、(d)は非導体部が形成された基板間に接着材を挟み込む状態を示す回路未形成領域における断面図、(e)は多層プリント配線板を示す回路未形成領域における断面図である。It is a figure which shows the manufacturing method of the multilayer printed wiring board which concerns on Example 2 of this invention in order of a process, (a) is sectional drawing which shows the copper clad laminated board used as a board | substrate material, (b) is parallel stripe-like non- The partial enlarged plan view of the circuit non-formation area | region of the board | substrate which shows the area | region in which the conductor part was formed, (c) is sectional drawing in alignment with the BB line of the board | substrate shown in (b), (d) is a non-conductor part formed Sectional drawing in the circuit non-formation area | region which shows the state which pinches | interposes an adhesive material between the produced | generated boards, (e) is sectional drawing in the circuit non-formation area | region which shows a multilayer printed wiring board. 実施例1の試験結果であって、非導体部ピッチと膨れ箇所の数との関係を表すグラフである。It is a test result of Example 1, Comprising: It is a graph showing the relationship between a nonconductor part pitch and the number of swelling locations. 実施例2の試験結果であって、非導体部ピッチと膨れ箇所の数との関係を表すグラフである。It is a test result of Example 2, Comprising: It is a graph showing the relationship between a non-conductor part pitch and the number of swelling locations. 実施例で作製した多層プリント配線板及びこれを構成する2枚の基板を示す概略平面図である。It is a schematic plan view which shows the multilayer printed wiring board produced in the Example, and the two board | substrates which comprise this.

符号の説明Explanation of symbols

11…実施例1の基板における非導体部の縦方向のピッチ、P12…実施例1の基板における非導体部の横方向のピッチ、P…実施例2の基板における非導体部のピッチ、1,2…多層プリント配線板を構成する各基板、1a,2a…回路形成部、1b,2b…回路未形成領域、3…多層プリント配線板、10,20…多層プリント配線板、11,21…基板(片面CCL)、12,22…絶縁性基材(ポリイミド)、13,23…導体層(銅箔)、14,24…アウトガス拡散部(非導体部)、15,25…接着材(接着シート)。 P 11 ... Vertical pitch of the non-conductor portion in the substrate of Example 1, P 12 ... Horizontal pitch of the non-conductor portion in the substrate of Example 1, P 2 ... Pitch of the non-conductor portion in the substrate of Example 2 , 1, 2... Each substrate constituting the multilayer printed wiring board, 1a, 2a... Circuit forming portion, 1b, 2b... Circuit non-formation region, 3 ... multilayer printed wiring board, 10, 20 ... multilayer printed wiring board, DESCRIPTION OF SYMBOLS 21 ... Board | substrate (single-sided CCL), 12, 22 ... Insulating base material (polyimide), 13, 23 ... Conductor layer (copper foil), 14, 24 ... Outgas diffusion part (non-conductor part), 15, 25 ... Adhesive (Adhesive sheet).

Claims (3)

少なくとも一層の導体層において、回路形成部以外の領域に、絶縁性基材上の導体が11mm以下のピッチで規則的に除去されたアウトガス拡散部を有することを特徴とする多層プリント配線板。   A multilayer printed wiring board having an outgas diffusion portion in which a conductor on an insulating substrate is regularly removed at a pitch of 11 mm or less in a region other than the circuit formation portion in at least one conductor layer. 前記アウトガス拡散部は、基板面に沿う互いに垂直な2方向について11mm以下のピッチで導体が規則的に除去された正方形の非導体部からなるものであることを特徴とする請求項1に記載の多層プリント配線板。   The said outgas diffusion part consists of a square non-conductor part by which the conductor was regularly removed by the pitch of 11 mm or less about two mutually perpendicular directions along a substrate surface. Multilayer printed wiring board. 前記アウトガス拡散部は、11mm以下のピッチで導体が規則的に除去された平行な筋状の非導体部からなるものであることを特徴とする請求項1に記載の多層プリント配線板。   2. The multilayer printed wiring board according to claim 1, wherein the outgas diffusion portion is composed of parallel streaky non-conductor portions from which conductors are regularly removed at a pitch of 11 mm or less.
JP2006048005A 2006-02-24 2006-02-24 Multilayer printed wiring board Withdrawn JP2007227712A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062440A (en) * 2011-09-14 2013-04-04 Fujikura Ltd Printed board and manufacturing method of the same
JP2022000976A (en) * 2018-04-25 2022-01-04 株式会社村田製作所 substrate

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2013062440A (en) * 2011-09-14 2013-04-04 Fujikura Ltd Printed board and manufacturing method of the same
JP2022000976A (en) * 2018-04-25 2022-01-04 株式会社村田製作所 substrate
JP7136302B2 (en) 2018-04-25 2022-09-13 株式会社村田製作所 substrate

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