JP3049972B2 - Multilayer wiring board - Google Patents
Multilayer wiring boardInfo
- Publication number
- JP3049972B2 JP3049972B2 JP30094092A JP30094092A JP3049972B2 JP 3049972 B2 JP3049972 B2 JP 3049972B2 JP 30094092 A JP30094092 A JP 30094092A JP 30094092 A JP30094092 A JP 30094092A JP 3049972 B2 JP3049972 B2 JP 3049972B2
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- wiring board
- wiring pattern
- adhesive
- connection
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000000853 adhesive Substances 0.000 claims description 27
- 230000001070 adhesive effect Effects 0.000 claims description 27
- 238000007747 plating Methods 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 13
- 238000001020 plasma etching Methods 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 238000007788 roughening Methods 0.000 claims description 3
- 230000003746 surface roughness Effects 0.000 claims description 3
- 238000003486 chemical etching Methods 0.000 claims description 2
- 239000010410 layer Substances 0.000 description 11
- 238000000034 method Methods 0.000 description 11
- 239000004593 Epoxy Substances 0.000 description 9
- 239000002245 particle Substances 0.000 description 8
- 239000013039 cover film Substances 0.000 description 6
- 239000010408 film Substances 0.000 description 6
- 239000011888 foil Substances 0.000 description 6
- 238000003475 lamination Methods 0.000 description 6
- 239000000463 material Substances 0.000 description 6
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 4
- 230000010354 integration Effects 0.000 description 4
- 239000011229 interlayer Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- 238000003825 pressing Methods 0.000 description 3
- 229910001415 sodium ion Inorganic materials 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- 239000004642 Polyimide Substances 0.000 description 2
- 239000012790 adhesive layer Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000012787 coverlay film Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 239000000945 filler Substances 0.000 description 2
- 150000003949 imides Chemical class 0.000 description 2
- 239000011256 inorganic filler Substances 0.000 description 2
- 229910003475 inorganic filler Inorganic materials 0.000 description 2
- 238000010030 laminating Methods 0.000 description 2
- 229920000728 polyester Polymers 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- KXGFMDJXCMQABM-UHFFFAOYSA-N 2-methoxy-6-methylphenol Chemical compound [CH]OC1=CC=CC([CH])=C1O KXGFMDJXCMQABM-UHFFFAOYSA-N 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000003054 catalyst Substances 0.000 description 1
- 239000000919 ceramic Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 239000011889 copper foil Substances 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 239000007822 coupling agent Substances 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- -1 etc. Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 238000007429 general method Methods 0.000 description 1
- 239000003365 glass fiber Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000011344 liquid material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000004745 nonwoven fabric Substances 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920001568 phenolic resin Polymers 0.000 description 1
- 239000002985 plastic film Substances 0.000 description 1
- 229920006255 plastic film Polymers 0.000 description 1
- 229920003055 poly(ester-imide) Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 229920006267 polyester film Polymers 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000004576 sand Substances 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 239000012815 thermoplastic material Substances 0.000 description 1
- 238000012546 transfer Methods 0.000 description 1
- JOYRKODLDBILNP-UHFFFAOYSA-N urethane group Chemical group NC(=O)OCC JOYRKODLDBILNP-UHFFFAOYSA-N 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【0001】[0001]
【産業上の利用分野】本発明は、多層配線板の上下回路
の接続構造に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a structure for connecting upper and lower circuits of a multilayer wiring board.
【0002】[0002]
【従来の技術】多層配線板は、信号回路、電源、アース
回路等を内蔵できることから、配線の高密度化の有効な
方法として種々の電子機器に多用されている。従来の多
層印刷配線板の代表的製造法は、相互接続部以外をカバ
ーレイフィルム等で覆い絶縁性を得ながら、銅めっき等
により各層の配線パターンを相互に電気的に接続するこ
とが一般的に行われている。また、比較的新しい試みと
して、相互接続部以外をカバーレイフィルムやマスクフ
ィルム、レジストフィルム等(これらをカバーフィルム
と以下総称)で覆う等して絶縁性を得ながら、相互接続
部を導電粒子を分散した接着剤よりなる材料を用いて各
層の配線パターンを相互に接続することも提案(例えば
特開昭61−49499号公報や、特開平2−3659
3号公報)されており、この場合の導電粒子としてはは
んだ粒子が用いられている。2. Description of the Related Art A multilayer wiring board can incorporate a signal circuit, a power supply, an earth circuit, and the like, and is therefore often used in various electronic devices as an effective method for increasing the wiring density. A typical method of manufacturing a conventional multilayer printed wiring board is to cover the portions other than the interconnections with a coverlay film or the like and obtain electrical insulation, and electrically connect the wiring patterns of each layer to each other by copper plating or the like. It has been done. In addition, as a relatively new attempt, the interconnects are covered with conductive particles while obtaining insulation by covering other than the interconnects with a coverlay film, mask film, resist film, etc. (collectively referred to as cover films hereinafter). It has also been proposed to connect the wiring patterns of each layer to each other using a material made of a dispersed adhesive (for example, Japanese Patent Application Laid-Open No. 61-49499 and Japanese Patent Application Laid-Open No. 2-3659).
No. 3), and solder particles are used as the conductive particles in this case.
【0003】[0003]
【発明が解決しようとする課題】上記従来の方法はいず
れも、相互接続部以外をカバーフィルムで覆うため、多
層配線板とした時厚みの減少が図り難く薄型化の妨げと
なっており、またカバーフィルムを必要部にプレスする
ためコストアップの一因となっている。また配線パター
ンの相互接続法については、銅等でめっきする方法は複
雑なめっき工程が必要であり、またカバーフィルムを熱
圧着する時に銅めっきを破壊しやすい欠点がある。導電
粒子と接着剤よりなる材料で接続する場合は、導電粒子
が接着中の全体に均一分散されているので接続時の熱圧
着により接着剤が流動し、配線パターンの接続を必要と
する部分以外でも導通してしまい、導電粒子がはんだの
場合は特に隣接配線パターンで溶融して連結しリークす
る等、ますます進行する配線の細線化に対応不可能とな
ってきた。本発明は、カバーフィルムやめっき工程が不
要で配線の細線化に対応可能な層間接続を用いた多層配
線板に関する。In any of the above-mentioned conventional methods, since the portions other than the interconnecting portions are covered with a cover film, it is difficult to reduce the thickness of a multilayer wiring board, which hinders the reduction in thickness. Pressing the cover film to the necessary part is one of the causes of cost increase. As for the interconnection method of the wiring patterns, the method of plating with copper or the like requires a complicated plating step, and has a disadvantage that the copper plating is easily broken when the cover film is thermocompressed. When connecting with a material consisting of conductive particles and an adhesive, since the conductive particles are uniformly dispersed throughout the bonding, the adhesive flows due to thermocompression bonding at the time of connection, and other than the parts that require connection of the wiring pattern However, when the conductive particles are solder, it becomes impossible to cope with the increasingly thinning of the wiring, especially when the conductive particles are melted and connected and leaked in the adjacent wiring pattern. The present invention relates to a multilayer wiring board using an interlayer connection which does not require a cover film or a plating step and can cope with thinning of wiring.
【0004】[0004]
【課題を解決するための手段】本発明は、絶縁基板に配
線パターンを形成してなる複数枚以上の両面配線板間
の、対向する配線パターンの少なくとも一方が基板面か
ら突出して他の配線板の配線パターンと接触し、接続を
要する配線パターン以外の対向配線板間が接着剤で積層
一体化してなる多層配線板に関するものである。すなわ
ち、本発明は、絶縁基板に配線パターンを形成してなる
複数枚以上の両面配線板の両面配線パターンの少なくと
も一方が基板上から突出して他の配線板の配線パターン
と接触し、接続を要する配線パターン以外の対向配線板
間が接着剤で積層一体化してなる多層印刷配線板であっ
て、配線パターンの少なくとも一方の表面が表面粗さで
0.2〜20μmの微小凹凸面を、配線パターン形成時
のめっきの粒界構造、薬液やプラズマによるエッチン
グ、機械的研磨による粗化、配線パターンへの微小凹凸
面の加圧刻印により形成したものであり、接着剤が基材
を含まないものである多層印刷配線板。 According to the present invention, at least one of opposing wiring patterns between a plurality of double-sided wiring boards each having a wiring pattern formed on an insulating substrate is protruded from the substrate surface and the other wiring board is formed. The present invention relates to a multilayer wiring board in which opposing wiring boards other than wiring patterns which need to be connected and contact with the above wiring pattern are laminated and integrated with an adhesive. Sand
That is, the present invention comprises forming a wiring pattern on an insulating substrate.
Minimize double-sided wiring patterns on multiple double-sided wiring boards
One of them protrudes from the board and the wiring pattern of the other wiring board
Opposite wiring board other than wiring pattern that needs to be connected
A multi-layer printed wiring board that is laminated and integrated with an adhesive
At least one surface of the wiring pattern has a surface roughness
When forming a fine uneven surface of 0.2 to 20 μm
Grain structure of plating, chemical etching and plasma etching
Roughness, roughening due to mechanical polishing, fine irregularities on the wiring pattern
It is formed by pressure stamping on the surface, and the adhesive is
A multilayer printed wiring board which does not contain any.
【0005】本発明の構成を図面を参照しながら説明す
る。図1は、本発明の一実施例を説明する断面模式図で
ある。1は絶縁基板であり、フェノール樹脂、エポキシ
樹脂、ポリイミド等を、紙、ガラス布、ガラス不織布、
等の基材に含浸し加熱加圧したものや、ポリエステルや
ポリイミド等のプラスチックフィルム、AlやFe等の
金属、及びセラミックス等がある。The configuration of the present invention will be described with reference to the drawings. FIG. 1 is a schematic sectional view illustrating an embodiment of the present invention. Reference numeral 1 denotes an insulating substrate made of phenolic resin, epoxy resin, polyimide, etc., paper, glass cloth, glass nonwoven fabric,
Or the like, which is impregnated into a base material such as polyester, heated and pressed, a plastic film such as polyester or polyimide, a metal such as Al or Fe, and a ceramic.
【0006】配線パターン2は、図1のように絶縁基板
1の両面に形成するが、多層配線板を構成したときの最
外層は配線パターンのない片面板でも良い。対向する配
線パターン2は図1のように基板面から少なくとも一方
が突出することが必要である。他の対向する配線パター
ンは突出状や、図2の2’に示すように平面状や、図示
してないが凹面状等いずれでも良い。接続後の配線パタ
ーンの高さが均一な平面状となることが、接続部の信頼
性向上の点から好ましい。これらの配線パターンは、テ
ンティング法、アディティブ法、及び転写法等の一般手
段で形成できる。 配線パターンの少なくとも接続を必
要とする表面は、微小凹凸であることが好ましい。この
微小凹凸を得る方法としては例えば、配線パターン形成
時のめっきの粒界構造、薬液やプラズマ等によるエッチ
ング、機械的研磨による粗化、及び配線パターンへの微
小凹凸面の加圧刻印、等を例示出来る。凹凸は、表面粗
さで0.2〜20μm程度が好ましい。0.2μm以下
では接触界面からの接着剤が排除し難く十分な配線パタ
ーン同士の接触が得られない。20μm以上では精度の
高い凹凸を形成し難く、また細線接続も得にくい。これ
らのことから0.5〜10μmがより好ましい。The wiring pattern 2 is formed on both sides of the insulating substrate 1 as shown in FIG. 1, but the outermost layer when a multilayer wiring board is formed may be a single-sided board without a wiring pattern. It is necessary that at least one of the opposed wiring patterns 2 protrudes from the substrate surface as shown in FIG. The other opposing wiring pattern may be in a protruding shape, a flat shape as shown by 2 'in FIG. 2, or a concave shape (not shown). It is preferable that the height of the wiring pattern after connection be uniform and planar, from the viewpoint of improving the reliability of the connection portion. These wiring patterns can be formed by general means such as a tenting method, an additive method, and a transfer method. It is preferable that at least the surface of the wiring pattern that requires connection has minute irregularities. Examples of the method of obtaining the fine irregularities include a grain boundary structure of plating at the time of forming a wiring pattern, etching with a chemical solution or plasma, roughening by mechanical polishing, and pressure stamping of a fine irregularity surface on a wiring pattern. Can be illustrated. The unevenness is preferably about 0.2 to 20 μm in surface roughness. When the thickness is less than 0.2 μm, the adhesive from the contact interface is hardly removed, and sufficient contact between the wiring patterns cannot be obtained. If it is 20 μm or more, it is difficult to form highly accurate unevenness, and it is also difficult to obtain a fine wire connection. For these reasons, the thickness is more preferably 0.5 to 10 μm.
【0007】絶縁基板1と配線パターン2の間に接着層
が存在しても良い。接着層が存在すると、接続時にクッ
ション層として作用し接続部が均一となり好ましい。層
間接続法は、接続を必要とする配線パターン2を有する
第1及び第2の配線板3、4の間に、接着剤5を配置し
接着剤で積層一体化し、2つの回路基板同士を接着する
と共に、これらの接続を必要とする配線パターン間の電
気的導通を得るものである。ここに接続を必要とする配
線パターン2は、パターン全体でもパターンの一部でも
良く、接続面に接続不要配線パターン6(例えばバイア
ホール部)が存在しても良い。[0007] An adhesive layer may exist between the insulating substrate 1 and the wiring pattern 2. The presence of the adhesive layer is preferable because it acts as a cushion layer at the time of connection and the connection portion becomes uniform. In the interlayer connection method, an adhesive 5 is arranged between first and second wiring boards 3 and 4 having a wiring pattern 2 requiring connection, laminated and integrated with the adhesive, and the two circuit boards are bonded to each other. At the same time, electrical continuity between the wiring patterns requiring these connections is obtained. The wiring pattern 2 that needs to be connected here may be the entire pattern or a part of the pattern, and a connection-free wiring pattern 6 (for example, a via hole) may be present on the connection surface.
【0008】接着剤5は、図1のようにフィルム状で
も、図2に示すように例えば液状物を一方の配線パター
ン面に塗布や印刷等により形成したものでも良い。フィ
ルム状であると取扱いが容易で一定厚みの供給が可能で
あり、接着剤塗布作業が不要となり好適である。接着剤
5としては、シート等に用いられる熱可塑性材料や、
熱、光、電子線等のエネルギーによる硬化性材料が広く
適用出来る。多層配線板の耐熱性や耐湿性に優れること
から硬化性材料が好ましく、中でもエポキシ系接着剤や
イミド系接着剤は、分子構造上接着性や耐熱性に優れる
ことや硬化時間が広く設定出来ることから好ましい。The adhesive 5 may be in the form of a film as shown in FIG. 1 or may be formed by applying a liquid material to one of the wiring pattern surfaces by coating or printing as shown in FIG. When the film is in the form of a film, it is easy to handle and can be supplied at a constant thickness, so that it is not necessary to apply an adhesive, which is preferable. As the adhesive 5, a thermoplastic material used for a sheet or the like,
A curable material using energy such as heat, light, and an electron beam can be widely applied. Curable materials are preferred because they have excellent heat resistance and moisture resistance of the multilayer wiring board.Epoxy-based adhesives and imide-based adhesives have excellent adhesiveness and heat resistance due to their molecular structure, and can be set over a wide range of curing times. Is preferred.
【0009】エポキシ系接着剤は、例えば高分子量エポ
キシ、固形エポキシと液状エポキシ、ウレタンやポリエ
ステル、NBR等で変性したエポキシを主成分とし、硬
化剤や触媒、カップリング剤、フィラー等を添加してな
るものが一般的である。これら材料は、抽出水のNaイ
オンやClイオンが20ppm以下の高純度品である
と、多層配線板の耐電食性が向上することが好ましい。
従来から多層配線板に多用されているエポキシ系やイミ
ド系接着剤とガラス繊維等の無機フィラーよりなるプリ
プレグは、無機フィラーが配線パターン相互の接触の妨
げとなり導電性が十分得られず、また多層配線板とした
時厚みを薄くし難いので、本発明の実施には好ましくな
い。フィラーを含む場合は、少なくとも接続条件下で溶
融もしくは軟化するか、配線パターンの接続を必要とす
る表面の微小凹凸に埋まる等して、配線パターン相互の
接触の妨げとならないようにすべきである。The epoxy-based adhesive contains, for example, a high-molecular-weight epoxy, a solid epoxy and a liquid epoxy, an epoxy modified with urethane, polyester, NBR, or the like as a main component, and is added with a curing agent, a catalyst, a coupling agent, a filler, and the like. Is common. When these materials are high-purity products in which Na ions and Cl ions of the extraction water are 20 ppm or less, it is preferable that the electric corrosion resistance of the multilayer wiring board is improved.
Conventionally, a prepreg composed of an epoxy-based or imide-based adhesive and an inorganic filler such as glass fiber, which has been widely used for a multilayer wiring board, has a problem in that the inorganic filler hinders contact between wiring patterns and does not provide sufficient conductivity, and the multilayer Since it is difficult to reduce the thickness when the wiring board is used, it is not preferable for implementing the present invention. If a filler is included, it should be melted or softened at least under the connection conditions, or be buried in fine irregularities on the surface that requires connection of the wiring pattern, so as not to hinder contact between the wiring patterns. .
【0010】積層一体化に際しては、配線パターン面の
接続を必要とする部分を位置合わせし加熱加圧する。こ
の時積層を必要とする所定枚の配線板に例えば貫通孔を
形成しておきピン等で位置合わせするいわゆるピンラミ
ネーション法が好適であり、一体化の方法としては、プ
レスやロールラミネータ等の一般的な方法で良い。ピン
ラミネーション法の貫通孔をスルーホールめっきするこ
とや、導電性接着剤で充填することで、全層間の電気的
接続を得ることも出来る。At the time of lamination and integration, a portion of the wiring pattern surface that requires connection is positioned and heated and pressed. At this time, a so-called pin lamination method in which, for example, a through-hole is formed in a predetermined number of wiring boards that require lamination and alignment is performed with pins or the like is preferable. As a method of integration, a general method such as pressing or a roll laminator is used. Good way. Electrical connection between all layers can also be obtained by plating the through-holes of the pin lamination method with through-holes or filling them with a conductive adhesive.
【0011】図3は図1の構成の積層一体化後を示す断
面図である。加熱加圧により、配線パターン上の接続を
必要とする部分2−2’が接触して電気的接続を可能と
し、接着剤は流動して両基板1−1’間を充填して接着
する。接続不要配線パターン6は絶縁性が保たれる。こ
の層を任意に積層することで任意の多層配線板とするこ
とが出来る。接着剤の最適充填量は接着剤の厚みで管理
できるが、積層一体化により端部に流出させて不要部を
除去すると気泡の混入が少なく好ましい。FIG. 3 is a sectional view showing the structure of FIG. 1 after lamination and integration. Due to the heating and pressing, the portions 2-2 'on the wiring pattern which need to be connected come into contact with each other to enable electrical connection, and the adhesive flows to fill and bond between the two substrates 1-1'. The connection unnecessary wiring pattern 6 is kept insulative. By arbitrarily laminating this layer, an arbitrary multilayer wiring board can be obtained. Although the optimum filling amount of the adhesive can be controlled by the thickness of the adhesive, it is preferable that the unnecessary portion is removed by flowing out to the end by laminating and integrating, so that air bubbles are less mixed.
【0012】[0012]
【作用】本発明によれば、対向する配線パターンの少な
くとも一方が基板面から突出して他の配線パターンと接
触し相互接続部を形成し、接続を要する配線パターン以
外の対向配線板間が接着剤で積層一体化してなる。その
ため相互接続部以外の配線板面は絶縁性接着剤に接する
ためカバーフィルムが不要であり、隣接パターン間でリ
ークが発生しない。相互接続部は配線パターン同士の接
触により電気的接続を得ているのでめっきが不要であ
る。また配線パターン同士の接触であるため、接続部の
抵抗が低い。接続部は導電粒子を用いないので、熱圧着
の条件が広範囲に適用可能である。そのため接続抵抗が
安定化し信頼性も向上し回路の細線化に対応可能であ
り、加えて多層配線板の厚みの減少やコスト低減にも有
効な多層配線板が極めて容易に得られる。According to the present invention, at least one of the opposing wiring patterns protrudes from the substrate surface and comes into contact with another wiring pattern to form an interconnecting portion. To be laminated and integrated. Therefore, the surface of the wiring board other than the interconnecting portion is in contact with the insulating adhesive, so that a cover film is not required, and no leak occurs between adjacent patterns. Since the interconnections are electrically connected by contact between the wiring patterns, plating is unnecessary. Further, since the wiring patterns are in contact with each other, the resistance of the connection portion is low. Since the connecting portion does not use conductive particles, the conditions of thermocompression bonding can be widely applied. Therefore, the connection resistance is stabilized, the reliability is improved, and it is possible to cope with the thinning of the circuit. In addition, a multilayer wiring board which is effective in reducing the thickness and cost of the multilayer wiring board can be obtained very easily.
【0013】[0013]
【実施例】以下実施例でさらに詳細に説明するが、本発
明はこれに限定されない。また、説明を分かりやすくす
るため2枚の両面基板を層間接続した4層配線板につい
て述べるが、2枚の両面基板のうち1枚が片面基板でも
よく、4層をこえる多層配線板にも当然適用できる。The present invention will be described in more detail with reference to the following Examples, but it should not be construed that the present invention is limited thereto. In addition, for simplicity of description, a four-layer wiring board in which two double-sided boards are connected to each other will be described. However, one of the two double-sided boards may be a single-sided board, and a multilayer wiring board having more than four layers may be used. Applicable.
【0014】実施例1〜4 厚み0.2mmのガラスエポキシ基板の両面に接着剤1
0μmを介して銅箔18μmを形成してなる両面基板
を、パターン印刷及びエッチングを行った接続を必要と
する配線パターン面の異なる4種の配線板を用意した。
これらの接続を必要とする配線パターンの最小幅は50
μmであった。配線パターン面として、電解箔(Rz=
0.8μm、実施例1)、両面電解箔(Rz=7.3μ
m、実施例2)、圧延箔の表面Snめっき(Rz=3.
5μm、実施例3)、圧延箔の表面プラズマエッチング
(Rz=2.2μm、実施例4)、である。ここでRz
は、JIS.B0601の十点平均粗さ(基準長さ0.
8mm)である。ポリエステルフィルムを剥離剤処理し
たセパレータ上に、高分子量エポキシを主成分とする厚
み30μmの接着剤(純水で100℃10h抽出後の抽
出水のNaイオン、Clイオンがそれぞれ10ppm以
下)を形成した。前記配線板の一方の接続を必要とする
配線パターンと、他の配線パターンとを同じ処理面同士
を対向させ位置合わせして、ロールで軽く圧着後セパレ
ータを剥離し、他の配線板を位置合わせし、180℃3
0kg/cm2 で30分加熱加圧して接着剤を硬化し
た。端部の余剰部を除去して、2枚の両面基板を層間接
続した4層配線板を得た。実施例1〜4はいずれも十分
な層間接続特性を示した。接続部の断面を走査型電子顕
微鏡で観察したところ、配線パターン表面の凹凸が接触
していた。Examples 1-4 Adhesive 1 was applied to both sides of a glass epoxy substrate having a thickness of 0.2 mm.
With respect to a double-sided substrate having a copper foil of 18 μm formed through 0 μm, four types of wiring boards having different wiring pattern surfaces which require connection by pattern printing and etching were prepared.
The minimum width of the wiring pattern that requires these connections is 50
μm. Electrolytic foil (Rz =
0.8 μm, Example 1), double-sided electrolytic foil (Rz = 7.3 μm)
m, Example 2), surface Sn plating of a rolled foil (Rz = 3.
5 μm, Example 3) and surface plasma etching of the rolled foil (Rz = 2.2 μm, Example 4). Where Rz
Is JIS. B0601 10-point average roughness (reference length 0.
8 mm). An adhesive having a high molecular weight epoxy as a main component and having a thickness of 30 μm (each of Na ion and Cl ion of extracted water after extraction at 100 ° C. for 10 hours with pure water, each having a Na ion and a Cl ion of 10 ppm or less) was formed on a separator obtained by treating a polyester film with a release agent. . The wiring pattern that requires one connection of the wiring board and the other wiring pattern are aligned with the same processing surface facing each other, lightly pressed with a roll, the separator is peeled off, and the other wiring board is aligned. And 180 ℃ 3
0 kg / cm 2 For 30 minutes to cure the adhesive. Excess edge portions were removed to obtain a four-layer wiring board in which two double-sided boards were connected in layers. Examples 1 to 4 all showed sufficient interlayer connection characteristics. When the cross section of the connection portion was observed with a scanning electron microscope, the irregularities on the surface of the wiring pattern were in contact.
【0015】実施例5〜6 実施例1〜4と同様であるが、対向する配線パターンの
組合せを変えた。実施例5は実施例1の電解箔と、実施
例2の両面電解箔とを対向させた。実施例6は実施例1
の電解箔と、実施例3の表面Snめっきとを対向させ
た。実施例5〜6はいずれも十分な層間接続特性を示し
た。Examples 5 to 6 The same as Examples 1 to 4, but the combination of the wiring patterns facing each other was changed. In Example 5, the electrolytic foil of Example 1 was opposed to the double-sided electrolytic foil of Example 2. Example 6 is Example 1
And the surface Sn plating of Example 3 were opposed to each other. Examples 5 to 6 all showed sufficient interlayer connection characteristics.
【0016】[0016]
【発明の効果】以上のように本発明によれば、カバーフ
ィルムやめっき工程が不要で回路の細線化に対応可能で
あり、加えて多層配線板の厚みの減少やコスト低減にも
有効な接続信頼性が向上した多層配線板が極めて合理的
に容易に得られる。As described above, according to the present invention, a cover film and a plating step are not required, and it is possible to cope with thinning of a circuit, and in addition, a connection effective for reducing the thickness of a multilayer wiring board and reducing costs. A multilayer wiring board with improved reliability can be obtained very reasonably easily.
【図1】本発明の構成の一実施例を示す断面模式図であ
る。FIG. 1 is a schematic sectional view showing an embodiment of the configuration of the present invention.
【図2】本発明の構成の一実施例を示す断面模式図であ
る。FIG. 2 is a schematic sectional view showing an embodiment of the configuration of the present invention.
【図3】本発明の積層一体化後の一実施例を示す断面模
式図である。FIG. 3 is a schematic sectional view showing one embodiment of the present invention after lamination and integration.
1 絶縁基板 2 配線パターン 3 第1の配線板 4 第2の配線板 5 接着剤 6 接続不要配線パターン DESCRIPTION OF SYMBOLS 1 Insulating board 2 Wiring pattern 3 First wiring board 4 Second wiring board 5 Adhesive 6 Connection-free wiring pattern
───────────────────────────────────────────────────── フロントページの続き (72)発明者 太田 共久 茨城県下館市大字小川1500番地 日立化 成工業株式会社 下館研究所内 (72)発明者 山口 豊 茨城県下館市大字小川1500番地 日立化 成工業株式会社 下館研究所内 (56)参考文献 特開 昭54−44765(JP,A) 特開 平3−289195(JP,A) 特開 昭63−53994(JP,A) 特開 平2−226788(JP,A) (58)調査した分野(Int.Cl.7,DB名) H05K 3/46 ──────────────────────────────────────────────────の Continuing on the front page (72) Inventor Kyohisa Ota 1500 Oji Ogawa, Shimodate City, Ibaraki Pref.Hitachi Chemical Industry Co., Ltd. (56) References JP-A-54-44765 (JP, A) JP-A-3-289195 (JP, A) JP-A-63-53994 (JP, A) JP-A-2-226788 (JP, A) (58) Field surveyed (Int. Cl. 7 , DB name) H05K 3/46
Claims (1)
数枚以上の両面配線板の両面配線パターンの少なくとも
一方が基板上から突出して他の配線板の配線パターンと
接触し、接続を要する配線パターン以外の対向配線板間
が接着剤で積層一体化してなる多層印刷配線板であっ
て、配線パターンの少なくとも一方の表面が表面粗さで
0.2〜20μmの微小凹凸面を、配線パターン形成時
のめっきの粒界構造、薬液やプラズマによるエッチン
グ、機械的研磨による粗化、配線パターンへの微小凹凸
面の加圧刻印により形成したものであり、接着剤が基材
を含まないものである多層印刷配線板。 At least one of the double-sided wiring patterns of a plurality of double-sided wiring boards having a wiring pattern formed on an insulating substrate projects from the substrate and comes into contact with the wiring pattern of another wiring board, thereby requiring wiring. A multilayer printed wiring board in which opposing wiring boards other than patterns are laminated and integrated with an adhesive.
At least one surface of the wiring pattern has a surface roughness
When forming a fine uneven surface of 0.2 to 20 μm
Grain structure of plating, chemical etching and plasma etching
Roughness, roughening due to mechanical polishing, fine irregularities on the wiring pattern
It is formed by pressure stamping on the surface, and the adhesive is
A multilayer printed wiring board which does not contain any.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30094092A JP3049972B2 (en) | 1992-11-11 | 1992-11-11 | Multilayer wiring board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP30094092A JP3049972B2 (en) | 1992-11-11 | 1992-11-11 | Multilayer wiring board |
Publications (2)
Publication Number | Publication Date |
---|---|
JPH06152138A JPH06152138A (en) | 1994-05-31 |
JP3049972B2 true JP3049972B2 (en) | 2000-06-05 |
Family
ID=17890935
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP30094092A Expired - Fee Related JP3049972B2 (en) | 1992-11-11 | 1992-11-11 | Multilayer wiring board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP3049972B2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2006216754A (en) * | 2005-02-03 | 2006-08-17 | Sumitomo Bakelite Co Ltd | Circuit board and method of manufacturing the same |
JP5036591B2 (en) * | 2007-03-19 | 2012-09-26 | 京セラ株式会社 | Wiring board |
WO2011081129A1 (en) * | 2009-12-28 | 2011-07-07 | 株式会社メイコー | Method for manufacturing printed circuit substrate and method for manufacturing probe substrate using the same |
-
1992
- 1992-11-11 JP JP30094092A patent/JP3049972B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
JPH06152138A (en) | 1994-05-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP4392157B2 (en) | WIRING BOARD SHEET MATERIAL AND ITS MANUFACTURING METHOD, AND MULTILAYER BOARD AND ITS MANUFACTURING METHOD | |
JP2587596B2 (en) | Circuit board connecting material and method for manufacturing multilayer circuit board using the same | |
JPH0738222A (en) | Rigid-flexible circuit board and preparation thereof | |
WO2001045478A1 (en) | Multilayered printed wiring board and production method therefor | |
JP2001028483A (en) | Wiring board, multilayer wiring board, circuit component package, and manufacturing method of wiring board | |
KR19990013967A (en) | Wiring board and manufacturing method thereof | |
JPH05198946A (en) | Manufacture of multilayer printed circuit board | |
JP2004319962A (en) | Flex rigid printed wiring board and its manufacturing method | |
JP2004079773A (en) | Multilayer printed wiring substrate and its production method | |
JP2002246536A (en) | Method for manufacturing three-dimensional mounting package and package module for its manufacturing | |
JP2017135357A (en) | Printed wiring board and manufacturing method thereof | |
JP3049972B2 (en) | Multilayer wiring board | |
KR101281898B1 (en) | Multilayer printed wiring board and method for producing same | |
JP2004273575A (en) | Multilayer printed wiring board and its manufacturing method | |
JP2003318550A (en) | Laminated wiring board and multilayer wiring assembly, and method for manufacturing the same | |
JPH0794868A (en) | Multilayered wiring board and its manufacture | |
JP3173249B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
CN216087116U (en) | Through hole between wiring boards | |
JP3738536B2 (en) | Method for manufacturing printed wiring board | |
JP2002246745A (en) | Three-dimensional mounting package and its manufacturing method, and adhesive therefor | |
JP3324660B2 (en) | Multilayer wiring board and adhesive film used for it | |
JP3304061B2 (en) | Manufacturing method of printed wiring board | |
JP3324661B2 (en) | Multilayer wiring board | |
JPH09181452A (en) | Multilayer printed wiring board manufacturing method | |
JP3509315B2 (en) | Circuit board manufacturing method |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 8 Free format text: PAYMENT UNTIL: 20080331 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Year of fee payment: 9 Free format text: PAYMENT UNTIL: 20090331 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20100331 Year of fee payment: 10 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110331 Year of fee payment: 11 |
|
FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20110331 Year of fee payment: 11 |
|
LAPS | Cancellation because of no payment of annual fees |