JP2007208058A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve the problem that the formation of a highly reliable fine gate electrode has been made difficult while being accompanied by the fining of semiconductor processes. <P>SOLUTION: In addition to the top surface of the gate electrode 105, metal silicides 110 are formed on the side surfaces of the gate electrode 105 so as to be able to form the highly reliable gate electrode 105, even though the width of the gate electrode 105 is not increased to a desired largeness. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device that realizes a small area, high speed, and high reliability, and a manufacturing method thereof.

  In recent years, with the miniaturization of semiconductor processes, it has become more difficult to form a highly reliable fine gate electrode.

  A conventional semiconductor device having a dual gate structure uses a polysilicon electrode doped with an N-type impurity (for example, phosphorus) as a gate electrode of an N-type channel MOS transistor (hereinafter referred to as NMOS), and a P-type channel MOS transistor (hereinafter referred to as an NMOS transistor). A high performance MOS device is realized by using a polysilicon electrode doped with a P-type impurity (for example, boron) as a gate electrode of PMOS. However, at the boundary portion of the gate electrode extending over the N-type impurity doped region and the P-type impurity doped region, a region that is neither N-type nor P-type, or an intrinsic region in which both the N-type impurity and the P-type impurity are doped. Since there is a region, the resistance value becomes extremely high at the boundary between the N-type impurity doped region and the P-type impurity doped region, and it becomes difficult to supply a potential to both NMOS and PMOS with a single polysilicon electrode. ing.

  In addition, the processing dimension of the gate electrode is the smallest in a fine process, and the gate electrode has a high resistance, causing a reduction in the performance of the MOS transistor.

  To solve these problems, the upper surface of the polysilicon gate electrode and the surface of the source / drain diffusion layer are metal-silicided using titanium, cobalt, nickel, molybdenum, etc., so that the gate electrode is doped with N-type impurities. The resistance of the boundary between the region and the P-type impurity doped region and the thin-line gate electrode is reduced.

  However, with further miniaturization of the semiconductor process, when the minimum width of the gate electrode becomes 100 nm or less, peeling of the metal silicide due to interfacial stress, disconnection of the metal silicide due to local thermal aggregation, and a decrease in allowable current density When the reliability problem becomes obvious and the boundary between the N-type impurity doped region and the P-type impurity doped region of the gate electrode coincides with the location where the metal silicide is poorly formed, the device performance is improved by increasing the resistance of the gate electrode. There has been a problem that the yield is lowered due to a decrease or a gate electrode disconnection.

  A conventional semiconductor device will be described below with reference to the drawings. 5A and 5B are diagrams schematically showing the structure of a conventional semiconductor device. Specifically, FIG. 5A is a plan view showing only some components, and FIG. 5B is a view showing a cross section taken along the line A1-A1 'of FIG. 5A.

  First, in FIG. 5A, a region 201 (hereinafter referred to as an NMOS formation region) doped with an N-type impurity necessary for forming an NMOS on a substrate (not shown) and a PMOS are formed. A region 202 (hereinafter referred to as a PMOS formation region) doped with necessary P-type impurities, an NMOS source / drain diffusion layer 203 doped with N-type impurities, and a PMOS source / drain doped with P-type impurities. The drain diffusion layer 204, the gate electrode 205 constituting the complementary MOS transistor, the portion 206 where the gate electrode 205 is enlarged at the boundary region between the NMOS formation region 201 and the PMOS formation region 202, and the potential to the gate electrode 205 For this purpose, a through hole 207 and a gate electrode pad 208 are shown.

  Next, in FIG. 5B, a PMOS source / drain diffusion layer 204 doped with a P-type impurity, which is partitioned by an element isolation region 211 formed on a substrate (not shown), and a gate insulating film Gate electrode 205 formed on (not shown) and on element isolation region 211, sidewall 209 formed on the side surface of gate electrode 205, and PMOS source / drain diffusion doped with P-type impurities A metal silicide 210 formed on the upper surface of the layer 204 and the upper surface of the gate electrode 205 and a through hole 207 formed on the gate electrode 205 for supplying a potential to the gate electrode 205 are shown.

  Note that the conventional semiconductor device shown in FIG. 5B has a structure in which the sidewall 209 is formed on the side surface of the gate electrode 205, but the semiconductor device has a structure in which the sidewall 209 is not formed. Similarly, only the upper surface of the gate electrode 205 has a metal silicide structure.

  In the prior art shown in FIGS. 5A and 5B, by providing a portion 206 in which the gate electrode 205 is thickened to a desired width in the boundary region between the NMOS formation region 201 and the PMOS formation region 202, the metal silicide is formed. High resistance and disconnection of the gate electrode 205 due to poor formation are suppressed. Such a technique is described in Patent Document 1, for example.

Further, in the prior art shown in FIGS. 5A and 5B, when the through hole 207 is formed to supply a potential to the gate electrode 205, it corresponds to the misalignment between the gate electrode 205 and the through hole 207. The gate electrode 205 is thickened to a desired width for the purpose and for the purpose of reliably connecting the gate electrode 205 and the through hole 207 by suppressing the formation failure of the metal silicide at the connection portion between the gate electrode 205 and the through hole 207. The gate electrode pad 208 is formed.
JP 2001-77210 A

  However, the conventional semiconductor device has the following problems. In the conventional semiconductor device shown in FIGS. 5A and 5B, a schematic diagram when the gate electrode 205 is formed as an actual pattern is shown in FIG. 6, and the problem will be described using this.

  Specifically, an NMOS formation region 201, a PMOS formation region 202, an NMOS source / drain diffusion layer 203 formed of an N-type impurity diffusion region, and a PMOS layer formed of a P-type impurity diffusion region on a substrate (not shown). Source / drain diffusion layer 204, the actual finished shape 305 of the gate electrode constituting the complementary MOS transistor, and the region where the gate electrode 305 is thickened to a predetermined width in the boundary region between the NMOS formation region 201 and the PMOS formation region 202 306, a through hole 207 for supplying a potential to the gate electrode 305, and a gate electrode pad 308 are shown.

  Here, S31 indicates a distance between the NMOS source / drain diffusion layer 203 or the PMOS source / drain diffusion layer 204 and a portion 306 in which the gate electrode is thickened to a predetermined width, and S32 indicates the gate electrode is predetermined. The distance between the NMOS source / drain diffusion layer 203 and the PMOS source / drain diffusion layer 204 with the thickened portion 306 interposed therebetween is shown. S33 indicates the distance between the NMOS source / drain diffusion layer 203 or the PMOS source / drain diffusion layer 204 and the gate electrode pad 308.

  Due to the optical proximity effect and the difference in etching rate depending on the pattern shape, the finished shape of the gate electrode 305 has a rounded corner portion with respect to the layout pattern (the broken line portion of the gate electrode 305). In the conventional semiconductor device shown in FIG. 6, when the misalignment between the source / drain diffusion layers 203 and 204 and the gate electrode 305 occurs, the portion 306 where the gate electrode is thickened and the gate electrode pad portion 308 are rounded. The gate length of the MOS transistor fluctuates due to the influence of the banded portion, which causes an increase in variation in MOS transistor characteristics and a decrease in performance. In order to avoid this, it is necessary to set a sufficient distance in S31, S32 and 33 that does not affect the gate length of the MOS transistor. Therefore, in the conventional semiconductor device, the MOS transistor cannot be disposed in the vicinity of the portion 306 where the gate electrode is thickened and the gate electrode pad 308, which has been an obstacle to reducing the LSI area.

  In view of the above problems, an object of the present invention is to provide a semiconductor device corresponding to a fine process and a manufacturing method thereof, and in particular, a highly reliable gate electrode without increasing the width of the gate electrode. By forming, it is to realize high integration of LSI and reduction of area. At the same time, it is an object to realize high speed and high reliability of LSI.

  In order to achieve the above object, a semiconductor device according to the present invention includes a first conductor formed on a substrate, and a first conductor formed so as to be in contact with at least a part of an upper surface and a side surface of the first conductor. 2 conductors.

  In the conventional semiconductor device, the second conductor is connected only to the upper surface of the first conductor. For this reason, in order to suppress the formation failure of the second conductor, it is necessary to form the first conductor so as to have a desired width, and to secure a region for forming the second conductor. there were. In contrast, in the semiconductor device according to the present invention, the first conductor is formed to have a desired thickness by forming the second conductor on the side surface in addition to the upper surface of the first conductor. Even if the width is not increased, the first conductor and the second conductor that sufficiently satisfy the manufacturing standard can be formed, and high integration and reduction in area of the LSI can be realized. At the same time, high speed and high reliability of the LSI can be realized.

  In the semiconductor device according to the present invention, the first conductor includes a first part having an N-type conductor layer, a second part having a P-type conductor layer, a first part, and a second part. And a third part having a rectifying characteristic which becomes a PN junction region at the boundary between the first part and the second conductor is provided so as to straddle the third part, and the first part via the second conductor And the second part are electrically connected.

  In the conventional semiconductor device, the second conductor is connected to the upper surface of the first conductor regardless of the portion having the N-type conductor layer and the portion having the P-type conductor layer in the first conductor. It is formed so that. In the boundary region between the portion having the N-type conductor layer and the portion having the P-type conductor layer in the first conductor, that is, the PN junction region of the first conductor, the manufacturing standard of the first conductor In addition, it is necessary to satisfy stricter manufacturing standards that take into account the electrical characteristics of the PN junction region. Therefore, it is necessary to form the first conductor so that the PN junction region has a desired width. In contrast, in the semiconductor device according to the present invention, the second conductor is formed not only on the upper surface of the first conductor but also on the side surface so as to straddle the PN boundary region of the first conductor. As a result, it is possible to form the first conductor sufficiently satisfying the manufacturing standard without increasing the width of the first conductor to a desired thickness, and the high integration of the LSI and the reduction of the area can be achieved. Can be realized. At the same time, high speed and high reliability of the LSI can be realized.

  In the semiconductor device according to the present invention, the first conductor includes a first part having an N-type conductor layer, a second part having a P-type conductor layer, an intrinsic region or a non-doped region (N-type conductor). A third portion that is neither a layer nor a P-type conductor layer), and the second conductor is provided so as to straddle the third portion, and the first conductor via the second conductor. The part and the second part are electrically connected.

  In the conventional semiconductor device, the second conductor is connected to the upper surface of the first conductor regardless of the portion having the N-type conductor layer and the portion having the P-type conductor layer in the first conductor. It is formed so that. In addition, in the boundary portion between the portion having the N-type conductor layer and the portion having the P-type conductor layer in the first conductor, a region that is intrinsic due to the mutual diffusion of impurities, a non-doped state in which the impurities are not diffused, and In the third region where the resistance is increased in the region, it is necessary to satisfy a stricter manufacturing standard in consideration of electrical characteristics in addition to the manufacturing standard of the first conductor. Therefore, it is necessary to form the first conductor so that the third region which is an intrinsic region or a non-doped region and has a high resistance has a desired width, and a region for forming the first conductor is secured. There was a need. On the other hand, in the semiconductor device according to the present invention, the third region which is an intrinsic region or a non-doped region at the boundary between the portion having the N-type conductor layer and the portion having the P-type conductor layer of the first conductor. In addition to the top surface of the first conductor, the second conductor is formed on the side surface so as to straddle the first conductor without expanding the first conductor to a desired width. The first conductor that sufficiently satisfies the manufacturing standard can be formed, and high integration and reduction in area of the LSI can be realized. At the same time, high speed and high reliability of the LSI can be realized.

  The semiconductor device according to the present invention further includes a through hole for supplying a potential to the first conductor, and the through hole is located on the upper surface and the side surface of the first conductor on which the second conductor is formed. And is electrically connected to the second conductor.

  The conventional semiconductor device is formed so that the second conductor is connected only to the upper surface of the first conductor. In addition, in order to obtain a good electrical connection between the first conductor and the through-hole for supplying a potential to the first conductor, the first conductor is adjusted to have a desired width. It was necessary to secure a region for forming the conductor. On the other hand, in the semiconductor device according to the present invention, in the region connecting the through hole and the first conductor, the second conductor is provided not only on the upper surface of the first conductor but also on the side surface. By forming the first conductor, the through-hole and the first conductor can be electrically connected to each other without expanding the first conductor to a desired width. In addition, the area can be reduced. At the same time, high speed and high reliability of the LSI can be realized.

  In the semiconductor device according to the present invention, the first conductor is preferably a gate electrode made of polysilicon, and the second conductor is preferably a metal silicide made of titanium, cobalt, nickel, or molybdenum.

  Next, in order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a substrate, a step of forming a sidewall so as to cover a side surface of the gate electrode, The method includes a step of removing at least a part of the sidewall and a step of forming a metal silicide on the upper surface and side surfaces of the gate electrode.

  According to the method for manufacturing a semiconductor device according to the present invention, metal silicide is formed not only on the upper surface but also on the side surface of the gate electrode, thereby removing metal silicide due to interfacial stress and disconnection of metal silicide due to local thermal aggregation. It is possible to suppress the deterioration of the device performance due to the high resistance of the gate electrode and the reduction of the yield due to the disconnection.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode film on a substrate and a step of forming a P-type conductor layer at a first portion of the gate electrode film. A step of forming an N-type conductor layer on the second portion of the gate electrode film, a step of selectively etching the gate electrode film to form a gate electrode, and a sidewall so as to cover the side surface of the gate electrode Forming a PN junction region at a boundary region between the first region having the P-type conductor layer and the second region having the N-type conductor layer, and straddling the third region having the rectifying characteristic The method includes a step of removing a part of the wall and a step of forming a metal silicide on the upper surface and the side surface of the gate electrode from which the sidewall has been removed.

  According to the method for manufacturing a semiconductor device of the present invention, the third part having a rectifying characteristic becomes a PN junction region at the boundary between the first part having the P-type conductor layer and the second part having the N-type conductor layer. The metal silicide is formed not only on the top surface of the gate electrode but also on the side surface so as to straddle the gate electrode, thereby suppressing the separation of the metal silicide due to interface stress and the disconnection of the metal silicide due to local thermal aggregation. It is possible to prevent a decrease in device performance due to resistance and a decrease in yield due to disconnection.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode film on a substrate and a step of forming a P-type conductor layer at a first portion of the gate electrode film. A step of forming an N-type conductor layer on the second portion of the gate electrode film, a step of selectively etching the gate electrode film to form a gate electrode, and a sidewall so as to cover the side surface of the gate electrode Across the third region which is an intrinsic region or a non-doped region and has a high resistance at the boundary between the step of forming the first portion having the P-type conductor layer and the second portion having the N-type conductor layer. The method includes a step of removing a part of the sidewall and a step of forming a metal silicide on the upper surface and the side surface of the gate electrode from which the sidewall has been removed.

  According to the method for manufacturing a semiconductor device of the present invention, the intrinsic region or the non-doped region at the boundary between the first part having the P-type conductor layer and the second part having the N-type conductor layer becomes the high resistance. The metal silicide is formed not only on the upper surface but also on the side surface of the gate electrode so as to straddle the region of the gate electrode, thereby suppressing the separation of the metal silicide due to interfacial stress and the disconnection of the metal silicide due to local thermal aggregation. Therefore, it is possible to prevent a decrease in device performance due to an increase in resistance and a decrease in yield due to disconnection.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a gate electrode on a substrate, a step of forming a sidewall so as to cover a side surface of the gate electrode, A step of removing at least a part of the wall, a step of forming a metal silicide on the surface of the gate electrode, and a through hole for supplying a potential to the gate electrode are formed on the gate electrode that has been removed from the sidewall and is made of the metal silicide. And a step of forming it so as to be positioned.

  According to the method for manufacturing a semiconductor device according to the present invention, the upper surface and the side surface of the gate electrode connected to the through hole are converted into metal silicide. Therefore, it is possible to suppress the disconnection of the metal silicide due to the thermal aggregation, and to prevent the device performance from decreasing due to the high resistance of the junction between the through hole and the gate electrode, and the yield due to the disconnection.

  As described above, according to the present invention, a highly reliable conductor can be formed by covering the upper surface and the side surface of the first conductor with the second conductor. Furthermore, as a result, the connectivity between the conductor and the through hole can be improved. As a result, a highly reliable semiconductor device capable of reducing the area and increasing the speed can be realized, and such a semiconductor device can be manufactured.

<< First Embodiment >>
Hereinafter, a semiconductor device according to a first embodiment of the present invention will be described with reference to the drawings. First, the structure of the semiconductor device will be described.

  FIGS. 1A to 1C are diagrams schematically showing the structure of the semiconductor device of the first embodiment. Specifically, FIG. 1A is a plan view showing only some components, and FIG. 1B shows a cross section taken along line X1-X1 ′ of FIG. ) Is a view showing a cross section taken along line X2-X2 ′ of FIG. With reference to FIGS. 1A to 1C, the present embodiment including a MOS transistor will be described.

  First, the planar configuration of the semiconductor device according to the first embodiment of the present invention will be described. In FIG. 1A, an impurity diffusion region 100 constituting a source region and a drain region is formed on a substrate (not shown). A plurality of source / drain contacts (not shown) are formed on the impurity diffusion region 100 to electrically connect the wiring layer (not shown) and the impurity diffusion region 100.

  In addition, a plurality of gate electrodes 105 are formed on the impurity diffusion region 100 via a gate insulating film (not shown) made of, for example, SiON or the like, and a through hole 107 for supplying a potential to the gate electrode 105 is formed. Is formed. A wiring layer (not shown) is formed on the through hole 107 and is electrically connected to the gate electrode 105.

  Further, the MOS transistor is connected between the gate electrode wiring part 111 from the pad part of the gate electrode 105 to which the through hole 107 for supplying the potential to the MOS transistor is connected to the impurity diffusion region 100 and the gate electrode 105 as a wiring. The gate electrode wiring portion 112 is made of metal silicide (not shown) on the side surface of the gate electrode 105 in addition to the upper surface of the gate electrode 105 in order to improve the MOS transistor characteristics and increase the reliability. Is formed.

  Each gate electrode 105 is formed by using, for example, polysilicon, and the source / drain contact (not shown) and the through hole 107 are formed by burying tungsten or the like. The metal silicide (not shown) is formed using, for example, titanium, cobalt, nickel, molybdenum, or the like.

Next, a cross-sectional configuration of the semiconductor device according to the first embodiment of the present invention will be described. As shown in FIGS. 1B and 1C, an impurity diffusion region 100 is formed in a region partitioned by an element isolation region 108 made of, for example, SiO ₂ on a substrate (not shown).

Further, a gate insulating film (not shown) made of, for example, SiON or the like is formed on each impurity diffusion region 100, and the gate electrode 105 is formed via the gate insulating film (not shown) on the impurity diffusion region 100. Is formed. A side wall 109 made of, for example, SiO ₂ is formed on the side surface of the gate electrode 105.

  A gate electrode 105 and a sidewall 109 are also formed on each element isolation region 108 and connected to the gate electrode 105 on each impurity diffusion region 100.

  A metal silicide 110 is formed on the upper surface of the gate electrode 105 and the upper surface of the impurity diffusion region 100 constituting the source region and the drain region.

  In addition, an interlayer insulating film (not shown) is formed so as to cover the substrate (not shown), the impurity diffusion region 100, the element isolation region 108, and the gate electrode 105, and the through hole 107 has an interlayer insulating film (not shown). ) Is embedded in the opening.

  Here, as shown in FIG. 1C, the gate electrode wiring portion 111 from the pad portion of the gate electrode 105 to which the through hole 107 is connected to the impurity diffusion region 100, and the gate electrode 105 as a wiring are used for the MOS. The gate electrode wiring part 112 connecting the transistors is formed on the side surface of the gate electrode 105 for the purpose of improving the propagation characteristics of the potential to the MOS transistor and the purpose of improving the reliability of the gate electrode 105. The removed side wall 109 is removed or not formed, and the metal silicide 110 is formed on the side surface of the gate electrode 105 in addition to the upper surface of the gate electrode 105. Here, the metal silicide 110 is formed using, for example, titanium, cobalt, nickel, molybdenum, or the like.

  In the conventional semiconductor device, as shown in FIGS. 5A and 5B, the side surface of the gate electrode 205 is covered with the sidewall 209, and only the upper surface of the gate electrode 205 is covered with the metal silicide 210. It was.

  In contrast, in the semiconductor device according to the first embodiment of the present invention, the gate electrode wiring portion 111 from the pad portion of the gate electrode 105 to which the through hole 107 is connected to the impurity diffusion region 100 and the gate electrode 105 are used as wirings. By forming the metal silicide 110 on the side surface in addition to the upper surface of the gate electrode 105 with respect to the gate electrode wiring portion 112 that connects the MOS transistors by using the metal transistor 110, the formation layer of the metal silicide 110 is multifaceted. It is possible to form a highly conductive and highly reliable gate electrode without expanding the gate electrode 105 to a desired width, thereby reducing the LSI area, speeding up, and increasing reliability. realizable.

  Note that the semiconductor device of the present invention shown in FIGS. 1A to 1C has a structure in which the side wall 109 is formed on a part of the side surface of the gate electrode 105, but the side wall 109 is formed. Similarly, a semiconductor device having no structure may have a structure in which the metal silicide 110 is formed on the side surface in addition to the upper surface of the gate electrode 105.

Next, a method for manufacturing a semiconductor device according to the first embodiment of the present invention will be described. For example, the impurity diffusion region 100 and the element isolation region 108 are formed on a semiconductor substrate (not shown) by an element isolation technique using a selective oxidation method or the like through a predetermined lithography process. Next, after a predetermined lithography process, a gate insulating film (not shown) made of SiON or the like is formed, and then a gate electrode 105 made of polysilicon or the like is formed. Next, after an insulating film made of SiO ₂ or the like is formed so as to cover the gate electrode 105 by a CVD method or the like, a sidewall 109 is formed by anisotropic etching or the like. Next, through a predetermined lithography process, the gate electrode wiring portion 111 from the pad portion of the gate electrode 105 to which the through-hole 107 for supplying a potential is connected to the impurity diffusion region 100 and the gate electrode 105 as a wiring are used as a MOS. The metal silicide 110 is formed in a self-aligned manner after removing the sidewall 109 with the gate electrode wiring portion 112 connecting the transistors. Next, an interlayer insulating film (not shown) made of SiO ₂ or the like is formed by a CVD method or the like, then a through hole 107 is opened through a predetermined lithography process, and a desired melting point metal such as tungsten is buried. A semiconductor device is configured.

  As described above, the semiconductor device according to the first embodiment of the present invention shown in FIGS. 1A to 1C is manufactured.

<< Second Embodiment >>
Hereinafter, a semiconductor device according to a second embodiment of the present invention will be described with reference to the drawings. First, the structure of the semiconductor device will be described.

  2A to 2C are diagrams schematically showing the structure of the semiconductor device of this embodiment. Specifically, FIG. 2A is a plan view showing only some of the components, and FIG. 2B shows a cross section taken along line X3-X3 ′ of FIG. ) Is a view showing a cross section taken along line X4-X4 ′ of FIG. This embodiment including a MOS transistor will be described with reference to FIGS.

  First, the planar configuration of the semiconductor device according to the second embodiment of the present invention will be described. In FIG. 2A, an N-type impurity diffusion region 103 constituting an NMOS source region and drain region is formed in an NMOS formation region 101 on a substrate (not shown), and in the PMOS formation region 102. A P-type impurity diffusion region 104 constituting a source region and a drain region of the PMOS is formed. A plurality of source / drain contacts (not shown) are formed on the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104, respectively, and a wiring layer (not shown), the N-type impurity diffusion region 103, The p-type impurity diffusion region 104 is electrically connected.

  A plurality of gate electrodes 105 are formed on the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104 via a gate insulating film (not shown) made of, for example, SiON. A through hole (not shown) for supplying a potential is formed in. A wiring layer (not shown) is formed on the through hole (not shown), and the through hole (not shown) and the gate electrode 105 are electrically connected.

  The gate electrode 105 is formed so as to straddle the boundary 116 between the NMOS formation region 101 and the PMOS formation region 102, and the gate electrodes of the NMOS and PMOS are connected to each other using the gate electrode 105 as a wiring. Yes. Here, the gate electrode 105 formed so as to straddle the boundary 116 between the NMOS formation region 101 and the PMOS formation region 102 forms a PN junction having a rectifying characteristic at the boundary 116.

  Here, from the purpose of improving the conductivity of the PN junction having rectification characteristics at the boundary 116 between the NMOS formation region 101 and the PMOS formation region 102 and the purpose of improving the reliability of the gate electrode 105, the gate electrode wiring In the portion 113, metal silicide (not shown) is formed on the side surface of the gate electrode 105 in addition to the upper surface of the gate electrode 105.

  Each gate electrode 105 is formed using, for example, polysilicon, and the source / drain contact (not shown) and the through hole (not shown) are formed by embedding tungsten or the like. The metal silicide (not shown) is formed using, for example, titanium, cobalt, nickel, molybdenum, or the like.

Next, a cross-sectional configuration of the semiconductor device according to the second embodiment of the present invention will be described. As shown in FIGS. 2B and 2C, a P-type impurity diffusion region 104 partitioned by an element isolation region 108 made of, for example, SiO ₂ is formed in a PMOS formation region 102 on a substrate (not shown). Is formed.

Further, a gate insulating film (not shown) made of, for example, SiON or the like is formed on the P-type impurity diffusion region 104, and the gate is interposed via the gate insulating film (not shown) on the P-type impurity diffusion region 104. An electrode 105 is formed. A side wall 109 made of, for example, SiO ₂ is formed on the side surface of the gate electrode 105.

  A gate electrode 105 and sidewalls 109 are also formed on each element isolation region 108 on the N-type impurity diffusion region 103 and connected to the gate electrode 105 on the P-type impurity diffusion region 104.

  A metal silicide 110 is formed on the upper surface of the gate electrode 105 and the upper surfaces of the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104.

  An interlayer insulating film (not shown) is formed so as to cover the substrate (not shown), the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104, the element isolation region 108, and the gate electrode 105. A through hole (not shown) for supplying a potential to the electrode 105 is formed so as to bury tungsten or the like in an opening of an interlayer insulating film (not shown).

  Here, from the purpose of improving the conductivity of the PN junction having rectification characteristics at the boundary 116 between the NMOS formation region 101 and the PMOS formation region 102 and the purpose of improving the reliability of the gate electrode 105, the gate electrode wiring In the portion 113, the metal silicide 110 is formed on the side surface of the gate electrode 105 in addition to the upper surface of the gate electrode 105.

  In the conventional semiconductor device, as shown in FIGS. 5A and 5B, the side surface of the gate electrode 205 is covered with the sidewall 209, and only the upper surface of the gate electrode 205 is covered with the metal silicide 210. It was.

  In contrast, in the case of the semiconductor device according to the second embodiment of the present invention, in addition to the upper surface of the gate electrode 105 with respect to the gate electrode wiring portion 113 that connects the NMOS and PMOS using the gate electrode 105 as a wiring, By forming the metal silicide 110 also on the side surfaces, the formation layer of the metal silicide 110 can be multifaceted, and without increasing the gate electrode 105 to a desired width, the conductivity is high and the reliability is high. A gate electrode can be formed, and an LSI can be reduced in area, speeded up, and improved in reliability.

  2A to 2C, the sidewall 109 is formed on the side surface of the gate electrode 105, but the sidewall 109 is not formed. Similarly, the semiconductor device having the structure may have a structure in which the metal silicide 110 is formed on the side surface in addition to the upper surface of the gate electrode 105.

Next, a method for manufacturing a semiconductor device according to the second embodiment of the present invention will be described. For example, the impurity diffusion regions 103 and 104 and the element isolation region 108 are formed on a semiconductor substrate (not shown) by an element isolation technique using a selective oxidation method through a predetermined lithography process. Next, after forming a gate insulating film (not shown) made of SiON or the like and a conductive film made of polysilicon or the like, impurities are implanted into the impurity diffusion regions 103 and 104 by an ion implantation method or the like. After forming the P-type conductor layer, the gate electrode 105 is formed through a predetermined lithography process. Next, after an insulating film made of SiO ₂ or the like is formed so as to cover the gate electrode 105 by a CVD method or the like, a sidewall 109 is formed by anisotropic etching or the like. Next, impurities are implanted into the impurity diffusion regions 103 and 104 by ion implantation or the like to form the source / drain of the MOS transistor. Next, after a predetermined lithography process, the sidewall 109 in the region 113 straddling the boundary between the N-type conductor layer and the P-type conductor layer of the gate electrode 105 is removed, and then the metal silicide 110 is formed in a self-aligning manner. Next, an interlayer insulating film (not shown) made of SiO ₂ or the like is formed by a CVD method or the like, then a through hole 107 is opened through a predetermined lithography process, and a desired melting point metal such as tungsten is buried. A semiconductor device is configured.

  As described above, the semiconductor device according to the second embodiment of the present invention shown in FIGS. 2A to 2C is manufactured.

<< Third Embodiment >>
Hereinafter, a semiconductor device according to a third embodiment of the present invention will be described with reference to the drawings. First, the structure of the semiconductor device will be described.

  3A to 3C are views schematically showing the structure of the semiconductor device of this embodiment. Specifically, FIG. 3A is a plan view showing only some components, and FIG. 3B shows a cross section taken along line X5-X5 ′ of FIG. 3A, and FIG. ) Is a diagram showing a cross section taken along line X6-X6 ′ of FIG. With reference to FIGS. 3A to 3C, the present embodiment including a MOS transistor will be described.

  First, the planar configuration of the semiconductor device according to the third embodiment of the present invention will be described. In FIG. 3A, an N-type impurity diffusion region 103 constituting an NMOS source region and drain region is formed in an NMOS formation region 101 on a substrate (not shown), and in the PMOS formation region 102. A P-type impurity diffusion region 104 constituting a source region and a drain region of the PMOS is formed. A plurality of source / drain contacts (not shown) are formed on the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104, respectively, and a wiring layer (not shown), the N-type impurity diffusion region 103, The p-type impurity diffusion region 104 is electrically connected.

  A plurality of gate electrodes 105 are formed on the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104 via a gate insulating film (not shown) made of, for example, SiON. A through hole (not shown) for supplying a potential is formed in. A wiring layer (not shown) is formed on the through hole (not shown), and the through hole (not shown) and the gate electrode 105 are electrically connected.

  The gate electrode 105 is formed so as to straddle the boundary between the NMOS formation region 101 and the PMOS formation region 102, and the NMOS and PMOS gate electrodes are connected to each other using the gate electrode 105 as a wiring. Here, the gate electrode 105 formed so as to straddle the boundary between the NMOS formation region 101 and the PMOS formation region 102 is an intrinsic state due to the mutual diffusion of impurities at the boundary between the NMOS formation region 101 and the PMOS formation region 102. Alternatively, the high resistance region 115 which is not doped and is in a non-doped state is formed.

  Here, for the purpose of improving the conductivity of the high resistance region 115 at the boundary between the NMOS formation region 101 and the PMOS formation region 102 and the purpose of improving the reliability of the gate electrode 105, In addition to the upper surface of the gate electrode 105, metal silicide (not shown) is also formed on the side surface of the gate electrode 105.

  Each gate electrode 105 is formed, for example, using polysilicon or the like, and source / drain contacts (not shown) and through holes (not shown) are formed by embedding tungsten or the like. The metal silicide (not shown) is formed using, for example, titanium, cobalt, nickel, molybdenum, or the like.

Next, a cross-sectional configuration of the semiconductor device according to the third embodiment of the present invention will be described. As shown in FIGS. 3B and 3C, a P-type impurity diffusion region 104 partitioned by an element isolation region 108 made of, for example, SiO ₂ is formed in a PMOS formation region 102 on a substrate (not shown). Is formed.

Further, a gate insulating film (not shown) made of, for example, SiON or the like is formed on the P-type impurity diffusion region 104, and the gate is interposed via the gate insulating film (not shown) on the P-type impurity diffusion region 104. An electrode 105 is formed. A side wall 109 made of, for example, SiO ₂ is formed on the side surface of the gate electrode 105.

  A gate electrode 105 and sidewalls 109 are also formed on each element isolation region 108 on the N-type impurity diffusion region 103 and connected to the gate electrode 105 on the P-type impurity diffusion region 104.

  A metal silicide 110 is formed on the upper surface of the gate electrode 105 and the upper surfaces of the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104.

  An interlayer insulating film (not shown) is formed so as to cover the substrate (not shown), the N-type impurity diffusion region 103 and the P-type impurity diffusion region 104, the element isolation region 108, and the gate electrode 105. A through hole (not shown) for supplying a potential to the electrode 105 is formed so as to bury tungsten or the like in an opening of an interlayer insulating film (not shown).

  Here, at the boundary between the NMOS formation region 101 and the PMOS formation region 102, the gate electrode wiring portion 114 is used for the purpose of improving the conductivity of the high resistance region 115 and the purpose of improving the reliability of the gate electrode 105. The metal silicide 110 is formed on the side surface of the gate electrode 105 in addition to the upper surface of the gate electrode 105.

  In the conventional semiconductor device, as shown in FIGS. 5A and 5B, the side surface of the gate electrode 205 is covered with the sidewall 209, and only the upper surface of the gate electrode 205 is covered with the metal silicide 210. It was.

  In contrast, in the semiconductor device according to the third embodiment of the present invention, the gate electrode 105 is used as a wiring, and the gate electrode wiring portion 114 that connects the NMOS and the PMOS is not only the upper surface of the gate electrode 105 but also the side surface. In contrast, by forming the metal silicide 110, the formation layer of the metal silicide 110 can be multifaceted, and the gate electrode 105 has a high conductivity and high reliability without expanding the gate electrode 105 to a desired width. An electrode can be formed, and an LSI can be reduced in area, speeded up, and improved in reliability.

  3A to 3C, the sidewall 109 is formed on the side surface of the gate electrode 105, but the sidewall 109 is not formed. Similarly, the semiconductor device having the structure may have a structure in which the metal silicide 110 is formed on the side surface in addition to the upper surface of the gate electrode 105.

Next, a method for manufacturing a semiconductor device according to the third embodiment of the present invention will be described. For example, the impurity diffusion regions 103 and 104 and the element isolation region 108 are formed on a semiconductor substrate (not shown) by an element isolation technique using a selective oxidation method through a predetermined lithography process. Next, after forming a gate insulating film (not shown) made of SiON or the like and a conductive film made of polysilicon or the like, impurities are implanted into the impurity diffusion regions 103 and 104 by an ion implantation method or the like to form an N-type conductor layer. Then, after forming the P-type conductor layer, the gate electrode 105 is formed through a predetermined lithography process. Next, after an insulating film made of SiO ₂ or the like is formed so as to cover the gate electrode 105 by a CVD method or the like, a sidewall 109 is formed by anisotropic etching or the like. Next, impurities are implanted into the impurity diffusion regions 103 and 104 by ion implantation or the like to form the source / drain of the MOS transistor. Next, through a predetermined lithography process, the sidewalls 109 of the region 114 extending over the region 115 which has become an intrinsic semiconductor region or a non-doped region and has a high resistance at the boundary between the N-type conductor layer and the P-type conductor layer of the gate electrode 105 are removed. In addition, the metal silicide 110 is formed in a self-aligning manner. Next, an interlayer insulating film (not shown) made of SiO ₂ or the like is formed by a CVD method or the like, then a through hole 107 is opened through a predetermined lithography process, and a desired melting point metal such as tungsten is buried. A semiconductor device is configured.

  As described above, the semiconductor device according to the third embodiment of the present invention shown in FIGS. 3A to 3C is manufactured.

<< Fourth Embodiment >>
Hereinafter, a semiconductor device according to a fourth embodiment of the present invention will be described with reference to the drawings. First, the structure of the semiconductor device will be described.

  4A to 4C are views schematically showing the structure of the semiconductor device of the fourth embodiment. Specifically, FIG. 4A is a plan view showing only some of the components, and FIG. 4B shows a cross section taken along line X7-X7 ′ of FIG. 4A, and FIG. ) Is a diagram showing a cross section taken along line X8-X8 ′ of FIG. With reference to FIGS. 4A to 4C, the present embodiment including a MOS transistor will be described.

  First, the planar configuration of the semiconductor device according to the fourth embodiment of the present invention will be described. In FIG. 4A, an impurity diffusion region 100 constituting a source region and a drain region is formed on a substrate (not shown). A plurality of source / drain contacts (not shown) are formed on the impurity diffusion region 100 to electrically connect the wiring layer (not shown) and the impurity diffusion region 100.

  In addition, a plurality of gate electrodes 105 are formed on the impurity diffusion region 100 via a gate insulating film (not shown) made of, for example, SiON or the like, and a through hole 107 for supplying a potential to the gate electrode 105 is formed. Is formed. Here, FIG. 4A is a schematic view when a misalignment of the through hole 107 with respect to the gate electrode 105 occurs. A wiring layer (not shown) is formed on the through hole 107, and the gate The electrode 105 is electrically connected.

  Further, the MOS transistor is connected between the pad portion of the gate electrode 105 to which the through hole 107 for supplying a potential to the MOS transistor is connected and the gate electrode wiring portion 117 to the impurity diffusion region 100 and the gate electrode 105 as a wiring. The gate electrode wiring portion 112 is made of metal silicide (not shown) on the side surface of the gate electrode 105 in addition to the upper surface of the gate electrode 105 in order to improve the MOS transistor characteristics and increase the reliability. Is formed.

  Each gate electrode 105 is formed by using, for example, polysilicon, and the source / drain contact (not shown) and the through hole 107 are formed by burying tungsten or the like. The metal silicide (not shown) is formed using, for example, titanium, cobalt, nickel, molybdenum, or the like.

Next, a cross-sectional configuration of the semiconductor device according to the fourth embodiment of the present invention will be described. As shown in FIGS. 4B and 4C, an impurity diffusion region 100 is formed in a region partitioned by an element isolation region 108 made of, for example, SiO ₂ on a substrate (not shown).

Further, a gate insulating film (not shown) made of, for example, SiON or the like is formed on each impurity diffusion region 100, and the gate electrode 105 is formed via the gate insulating film (not shown) on the impurity diffusion region 100. Is formed. A side wall 109 made of, for example, SiO ₂ is formed on the side surface of the gate electrode 105.

  A gate electrode 105 and a sidewall 109 are also formed on each element isolation region 108 and connected to the gate electrode 105 on each impurity diffusion region 100.

  A metal silicide 110 is formed on the upper surface of the gate electrode 105 and the upper surface of the impurity diffusion region 100 constituting the source region and the drain region.

  In addition, an interlayer insulating film (not shown) is formed so as to cover the substrate (not shown), the impurity diffusion region 100, the element isolation region 108, and the gate electrode 105, and the through hole 107 has an interlayer insulating film (not shown). ) Is embedded in the opening.

  Here, as shown in FIG. 4C, in the gate electrode wiring portion 117 from the pad portion of the gate electrode 105 to which the through hole 107 is connected to the impurity diffusion region 100, the propagation characteristic of the potential to the MOS transistor is shown. For the purpose of improving and the purpose of improving the reliability of the gate electrode 105, the side wall 109 formed on the side surface of the gate electrode 105 is removed or not formed, and in addition to the upper surface of the gate electrode 105, the gate A metal silicide 110 is also formed on the side surface of the electrode 105. Here, the metal silicide 110 is formed using, for example, titanium, cobalt, nickel, molybdenum, or the like.

  In the conventional semiconductor device, as shown in FIGS. 5A and 5B, the side surface of the gate electrode 205 is covered with the sidewall 209, and only the upper surface of the gate electrode 205 is covered with the metal silicide 210. It was. Further, even when the through hole 207 is misaligned with the gate electrode 205, the pad portion of the gate electrode 205 is enlarged so that an excellent electrical connection can be obtained between the through hole 207 and the gate electrode 205. Was.

  On the other hand, in the semiconductor device of the fourth embodiment of the present invention, the gate electrode wiring part 117 from the pad part of the gate electrode 105 to which the through hole 107 is connected to the impurity diffusion region 100 and the gate electrode 105 are used as wirings. By forming the metal silicide 110 on the side surface in addition to the upper surface of the gate electrode 105 with respect to the gate electrode wiring portion 112 that connects the MOS transistors by using the metal transistor 110, the formation layer of the metal silicide 110 is multifaceted. Even if the through hole 107 is misaligned with the gate electrode 105, the gate electrode 105 is electrically expanded between the through hole 107 and the gate electrode 105 without expanding the gate electrode 105 to a desired width. A highly reliable gate electrode with high conductivity and high reliability can be formed. Furthermore, since it is not necessary to form the gate electrode pad 208 that is necessary in the conventional semiconductor device, the illustrated interval S13 can be set narrow, and the LSI can be reduced in area, speeded up, and improved in reliability. realizable.

  4A to 4C, the side wall 109 is formed on the side surface of the gate electrode 105, but the side wall 109 is not formed. Similarly, the semiconductor device having the structure may have a structure in which the metal silicide 110 is formed on the side surface in addition to the upper surface of the gate electrode 105.

Next, a method for manufacturing a semiconductor device according to the fourth embodiment of the present invention will be described. For example, the impurity diffusion region 100 and the element isolation region 108 are formed on a semiconductor substrate (not shown) by an element isolation technique using a selective oxidation method or the like through a predetermined lithography process. Next, after a predetermined lithography process, a gate insulating film (not shown) made of SiON or the like is formed, and then a gate electrode 105 made of polysilicon or the like is formed. Next, after an insulating film made of SiO ₂ or the like is formed so as to cover the gate electrode 105 by a CVD method or the like, a sidewall 109 is formed by anisotropic etching or the like. Next, through a predetermined lithography process, the side wall 109 of the gate electrode wiring part 117 from the pad part of the gate electrode 105 to which the through-hole 107 for supplying a potential is connected to the impurity diffusion region 100 is removed, and then self-alignment is performed. Thus, a metal silicide 110 is formed. Next, an interlayer insulating film (not shown) made of SiO ₂ or the like is formed by a CVD method or the like, then a through hole 107 is opened through a predetermined lithography process, and a desired melting point metal such as tungsten is buried. A semiconductor device is configured.

  As described above, the semiconductor device according to the fourth embodiment of the present invention shown in FIGS. 4A to 4C is manufactured.

  In the semiconductor device and the manufacturing method thereof according to the present invention, a highly reliable conductor can be formed by covering the upper surface and the side surface of the first conductor with the second conductor. This is useful for reduction, high speed, high reliability, and the like.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows the structure of the semiconductor device which concerns on the 1st Embodiment of this invention, (a) is a top view, (b), (c) is sectional drawing. It is a figure which shows the structure of the semiconductor device which concerns on the 2nd Embodiment of this invention, (a) is a top view, (b), (c) is sectional drawing. It is a figure which shows the structure of the semiconductor device which concerns on the 3rd Embodiment of this invention, (a) is a top view, (b), (c) is sectional drawing. It is a figure which shows the structure of the semiconductor device which concerns on the 4th Embodiment of this invention, (a) is a top view, (b), (c) is sectional drawing. 1 shows a structure of a conventional semiconductor device, (a) is a plan view, and (b) is a cross-sectional view. It is a top view which shows the structure of the conventional semiconductor device, and reflects the actual finishing shape of a gate electrode especially.

Explanation of symbols

100 Impurity diffusion region 101 NMOS formation region 102 PMOS formation region 103 N type impurity diffusion region 104 P type impurity diffusion region 105 Gate electrode 107 Through hole 108 Element isolation region 109 Side wall 110 Metal silicide 111 to 114, 117 Gate electrode wiring portion 115 High resistance region 116 of gate electrode Boundary part of gate electrode (PN junction)

Claims (9)

A first conductor formed on the substrate;
A semiconductor device comprising: a second conductor formed so as to be in contact with an upper surface and a side surface of at least a part of the first conductor. The semiconductor device according to claim 1,
The first conductor includes a first portion having an N-type conductor layer, a second portion having a P-type conductor layer, and a PN junction region at a boundary between the first portion and the second portion. And a third part having a rectifying characteristic,
The second conductor is provided so as to straddle the third part,
The semiconductor device, wherein the first part and the second part are electrically connected through the second conductor. The semiconductor device according to claim 1,
The first conductor includes an intrinsic region or a first region having an N-type conductor layer, a second region having a P-type conductor layer, and a boundary between the first region and the second region. A third region which is a non-doped region and has a high resistance,
The second conductor is provided so as to straddle the third part,
The semiconductor device, wherein the first part and the second part are electrically connected through the second conductor. The semiconductor device according to any one of claims 1 to 3,
A through hole for supplying a potential to the first conductor;
The through hole is provided so as to be positioned on an upper surface and a side surface of the first conductor on which the second conductor is formed, and is electrically connected to the second conductor. A semiconductor device. The semiconductor device according to any one of claims 1 to 4,
The first conductor is a gate electrode made of polysilicon;
The semiconductor device, wherein the second conductor is a metal silicide made of titanium, cobalt, nickel, or molybdenum. Forming a gate electrode on the substrate;
Forming a sidewall so as to cover a side surface of the gate electrode;
Removing at least a portion of the sidewall;
And a step of forming a metal silicide on the upper surface and side surfaces of the gate electrode. Forming a gate electrode film on the substrate;
Forming a P-type conductor layer at a first portion of the gate electrode film;
Forming an N-type conductor layer at the second portion of the gate electrode film;
Selectively etching the gate electrode film to form a gate electrode;
Forming a sidewall so as to cover a side surface of the gate electrode;
A part of the sidewall so as to straddle a third part that becomes a PN junction region at the boundary between the first part having the P-type conductor layer and the second part having the N-type conductor layer and has a rectifying characteristic Removing the
And a step of forming a metal silicide on the upper and side surfaces of the gate electrode from which the sidewall has been removed. Forming a gate electrode film on the substrate;
Forming a P-type conductor layer at a first portion of the gate electrode film;
Forming an N-type conductor layer at the second portion of the gate electrode film;
Selectively etching the gate electrode film to form a gate electrode;
Forming a sidewall so as to cover a side surface of the gate electrode;
The side wall of the sidewall extends across the third region which becomes an intrinsic region or a non-doped region and has a high resistance at the boundary between the first region having the P-type conductor layer and the second region having the N-type conductor layer. A step of removing a portion;
And a step of forming a metal silicide on the upper and side surfaces of the gate electrode from which the sidewall has been removed. Forming a gate electrode on the substrate;
Forming a sidewall so as to cover a side surface of the gate electrode;
Removing at least a portion of the sidewall;
Metal silicidation of the upper and side surfaces of the gate electrode;
Forming a through hole for supplying a potential to the gate electrode so as to be positioned on the gate electrode from which the sidewall has been removed and is made into a metal silicide. .

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