JP2007096865A - Level conversion circuit - Google Patents

Abstract

A voltage level of a logic signal can be converted stably and at high speed even when an input signal has a low voltage.
A latch circuit includes first and second conductive Nch transistors (105, 106), and first and second latch inverters (103, 104) each having an input terminal and an output terminal connected to each other. Configure. The first conductive Nch-type transistor 105 has a drain terminal connected to the input terminal of the first latching inverter 103 and inputs an inverted signal of the input signal to the source terminal. The second conductive Nch transistor 106 has a drain terminal connected to the input terminal of the second latch inverter 104 and inputs the input signal to the source terminal. The EXOR circuit 108 to which the input signal and the delay signal of the input signal are input controls on / off of the first and second conductive Nch transistors (105, 106).
[Selection] Figure 1

Description

  The present invention relates to a level conversion circuit that converts the voltage level of an input logic signal.

  When signals are input / output between semiconductor devices having different power supply voltages, a level conversion circuit is used to convert the signal voltage level to the voltage level of each power supply (see, for example, Patent Document 1). .

  For example, FIG. 8 is a block diagram showing an example of the configuration of a conventional level conversion circuit. 8 includes an inverter 501 that inverts an input signal IN, an inverter 502 that inverts an output (input inversion signal) of the inverter 501 to a positive phase, and an Nch in which the input signal IN is connected to a gate terminal. Type transistor 503, Nch type transistor 504 having the output of inverter 502 connected to the gate terminal, and Pch type transistors 505 and 506 for raising the drain terminals of Nch type transistors 503 and 504 to a high level, respectively. ing.

  In the following description, the connection point between the drain terminal of the Nch transistor 503 and the drain terminal of the Pch transistor 505 is a node W511, and the connection point of the drain terminal of the Nch transistor 504 and the drain terminal of the Pch transistor 506 is the node. Node W512 is assumed.

  In level conversion circuit 500, the gate terminal of Pch-type transistor 505 is connected to node W512, and the gate terminal of Pch-type transistor 506 is connected to node W511, thereby forming a cross couple that is complementary to each other. The node W511 is connected to the output terminal, and the signal at the node W511 is output as the output signal OUT.

  Further, a voltage (high-voltage side power supply voltage) is supplied to the source terminals of the Pch transistors 505 and 506 as a source potential from a power supply (VDDH) equivalent to the high level of the output signal OUT, and the Nch transistors 503 and 504 A GND potential is supplied as a source potential to the source terminal. The inverters 501 and 502 are supplied with a power supply voltage (low-voltage power supply voltage) equivalent to the high level of the input signal IN.

  In the above-described level conversion circuit 500, in a steady state, for example, when the input signal IN is at a low level, the inverter 501 outputs a high level, the inverter 502 outputs a low level, the Nch transistor 503 is on, and the Nch The type transistor 504 is off, the Pch type transistor 505 is off, and the Pch type transistor 506 is on.

  Therefore, the node W511 is at a low level, the other node W512 is at a high level, and the output signal OUT is at a low level. Further, since the Nch transistor 503 and the Pch transistor 505, and the Nch transistor 504 and the Pch transistor 506 are in a complementary relationship, no current flows in this steady state.

  Thereafter, when the input signal IN transits to a high level, the inverter 501 outputs a low level, and the inverter 502 outputs a high level, so that the Nch transistor 503 is turned off and the Nch transistor 504 is turned on. The node W512 transits from the high level to the low level, but when the threshold voltage of the Pch transistor 505 is exceeded, the Pch transistor 505 that has been turned off until then transitions on. Accordingly, the node W511 changes from the low level to the high level, and when all the state transitions are completed, the output signal OUT indicates the high level. The operation when the input signal IN changes from the low level to the high level has been described above, but the same applies to the reverse change.

As described above, according to the level conversion circuit 500, the voltage level of the input signal IN can be converted to a higher voltage level of the power supply.
JP 59-122222 A

  With recent reduction in power consumption, voltage, and miniaturization of semiconductor devices, the input signal of the level conversion circuit has been reduced in amplitude.

  Therefore, in the level conversion circuit 500 described above, when the power supply voltage of the inverters 501 and 502 is lowered as the input signal IN is lowered to a high level, the Nch transistor 503 and the Nch transistor 504 are turned on. Therefore, the gate voltage can be increased only near the threshold voltage. In this case, the drain currents of the Nch transistors 503 and 504 necessary for lowering the voltages at the nodes W511 and W512 are reduced. If the drain current of the Nch type transistors 503 and 504 is smaller than the drain current during the on operation of the Pch type transistors 505 and 506, the gate potential of the cross-coupled Pch type transistors 505 and 506 cannot be lowered. The level conversion circuit 500 may not be able to operate normally.

  In order to improve the operation stability when the input signal IN is at a low voltage, the Nch transistors 503 and 504 have a large gate width or a threshold voltage in order to increase the drain current during the ON operation. It can be lowered. Further, in order to reduce the drain current during the on-operation in the Pch transistors 505 and 506, the on resistance value of the Pch transistors 505 and 506 is increased by reducing the gate width or increasing the gate length. It is also possible to make a slight improvement by such a method.

  However, increasing the drain current during the on operation of the Nch transistors 503 and 504 increases the leakage current during the off time.

  Further, if the on-resistance value of the Pch transistors 505 and 506 is increased, the rising transition to the high level voltage of the node W511 or the node W512 at the time of the transition operation is delayed due to insufficient current capability at the time of the on-state, which is not suitable for high-speed operation. There's a problem.

  Even if the node W511 and the node W512 can be changed to the high level, the high level voltage is lower than the voltage of the high-voltage side power supply voltage, and the high level voltage of the output signal OUT is insufficient. There is sex.

  There is also a problem that it is difficult to design in consideration of manufacturing variations.

  The present invention has been made paying attention to the above problems, and provides a level conversion circuit capable of converting the voltage level of a logic signal stably and at high speed even when the input logic signal (input signal) is a low voltage. The purpose is to do.

In order to solve the above problems, the invention of claim 1
A level conversion circuit that outputs an output signal obtained by converting a voltage level of an input signal,
First and second inverter circuits operating with a first power source, a first conductive switch for switching on and off the input signal to the input terminal of the first inverter circuit, and the second inverter circuit A second conductive switch for switching on / off the input of the inverted signal of the input signal to the input terminal, and one of the input terminals and output terminals of the first and second inverter circuits; A latch circuit having an output signal terminal for outputting the output signal,
A third inverter circuit that operates with a second power source, inverts the input signal, and generates the inverted signal;
A control circuit for controlling the first conductive switch and the second conductive switch to an ON state when the input signal transitions;
The first and second inverter circuits are connected to each other at their input terminals and output terminals.
The first conductive switch includes a first conductive transistor having a drain terminal connected to an input terminal of the first inverter circuit and a source terminal to which the inverted signal is input.
The second conductive switch includes a second conductive transistor having a drain terminal connected to an input terminal of the second inverter circuit and a source terminal receiving the input signal.
The control circuit is configured to switch on and off by controlling the potential of the gate terminal of each of the first conductive transistor and the second conductive transistor.

The invention of claim 2
The level conversion circuit according to claim 1,
The first power supply is a power supply that supplies the same voltage level as the voltage amplitude of the output signal,
The second power supply is a power supply that supplies the same voltage level as the voltage amplitude of the input signal whose voltage amplitude is lower than that of the output signal.

  As a result, it is possible to realize operational stability and high-speed operation when a low voltage is input.

The invention of claim 3
A level conversion circuit that outputs an output signal obtained by converting a voltage level of an input signal,
First and second inverter circuits operating with a first power source, a first conductive switch for switching on and off the input signal to the input terminal of the first inverter circuit, and the second inverter circuit A second conductive switch for switching on / off the input of the inverted signal of the input signal to the input terminal, and one of the input terminals and output terminals of the first and second inverter circuits; A latch circuit having an output signal terminal for outputting the output signal,
A third inverter circuit that operates with a second power source, inverts the input signal, and generates the inverted signal;
A control circuit for controlling the first conductive switch and the second conductive switch to an ON state when the input signal transitions;
The first and second inverter circuits are connected to each other at their input terminals and output terminals.
The first conductive switch has a drain terminal connected to the input terminal of the first inverter circuit, a source terminal to which the inverted signal is input, and a drain terminal connected to the first inverter circuit. A first PchMOS transistor connected to the input terminal and having the inverted signal input to the source terminal;
The second conductive switch has a drain terminal connected to the input terminal of the second inverter circuit, a second NchMOS transistor in which the input signal is input to the source terminal, and a drain terminal connected to the second inverter circuit. A second PchMOS transistor connected to the input terminal and having the input signal input to the source terminal;
The control circuit is configured to switch on and off by controlling the potentials of the gate terminals of the first and second Nch MOS transistors and the first and second Pch MOS transistors. To do.

The invention of claim 4
The level conversion circuit according to claim 3, wherein
The first power supply is a power supply that supplies the same voltage level as the voltage amplitude of the output signal,
The second power supply is a power supply that supplies the same voltage level as the voltage amplitude of the input signal whose voltage amplitude is lower than that of the output signal.

  As a result, the latch circuit is charged and discharged at a higher speed, so that it is possible to further improve the operational stability and the high speed operation at the time of low voltage input.

The invention of claim 5
A level conversion circuit according to any one of claims 1 and 3,
The control circuit is configured by an exclusive OR circuit that outputs an exclusive OR of the input signal and a signal obtained by delaying the input signal, and the first circuit is configured to output the first OR signal by a pulse signal output from the exclusive OR circuit. And the second conductive switch is controlled to be turned on / off.

  Thereby, a signal for controlling on / off of the conductive switch is generated according to the input signal.

The invention of claim 6
A level conversion circuit according to any one of claims 1 and 3,
The control circuit is configured to control on and off of the first and second conductive switches at an arbitrary timing when the input signal transitions.

  This makes it possible to control the output of the voltage level converted signal at an arbitrary timing.

The invention of claim 7
A level conversion circuit according to any one of claims 1 and 3,
A plurality of the latch circuits are provided for one control circuit,
The control circuit is configured to control on and off of the first and second conductive switches in each latch circuit.

  As a result, a plurality of latch circuits can synchronize and output a voltage level converted signal at the same timing.

  According to the present invention, the voltage level of a logic signal can be converted stably and at high speed even when the input logic signal (input signal) is low in voltage.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

Embodiment 1 of the Invention
FIG. 1 is a block diagram showing a configuration of a level conversion circuit 100 according to the first embodiment of the present invention. The level conversion circuit 100 converts a voltage (referred to as a low voltage side voltage) of an input signal (input signal IN) input from an input signal terminal into a voltage (referred to as a high voltage side voltage) higher than that voltage and outputs a converted signal. This circuit outputs an output signal OUT from a terminal.

  As shown in FIG. 1, the level conversion circuit 100 includes an inverter 101, an inverter 102, a first latching inverter 103, a second latching inverter 104, a first conductive Nch transistor 105, and a second conductive circuit. An Nch transistor 106, a delay circuit 107, and an EXOR circuit 108 are provided.

  The inverter 101 is composed of a low-voltage side element that operates with a first voltage source (hereinafter referred to as VDDL) of a low-voltage side voltage, operates with a voltage supplied from VDDL, and inverts the input signal. And output it. VDDL is the same voltage as the high level of the input signal IN.

  The inverter 102 is composed of the low-voltage side element, operates with the voltage supplied from VDDL, inverts the output of the inverter 101, and outputs a signal in phase with the input signal IN (inverted signal W0). It has become.

  The first latching inverter 103 and the second latching inverter 104 are composed of elements on the high voltage side that operate with a second voltage source (hereinafter referred to as VDDH) having a voltage higher than VDDL. It operates with the voltage supplied from VDDH. Both the input terminal and the output terminal of the first latching inverter 103 and the second latching inverter 104 are connected. That is, the first latching inverter 103 and the second latching inverter 104 serve as a hold element that holds an input signal. Hereinafter, for convenience of description, input terminals of the first latching inverter 103 and the second latching inverter 104 are referred to as a terminal W1 and a terminal W2, respectively. The output terminal of the first latching inverter 103 (that is, the terminal W2) is connected to the conversion signal output terminal, and the output signal of the first latching inverter 103 is output as the output signal OUT.

  Each of the inverters 101 and 102, the first latch inverter 103, and the second latch inverter 104 includes a Pch transistor that drives the output terminal to a high level and an Nch that drives the output terminal to a low level. The following description will be made on the assumption that the CMOS inverter is composed of a type transistor.

  The first conductive Nch-type transistor 105 is composed of the high-voltage side element, and operates with a voltage supplied from VDDH. An inverted signal NIN (an output signal of the inverter 101) is input to the source terminal of the first conductive Nch transistor 105, and the drain terminal is connected to the terminal W1.

  The second conductive Nch-type transistor 106 is composed of the high-voltage side element, and operates with a voltage supplied from VDDH. An inverted signal W0 (an output signal of the inverter 102) is input to the source terminal of the second conductive Nch transistor 106, and the drain terminal is connected to the terminal W2.

  The inverter 101, the inverter 102, the first latching inverter 103, the second latching inverter 104, the first conductive Nch-type transistor 105, and the second conductive Nch-type transistor 106 constitute a latch circuit. Is done. In this latch circuit, the slew and hold of the input signal IN can be controlled by controlling the voltages of the gate terminals of the first conductive Nch transistor 105 and the second conductive Nch transistor 106.

  The delay circuit 107 is composed of the low-voltage side element, and operates with the voltage supplied from VDDL to generate a signal (output signal W5) in which the timing of the input signal IN is delayed.

  The EXOR circuit 108 is composed of the low-voltage side element, operates with a voltage supplied from VDDL, and outputs a signal (output signal W3) indicating an exclusive OR of the input signal IN and the output signal W5. It is like that. That is, the delay circuit 107 and the EXOR circuit 108 form a control circuit that controls the through and hold of the latch circuit. Therefore, the output terminal of the EXOR circuit 108 is connected to the gate terminals of the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106, and receives the output signal W3.

  The operation of the level conversion circuit 100 will be described with reference to the timing chart of FIG. In the initial state, the input signal IN is at a low level, the inverted signal NIN and the level at the terminal W1 are at a high level, respectively, and the inverted signal W0 (the output signal of the inverter 102) and the signal at the terminal W2 (that is, the output signal OUT). In the following description, it is assumed that the output signal W3 (the output of the EXOR circuit 108) is at a low level, respectively.

  When the input signal IN starts to transition from the low level to the high level, the delay circuit 107 outputs the low level output signal W5 as shown in FIG. 2 during the period in which the signal propagation is delayed. The circuit 108 outputs a high level pulse (output signal W3).

  While the output (output signal W3) of the EXOR circuit 108 is at a high level, that is, while the levels of the gate terminals of the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 are high, the first The conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 are opened, the inverted signal NIN and the inverted signal W0 (in phase with the input signal IN) are the first latching inverter 103 and the second 2 is input to the latching inverter 104. As a result, the inverted signal NIN (low level) is applied to the terminal W1 (input terminal side) of the first latching inverter 103 via the first conductive Nch-type transistor 105 and discharged from the high level to the low level. Begins. At the same time, an inverted signal W0 (high level) is applied to the terminal W2 (input terminal side) of the second latching inverter 104 via the second conductive Nch-type transistor 106, and the charge from the low level to the high level is applied. Begins.

  As a result, the Pch transistor in the second latching inverter 104 that has driven the terminal W1 to the high level transitions in the off direction because the gate terminal (terminal W2) transitions to the high level. At the same time, the Nch transistor in the first latching inverter 103 that has driven the terminal W2 to the low level shifts in the off direction because the gate terminal (terminal W1) shifts to the low level. That is, the first latch inverter 103 and the second latch inverter 104 complement each other, and the transition of the terminal W1 to the low level and the terminal W2 to the high level is accelerated. Therefore, the level of the output signal OUT changes from the low level to the high level in a short time. Therefore, it is necessary to design the delay time of the delay circuit 107 so as to secure a time for the levels of the terminals W1 and W2 to transition.

  After a delay period by the delay circuit 107, the output signal W5 of the delay circuit 107 transitions from a low level to a high level. That is, since both the input signal IN and the output signal W5 are at a high level, the output (output signal W3) of the EXOR circuit 108 is at a low level. As a result, the gate terminals of the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 are closed, so that the latch circuit sets the high level (VDDH level, that is, the level of the second voltage source). Is held and output from the conversion signal output terminal.

  Next, the operation when the input signal IN is high level, the inverted signal NIN and the signal level at the terminal W1 are both low level, the signal level at the terminal W2 (that is, the level at the conversion signal output terminal) and the inverted signal W0 are both high level. Will be explained.

  When the output of the EXOR circuit 108 (output signal W3) is in the low level and the input signal IN starts to transition from the high level to the low level, the delay circuit 107 causes the input signal IN to propagate as shown in FIG. Since the high level output signal W5 is output during the delay period, the EXOR circuit 108 outputs a high level pulse (output signal W3).

  While the output of the EXOR circuit 108 is at a high level, that is, while the gate terminals of the first conductive Nch transistor 105 and the second conductive Nch transistor 106 are at a high level, the first conductive Nch transistor 105 And the gate of the second conductive Nch transistor 106 are opened, and the inverted signal NIN and the inverted signal W0 (in phase with the input signal IN) are input to the first latch inverter 103 and the second latch inverter 104, respectively. The As a result, the inverted signal NIN (high level) is applied to the terminal W1 (input terminal side) of the first latching inverter 103 via the first conductive Nch-type transistor 105, and charging is performed from the low level to the high level. Begins. At the same time, an inverted signal W0 (low level) is applied to the terminal W2 (input terminal side) of the second latching inverter 104 via the second conductive Nch-type transistor 106, and charging from the high level to the low level is performed. Begins.

  As a result, the gate terminal (terminal W2) of the Nch-type transistor in the second latching inverter 104 that has driven the terminal W1 to the low level changes to the low level so that the terminal W2 changes to the high level. Since the gate terminal (terminal W1) of the Pch transistor in the first latching inverter 103 that has been driven to the level transitions to the high level, it complements by transitioning to the off direction, so that the terminal W1 goes to the high level. W2 accelerates both low level transitions. Therefore, the level of the signal output from the conversion signal output terminal changes from a high level to a low level in a short time.

  After a delay period by the delay circuit 107, the output signal W5 of the delay circuit 107 transitions from a low level to a high level. That is, since both the input signal IN and the output signal W5 are at a high level, the output (output signal W3) of the EXOR circuit 108 is at a low level. As a result, the gate terminals of the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 are closed, so that a low level signal is held by the latch circuit, and a low-level signal is output from the conversion signal output terminal. A level signal is output.

  As described above, according to the present embodiment, even if the voltage level of the input signal is lowered, in the latch circuit constituted by the two inverter circuits driven by the high-voltage side power supply and the conductive transistor, Since the inverter circuit amplifies the input signal to the amplitude of the high-voltage side voltage, it is difficult to be affected by manufacturing variations and the like, and it is possible to realize voltage level conversion stably and at high speed.

  Furthermore, since a control circuit for generating and controlling a signal for controlling the level conversion operation at an arbitrary timing with respect to the latch circuit is provided, voltage level conversion can be achieved at an appropriate timing.

<< Embodiment 2 of the Invention >>
In the first embodiment, since the conductive transistors are only the first conductive Nch type transistor 105 and the second conductive Nch type transistor 106, for example, the input signal IN transits to a low level, When the source terminal of one conductive Nch transistor 105 is at a high level and the gate terminal is at a high level (that is, the output signal W3 is at a high level), the gate W1 is charged when the terminal W1 corresponding to the drain terminal is charged from a low level to a high level. When the potential at the terminal W1 transitions until the potential difference between the source terminal and the source terminal becomes equal to or lower than the threshold voltage of the first conductive Nch-type transistor 105, the drain current of the first conductive Nch-type transistor 105 decreases and the variable movement Becomes dull.

  Therefore, as a second embodiment, an example of a level conversion circuit capable of realizing a higher speed operation at a lower voltage than the first embodiment will be described.

  FIG. 3 is a block diagram showing a configuration of the level conversion circuit 200 according to the second embodiment of the present invention. As shown in FIG. 3, in the level conversion circuit 200, a first conductive Pch transistor 201, a second conductive Pch transistor 202, and an inverter 203 are added to the level conversion circuit 100 of the first embodiment. Has been configured. In each embodiment described below, components having the same functions as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted.

  The first conductive Pch-type transistor 201 is composed of the high-voltage side element, and operates with a voltage supplied from VDDH. An inverted signal NIN is input to the source terminal of the first conductive Pch-type transistor 201, and the drain terminal is connected to the terminal W1.

  The second conductive Pch-type transistor 202 is composed of the high-voltage side element, and operates with a voltage supplied from VDDH. An inverted signal W0 (an output signal of the inverter 102) is input to the source terminal of the second conductive Pch transistor 202, and the drain terminal is connected to the terminal W2.

  The inverter 203 is composed of the low-voltage side element, operates with the voltage supplied from VDDL, and outputs a signal (output signal W4) obtained by inverting the output signal W3 of the EXOR circuit 108.

  Inverter 101, inverter 102, first latch inverter 103, second latch inverter 104, first conductive Nch transistor 105, second conductive Nch transistor 106, first conductive Pch The type transistor 201 and the second conductive Pch type transistor 202 constitute a latch circuit. In this latch circuit, the voltages of the gate terminals of the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 are controlled by the output signal W3, and further, the first conductive Pch-type transistor 201 and the second conductive Nch-type transistor 201 By controlling the voltage of the gate terminal of the conductive Pch type transistor 202 by the output signal W4, the through and hold of the input signal IN can be controlled.

  As described above, the level conversion circuit 200 is different from the first embodiment in that the first embodiment uses only a first conductive Nch transistor 105 and a second conductive Nch transistor 106 as conductive switches. However, in the second embodiment, the first conductive Pch-type transistor 201 and the second conductive Pch-type transistor 202 are used together to form a complementary conductive switch.

  The operation of the level conversion circuit 200 will be described with reference to the timing chart of FIG. In the initial state, the input signal IN is low level, the inverted signal NIN and the level at the terminal W1 are high level, the inverted signal W0 and the signal at the terminal W2 (that is, the output signal OUT) are respectively low level, and the output signal W3 ( The following description will be made assuming that the output of the EXOR circuit 108 is low level and the output signal W4 (output of the inverter 203) is high level.

  When the input signal IN starts to transition from the low level to the high level, the delay circuit 107 outputs the low level output signal W5 as shown in FIG. 4 during the period in which the signal propagation is delayed. The circuit 108 outputs a high level pulse, and the inverter 203 outputs a low level pulse.

  While the output of the EXOR circuit 108 is high level, that is, while the output signal W3 is high level and the output signal W4 is low level, the first conductive Nch transistor 105, the second conductive Nch transistor 106, First latch inverter 103 and gates of first conductive Pch transistor 201 and second conductive Pch transistor 202 are opened, inverted signal NIN and inverted signal W0 are hold elements, and second latch Is input to each inverter 104. An inversion signal NIN (low level) is applied to the terminal W1 of the first latching inverter 103 via the first conductive Nch type transistor 105 and the first conductive Pch type transistor 201. Discharge to level begins. At the same time, an inversion signal W0 (high level) is applied to the terminal W2 of the second latching inverter 104 via the second conductive Nch transistor 106 and the second conductive Pch transistor 202, so that the terminal W2 changes from low level to high level. Charging to the level begins.

  As a result, the Pch transistor in the second latching inverter 104 that has driven the terminal W1 to the high level transitions in the OFF direction because the gate terminal (terminal W2) transitions to the high level, and at the same time the terminal W2 The Nch transistor in the first latching inverter 103 that has been driven to the low level transitions in the off direction because the gate terminal (terminal W1) transitions to the high level. That is, the first latch inverter 103 and the second latch inverter 104 complement each other, and the transition of the terminal W1 to the low level and the terminal W2 to the high level are both accelerated. Therefore, the level of the output signal OUT changes from the low level to the high level in a short time. Therefore, also in this embodiment, it is necessary to design the delay time of the delay circuit 107 so as to secure a time for the levels of the terminals W1 and W2 to transit.

  After a delay period by the delay circuit 107, the output signal W5 of the delay circuit 107 transitions from a low level to a high level. That is, since both the input signal IN and the output signal W5 are at a high level, the output (output signal W3) of the EXOR circuit 108 is at a low level. That is, the output signal W3 is at a low level and the output signal W4 is at a high level, and the first conductive Nch transistor 105, the second conductive Nch transistor 106, the first conductive Pch transistor 201, and the second Since the gate terminal of the conductive Pch transistor 202 is closed, a high level signal (VDDH level, that is, the level of the second voltage source) is held by the latch circuit, and is output from the conversion signal output terminal.

  Next, the operation when the input signal IN is high level, the inverted signal NIN and the signal level at the terminal W1 are both low level, the signal level at the terminal W2 (that is, the level at the conversion signal output terminal) and the inverted signal W0 are both high level. Will be explained.

  When the output (output signal W3) of the EXOR circuit 108 is at the low level and the output signal W4 is at the high level, and the input signal IN starts to transition from the high level to the low level, the delay circuit 107, as shown in FIG. During the period in which propagation of the input signal IN is delayed, the high-level output signal W5 is output. Therefore, the EXOR circuit 108 outputs a high-level pulse (output signal W3), and the inverter 203 has a low level. Output a pulse.

  While the output (output signal W3) of the EXOR circuit 108 is at the high level, the gates of the first conductive Nch transistor 105 and the second conductive Nch transistor 106 are opened, and at the same time the output signal W4 is at the low level. In addition, the gates of the first conductive Pch-type transistor 201 and the second conductive Pch-type transistor 202 are opened, and the inverted input signal NIN and the inverted signal W0 are the first latch inverter 103 and the second 2 are respectively input to the latching inverters 104. An inversion signal NIN (high level) is applied to the terminal W1 of the first latching inverter 103 via the first conductive Nch type transistor 105 and the first conductive Pch type transistor 201. Charging to the level begins. At the same time, an inversion signal W0 (low level) is applied to the terminal W2 of the second latching inverter 104 via the second conductive Nch type transistor 106 and the second conductive Pch type transistor 202. Low level discharge begins.

  As a result, the Nch-type transistor in the second latching inverter 104 that has driven the terminal W1 to the low level transitions in the off direction because the gate terminal (terminal W2) transitions to the low level, and at the same time the terminal W2 The Pch transistor in the first latching inverter 103 that has been driven to the high level transitions in the off direction because the gate terminal (terminal W1) transitions to the high level.

  That is, the first latching inverter 103 and the second latching inverter 104 complement each other, and the transition of the terminal W1 to the high level and the terminal W2 to the low level are both accelerated. Therefore, the level of the output signal OUT changes from a high level to a low level in a short period of time.

  After a delay period by the delay circuit 107, the output signal W5 of the delay circuit 107 transitions from a low level to a high level. That is, since both the input signal IN and the output signal W5 are at a high level, the output (output signal W3) of the EXOR circuit 108 is at a low level. As a result, the gate terminals of the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 are closed, and at the same time, the output of the inverter 203 (output signal W4) becomes high level, and the first conductive Pch Since the gate terminals of the type transistor 201 and the second conductive Pch type transistor 202 are closed, a low level signal (that is, the low level of the second voltage source) is held by the latch circuit, and the conversion signal output terminal Is output.

  Also in the level conversion circuit 200 described above, for example, the input signal IN transits to a high level, and the inverted signal NIN input to the source terminal of the first conductive Nch transistor 105 is at the low level and the output input to the gate terminal. When the signal W3 is at the high level, the drain terminal (terminal W1) is charged from the low level to the high level, and the potential difference between the output signal W3 and the signal at the terminal W1 is equal to or lower than the threshold voltage of the first conductive Nch transistor 105. When the potential of the terminal W1 transitions until the current becomes N, the drain current of the first conductive Nch transistor 105 decreases.

  However, in the level conversion circuit 200, not only the first conductive Nch-type transistor 105 and the second conductive Nch-type transistor 106 as the conductive transistors, but also the first conductive Pch-type transistor 201 and the second conductive transistor as described above. Since the two conductive Pch transistors 202 are complementary, the inverted signal NIN input to the source terminal of the first conductive Pch transistor 201 is high and the output signal W4 input to the gate terminal is low. In the case of the level, since the potential between the gate and the source terminal does not become lower than the threshold voltage of the first conductive Pch-type transistor 201, the variable movement is easily performed. That is, the second embodiment has a feature that can realize a higher speed operation at a lower voltage than the first embodiment.

<< Embodiment 3 of the Invention >>
As a third embodiment, an example of a level conversion circuit capable of executing a level conversion operation at an arbitrary timing will be described.

  FIG. 5 is a block diagram showing a configuration of the level conversion circuit 300 according to the third embodiment of the present invention. As shown in FIG. 3, the level conversion circuit 300 includes a switch 301 instead of the first conductive Nch transistor 105 of the level conversion circuit 100, and a switch 302 instead of the second conductive Nch transistor 106. Instead of the delay circuit 107 and the EXOR circuit 108, a control circuit 303 is provided.

  The switch 301 switches whether or not to input the inverted signal NIN to the terminal W1 in accordance with a control signal (described later) output from the control circuit 303. Specifically, when a high level pulse is input as a control signal, the switch 301 is opened and the inverted signal NIN is input to the terminal W1. Specifically, the switch 301 is a conductive switch similar to the first conductive Nch-type transistor 105 in the first embodiment, or the first conductive Nch-type transistor 105 in the second embodiment and the first conductive switch. This is a complementary conductive switch similar to that constituted by the Pch transistor 201, and is constituted by the high-voltage side element so as to operate at VDDH.

The switch 302 switches whether to input the inverted signal W0 to the terminal W2 in accordance with a control signal (described later) output from the control circuit 303. Specifically, when a high level pulse is input as a control signal, the switch 302 is opened and the inverted signal W0 is input to the terminal W2. Specifically, the switch 302 is a conductive switch similar to the second conductive Nch-type transistor 106 in the first embodiment, or the second conductive Nch-type transistor 106 in the second exemplary embodiment and the second conductive switch. The control circuit 303 is a complementary conductive switch similar to that formed by the Pch-type transistor 202 and is configured by the high-voltage side element so as to operate at VDDH. A control signal for controlling on / off of the signal is output. Specifically, the control circuit 303 generates a pulse for operating the level conversion operation in the level conversion circuit 300 at an arbitrary timing, and synchronizes with the transition timing of the input signal IN or the level conversion output OUT at an arbitrary timing. For example, the control signal is generated in accordance with the semiconductor device system.

  The operation of the level conversion circuit 300 will be described with reference to FIG. In the example of FIG. 6, the control circuit 303 outputs a high level pulse as the control signal in synchronization with the transition timing of the input signal IN.

  As an example of the initial state, the input signal IN is low level, the inverted signal NIN and the signal at the terminal W1 are high level, the inverted signal W0 and the signal at the terminal W2 (that is, the output signal OUT) are low level, The control signal output from the control circuit is at a low level.

  When the input signal IN transitions from the low level to the high level, the inverted signal NIN transitions to the low level, and the inverted signal W0 transitions to the high level. When the control circuit 303 generates a high level pulse as the control signal at the timing shown in FIG. 6, the switches 301 and 302 are opened, and the inverted signal NIN and the inverted signal W0 are the first latch inverter 103 and the hold element. Each is input to the second latch inverter 104. The first latching inverter 103 is applied with an inversion signal NIN (low level) at the terminal W1 and starts discharging from the high level to the low level. At the same time, the second latching inverter 104 is applied with the inverted signal W0 (high level) to the terminal W2, and charging starts from the low level to the high level.

  The Pch transistor in the second latching inverter 104 that has driven the terminal W1 to the high level transitions in the off direction because the gate terminal (terminal W2) transitions to the high level. At the same time, the Nch transistor in the first latching inverter 103 that has driven the terminal W2 to the low level shifts in the off direction because the gate terminal (terminal W1) shifts to the low level. That is, the first latching inverter 103 and the second latching inverter 104 complement each other, and the transition of the terminal W1 to the low level and the terminal W2 to the high level is accelerated. Therefore, the level of the output signal OUT changes from the low level to the high level in a short time.

  That is, the control circuit 303 needs to be designed so that the high-level pulse generation period of the output control signal can secure the signal level at the terminal W1 and the time for the signal level at the terminal W2 to transition.

  When the control signal output from the control circuit 303 returns to the low level, the switches 301 and 302 are closed, and a high level signal (VDDH level, that is, the level of the second voltage source) is held by the latch circuit and converted. Output from signal output terminal.

  Similarly, when the input signal IN is high level, NIN is low level, the inverted signal W0 and the signal at the terminal W2 (ie, the output signal OUT) are high level, and the control signal is low level, the input signal IN is high level. When transitioning from low to low, the inverted signal NIN transitions to high level, and the inverted signal W0 transitions to low level.

  When the control circuit 303 generates a high level pulse as a control signal at the timing shown in FIG. 6, the switches 301 and 302 are opened, and the first latch inverter 103 and the inverted input signal NIN and the inverted signal W0 are hold elements and Each is input to the second latch inverter 104. In the first latch inverter 103, the inverted signal NIN (high level) is applied to the terminal W1, and charging from the low level to the high level starts. At the same time, the inversion signal W0 (high level) is applied to the terminal W2 of the second latch inverter 104, and discharge from the high level to the low level starts.

  The Nch transistor in the second latching inverter 104 that has driven the terminal W1 to the low level shifts in the off direction because the gate terminal (terminal W2) shifts to the low level. At the same time, the Pch transistor in the first latching inverter 103 that has driven the terminal W2 to the high level shifts in the off direction because the gate terminal (terminal W1) shifts to the high level. That is, the first latch inverter 103 and the second latch inverter 104 are complementary to each other, and W1 goes to a high level, W2 accelerates a low level transition, and the output signal OUT changes from a high level to a low level in a short time. Transition to level.

  That is, the control circuit 303 needs to be designed so that the high-level pulse generation period of the output control signal can secure the signal level at the terminal W1 and the time for the signal level at the terminal W2 to transition.

  When the control signal output from the control circuit 303 returns to the low level, the switches 301 and 302 are closed, the low level signal is held by the latch circuit, and the low level signal is output from the conversion signal output terminal. .

  As described above, according to the present embodiment, the level conversion operation is not executed at a fixed timing as in the level conversion circuit 100 or the level conversion circuit 200, but can be executed at an arbitrary timing. .

<< Embodiment 4 of the Invention >>
FIG. 7 is a block diagram showing a configuration of the level conversion circuit 400 according to the fourth embodiment of the present invention. As shown in FIG. 7, the level conversion circuit 400 includes two sets of level conversion units (level conversion units 401 and 402) and one control circuit 303.

  The level conversion units 401 and 402 include an inverter 101, an inverter 102, a latch circuit (first latch inverter 103 and second latch inverter 104), and switches 301 and 302, respectively. That is, the level conversion units 401 and 402 have the same configuration as that of the level conversion circuit 300 excluding the control circuit 303. Therefore, the level conversion units 401 and 402 operate in the same manner as the level conversion circuit 300 according to the control signal output from the control circuit 303.

  In the level conversion circuit 400 described above, since the plurality of level conversion units are controlled by the single control circuit 303, the plurality of level conversion units can synchronize and output a signal whose level has been converted at the same timing. .

  The level conversion circuit according to the present invention has an effect that the voltage level of the logic signal can be converted stably and at high speed even when the input logic signal (input signal) is at a low voltage. It is useful as a level conversion circuit for converting levels.

1 is a block diagram illustrating a configuration of a level conversion circuit according to a first embodiment. 3 is a timing chart regarding the level conversion circuit according to the first embodiment. FIG. 5 is a block diagram illustrating a configuration of a level conversion circuit according to a second embodiment. 10 is a timing chart regarding the level conversion circuit according to the second embodiment. FIG. 6 is a block diagram illustrating a configuration of a level conversion circuit according to a third embodiment. 10 is a timing chart regarding the level conversion circuit according to the third embodiment. FIG. 6 is a block diagram illustrating a configuration of a level conversion circuit according to a fourth embodiment. It is a block diagram which shows an example of a structure of the conventional level conversion circuit.

Explanation of symbols

100 level conversion circuit 101-102 inverter 103 first latch inverter 104 second latch inverter 105 first conductive Nch transistor 106 second conductive Nch transistor 107 delay circuit 108 EXOR circuit 200 level conversion circuit 201 first conductive Pch type transistor 202 second conductive Pch type transistor 203 inverter 300 level conversion circuit 301 to 302 switch 303 control circuit 400 level conversion circuit 401 to 402 level conversion unit

Claims (7)

A level conversion circuit that outputs an output signal obtained by converting a voltage level of an input signal,
First and second inverter circuits operating with a first power source, a first conductive switch for switching on and off the input signal to the input terminal of the first inverter circuit, and the second inverter circuit A second conductive switch for switching on / off the input of the inverted signal of the input signal to the input terminal, and one of the input terminals and output terminals of the first and second inverter circuits; A latch circuit having an output signal terminal for outputting the output signal,
A third inverter circuit that operates with a second power source, inverts the input signal, and generates the inverted signal;
A control circuit for controlling the first conductive switch and the second conductive switch to an ON state when the input signal transitions;
The first and second inverter circuits are connected to each other at their input terminals and output terminals.
The first conductive switch includes a first conductive transistor having a drain terminal connected to the input terminal of the first inverter circuit and the inverted signal input to a source terminal;
The second conductive switch includes a second conductive transistor having a drain terminal connected to an input terminal of the second inverter circuit and a source terminal receiving the input signal.
The level conversion circuit, wherein the control circuit is configured to switch on and off by controlling potentials of gate terminals of the first conductive transistor and the second conductive transistor. The level conversion circuit according to claim 1, wherein
The first power supply is a power supply that supplies the same voltage level as the voltage amplitude of the output signal,
The level conversion circuit according to claim 1, wherein the second power source is a power source that supplies the same voltage level as the voltage amplitude of the input signal whose voltage amplitude is lower than that of the output signal. A level conversion circuit that outputs an output signal obtained by converting a voltage level of an input signal,
First and second inverter circuits operating with a first power source, a first conductive switch for switching on and off the input signal to the input terminal of the first inverter circuit, and the second inverter circuit A second conductive switch for switching on / off the input of the inverted signal of the input signal to the input terminal, and one of the input terminals and output terminals of the first and second inverter circuits; A latch circuit having an output signal terminal for outputting the output signal,
A third inverter circuit that operates with a second power source, inverts the input signal, and generates the inverted signal;
A control circuit for controlling the first conductive switch and the second conductive switch to an ON state when the input signal transitions;
The first and second inverter circuits are connected to each other at their input terminals and output terminals.
The first conductive switch has a drain terminal connected to the input terminal of the first inverter circuit, a source terminal to which the inverted signal is input, and a drain terminal connected to the first inverter circuit. A first PchMOS transistor connected to the input terminal and having the inverted signal input to the source terminal;
The second conductive switch has a drain terminal connected to the input terminal of the second inverter circuit, a second NchMOS transistor in which the input signal is input to the source terminal, and a drain terminal connected to the second inverter circuit. A second PchMOS transistor connected to the input terminal and having the input signal input to the source terminal;
The control circuit is configured to switch on and off by controlling the potentials of the gate terminals of the first and second Nch MOS transistors and the first and second Pch MOS transistors. Level conversion circuit. The level conversion circuit according to claim 3, wherein
The first power supply is a power supply that supplies the same voltage level as the voltage amplitude of the output signal,
The level conversion circuit according to claim 1, wherein the second power source is a power source that supplies the same voltage level as the voltage amplitude of the input signal whose voltage amplitude is lower than that of the output signal. A level conversion circuit according to any one of claims 1 and 3,
The control circuit is configured by an exclusive OR circuit that outputs an exclusive OR of the input signal and a signal obtained by delaying the input signal, and the first circuit is configured to output the first OR signal by a pulse signal output from the exclusive OR circuit. And a level conversion circuit configured to control on / off of the second conductive switch. A level conversion circuit according to any one of claims 1 and 3,
The level conversion circuit, wherein the control circuit is configured to control on and off of the first and second conductive switches at an arbitrary timing when the input signal transitions. A level conversion circuit according to any one of claims 1 and 3,
A plurality of the latch circuits are provided for one control circuit,
The level conversion circuit, wherein the control circuit is configured to control on and off of the first and second conductive switches in each latch circuit.

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