JP2007096216A - Semiconductor integrated circuit device - Google Patents

Abstract

A conventional semiconductor integrated circuit device has a maximum number of I / O units arranged on one side of a core region. For example, when the number of I / Os to be arranged is small, I An unnecessary space is generated in the / O area and the occupied area is increased.
A semiconductor integrated circuit device (1a) including a plurality of first pads (23) and a plurality of second pads (24) connected to a core region (11), wherein each of the first pads provided on at least one side of the core region (11). One pad 23 and each second pad 24 are arranged side by side in the length direction of the one side.
[Selection] Figure 2

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a wire bonding pad and a wafer test pad.

  In recent years, with the higher integration and higher functionality of semiconductor integrated circuit devices, the number of I / O (Input / Output) has increased, and the occupied area of the chip is often determined by the configuration of the I / O. Is coming.

  Therefore, a narrow I / O is created as a standard library so that the occupied area of the chip is reduced even if the number of I / Os is large. In addition, the pads provided in the standard library are formed on a wafer bonding pad (WBP: Wire Bonding Pad) for connecting the diced IC chip and the input / output pins of the package, and on the wafer. A wafer test pad (PP: Probing Pad) for performing a test by bringing a probe pin into contact with the IC chip is included.

  FIG. 1 is a diagram schematically showing a main part of an example of a conventional semiconductor integrated circuit device. In FIG. 1, reference numeral 1 denotes a semiconductor integrated circuit device (IC chip), 2 denotes an I / O unit (I / O), 11 denotes a core area, and 12 denotes an I / O area.

  As shown in FIG. 1, the I / O area 12 includes, for example, an I / O circuit unit 21 including an input buffer, an output buffer, an input / output buffer, and the like, and a circuit (core circuit) formed in the core area 11. An ESD protection element portion 22 for protecting against static electricity, a wire bonding pad 23 for connecting the IC chip 1 to an input / output pin of an IC package (not shown), and a prober for the IC chip 1 formed on the wafer. A wafer test pad 24 for testing by bringing pins into contact is provided.

  Here, in the I / O region 12 of the conventional IC chip 1, for example, an I / O circuit unit 21, ESD is provided in order to allow a large number of I / Os to be installed while keeping the occupied area of the IC chip 1 small. A narrow I / O unit 2 is formed in the core region 11, in which the protection element portion 22, the wire bonding pad 23 and the wafer test pad 24 are sequentially arranged from the core circuit region 11 in the outer direction (height direction). It is provided for each wiring of the circuit.

  That is, the conventional IC chip 1 has, for example, an I / O circuit unit 21 that constitutes one I / O, ESD protection in order to arrange the maximum number of I / O units 2 on one side of the core region 11. The element part 22, the wire bonding pad 23 and the wafer test pad 24 are stacked in the height direction so as to be narrowed.

  In FIG. 1 (the same applies to other figures), the core area 11 includes a circuit that realizes the function of each IC chip 1, such as a memory circuit such as a RAM, a ROM, or a flash EEPROM, or an MPU, a DSP, or the like. An arithmetic circuit or other various logic circuits (not shown) are formed. In addition, wiring between the circuit in the core region 11, the I / O circuit unit 21, the ESD protection element unit 22, the wire bonding pad 23, and the wafer test pad 24 is omitted. Needless to say, this is done.

  Further, in this specification, the case where the I / O region 12 is provided with an I / O circuit portion 21, an ESD protection element portion 22, a wire bonding pad 23, and a wafer test pad 24 is described as an example. However, for example, the pads are not limited to those for wire bonding and wafer testing, and may be an IC chip provided with a part for realizing other functions as an I / O unit. Of course.

  Conventionally, as a master slice type semiconductor integrated circuit laid out by DA (Design Automation) processing, a cell consisting of an input buffer circuit and an input / output buffer circuit or an output buffer circuit is repeatedly and regularly arranged on at least one side of the semiconductor substrate. An arrangement is also proposed (for example, see Patent Document 1).

JP 60-059766 A

  As described above, the conventional IC chip (semiconductor integrated circuit device) 1 is provided with the narrow I / O unit 2 so that a large number of I / Os can be arranged while keeping the occupied area small. ing.

  However, as shown in FIG. 1, in each IC chip 1, for example, the I / O to be arranged with respect to the size of a certain side of the core region 11 (the length of any one side of the core region 11). There are cases where the number (required number of wire bonding pads 23 and wafer test pads 24) is small, and in such a case, the interval between the I / O units 2 is set wide. . However, if the interval between the I / O units 2 is set wide, useless empty space is generated in the I / O region 12, and as a result, the occupied area of the IC chip 1 is increased.

  An object of the present invention is to provide a semiconductor integrated circuit device having a small occupied area by minimizing a wasteful I / O area.

  According to the present invention, there is provided a semiconductor integrated circuit device including a plurality of first pads and a plurality of second pads connected to the core region, wherein each of the first pads provided on at least one side of the core region. In addition, a semiconductor integrated circuit device is provided in which the second pads are arranged in the length direction of the one side.

  According to the present invention, it is possible to provide a semiconductor integrated circuit device having a small occupation area by minimizing a wasteful I / O region.

Hereinafter, embodiments of a semiconductor integrated circuit device according to the present invention will be described in detail with reference to the accompanying drawings.
The semiconductor integrated circuit device according to the present invention is useless, for example, by freely combining the parts for wire bonding, wafer test pad, I / O circuit and ESD protection element in the I / O unit. The free space is made as small as possible to reduce the chip size.

  FIG. 2 is a diagram schematically showing the main part of the first embodiment of the semiconductor integrated circuit device according to the present invention. In FIG. 2, reference numeral 1a denotes a semiconductor integrated circuit device (IC chip), 2a denotes an I / O unit, 11 denotes a core area, and 12 denotes an I / O area.

  As shown in FIG. 2, the I / O area 12 includes, for example, an I / O circuit unit 21 including an input buffer, an output buffer, or an input / output buffer, and a circuit (core circuit) formed in the core area 11. A prober is brought into contact with the ESD protection element portion 22 that protects from the IC, the wire bonding pad 23 that connects the IC chip 1a to the input / output pins of the IC package (not shown), and the IC chip 1a formed on the wafer. A wafer test pad 24 for performing a test is provided.

  Here, as is clear from the comparison between FIG. 2 and FIG. 1, the I / O unit 2a in the IC chip 1a of the first embodiment is an I / O circuit like the conventional I / O unit 2. The part 21, the ESD protection element part 22, the wire bonding pad 23, and the wafer test pad 24 are not simply stacked in the height direction (outward from the core circuit area 11), but are provided on one side of the core area 11. The / O circuit portion 21 and the ESD protection element portion 22 are arranged side by side in the length direction (lateral direction) of one side, and the wire bonding pad 23 is disposed above the I / O circuit portion 21 and the ESD protection element portion 22. The wafer test pads 24 are arranged side by side in the horizontal direction.

  That is, for example, when the number of I / Os to be arranged with respect to the size of a certain side of the core region 11 (the number of wire bonding pads 23 and wafer test pads 24 required) is small, the conventional IC By disposing the I / O unit 2a of this embodiment so as to fill a useless space in the I / O area 12 of the chip 1, the height of the I / O unit 2a (I / O area 12) is reduced. The area occupied by the IC chip 1a can be reduced.

  Note that the wire bonding pads 23 and the wafer test pads 24 arranged in the horizontal direction are alternately arranged, and wire bonding processing for connecting the diced IC chip 1 and the input / output pins of the package, and the wafer In the process of bringing the probe pins into contact with the wafer test pad 24 during the test, the gap between adjacent pads is widened to facilitate the process.

FIG. 3 is a diagram schematically showing a main part of a second embodiment of the semiconductor integrated circuit device according to the present invention.
As apparent from the comparison between FIG. 3 and FIG. 2, the I / O unit 2b of the IC chip 1b of the second embodiment is the same as the I / O unit 2a of the IC chip 1a of the first embodiment described above. Only the bonding pads 23 and the wafer test pads 24 are arranged side by side in the horizontal direction, and the I / O circuit unit 21 and the ESD protection element unit 22 are the I / Os of the conventional IC chip 1 described with reference to FIG. Similar to the unit 2 (the larger sides of the I / O circuit portion 21 and the ESD protection element portion 22 are stacked), they are stacked in the height direction.

FIG. 4 is a diagram schematically showing a main part of a third embodiment of the semiconductor integrated circuit device according to the present invention.
As apparent from the comparison between FIG. 4 and FIG. 3, the I / O unit 2c of the IC chip 1c of the third embodiment is the same as the I / O unit 2a of the IC chip 1a of the second embodiment described above. The / O circuit unit 21 and the ESD protection element unit 22 are stacked in the height direction so that the sides of the I / O circuit unit 21 and the ESD protection element unit 22 having smaller sizes are stacked.

  Here, the I / O units 2a to 2c shown in FIGS. 2 to 4 schematically depict the I / O circuit unit 21, the ESD protection element unit 22, the wire bonding pad 23, and the wafer test pad 24. However, it goes without saying that the actual shape and size can vary.

  As described above, according to each embodiment of the present invention, the I / O circuit unit 21 and the ESD protection element unit 22 are separated into parts, and the wire bonding pads 23 and the wafers arranged in the horizontal direction are arranged. Arbitrary combinations are arranged between the test pad 24 and the core region 11.

  According to each of the embodiments of the semiconductor integrated circuit device of the present invention described above, although the width (size in the horizontal direction) of the I / O unit is increased, the expansion of the width is absorbed by a wasteful I / O area. Thus, the advantage of lowering the height can be utilized, and as a result, the area occupied by the IC chip can be reduced. This directly leads to an increase in the number of IC chips (effective number of dies) that can be obtained from one wafer, and the price of the semiconductor integrated circuit device can be reduced.

  Furthermore, by separating the I / O unit into parts, the parts can be shared with different types of semiconductor integrated circuit devices, so that an effect of reducing the I / O development man-hour can be expected.

  FIG. 5 is a diagram schematically showing an overall configuration of a fourth embodiment of the semiconductor integrated circuit device according to the present invention.

  As shown in FIG. 5, in the semiconductor integrated circuit device of the fourth embodiment, for example, the number of I / Os required for the size of the side on the upper side of the core region 11 is small. In the left side of the core region 11, the I / O unit 20 having a wide width direction (lateral direction) and a low height direction as in the first to third embodiments described above is disposed. Since the number of I / Os required for the size of the side is large, the conventional I / O unit 2 having a narrow width direction and a high height direction as shown in FIG. 1 is arranged. Yes. In this case, as compared with the conventional IC chip, the I / O unit 20 disposed on the upper side of the core region 11 reduces the height by d in the height direction, and the area occupied by the IC chip 1d can be reduced. Thus, the application of the present invention does not have to be performed for all the sides of the core region 11 and can be selectively applied to each side.

  In the above, the wire bonding pad and the wafer test pad are tested by bringing the probe pin into contact with the IC chip formed on the wafer and the pad for wire bonding the IC chip and the input / output pin of the package, respectively. Although described as a pad for performing, the present invention can be similarly applied even when a pad used for another purpose is provided for the I / O unit. Furthermore, it goes without saying that the present invention can be similarly applied to the I / O circuit portion and the ESD protection element portion even when a portion for realizing another function is provided for the I / O unit.

(Appendix 1)
A semiconductor integrated circuit device comprising a plurality of first pads and a plurality of second pads connected to a core region,
A semiconductor integrated circuit device, wherein the first pads and the second pads provided on at least one side of the core region are arranged side by side in the length direction of the one side.

(Appendix 2)
The semiconductor integrated circuit device according to appendix 1, wherein the first pad is a wire bonding pad for connecting the diced semiconductor integrated circuit device to an input / output pin of a package, and the second pad. The semiconductor integrated circuit device according to claim 1, wherein the pad is a wafer test pad for performing a test by bringing a probe pin into contact with the semiconductor integrated circuit device formed on the wafer.

(Appendix 3)
The semiconductor integrated circuit device according to attachment 2, further comprising an I / O circuit part and an ESD protection element part separated into parts, wherein the I / O circuit part and the ESD protection element part are arranged in the core region A semiconductor integrated circuit device, wherein the wire bonding pads and the wafer test pads arranged in the length direction of at least one side are arranged in any combination between the core region and the core region.

(Appendix 4)
The semiconductor integrated circuit device according to appendix 3, wherein the I / O circuit portion and the ESD protection element portion are arranged side by side in the length direction of at least one side of the core region, and the wire bonding pads and the wafers A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is arranged side by side in the length direction of at least one side of the core region so as to correspond to the test pad.

(Appendix 5)
The semiconductor integrated circuit device according to appendix 3, wherein the I / O circuit portion and the ESD protection element portion are arranged side by side in the length direction of at least one side of the core region, and the wire bonding pads and the wafers A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is arranged side by side in the height direction of at least one side of the core region so as to correspond to the test pad.

(Appendix 6)
The semiconductor integrated circuit device according to attachment 1, wherein each side of the core region in which the first pads and the second pads are arranged in the length direction of one side of the core region, A semiconductor integrated circuit device characterized in that the size of one side is larger than the size in which the number of the first pads and the second pads required for the one side are arranged in the length direction.

  The present invention can be widely applied to various semiconductor integrated circuit devices. In particular, the present invention is applied to a semiconductor integrated circuit device having a wire bonding pad and a wafer test pad, and wastes an I / O region. It is possible to reduce the occupancy area of the semiconductor integrated circuit device by making the space as small as possible.

It is a figure which shows typically the principal part of an example of the conventional semiconductor integrated circuit device. 1 is a diagram schematically showing a main part of a first embodiment of a semiconductor integrated circuit device according to the present invention. It is a figure which shows typically the principal part of 2nd Example of the semiconductor integrated circuit device based on this invention. It is a figure which shows typically the principal part of 3rd Example of the semiconductor integrated circuit device based on this invention. It is a figure which shows schematically the whole structure of 4th Example of the semiconductor integrated circuit device based on this invention.

Explanation of symbols

1, 1a, 1b, 1c, 1d Semiconductor integrated circuit device (IC chip)
2, 2a, 2b, 2c, 20 I / O unit (I / O)
DESCRIPTION OF SYMBOLS 11 Core area | region 12 I / O area | region 21 I / O circuit part 22 ESD protection element part 23 Wire bonding pad (1st pad)
24 Wafer test pad (second pad)

Claims (4)

A semiconductor integrated circuit device comprising a plurality of first pads and a plurality of second pads connected to a core region,
A semiconductor integrated circuit device, wherein the first pads and the second pads provided on at least one side of the core region are arranged side by side in the length direction of the one side.   2. The semiconductor integrated circuit device according to claim 1, wherein the first pad is a wire bonding pad for connecting the diced semiconductor integrated circuit device to an input / output pin of a package, and the first pad. 2. The semiconductor integrated circuit device according to claim 2, wherein the pad 2 is a wafer test pad for performing a test by bringing a probe pin into contact with the semiconductor integrated circuit device formed on the wafer.   3. The semiconductor integrated circuit device according to claim 2, further comprising an I / O circuit portion and an ESD protection element portion separated into parts, wherein the I / O circuit portion and the ESD protection element portion are arranged in the core. A semiconductor integrated circuit device, wherein the wire bonding pads and the wafer test pads arranged in the length direction of at least one side of the region are arranged in any combination between the wafer test pad and the core region. .   2. The semiconductor integrated circuit device according to claim 1, wherein one side of the core region in which the first pads and the second pads are arranged side by side in the length direction of one side of the core region is the core region. A semiconductor integrated circuit device characterized in that the size of one side is larger than the size in which the number of the first pads and the second pads required for the one side are arranged in the length direction.

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