JP2007095910A - Manufacturing method of wiring board - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method of a wiring board which can improve the etching factors of a wiring pattern and hardly causes problems due to a change in conductivity, etc. of metals. <P>SOLUTION: The manufacturing method of a wiring board includes a process of forming a predetermined wiring pattern WP by etching a plurality of copper layers stacked vertically. In etching, a kind of copper layer to be used for each copper layer is so selected that the lower the copper layer is located, the higher an etch rate may be. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a method for manufacturing a wiring board including a step of forming a predetermined wiring pattern by etching a plurality of copper layers stacked one above the other.

  Conventionally, a method of manufacturing a wiring board is known in which a resist film is formed on a surface of a substrate having a copper layer provided on at least one side, and etching is performed to form the copper layer in a predetermined wiring pattern. Yes. Moreover, when manufacturing a double-sided wiring board in which the wiring patterns on both sides are conductively connected through plated through holes, the following processes are generally employed.

  That is, as shown in FIG. 1, first, a double-sided copper-clad laminate in which copper foil layers 2 are laminated on both sides of an insulating substrate 1 is prepared. A through-hole SL is formed in this with a drill etc., Then, copper is plated and the copper plating layer 3 is formed. At this time, the inside of the through hole SL is also plated to form a plated through hole 3s. Next, a resist 4 corresponding to a predetermined wiring pattern is formed on the surface of the copper plating layer 3, and tenting is performed with a resist 4a that closes the plated through hole 3s. Next, etching is performed to form a predetermined wiring pattern WP, and finally the resist 4 is removed.

  According to such an etching process (subtractive method), the copper foil layer 2 generally has an etching rate lower than or equal to that of the copper plating layer 3, and therefore the cross-sectional shape of the wiring pattern WP is shown in FIG. ) Or (b). Such a phenomenon becomes particularly prominent when the thickness of the wiring pattern WP is large (for example, a pattern for large current).

  When the wiring pattern WP has a shape as shown in FIG. 2B, the etching factor is deteriorated and a problem such as a short circuit is likely to occur. Especially when a fine pattern is formed, an etching apparatus, an etching solution, and a pattern are formed. The need to devise special measures for the design has arisen.

  As a method for solving such a problem, the following Patent Document 1 discloses an etching process in which pure copper and alloy copper are used to change the etching rate of each layer (the rate is reduced as the upper layer is reduced). . Thereby, the undercut by etching can be reduced.

  However, if alloyed copper is used for a part of the wiring pattern as in the above process, the metal conductivity changes at that part, so circuit design problems are likely to occur, especially in high frequency circuits. In some cases, the board did not function.

JP-A-5-291256

  SUMMARY OF THE INVENTION An object of the present invention is to provide a method for manufacturing a wiring board that can improve the etching factor of a wiring pattern and is less likely to cause problems due to changes in metal conductivity.

The above object can be achieved by the present invention as described below.
That is, the wiring board manufacturing method of the present invention includes a step of forming a predetermined wiring pattern by etching a plurality of copper layers stacked one above the other. The etching is performed by selecting the type of each copper layer so as to increase the speed.

  According to the method for manufacturing a wiring board of the present invention, the bottom part of the wiring pattern is quickly etched to select the type of each copper layer so that the lower copper layer has a higher etching rate. The factor can be improved. In addition, since only the type of each copper layer is selected without using an alloy or the like, problems due to changes in metal conductivity and the like are less likely to occur.

  In the above, it is preferable that the plurality of copper layers have a copper plating layer formed on a copper foil layer. For example, when manufacturing a double-sided wiring board in which the wiring patterns on both sides are conductively connected with plated through holes, the lower copper foil layer is usually less etched (or equivalent) than the upper copper plated layer. However, in the present invention, since the etching rate is adjusted so that the etching rate of the lower copper foil layer is increased, the etching factor of the wiring pattern can be improved.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a process diagram showing an example of a method for manufacturing a wiring board according to the present invention, and FIG. 2 is an explanatory diagram for explaining the function and effect of the present invention.

  The method for manufacturing a wiring board of the present invention includes a step of forming a predetermined wiring pattern by etching a plurality of copper layers stacked one above the other. Any wiring board may be used as long as it includes such an etching process as a manufacturing process. In addition to a single-sided wiring board, a double-sided wiring board, a multilayer wiring board, a flexible wiring board, or the like may be used. In the present embodiment, as shown in FIG. 1, an example in which a double-sided wiring board in which wiring patterns WP on both sides are conductively connected through plated through holes 3 s is manufactured by a subtractive method is shown.

  In this example, first, a double-sided copper-clad laminate in which copper foil layers 2 are laminated on both sides of an insulating substrate 1 is prepared. As the insulating substrate 1, for example, an insulating film made of an epoxy resin, a phenol resin, or a polyimide resin, a cured product of a prepreg in which a glass fiber cloth or the like is impregnated with these resins, a polyimide film, a polyester film, or the like is used.

  The copper foil layer 2 of the double-sided copper-clad laminate is generally formed by thermocompression bonding with the insulating base material 1, but can also be formed by plating or the like. The thickness of the copper foil layer 2 is preferably 3 to 200 μm in order to efficiently obtain the effect of improving the etching factor by balancing the thickness.

  In general, since the etching rate of the copper foil layer 2 is lower or equivalent to that of the copper plating layer 3, the cross-sectional shape of the conventional wiring pattern WP is as shown in FIG. 2 (a) or (b). It was in shape. In the present invention, the wiring pattern is shown in FIG. 2C by selecting the type of each copper layer so that the lower copper layer (in this embodiment, the copper foil layer 2) has a higher etching rate. The shape can be improved and the etching factor can be improved.

  Thus, the copper foil layer 2 with a high etching rate has an etching rate profile as shown in FIG. 3, for example. In the case of the copper foil layer 2, the etching rate can be increased by about 20% as compared with the conventional copper foil, and even when compared with the copper plating layer 3, the etching rate can be increased by about 10 to 20%.

  As such a copper foil having a high etching rate, for example, a copper foil having a large impurity content, a copper foil having a dense crystal structure, or a copper foil obtained by a production method by electroless copper plating is effective.

  Next, a through-hole SL is formed in the double-sided copper-clad laminate. This step can be performed by drilling, punching, laser, or the like. The diameter of the through hole SL is, for example, 100 to 2000 μm.

  Next, copper is plated to form the copper plating layer 3. At this time, the inside of the through hole SL is also plated to form a plated through hole 3 s. The thickness of the copper plating layer 3 is preferably 5 to 100 μm in order to efficiently obtain the effect of improving the etching factor by balancing the thickness.

  The plating may be electrolytic plating or electroless plating, but the copper plating layer 3 obtained by electrolytic plating is preferable because the etching rate is reduced. A commercially available plating solution can be used as the plating solution.

  Next, a resist 4 corresponding to a predetermined wiring pattern is formed on the surface of the copper plating layer 3, and tenting is performed with a resist 4a that closes the plated through hole 3s. Any method may be used for forming the resist 4, and for example, a dry film resist, a liquid photosensitive resin, a printing ink, or the like can be used. In the case of using a dry film resist, a desired resist pattern is formed by laminating the dry film resist and then exposing and developing with a predetermined pattern.

  Next, etching is performed to form a predetermined wiring pattern WP. The wiring pattern WP is composed of a copper foil layer 2a after etching and a copper plating layer 3a after etching. For the etching, etching solutions having different etching rates of the copper foil layer 2 and the copper plating layer 3 are used, and etching solutions such as cupric chloride, ferric chloride, and alkaline etching solutions can be used. Examples of the etching method include an immersion method, a spray method (including a shower method), a foam etching method, and the like.

  The degree of etching can be adjusted by etching time and liquid concentration. In the present invention, as shown in FIG. 2C, the line width of the bottom surface is 90% to 120% with respect to the line width of the upper surface of the wiring pattern WP. It is preferable to set the conditions so as to be within the range of%. Since the etching factor is improved, the present invention is particularly effective in the case where the line width on the upper surface of the wiring pattern WP, which conventionally requires a device for etching in the case of refinement, is 20 to 100 μm.

  Next, the resist 4 is removed, but can be peeled off with a chemical or the like. As a result, a double-sided wiring board in which the wiring patterns WP on both sides are conductively connected through the plated through hole 3s can be obtained.

  Next, if necessary, various metal plating steps, solder resist and coverlay forming steps may be performed. In the case of a multilayer wiring board or the like, it is possible to further perform processes such as stacking and integration of wiring boards, formation of an interlayer connection structure, build-up to an upper layer, and the like.

[Other Embodiments]
(1) In the above-mentioned embodiment, although the example which etches the two copper layers in which the copper plating layer was formed on the copper foil layer was shown, three or more copper layers may be sufficient. In that case, what is necessary is just to select the kind of each copper layer so that an etching rate may become high sequentially in the lower copper layer.

  (2) In the present invention, the plurality of copper layers may be all copper plating layers or all copper foil layers, and the copper plating layer and the copper foil layer are upside down as compared with the above-described embodiment. It may be.

Process drawing which shows an example of the manufacturing method of the wiring board of this invention Explanatory drawing for demonstrating the effect of this invention The graph which shows the example which compared the etching rate of the copper foil used for this invention, and the conventional copper foil

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Insulation base material 2 Copper foil layer 2a Copper foil layer after etching 3 Copper plating layer 3a Copper plating layer after etching 3s Plating through hole 4 Resist WP Wiring pattern

Claims (2)

In a method for manufacturing a wiring board, including a step of forming a predetermined wiring pattern by etching a plurality of copper layers stacked vertically
A method of manufacturing a wiring board, comprising selecting and etching the type of each copper layer so that the lower copper layer has a higher etching rate. The method for manufacturing a wiring board according to claim 1, wherein the plurality of copper layers are obtained by forming a copper plating layer on a copper foil layer.

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