JP2007081294A - Nonvolatile semiconductor memory device and manufacturing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory device which is improved in memory holding properties. <P>SOLUTION: In the nonvolatile semiconductor memory device, a charge holding part 13 is not located on an element isolation insulating film 11, so that charges injected into the charge holding part 13 on an active region hardly moves to the element isolation insulating region 11, and charge stored in the charge holding part 13 on a channel region 19 never decreases in charge density, Therefore, the semiconductor memory device of this design can be improved in memory holding properties. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a nonvolatile semiconductor memory device and a manufacturing method thereof.

  Currently, flash memories are widely known as electrically rewritable nonvolatile semiconductor memory devices. This flash memory stores information by accumulating charges in a conductive charge accumulation region called a floating gate.

  As a charge storage region, for example, a type using an insulating film such as an oxide film / nitride film / oxide film has been proposed. When an insulating film is used as the charge storage region, charges can be stored independently on the source side and the drain side, so that one element can store 2-bit information.

  7A to 7C show a nonvolatile semiconductor memory device of a type using an insulating film as a charge storage region as a first conventional example. 7A is a plan view of this conventional example, FIG. 7B is a cross-sectional view along B-B ′ in FIG. 7A, and FIG. 7C is a cross-sectional view along A-A ′ in FIG. 7A. This conventional example is a so-called MONOS (Metal / Oxide / Nitride / Oxide / Silicon) type non-volatile semiconductor memory having a stacked structure of oxide film / nitride film / oxide film disposed under a gate electrode as a charge storage region. An apparatus is shown (for example, refer to Patent Document 1 (Japanese Patent Laid-Open No. 2004-221448)).

  7A to 7C, reference numeral 710 denotes a semiconductor substrate, 711 denotes an element isolation insulating film, 712 denotes a lower insulating film, 713 denotes a nitride film serving as a charge holding region, 714 denotes an upper insulating film, 715 denotes a gate electrode, and 716 denotes a source region. , 717 are drain regions.

  Data is written by injecting electrons and trapping them in the nitride film 713 to increase the threshold value of the nonvolatile semiconductor memory device (memory cell transistor). Specifically, by applying 8 (V) to the gate electrode 715, 5 (V) to the drain region 717, and 0 (V) to the source region 716 and the semiconductor substrate 710, hot electrons generated near the drain region 717 are applied. Is written to the drain side of the nitride film 713 and trapped. Here, by reversing the voltage application conditions to the source region 716 and the drain region 717 at the time of writing, it becomes possible to trap electrons only on the source side of the nitride film 713 in FIG. 7B. That is, 2 bits can be stored in one element.

  On the other hand, data is erased by injecting holes into the silicon nitride film 713 to neutralize the trapped electrons and lower the threshold value of the memory cell transistor. Specifically, -6 (V) is applied to the gate electrode 715, 5 (V) is applied to the source region 716 and the drain region 717, and hot holes generated by band-to-band tunneling are injected into the silicon nitride film 713, thereby erasing. I do.

  Next, as a second conventional example, FIG. 8A to FIG. 8C show a nonvolatile semiconductor memory in which the separation of the storage portion of 2 bits is improved as compared with the MONOS type nonvolatile semiconductor memory device of the first conventional example. An apparatus is shown (for example, refer to Patent Document 2 (Japanese Patent Laid-Open No. 2004-56095)). FIG. 8A is a plan view of this conventional example, FIG. 8B is a B-B ′ sectional view in FIG. 8A, and FIG. 8C is an A-A ′ sectional view in FIG. 8A.

  8A to 8C, reference numeral 810 denotes a semiconductor substrate, 811 denotes an element isolation insulating film, 812 denotes a lower insulating film, 813 denotes a nitride film serving as a charge holding region, 814 denotes an upper insulating film, 815 denotes a gate electrode, and 816 denotes a source region. , 817 are drain regions.

  The second conventional example is different from the first conventional example of the MONOS type in that the charge holding region 813 is opposed to the side wall of the gate electrode 815. In FIG. 8B, since the charge holding region 813 is separated by the gate electrode 815, the separation of the storage portion of 2 bits has been successfully improved as compared with the first conventional example.

  Incidentally, in the above-described nonvolatile semiconductor memory devices of the first and second conventional examples, the charge holding regions 713 and 813 extend to the element isolation insulating films 711 and 811.

  In order to explain this, first, a method of manufacturing the nonvolatile semiconductor memory device of the first conventional example shown in FIGS. 7A to 7C will be described. First, a lower insulating film 712, a nitride film 713 serving as a charge holding region, and an upper insulating film 714 are sequentially stacked on a semiconductor substrate 710 on which an element isolation insulating film 711 is formed, and then polysilicon is deposited. Then, after patterning using a resist, the polysilicon is etched to form the gate electrode 715. Here, the upper insulating film 714, the nitride film 713, and the lower insulating film 712 are simultaneously etched with the resist pattern. Thereafter, a source region 716 and a drain region 717 are formed, whereby the first conventional nonvolatile semiconductor memory device shown in FIGS. 7A to 7C is completed.

  As described above, in the nonvolatile semiconductor memory device of the first conventional example, when the gate electrode 715 is formed, the nitride film 713 which is a charge holding region is also formed at the same time, so the gate including the region on the element isolation insulating film 711 is formed. The charge accumulation region 713 is formed in the entire region below the electrode 715.

  Here, the reason why the gate electrode 715 extends to the element isolation insulating film 711 is that a large gate area is required to make contact with the gate electrode 715, and the contact portion usually has an element isolation region. Because it is above. Further, when a large number of nonvolatile semiconductor memory devices illustrated in FIGS. 7A to 7C are arranged to form a cell array, the gate electrode 715 functions as a word line, and one gate electrode serves as the gate electrode of a plurality of elements. This is because the gate electrode inevitably extends over the element isolation.

  Next, a method for manufacturing the nonvolatile semiconductor memory device of the second conventional example shown in FIGS. 8A to 8C will be described. First, a gate electrode 815 is formed over a semiconductor substrate 810 over which an element isolation insulating film 811 is formed with a gate insulating film 818 interposed therebetween. Thereafter, the lower insulating film 812 and the nitride film 813 are sequentially stacked and then etched back. Thereafter, an upper insulating film 814 is deposited, and a source region 816 and a drain region 817 are formed, whereby the nonvolatile semiconductor memory device of the second conventional example shown in FIGS. 8A to 8C is completed.

  As described above, since the nonvolatile semiconductor memory device of the second conventional example is manufactured by etching back the nitride film 813 which is the charge storage region, the periphery of the gate electrode 815 including the region above the element isolation insulating film 811 is formed. The charge accumulation region 813 is formed in all the regions.

  As described above, in the nonvolatile semiconductor memory devices of the first and second conventional examples, the charge holding regions 713 and 813 exist on the element isolation insulating films 711 and 811.

At the time of writing, electrons are injected only into the region on the channel region sandwiched between the element isolation insulating films 711 and 811 in the charge holding regions 713 and 813 in the gate width direction. That is, electrons are not injected into the regions above the element isolation regions 711 and 811 in the charge holding regions 713 and 813. Electrons injected into the charge holding regions 713 and 813 made of the nitride film gradually move to the charge holding regions 713 and 813 on the insulating films 711 and 811 with time as indicated by arrows in FIGS. 7C and 8C. . Here, since the threshold value of the memory cell transistor is determined by the density of charges stored in the charge holding regions 713 and 813 on the channel, the charge holding regions on the element isolation insulating films 711 and 811 as described above. When charges move to 713 and 813, the memory retention characteristics deteriorate. In the case of the first conventional example of the MONOS type shown in FIGS. 7A to 7C, although the charge moves in the channel direction in the charge holding region 713, the channel width is small, and the current on the element isolation insulating films 711 and 811 Charge transfer has a greater effect.
JP 2004-221448 A JP 2004-56095 A

  SUMMARY OF THE INVENTION An object of the present invention is to provide a nonvolatile semiconductor memory device that can improve memory retention characteristics and a method for manufacturing the same.

  In order to solve the above problems, a nonvolatile semiconductor memory device of the present invention includes a semiconductor substrate, an element isolation portion embedded in the semiconductor substrate, and formed in the semiconductor substrate and separated by the element isolation portion. An active region; a gate electrode formed on the semiconductor substrate via a gate insulating film; a source region and a drain region formed in the semiconductor substrate and located on at least both sides of the gate insulating film; and the semiconductor And a charge holding portion formed of a dielectric material to which a voltage is applied by the gate electrode. The charge holding portion exists on the active region but on the element isolation portion. It is characterized by not.

  In the nonvolatile semiconductor memory device of the present invention, since the charge holding portion does not exist on the element isolation portion, the charge injected into the charge holding portion on the active region does not move onto the element isolation portion, and the channel The charge density stored in the upper charge holding portion does not decrease. Therefore, the memory retention characteristic is improved.

  Further, in the nonvolatile semiconductor memory device of one embodiment, the charge holding portion is formed between the gate electrode and the gate insulating film.

  In this embodiment, charge is independently held on the source side and the drain side of the charge holding portion formed between the gate electrode and the gate insulating film, and 2-bit information is stored in one element. Can do.

  In the nonvolatile semiconductor memory device according to one embodiment, at least a part of the charge holding unit exists below the upper end surface of the element isolation unit.

  In this embodiment, it is easy to manufacture so that no charge holding portion exists on the element isolation insulating film.

  In the nonvolatile semiconductor memory device according to one embodiment, the charge holding portion is disposed so as to face the side wall of the gate electrode with an insulating film interposed therebetween.

  According to this embodiment, by disposing the charge holding portions on both sides of the side wall of the gate electrode, it is possible to reliably separate the 2-bit storage portion.

  In the nonvolatile semiconductor memory device of one embodiment, the charge holding unit is sandwiched between the first insulating film and the second insulating film.

  According to this embodiment, the first and second insulating films sandwiching the charge holding portion can suppress the leakage of charges from the charge holding portion, and can obtain good memory holding characteristics.

In one embodiment of the method for manufacturing a nonvolatile semiconductor memory device, the step of forming a groove for element isolation in a semiconductor substrate;
Filling the trench with an element isolation insulating film;
Forming a charge holding portion on the semiconductor substrate via an insulating film;
Removing the portion of the charge holding portion existing on the element isolation insulating film;
Forming a gate electrode on the charge holding portion;
A step of implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source region and a drain region.

  According to the manufacturing method of this embodiment, it is possible to satisfactorily manufacture a nonvolatile semiconductor memory device having no charge holding portion on the element isolation insulating film through the above-described steps.

According to one embodiment, a method for manufacturing a nonvolatile semiconductor memory device includes a step of forming a dielectric film serving as a charge holding portion on a semiconductor substrate via an insulating film;
Forming a groove for element isolation in the semiconductor substrate through the dielectric film;
Filling the trench with an element isolation insulating film;
Forming a gate electrode on the charge holding portion;
A step of implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source region and a drain region.

  According to the manufacturing method of this embodiment, it is possible to satisfactorily manufacture a nonvolatile semiconductor memory device having no charge holding portion on the element isolation insulating film through the above-described steps.

According to one embodiment, a method for manufacturing a nonvolatile semiconductor memory device includes a step of forming a groove for element isolation in a semiconductor substrate,
Filling the trench with an element isolation insulating film;
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a charge holding portion so as to face the side wall of the gate electrode through an insulating film;
Removing the portion of the charge retention portion on the element isolation insulating film;
A step of implanting impurities into the semiconductor substrate using the gate electrode and the charge holding portion as a mask to form a source region and a drain region.

  According to the manufacturing method of this embodiment, it is possible to satisfactorily manufacture a nonvolatile semiconductor memory device having no charge holding portion on the element isolation insulating film through the above-described steps.

  Moreover, the portable electronic device of one Embodiment is provided with the said non-volatile semiconductor memory device.

  According to this embodiment, by providing the nonvolatile semiconductor memory device, a portable electronic device having excellent memory retention characteristics can be realized.

  According to the nonvolatile semiconductor memory device of the present invention, since the charge holding portion does not exist on the element isolation portion, the charge injected into the charge holding portion on the active region does not move onto the element isolation portion, The charge density stored in the charge holding portion on the channel does not decrease. Therefore, the memory retention characteristic is improved.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
1A to 1C show a nonvolatile semiconductor memory device according to a first embodiment of the present invention. 1A is a plan view of the first embodiment, FIG. 1B is a BB ′ sectional view in FIG. 1A, and FIG. 1C is an AA ′ sectional view in FIG. 1A.

  As shown in FIG. 1C, the first embodiment includes a semiconductor substrate 10, an element isolation insulating film 11 as an element isolation portion embedded in the semiconductor substrate 10, and a first portion formed between the element isolation insulating films 11. 2 has a lower insulating film 12 as an insulating film. In addition, a charge holding portion 13 made of a silicon nitride film is formed on the lower insulating film 12 between the element isolation insulating films 11. An upper insulating film 14 as a first insulating film is formed on the charge holding portion 13, and a gate electrode 15 is formed on the upper insulating film 14.

  As shown in FIGS. 1A and 1B, a source region 16 and a drain region 17 are formed in the semiconductor substrate 10. A channel region 19 is formed between the source region 16 and the drain region 17. The source region 16, the drain region 17, and the channel region 19 constitute an active region. Here, the charge holding portion 13 exists on the active region, but does not exist on the element isolation insulating film 11 as the element isolation portion.

  Therefore, when storing charges independently on the source side and the drain side of the charge holding unit 13 below the gate electrode 15 and storing 2-bit information in one element, it is injected into the charge holding unit 13 on the active region. The charged charges do not move onto the element isolation insulating film 11 as the element isolation part. Therefore, since the charge density stored in the charge holding portion 13 on the channel region 19 does not decrease, the memory holding characteristics can be improved.

  As the semiconductor substrate 10, for example, a P-type silicon substrate, an SOI (silicon on insulator) substrate, or the like can be used. The element isolation insulating film 11 is formed of a silicon oxide film formed by STI (shallow trench isolation) or a silicon oxide film formed by a LOCOS (local oxidation of silicon) method. ing.

  Further, the upper end 11 </ b> A of the element isolation insulating film 11 as the element isolation part is located above the upper end 13 </ b> A of the charge holding part 13. Alternatively, the upper end 11 </ b> A of the element isolation insulating film 11 is positioned at substantially the same height as the upper end 13 </ b> A of the charge holding unit 13. This makes it possible to satisfactorily manufacture a nonvolatile semiconductor memory device having the charge holding portion 13 that exists on the active region but does not exist on the element isolation insulating film 11.

  The lower insulating film 12 is formed of, for example, a silicon oxide film having a thickness of about 1 nm to 10 nm and functions as a potential barrier. The charge holding portion 13 has a trap level for holding charges therein and functions as a region for holding charges. The charge holding unit 13 is formed of, for example, a nitride film having a thickness of about 1 nm to 15 nm. The upper insulating film 14 is formed of, for example, a silicon oxide film having a film thickness of about 1 nm to 20 nm and functions as a potential barrier. Therefore, in the first embodiment, the upper insulating film 14 and the lower insulating film 12 sandwiching the charge holding unit 13 can suppress the leakage of charges from the charge holding unit 13 and obtain a good memory holding characteristic.

  The gate electrode 15 can be made of, for example, N-type doped polycrystalline silicon. The source region 16 and the drain region 17 are formed from a region doped with an N-type impurity at a high concentration, for example.

  As described above, in the first embodiment, unlike the conventional nonvolatile semiconductor memory device, the charge holding portion 13 does not exist on the element isolation insulating film 11. Since the charge holding portion 13 does not exist on the element isolation insulating film 11, electrons injected into the charge holding region 13 above the channel region 19 by the write operation do not move onto the element isolation insulating film 11. Therefore, in the first embodiment, since the charge transfer to the charge holding region on the element isolation insulating film, which is the cause of the conventional deterioration of the memory holding characteristic, can be prevented, the memory holding characteristic can be improved.

(Production method)
Next, with reference to FIGS. 2A to 2D, a method for manufacturing the nonvolatile semiconductor memory device of the first embodiment will be described. 2A to 2D are cross-sectional views in the gate width direction.

  First, as shown in FIG. 2A, after a silicon oxide film 112 having a thickness of 1 nm to 10 nm to be the lower insulating film 12 is formed on the semiconductor substrate 10 which is a silicon substrate doped with a P-type impurity by thermal oxidation. Then, a silicon nitride film 113 having a film thickness of 1 nm to 15 nm to be the charge holding portion 13 is formed by a CVD (chemical vapor deposition) method.

  Next, as shown in FIG. 2B, using a resist (not shown), the deposited films (silicon oxide film 112 and nitride film 113) are patterned into the shape of the active region, and RIE (reactive ion etching) is performed. As a result, the deposited films (silicon oxide film 112 and silicon nitride film 113) are sequentially etched. Thereby, the lower insulating film 12 and the charge holding portion 13 are formed.

  Subsequently, the silicon substrate 10 is etched with the resist having the same pattern, and an element isolation groove 117 is formed in the semiconductor substrate 10 which is a silicon substrate. Thereafter, a 200 nm-thickness silicon oxide film 119 to be the element isolation insulating film 11 is deposited so as to fill the trench 117 by CVD.

  Next, as shown in FIG. 2C, the silicon insulating film 119 to be the element isolation insulating film 11 is flattened by CMP (Chemical Mechanical Polishing) process and polished to the vicinity of the upper end 13 </ b> A of the charge holding portion 13. Thereafter, the silicon insulating film 119 on the charge holding region 13 is removed with hydrofluoric acid, and the element isolation insulating film 11 is formed. Here, a region sandwiched between the element isolation insulating films 11 on the surface portion of the semiconductor substrate 10 which is a silicon substrate is a channel region 19.

  Next, as shown in FIG. 2D, a silicon oxide film having a film thickness of 1 nm to 20 nm to be the upper insulating film 14 and polycrystalline silicon doped in N-type are sequentially deposited by CVD, and patterned using a resist. After that, the polycrystalline silicon is etched by RIE to form the upper insulating film 14 and the gate electrode 15. Thereafter, for example, arsenic ions are implanted into the semiconductor substrate 10 which is a silicon substrate using the gate electrode 15 as a mask to form a source region 16 and a drain region 17. Thereby, the nonvolatile semiconductor memory device shown in FIGS. 1A to 1C is completed.

  As described with reference to FIG. 2B, after forming the nitride film 113 to be the charge holding portion 13, the nitride film 113 is etched with a resist pattern that forms the groove 117 for element isolation, thereby holding the charge. Part 13 is formed. Thereby, the charge holding portion 13 does not extend on the element isolation insulating film 11. Therefore, it is possible to avoid the phenomenon that causes the deterioration of the memory retention characteristic that the charge of the charge retention unit 13 moves to the element isolation region, and the memory retention characteristic can be improved.

(Second embodiment)
Next, with reference to FIGS. 3A to 3D in order, a method for manufacturing the nonvolatile semiconductor memory device according to the second embodiment of the invention will be described. 3A to 3D are cross-sectional views in the gate width direction, similar to FIG. 1C, which is a cross-sectional view along AA ′ in FIG.

  In the manufacturing method of the second embodiment, as shown in FIG. 3A, first, an oxide film 39 having a thickness of about 10 nm is formed on a silicon substrate 30 doped with a P-type impurity by thermal oxidation, and then CVD ( A nitride film 40 having a thickness of about 100 nm serving as a CMP (chemical mechanical polishing) stopper is formed by a chemical vapor deposition method. Thereafter, the nitride film 40 is patterned using a resist (not shown), and the nitride film 40 is etched by RIE (reactive ion etching). Subsequently, using the nitride film 40 as a mask, the silicon substrate 30 is etched to form a trench 131 serving as an element isolation region in the silicon substrate 30. Thereafter, a silicon oxide film is deposited to a thickness of 200 nm so as to fill the trench 131 by CVD. Thereafter, an unnecessary portion of the silicon oxide film is removed by a CMP process using the nitride film 40 as a stopper, and an element isolation insulating film 31 is formed.

  Here, the upper end 31A of the element isolation insulating film 31 extends 3 nm to 100 nm above the upper end surface 30A of the silicon substrate 30, and the upper end 31A is formed from a main portion 33A of the charge holding portion 33 to be formed later. Also be present above. Here, a region sandwiched between the element isolation insulating films 31 which are element isolation portions on the surface of the silicon substrate 30 is a channel region 39.

  Next, as shown in FIG. 3B, the nitride film 40 is removed using a phosphoric acid solution, and a silicon oxide film 132 having a thickness of 1 nm to 10 nm to be the lower insulating film 12 is formed by thermal oxidation. Thereafter, a silicon nitride film 133 having a film thickness of 1 nm to 15 nm to be the charge holding portion 34 is formed by CVD. Thereafter, a silicon oxide film 134 to be the upper insulating film 34 is deposited by CVD to a thickness of about 200 nm.

  Next, as shown in FIG. 3C, the silicon oxide film 132 and the silicon nitride film 133 on the element isolation insulating film 31 are removed by a CMP process, and the silicon oxide film 134 is polished until the film thickness becomes 1 nm to 20 nm. The upper insulating film 34 is formed. Here, since the silicon nitride film 133 on the channel region 39 is formed below the nitride film 133 on the element isolation insulating film 31, it becomes the charge holding portion 33 on the channel region 39 in the CMP process. The silicon nitride film 133 is not polished.

  Here, if it is difficult to control the film thickness of the upper insulating film 34 in the CMP process, the silicon nitride film 133 on the element isolation insulating film 31 serving as the element isolation portion is removed by the CMP process, and then the silicon After removing the oxide film 132 with hydrofluoric acid, a silicon oxide film to be the upper insulating film 34 may be deposited on the nitride film 133 by CVD.

  Next, as shown in FIG. 3D, N-type doped polycrystalline silicon is deposited by CVD, patterned using a resist, and then etched by RIE to form a gate electrode 35. Thereafter, using the gate electrode 35 as a mask, for example, arsenic ions are implanted to form a source region (not shown) and a drain region (not shown), thereby completing the nonvolatile semiconductor memory device.

  According to the nonvolatile semiconductor memory device manufactured by the manufacturing method of the second embodiment, as described with reference to FIG. 3C, the silicon nitride film 133 on the element isolation insulating film 31 is removed by the CMP process. . Therefore, since the charge holding portion 33 does not remain on the element isolation insulating film 31, a phenomenon that causes the deterioration of the memory holding characteristic that the charge moves to the charge holding portion on the element isolation insulating film as in the conventional case is avoided. And memory retention characteristics can be improved.

(Third embodiment)
Next, with reference to FIGS. 4A to 4C, a non-volatile semiconductor memory device as a third embodiment of the present invention will be described. 4A is a plan view of the third embodiment, FIG. 4B is a BB ′ sectional view in FIG. 4A, and FIG. 4C is an AA ′ sectional view in FIG. 4A.

  As shown in FIG. 4B, the third embodiment includes a semiconductor substrate 50, a source region 56 and a drain region 57 formed on the semiconductor substrate 50, and a gate electrode 55 formed on the semiconductor substrate 50. A channel region 59 is formed between the source region 56 and the drain region 57, and a gate insulating film 58 made of a silicon oxide film is formed between the channel region 59 and the gate electrode 55. A second insulating film 52 is formed so as to sandwich both side walls of the gate insulating film 58 and the gate electrode 55. In addition, a charge holding portion 53 made of a silicon nitride film is formed outside the second insulating film 52 so as to sandwich both side walls of the gate insulating film 58. A first insulating film 54 is formed so as to sandwich the charge holding portion 53 with the second insulating film 52. Note that the second insulating film 52 extends between the first portion 52A extending along the side wall of the gate electrode 55 and the gate insulating film 58 and the first insulating film 54. Two portions 52B.

  As shown in FIG. 4C, the third embodiment has element isolation insulating films 51 as element isolation parts embedded in the semiconductor substrate 50 on both sides of the second insulating film 52. Further, as shown in FIG. 4B, the third embodiment has a gate insulating film 58 made of a silicon oxide film on a semiconductor substrate 50, and a gate electrode 55 is formed on the gate insulating film 58. Yes.

  As the semiconductor substrate 50, for example, a P-type silicon substrate, an SOI (silicon-on-insulator) substrate, or the like can be used. The element isolation insulating film 51 is formed of a silicon oxide film formed by STI (shallow trench isolation) or a silicon oxide film formed by LOCOS (local oxidation of silicon). Yes. The gate insulating film 58 is formed from a silicon oxide film having a thickness of 1 nm to 10 nm as an example. The second insulating film 52 is formed of, for example, a silicon oxide film having a thickness of about 1 nm to 10 nm and functions as a potential barrier.

  The charge holding unit 53 has a trap level for holding charges therein, and is formed of, for example, a silicon nitride film having a thickness of about 1 nm to 15 nm and functions as a region for holding charges. The first insulating film 54 is formed of, for example, a silicon oxide film having a film thickness of about 1 nm to 20 nm and functions as a potential barrier. Further, as the gate electrode 55, for example, N-type doped polycrystalline silicon can be used. Further, as described above, the second insulating film 52, the charge holding portion 53, and the first insulating film 54 are formed on the side wall of the gate electrode 55. Further, the source region 56 and the drain region 57 are formed, for example, as regions doped with N-type impurities at a high concentration.

  The non-volatile semiconductor memory device of the third embodiment is different from the conventional non-volatile semiconductor memory device in that the charge holding portion 53 does not exist on the element isolation insulating film 51 which is an element isolation portion. In the third embodiment, since the charge holding portion 53 does not exist on the element isolation insulating film 51, the electrons injected into the charge holding portion 53 above the channel region 59 by the write operation exist above the channel region 59. However, it does not exist on the element isolation insulating film 51. That is, according to the third embodiment, since the charge transfer to the charge holding region on the element isolation insulating film, which has been a cause of deterioration of the memory holding characteristic in the conventional example, can be prevented, the memory holding characteristic can be improved.

  Next, with reference to FIGS. 5A to 5D and FIGS. 6A to 6D in order, a method for manufacturing the nonvolatile semiconductor memory device according to the third embodiment will be described. 5A to 5D are plan views, and FIGS. 6A to 6D are A-A ′ cross-sectional views of FIGS. 5A to 5D, respectively.

  First, as shown in FIGS. 5A and 6A, a silicon oxide film 69 having a thickness of about 10 nm is formed on a silicon substrate 50 doped with P-type impurities by thermal oxidation, and then a CMP stopper is formed by CVD. A nitride film 70 having a thickness of about 100 nm is formed. Thereafter, the silicon nitride film 70 is patterned using a resist (not shown), and further, the silicon nitride film 70 is etched by RIE (reactive ion etching).

  Subsequently, using the silicon nitride film 70 as a mask, the silicon substrate 50 is etched to form a trench 151 serving as an element isolation region in the silicon substrate 50. Thereafter, a silicon oxide film (not shown) is deposited to a thickness of 200 nm so as to fill the trench 151 by CVD. Thereafter, using the nitride film 70 as a stopper, an unnecessary portion of the silicon oxide film is removed by a CMP process, and an element isolation insulating film 51 is formed. Here, a region sandwiched between the element isolation insulating films 51 on the surface portion of the silicon substrate 50 is a channel region 59.

  Next, as shown in FIGS. 5B and 6B, the nitride film 70 is removed using a phosphoric acid solution, and then the oxide film 69 is removed using hydrofluoric acid. Thereafter, a silicon oxide film (not shown) having a thickness of 1 nm to 10 nm is formed by thermal oxidation to become the gate insulating film 58. Next, polycrystalline silicon doped N-type by CVD is deposited and patterned using a resist, and then the polycrystalline silicon is etched by RIE to form a gate electrode 55. Thereafter, a silicon oxide film 152 having a thickness of 1 nm to 10 nm to be the second insulating film 52 is deposited by thermal oxidation or CVD. Thereafter, a silicon nitride film 153 to be the charge holding portion 53 is deposited on the silicon oxide film 152 to be the second insulating film 52 by CVD to a thickness of about 1 nm to 15 nm.

  After that, the silicon nitride film 153 that becomes the charge holding portion 53 and the silicon oxide film 152 that becomes the second insulating film 52 are etched back by RIE, so that the silicon nitride film 153 that becomes the charge holding portion 53 is formed on the side wall of the gate electrode 55. Is formed. Subsequently, a silicon oxide film 154 having a thickness of 1 nm to 20 nm, which becomes the first insulating film 54, is deposited on the entire surface by CVD. Thereafter, for example, arsenic ions are implanted using the silicon oxide film 152 serving as the gate electrode 55 and the second insulating film 52, the silicon nitride film 153 serving as the charge holding portion 53, and the silicon oxide film 154 serving as the first insulating film 54 as a mask. Then, the source region 56 and the drain region 57 are formed. Thereafter, by etching back, a silicon oxide film 154 to be the first insulating film 54 is formed on the side wall of the gate electrode 55.

  Next, as shown in FIGS. 5C and 6C, after the channel portion is patterned with a resist 71, the silicon oxide film 152 that becomes the second insulating film 52 on the element isolation insulating film 51 and the silicon nitride that becomes the charge holding portion 53 are formed. The silicon oxide film 154 to be the film 153 and the first insulating film 54 is etched. Here, when the resist pattern 71 is patterned, in consideration of misalignment, the silicon nitride film 153 that becomes the charge holding portion 53 on the active region by an amount of misalignment from the end of the element isolation insulating film 51 that is an element isolation portion. The resist pattern 71 may be patterned so that is etched.

  By doing so, it is possible to prevent the charge holding portion 53 from extending to the element isolation insulating film 51 even when misalignment occurs. Further, when the silicon nitride film 153 serving as the charge holding portion 53 is removed at the end portion on the channel region 59, the amount of current in the channel region 59 below the removed portion cannot be changed by write / erase, Since only a constant current is added at the time of reading in the writing state and the erasing state, there is no particular problem in operation.

  Next, after the etching, as shown in FIGS. 5D and 6D, the resist pattern 71 is removed, thereby completing the nonvolatile semiconductor memory device of the third embodiment shown in FIGS. 4A to 4C.

  As described above, the charge holding portion 53 on the element isolation insulating film 51 is patterned by the resist 71 and then removed by etching, whereby the charge holding portion 53 does not exist on the element isolation insulating film 51. Therefore, according to the third embodiment, it is possible to avoid the movement of charges to the charge holding unit on the element isolation unit, which has been a cause of deterioration of the memory holding characteristic in the conventional example, and to improve the memory holding characteristic.

  In the above-described embodiment, the charge holding portion is made of a silicon nitride film. However, the charge holding portion may be made of a nitride film other than the silicon nitride film, and other dielectric materials (for example, silicon oxide Film, silicon oxynitride film, polyimide organic film, etc.). Further, according to the portable electronic device including the nonvolatile semiconductor memory device of the above-described embodiment, a portable electronic device having excellent memory retention characteristics can be realized.

1 is a plan view of a nonvolatile semiconductor memory device as a first embodiment of the present invention. It is B-B 'sectional drawing of FIG. 1A. It is A-A 'sectional drawing of FIG. 1A. It is sectional drawing explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device of the said 1st Embodiment. It is sectional drawing explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device of the said 1st Embodiment. It is sectional drawing explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device of the said 1st Embodiment. It is sectional drawing explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device of the said 1st Embodiment. It is sectional drawing explaining 1 process of the manufacturing method of the non-volatile semiconductor memory device as 2nd Embodiment of this invention. It is sectional drawing explaining 1 process of the said 2nd Embodiment. It is sectional drawing explaining 1 process of the said 2nd Embodiment. It is sectional drawing explaining 1 process of the said 2nd Embodiment. It is a top view of the non-volatile semiconductor memory device as 3rd Embodiment of this invention. It is B-B 'sectional drawing of FIG. 4A. It is A-A 'sectional drawing of FIG. 4A. It is a top view which shows 1 process of the manufacturing method of the said 3rd Embodiment. It is a top view which shows 1 process of the manufacturing method of the said 3rd Embodiment. It is a top view which shows 1 process of the manufacturing method of the said 3rd Embodiment. It is a top view which shows 1 process of the manufacturing method of the said 3rd Embodiment. It is A-A 'sectional drawing of FIG. 5A. It is A-A 'sectional drawing of FIG. 5B. It is A-A 'sectional drawing of FIG. 5C. It is A-A 'sectional drawing of FIG. 5D. It is a top view of the nonvolatile semiconductor memory device of the first conventional example. It is B-B 'sectional drawing of FIG. 7A. It is A-A 'sectional drawing of FIG. 7A. It is a top view of the non-volatile semiconductor memory device of the 2nd prior art example. It is B-B 'sectional drawing of FIG. 8A. It is A-A 'sectional drawing of FIG. 8A.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10,30 ... Semiconductor substrate 11,31 ... Element isolation insulating film 12,32 ... Lower insulating film 13,33 ... Charge holding part 14,34 ... Upper insulating film 15,35 ... Gate electrode 16 ... Source region 17 ... Drain region 19 39 ... Channel region 50 ... Semiconductor substrate 51 ... Element isolation insulating film 52 ... Second insulating film 53 ... Charge holding part 54 ... First insulating film 55 ... Gate electrode 59 ... Channel region 71 ... Resist

Claims (9)

A semiconductor substrate;
An element isolation portion embedded in the semiconductor substrate;
An active region formed in the semiconductor substrate and separated by the element isolation part;
A gate electrode formed on the semiconductor substrate via a gate insulating film;
A source region and a drain region formed in the semiconductor substrate and located on at least both sides of the gate insulating film;
A charge holding portion made of a dielectric material formed on the semiconductor substrate and applied with a voltage by the gate electrode;
With
The charge holding portion is
A non-volatile semiconductor memory device that exists on the active region but does not exist on the element isolation portion. The nonvolatile semiconductor memory device according to claim 1,
The non-volatile semiconductor memory device, wherein the charge holding portion is formed between the gate electrode and a gate insulating film. The nonvolatile semiconductor memory device according to claim 2,
The nonvolatile semiconductor memory device according to claim 1, wherein at least a part of the charge holding portion is present below the upper end surface of the element isolation portion. The nonvolatile semiconductor memory device according to claim 1,
The charge holding portion is
A non-volatile semiconductor memory device, wherein the non-volatile semiconductor memory device is disposed so as to face a side wall of the gate electrode with an insulating film interposed therebetween. The nonvolatile semiconductor memory device according to claim 1,
The nonvolatile semiconductor memory device, wherein the charge holding portion is sandwiched between a first insulating film and a second insulating film. A method for manufacturing the nonvolatile semiconductor memory device according to claim 1, comprising:
Forming a groove for element isolation in a semiconductor substrate;
Filling the trench with an element isolation insulating film;
Forming a charge holding portion on the semiconductor substrate via an insulating film;
Removing the portion of the charge holding portion existing on the element isolation insulating film;
Forming a gate electrode on the charge holding portion;
Implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source region and a drain region;
A method for manufacturing a nonvolatile semiconductor memory device. A method for manufacturing the nonvolatile semiconductor memory device according to claim 1, comprising:
Forming a dielectric film serving as a charge holding portion on a semiconductor substrate via an insulating film;
Forming a groove for element isolation in the semiconductor substrate through the dielectric film;
Filling the trench with an element isolation insulating film;
Forming a gate electrode on the charge holding portion;
Implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source region and a drain region;
A method for manufacturing a nonvolatile semiconductor memory device. A method for manufacturing the nonvolatile semiconductor memory device according to claim 4, comprising:
Forming a groove for element isolation in a semiconductor substrate;
Filling the trench with an element isolation insulating film;
Forming a gate insulating film on the semiconductor substrate;
Forming a gate electrode on the gate insulating film;
Forming a charge holding portion so as to face the side wall of the gate electrode through an insulating film;
Removing the portion of the charge retention portion on the element isolation insulating film;
And a step of injecting impurities into the semiconductor substrate using the gate electrode and the charge holding portion as a mask to form a source region and a drain region. A portable electronic device comprising the nonvolatile semiconductor memory device according to claim 1.

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