JP4427431B2 - Semiconductor memory device, semiconductor memory device manufacturing method, and semiconductor memory device operating method - Google Patents

Description

  The present invention relates to a semiconductor memory device, a semiconductor memory device manufacturing method, and a semiconductor memory device operating method. More specifically, the present invention relates to a semiconductor memory device including a field effect transistor having a floating gate on both side surfaces of a gate electrode via an insulating film, a manufacturing method thereof, and an operating method thereof.

  An example of a conventional semiconductor memory device (memory device) having a floating gate on the gate sidewall via an insulating film will be described with reference to FIG.

  A conventional semiconductor memory device has a control gate electrode 903 on a semiconductor substrate 901 with a gate insulating film 902 interposed therebetween, and the semiconductor substrate 901 has a conductivity type opposite to that of the semiconductor substrate 901 on both sides of the gate electrode 903. Diffusion regions, that is, source / drain regions 904 and 905 (see Japanese Patent Application Laid-Open No. 6-232424).

  In addition, floating gates 910 and 911 are provided on both side surfaces of the gate electrode 903 via gate side wall insulating films 908 and 909, and the floating gates 910 and 911 are formed by the floating gate insulating films 906 and 907, respectively. The semiconductor substrate 901 is insulated from the source / drain regions 904 and 905.

  Here, the thicknesses of the floating gate insulating films 906 and 907 may be different from each other. In particular, in this case, the floating gate insulating films 906 and 907 can be operated as a multi-value memory as described later.

  An interlayer insulating film 912 is deposited on the semiconductor substrate 901, the gate electrode 903, and the floating gates 910 and 911, and a metal wiring (not shown) is formed on the interlayer insulating film 912. The gate electrode 903, the source / drain regions 904 and 905, and the metal wiring are electrically connected by contact plugs.

  Here, in particular, only contact plugs 913 and 914 for connecting the metal wiring and the source / drain regions 904 and 905 are shown. In general, an element isolation band is provided on the semiconductor surface in order to electrically isolate devices from each other, but this is also omitted.

  Next, an example of a method for manufacturing the semiconductor memory device will be described with reference to FIGS. 12, 13A, and 13B. Here, in particular, an n-type device will be described. First, as shown in FIG. 13A, the entire surface of a p-type silicon substrate 901 on which an element isolation band (not shown) is formed is thermally oxidized, and then a polysilicon layer is deposited by a CVD method, and known lithography and dry etching are performed. This polysilicon layer is processed by a method to form a control gate electrode 903. Further, source / drain regions 904 and 905 are formed by ion implantation of n-type impurities, that is, phosphorus or arsenic.

  Then, after forming a thermal oxide film on the surfaces (including side surfaces) of the source / drain regions 904 and 905 and the gate electrode 903, the film thickness of the oxide film on the source / drain regions 904 and 905 is dry-etched. And the insulating films 906 and 907 are formed.

  Further, when the film thicknesses of the insulating films 906 and 907 on the source / drain regions 904 and 905 are changed from each other, after oxidation treatment is performed again, one of the source / drain regions 904 and 905 is changed. For example, dry etching may be performed by covering only the source / drain region 905 on the right side in the drawing with a resist. In this case, the insulating film 906 on the left side in the drawing is thinner than the insulating film 907 on the right side in the drawing, and a multi-value memory device can be formed as will be described later.

  Subsequently, after polysilicon is deposited on the entire surface by CVD, etch back is performed by dry etching to form floating gates 910 and 911 on both side walls of the gate electrode 903 as shown in FIG. 13B.

  At this time, the floating gates 910 and 911 are formed so as to surround the side walls along the gate electrode 903. More specifically, the floating gates 910 and 911 extend in the vertical direction on the paper surface, and are connected at the end of the gate electrode 903.

  For this reason, it is preferable to etch an unnecessary portion of the floating gate using a photoresist mask and dry etching (or wet etching) technique, and to divide the floating gates 910 and 911 on both sides as appropriate.

  Thereafter, after annealing for impurity activation in a nitrogen atmosphere, as shown in FIG. 12, the interlayer insulating film 912, the contact plugs 913, 914, and the metal wiring (not shown) are formed by a known method. To obtain the conventional memory device.

  Next, an example of a writing method to the conventional memory device will be described with reference to FIG. Information is written by charge injection into the floating gates 910 and 911. Here, the case of an n-type device will be described, and a state where electrons are accumulated in at least one of the floating gates 910 and 911 is defined as “write”, and a state where electrons are not accumulated is defined as “erase”.

  At the time of writing, for example, when a bias of 0 V or the like is applied to the semiconductor substrate 901 and the source / drain regions 904 and 905 and 10 V to the gate electrode 903, the insulating film is formed from the source / drain regions 904 and 905 by an electric field. Electron tunneling occurs to the floating gates 910 and 911 through 906 and 907, and charges 915 and 916 are injected into the floating gates 910 and 911.

  Next, the read principle of the conventional memory device will be described with reference to FIG. For example, the active layer on the left side of the drawing is the source region 904, the active layer on the right side of the drawing is the drain region 905, 0V to the semiconductor substrate 901 and the source region 904, 5V to the gate electrode 903, 1V to the drain region 905, etc. Is applied, an inversion layer 917 is generated in the channel region under the gate electrode 903, and a current flows between the source region 904 and the drain region 905.

  At this time, if charges 915 and 916 are accumulated in the floating gates 910 and 911, parasitic resistances 918 and 919 are generated under the floating gates 910 and 911 due to the potential of the charges 915 and 916, and the charges The amount of current is smaller than when 915 and 916 are not stored. That is, since the charge accumulation state can be detected based on the amount of current, information can be read out.

  In particular, as described above, when the tunnel insulating films 906 and 907 on the left and right in the drawing have different film thicknesses, the memory device can be operated in a multivalued manner. That is, in FIG. 14, the insulating film 906 on the left in the drawing is appropriately thinned with respect to the insulating film 907 on the right in the drawing, for example, when 10 V is applied to the control gate electrode 903, the floating gate on the left side of the drawing. Charge 915 is injected only into 910 (this is referred to as the first state), and charge 916 is also injected into the floating gate 911 on the right side of the page when 15 V is applied to the control gate electrode 903 (this is the second state). If the film thickness is designed as described above, the read current is different in each of the no-charge state, the first state, and the second state, so that each state is associated with information storage. Can be a multi-valued memory.

  The erase operation of the conventional memory device will be described with reference to FIG. At the time of erasing, for example, when a bias of 0 V or the like is applied to the semiconductor substrate 901 and the source / drain regions 904 and 905 and −10 V to the gate electrode 903, the floating gates 910 and 911 are reversed by an electric field. Electron tunneling occurs from the first through the insulating films 906 and 907 to the source / drain regions 904 and 905, and the charges 915 and 916 accumulated in the floating gates 910 and 911 are released, thereby erasing information. be able to.

  For increasing the capacity of a memory device, it is extremely important to increase the device operation speed. However, in the conventional semiconductor memory device, since writing and erasing operations are performed by electron tunneling between the floating gates 910 and 911 and the source / drain regions 904 and 905, it is difficult to increase the speed of writing and erasing. There was a problem that there was. This is because the region where electrons tunnel during writing and erasing is a very limited area in terms of the overlap between the floating gates 910 and 911 and the source / drain regions 904 and 905. .

This is because increasing the area of this portion in order to speed up writing and erasing results in an increase in the area occupied by the device on the wafer and an increase in manufacturing cost. This is a big problem for increasing the capacity of the memory device.
JP-A-6-232424

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor memory device that can perform writing or erasing at high speed and can be easily miniaturized (nonvolatile memory).

In order to solve the above problems, a semiconductor memory device according to the present invention provides:
A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A floating gate formed on both sides of the gate electrode via a gate sidewall insulating film;
A channel region provided in the semiconductor layer and disposed under the gate electrode;
A diffusion region provided in the semiconductor layer and disposed on both sides of the channel region;
A contact plug connected to the diffusion region,
The diffusion region overlaps a part of the floating gate,
The side surface of the floating gate has a shape substantially parallel to the contact plug,
The distance between the floating gate and the contact plug is smaller than the distance between the gate electrode and the floating gate,
Write and erase operations are performed by electron tunneling between the contact plug and the side surface of the floating gate .

According to the semiconductor memory device of the present invention, the diffusion region overlaps with a part of the floating gate, the side surface of the floating gate has a shape substantially along the contact plug, and the contact plug is Since it is in the vicinity of the floating gate, the semiconductor memory device can be programmed or erased by tunneling electrons between the floating gate and the contact plug. Thus, the area of the electron tunnel region can be increased without increasing the device area on the semiconductor layer, and writing or erasing can be performed at high speed. In addition, since the distance between the floating gate and the contact plug is smaller than the distance between the gate electrode and the floating gate, the tunneling probability of electrons from the contact plug to the floating gate is the floating floating. Since the tunneling probability of electrons from the gate to the gate electrode is higher, all the charges injected into the floating gate are not directly re-tunneled to the gate electrode, and charges are accumulated in the floating gate. can do. On the other hand, the tunneling probability of electrons from the floating gate to the contact plug is sufficiently larger than the tunneling probability of electrons from the gate electrode to the floating gate, and the charge can be extracted smoothly. Thus, writing or erasing can be performed reliably and at high speed.

  In one embodiment, the height dimension of the side surface of the floating gate having a shape substantially along the contact plug overlaps the diffusion region in the lower surface of the floating gate. It is larger than the length dimension of some channel directions.

  According to the semiconductor memory device of this embodiment, the height dimension of the side surface of the floating gate is the length in the channel direction of the part of the floating gate that overlaps the diffusion region in the lower surface of the floating gate. Since the area is larger than the dimension, the area of the floating gate facing the contact plug can be made larger than the area of the floating gate facing the diffusion region, so that the electrons can be reliably connected between the floating gate and the contact plug. Can be tunneled.

In one embodiment, the semiconductor memory device has an interlayer insulating film on the gate electrode and the diffusion region, and is made of a material different from the material of the interlayer insulating film between the floating gate and the contact plug. And a regulating insulating film that regulates the distance between the contact plug and the floating gate to be constant .

  According to the semiconductor memory device of this embodiment, since the regulating insulating film made of a material different from the material of the interlayer insulating film is provided between the floating gate and the contact plug, the floating gate has the interlayer insulating film. Therefore, the contact plug and the floating gate can be prevented from contacting each other by using an etching means for selectively etching the interlayer insulating film when forming the contact plug. it can. In addition, when a write or erase operation is performed by electron tunneling between the contact plug and the floating gate, the tunnel distance can be made constant, so that variations in operation performance can be prevented.

  In one embodiment, the regulation insulating film is made of a material having a tunnel barrier lower than that of the gate sidewall insulating film.

  According to the semiconductor memory device of this embodiment, since the regulation insulating film that functions as at least a part of the tunnel insulating film has high tunnel efficiency, writing and erasing can be speeded up.

  In one embodiment, the interlayer insulating film is made of silicon oxide, and the regulating insulating film is made of silicon nitride.

  According to the semiconductor memory device of this embodiment, since the interlayer insulating film is made of silicon oxide and the regulating insulating film is made of silicon nitride, the etching rate for the interlayer insulating film and the regulating It is possible to easily provide a large selection ratio with respect to the etching rate with respect to the insulating film. For this reason, when the interlayer insulating film is etched when forming the contact plug, the regulating insulating film can be used as an etching stopper, thereby preventing contact between the contact plug and the floating gate.

  In one embodiment, the distance between the side surface of the floating gate and the contact plug is less than 10 nm.

  According to the semiconductor memory device of this embodiment, since the distance between the floating gate and the contact plug is short, the tunnel efficiency between the two becomes high, and writing or erasing can be performed at high speed.

Also, a method for manufacturing a semiconductor memory device according to the present invention includes:
Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming a floating gate on both sides of the gate electrode via a gate sidewall insulating film;
Forming a diffusion region overlapping with a part of the floating gate in the semiconductor layer;
Forming a regulation insulating film that regulates a constant distance between the contact plug and the floating gate so as to cover the diffusion region and the floating gate;
Forming an interlayer insulating film made of a material different from the material of the regulatory insulating film so as to cover the regulatory insulating film;
Forming a contact hole on the diffusion region by anisotropic etching;
Expanding the inner diameter of the contact hole so that the regulation insulating film is exposed by wet etching;
And a step of forming the contact plug in the contact hole,
Write and erase operations are performed by electron tunneling between the contact plug and the side surface of the floating gate .

  According to the method for manufacturing a semiconductor memory device of the present invention, the contact hole is formed on the diffusion region by anisotropic etching, and the inner diameter of the contact hole is adjusted so that the regulation insulating film is exposed by wet etching. A widening step, so that even when misalignment occurs when the contact hole is formed, the distance between the floating gate and the contact plug can be made constant without using a special process device. be able to.

  Further, the diffusion region overlaps with a part of the floating gate, and the side surface of the floating gate can be shaped substantially along the contact plug, and the contact plug is placed in the vicinity of the floating gate. Therefore, writing or erasing operation of the semiconductor memory device can be performed by tunneling electrons between the floating gate and the contact plug. As described above, a semiconductor memory device can be manufactured in which the area of the electron tunnel region can be increased without increasing the device area on the semiconductor layer, and writing or erasing can be performed at high speed.

  In one embodiment of the method for manufacturing a semiconductor memory device, a material having a tunnel barrier lower than that of the gate sidewall insulating film is used as the regulating insulating film.

  According to the method of manufacturing a semiconductor memory device of this embodiment, the regulation insulating film is made of a material having a tunnel barrier lower than that of the gate side wall insulating film, so that the regulation functioning as at least a part of the tunnel insulating film is used. Since the insulating film for use has a high tunneling efficiency, a semiconductor memory device capable of writing and erasing at high speed can be obtained.

  In one embodiment of the method for manufacturing a semiconductor memory device, the interlayer insulating film is made of a material made of silicon oxide, and the regulating insulating film is made of a material made of silicon nitride.

  According to the method of manufacturing a semiconductor memory device of this embodiment, since the material made of silicon oxide is used as the interlayer insulating film and the material made of silicon nitride is used as the regulatory insulating film, the interlayer insulation is used. It is easy to provide a large selection ratio between the etching rate for the film and the etching rate for the regulation insulating film. For this reason, when the contact plug is formed, when the interlayer insulating film is etched, the regulating insulating film can be used as an etching stopper, thereby preventing contact between the contact plug and the floating gate.

  In one embodiment, the distance between at least a part of the floating gate and the contact plug is less than 10 nm.

  According to the method of manufacturing a semiconductor memory device of this embodiment, since the distance between at least a part of the floating gate and the contact plug is less than 10 nm, the distance between the floating gate and the contact plug is short. As a result, the tunnel efficiency between the two becomes high, and a semiconductor memory device capable of writing or erasing at high speed can be obtained.

Further, the operation method of the semiconductor memory device of the present invention is as follows:
An operation method of the semiconductor memory device,
Write and erase operations are performed by electron tunneling between the contact plug and the side surface of the floating gate.

According to the operation method of the semiconductor memory device of the present invention, hot carriers are not generated in writing and erasing, and charge is directly injected into or extracted from the floating gate by a tunnel phenomenon. In addition, writing and erasing can be performed at high speed.

  According to the semiconductor memory device of the present invention, the diffusion region overlaps with a part of the floating gate, the side surface of the floating gate has a shape substantially along the contact plug, and the contact plug is Since it is in the vicinity of the floating gate, the writing and erasing speed of the memory device can be increased without increasing the device area.

  According to the method for manufacturing a semiconductor memory device of the present invention, the contact hole is formed on the diffusion region by anisotropic etching, and the inner diameter of the contact hole is adjusted so that the regulation insulating film is exposed by wet etching. A side surface of the floating gate can be shaped substantially along the contact plug, and the contact plug can be in the vicinity of the floating gate, so that writing or erasing becomes faster, and Devices with small performance variations can be easily obtained.

According to the operation method of the semiconductor memory device of the present invention, since writing and erasing operations are performed by electron tunneling between the contact plug and the side surface of the floating gate, the memory device has high speed and low power consumption. Can be written and erased.

  Hereinafter, the present invention will be described in detail with reference to the illustrated embodiments.

(First embodiment)
FIG. 1 is a schematic cross-sectional view showing a first embodiment of the semiconductor memory device of the present invention. Although an n-type device will be described here, it can also be formed and used as a p-type device if the conductivity type of the impurity and the applied bias are reversed.

  This semiconductor memory device has a semiconductor substrate 101 (as a semiconductor layer) and a control gate electrode 103 formed on the semiconductor substrate 101 via a gate insulating film 102.

  For example, p-type silicon is used as the semiconductor substrate 101, a thermal oxide film having a thickness of 12 nm is used as the gate insulating film 102, and polysilicon having a thickness of 200 nm is used as the gate electrode 103, for example. Is used.

  Note that although the semiconductor substrate 101 is used here, a semiconductor layer provided over a substrate such as an insulator may be used. Further, an element isolation band by STI (Shallow Trench Isolation) or the like may be appropriately provided on the surface of the semiconductor substrate 101 (that is, the semiconductor layer).

  A channel region is provided above the semiconductor substrate 101 and below the gate electrode 103. On both sides of the channel region (or the gate electrode 103), diffusion regions having a conductivity type opposite to that of the semiconductor substrate 101, that is, source / drain regions 104 and 105 into which arsenic or the like is implanted are provided on the semiconductor substrate 101. It has been.

  A halo region having a high p-type impurity concentration may be formed adjacent to the source / drain regions 104 and 105 in the vicinity of the gate electrode 103.

  Floating gates 110 and 111 are provided on both side surfaces of the gate electrode 103 via gate sidewall insulating films 108 and 109, and the floating gates 110 and 111 are connected to the semiconductor substrate 101 by the floating gate insulating films 106 and 107. The source / drain regions 104 and 105 are insulated from each other.

  A silicon oxide film formed by surface thermal oxidation may be used as the floating gate insulating films 106 and 107 and the gate sidewall insulating films 108 and 109, and polysilicon is used as the floating gates 110 and 111. It may be used.

  The floating gate insulating films 106 and 107 and the gate sidewall insulating films 108 and 109 may be formed by using the same method as in the background art described above. However, in the first embodiment, the floating gate insulating films 106 and 107 and the gate sidewall insulating films 108 and 109 may have the same film thickness. That is, after the surface of the semiconductor substrate 101 and the surface (including side surfaces) of the gate electrode 103 are thermally oxidized, polysilicon is deposited on the entire surface without performing a dry etching process, and the floating gate 110 is etched back. 111 may be formed.

  The dry etching performed on the thermal oxide film performed in the background art described above may cause plasma damage to the surface of the semiconductor substrate 101 corresponding to the bottom of the floating gates 110 and 111, thereby deteriorating device characteristics. In the first embodiment, it is preferable not only to simplify the process but also from the viewpoint of device performance that the dry etching process is unnecessary.

  The positional relationship between the source / drain regions 104 and 105, the floating gates 110 and 111, and the control gate electrode 103 is such that the source / drain region 104 (105) It overlaps with a part of the floating gate 110 (111) and does not overlap with the gate electrode 103.

  An interlayer insulating film 112 is deposited on the source / drain regions 104 and 105, the floating gates 110 and 111, and the control gate electrode 103.

  The contact plugs 113 and 114 connected to the source / drain regions 104 and 105 are formed. Further, another contact plug (not shown) connected to the gate electrode 103 is formed. On the interlayer insulating film 112, metal wiring (not shown) that is electrically connected to the contact plugs 113, 114 and the other contact plugs is formed.

  The side surfaces of the floating gates 110 and 111 have a shape substantially along the contact plugs 113 and 114, and the contact plugs 113 and 114 are in the vicinity of the floating gates 110 and 111. Specifically, the side surfaces of the floating gates 110 and 111 are substantially perpendicular to the semiconductor substrate 101.

  The height dimension of the side surface of the floating gates 110 and 111 is the length dimension of the part of the channel direction overlapping the source / drain regions 104 and 105 in the lower surface of the floating gates 110 and 111. Bigger than.

  The distance between the floating gates 110 and 111 and the contact plugs 113 and 114 is smaller than the distance between the gate electrode 103 and the floating gates 110 and 111. For example, the distance between the floating gates 110 and 111 and the contact plugs 113 and 114 is 5 nm, and the distance between the gate electrode 103 and the floating gates 110 and 111 is 8 nm.

  Next, the write operation of the semiconductor memory device according to the first embodiment will be described with reference to FIG. For example, a voltage such as 0 V is applied to the source / drain regions 104 and 105 and the semiconductor substrate 101, and a voltage of 10 V is applied to the gate electrode 103. In this case, an inversion layer 117 is generated under the gate electrode 103, and the source / drain regions 104 and 105 have substantially the same potential.

  At this time, due to the electric field between the contact plugs 113 and 114 and the gate electrode 103, electrons tunnel from the contact plugs 113 and 114 to the floating gates 110 and 111, and charges 115 and 116 are injected.

  In the first embodiment, the distance between the contact plug 113 (114) and the floating gate 110 (111) is smaller than the distance between the floating gate 110 (111) and the control gate 103. Therefore, the tunneling probability of electrons from the contact plug 113 (114) to the floating gate 110 (111) is from the floating gate 110 (111) through the gate sidewall insulating film 108 (109). Thus, the probability that electrons tunnel to the control gate electrode 103 becomes higher. For this reason, all the charges 115 (116) injected into the floating gate 110 (111) are not re-tunneled to the control gate electrode 103 as they are, and the charges 115 (in the floating gate 110 (111) are not discharged. 116) can be stored.

  In the first embodiment, electron tunneling occurs mainly from the side surface of the floating gate 110. Thus, since the tunnel region is on the side surface of the floating gate 110 (111), the area of the tunnel region can be made very large and writing can be performed at high speed. Further, in order to increase the speed, it is only necessary to increase the height of the control gate 103 and the floating gates 110 and 111, and it is not necessary to increase the horizontal area, so that the chip area is not increased. .

  Next, the erase operation method of the semiconductor memory device of the first embodiment will be described with reference to FIG. For example, a voltage such as 0V is applied to one of the source / drain regions 104, 5V is applied to the other source / drain region 105, 0V is applied to the semiconductor substrate 101, and −5V is applied to the gate electrode 103.

  In this case, since the bias of the gate electrode 103 is negative, it is in a so-called accumulation state, an inversion layer is not formed under the gate electrode 103, and the source / drain regions 104 and 105 are insulated from each other. At this time, a high electric field is applied between the contact plug 114 on the right side (one side) and the gate electrode 103 in the figure, and the floating gate 111 on the right side (one side) in the figure leads to the one contact plug 114. Electron tunneling occurs, and the electric charge 116 accumulated on the right side (one side) in the figure is discharged to the one contact plug 114.

  The same reason as the above write operation, that is, the distance between the control gate 103 and the one floating gate 111 is set larger than the distance between the one floating gate 111 and the one contact plug 114. Therefore, the tunnel probability from the one floating gate 111 to the one contact plug 114 is sufficiently larger than the tunnel probability of electrons from the control gate electrode 103 to the one floating gate 111, The one charge 116 is extracted smoothly.

  On the other hand, since the electric field between the one contact plug 114 and the gate electrode 103 is small, the tunneling of electrons from the one floating gate 111 to the one contact plug 114 is negligibly small. The charge 115 stored in the other side remains stored in the floating gate 110 on the left side (the other side) in the drawing.

  Also in this erasing operation, the side surface of the one floating gate 111 is used as a tunnel region, so that the area of the tunnel region can be increased and erasing can be performed at high speed. If the voltages of the source / drain regions 104 and 105 at the time of erasure are switched, the charge 115 accumulated in the left floating gate 110 can be erased. If both 104 and 105 are set to 5 V, the floating gates 110 and 111 on both sides can be simultaneously erased.

  In the writing and erasing operations described here, since only electron tunneling is used, both writing and erasing can be performed with extremely low power consumption.

  Next, the read operation of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. 4A and 4B. In FIG. 4A and FIG. 4B, the contact plug and the interlayer insulating film are omitted.

  By this read operation, the amount of charge in the left floating gate 110 and the amount of charge in the right floating gate 111 can be read separately, so that one device can store 2-bit information. Can do.

  Here, a case where negative charges 115 are accumulated only in the left floating gate 110 will be described as an example.

  FIG. 4A is a readout for the charge in the left floating gate 110. In this case, a voltage of 3 V or the like is applied to the gate electrode 103 by applying a voltage such as 3 V to the left side of the source / drain region with the source region 104 as 0 V and a right side of the source / drain region as the drain region 105. Apply voltage. The semiconductor substrate 101 is set to 0V.

  At this time, an inversion layer 117 is formed below the gate electrode 103, and electrons flow from the source region 104 to the drain region 105, but are stored in the left floating gate 110 near the source region 104. Due to the influence of the potential of the charge 115, the amount of current is smaller than when there is no negative charge 115. That is, by detecting the magnitude of this current amount, the amount of charge in the left floating gate 110 can be detected. When this is used as information storage, 1-bit information can be stored.

  On the other hand, FIG. 4B shows the readout of the charge in the right floating gate 111. In this case, the source and drain are switched from those in FIG. 4A, and the left side is applied with 3V as the drain region 104, the right side is applied with 0V as the source region 105, 3V is applied to the gate electrode 103, and 0V is applied to the semiconductor substrate 101. To do.

  At this time, electrons flow from the source region 105 to the drain region 104. However, since there is no charge accumulated in the floating gate 111 on the right in the vicinity of the source region 105, compared with the case where there is a negative accumulated charge. Increases the amount of current. Although the negative charge 115 is accumulated in the floating gate 110 on the left, since the inversion layer 117 is pinched off in the vicinity thereof, the amount of current is not easily affected by the potential of the negative charge 115, and the presence or absence of the negative charge 115 is present. Therefore, the amount of current hardly fluctuates. The amount of charge in the right floating gate 111 has a central influence on the flow rate of electrons from the source region 105 to the drain region 104.

  That is, since it is possible to detect only the charge amount in the floating gate on the source side depending on which of the source / drain regions 104 and 105 is the source, it is possible to detect each of the floating gates on both sides. It can be used to store information bit by bit. That is, there is an advantage that 2-bit information can be stored in one memory device.

  As a typical method of using the semiconductor memory device of the first embodiment, as described above, first, as shown in FIG. 2, after batch writing is performed in all floating gates, as shown in FIG. In addition, a method can be used in which information is stored by appropriately erasing bit by bit and reading is performed bit by bit as shown in FIGS. 4A and 4B.

  According to the semiconductor memory device having the above configuration, the source / drain regions 104 and 105 overlap with a part of the floating gates 110 and 111, and the side surfaces of the floating gates 110 and 111 are connected to the contact plug 113. 114, and the contact plugs 113 and 114 are in the vicinity of the floating gates 110 and 111. Therefore, electrons are tunneled between the floating gates 110 and 111 and the contact plugs 113 and 114. Thus, the writing or erasing operation of the semiconductor memory device can be performed. Thus, the area of the electron tunnel region can be increased without increasing the device area on the semiconductor substrate 101, and writing or erasing can be performed at high speed.

  The height dimension of the side surface of the floating gates 110 and 111 is the length in the channel direction of the part of the floating gates 110 and 111 that overlaps the source / drain regions 104 and 105 in the lower surface. Therefore, the area of the floating gates 110 and 111 facing the contact plugs 113 and 114 can be made larger than the area of the floating gates 110 and 111 facing the source / drain regions 104 and 105. Electrons can be reliably tunneled between the floating gates 110 and 111 and the contact plugs 113 and 114.

  The distance between the side surfaces of the floating gates 110 and 111 and the contact plugs 113 and 114 is preferably less than 10 nm. As described above, since the distance between the floating gates 110 and 111 and the contact plugs 113 and 114 is short, the tunnel efficiency between the two becomes high, and writing or erasing can be performed at high speed.

( Reference example )
FIG. 5 shows a reference example of the semiconductor memory device of the present invention. This reference example is characterized in that writing is performed bit by bit using hot carriers. All operations except for the write operation conform to the first embodiment.

  The write operation to the right floating gate 111 will be described. For example, 7V is applied to the gate electrode 103, 0V to the semiconductor substrate 101, 0V to the left source / drain region 104, and 7V to the right source / drain region 105.

  As the voltage value here, a voltage that is insufficient to inject electrons from the contact plugs 113 and 114 to the floating gates 110 and 111 by tunneling is appropriately selected. The amount is negligible.

  On the other hand, an electron flow 118 occurs below the gate electrode 103. At this time, hot electrons 119 are generated by an electric field generated by the potential applied to the right source / drain region 105, particularly near the right floating gate 111, and electrons are injected into the right floating gate 111. . If the voltages of the left and right source / drain regions 104 and 105 are switched, it is possible to inject electrons only into the left floating gate 110. By combining with the erase method and read method described in the first embodiment, writing, erasing and reading can be performed for each individual bit.

(Second Embodiment)
A method for manufacturing a semiconductor memory device according to the second embodiment of the present invention will be described with reference to FIGS. Here again, a method for manufacturing an n-type device will be described as an example.

  First, as shown in FIG. 6A, an element isolation band (not shown) such as LOCOS or STI is provided on the surface of a semiconductor substrate, for example, a p-type silicon substrate 201. Although a p-type silicon substrate is used here, a p-type silicon layer provided on a glass substrate or the like can also be used.

  Next, after thermally oxidizing the surface of the silicon substrate 201 and further depositing a polysilicon layer by a CVD method or the like, patterning is performed by a well-known lithography technique and dry etching technique to form a gate insulating film 202 and a gate electrode 203. .

  For example, the thickness of the gate insulating film 202 is 7 nm, and the height of the gate electrode 203 is 200 nm. As described above, a thermal oxide film is used here as the gate insulating film 202, but a dielectric film may be deposited by a CVD method. As is well known, a metal material such as tungsten may be used for the gate electrode 203.

  Next, as shown in FIG. 6B, the surfaces of the semiconductor substrate 201 and the gate electrode 203 are thermally oxidized, and insulating films 206, 207, and 208 having a film thickness of, for example, 6 nm are formed on the surfaces. These insulating films 206, 207 and 208 can also be formed by the CVD method. After that, a conductive material, here a polysilicon layer, is deposited on the entire surface by a well-known CVD method, and then etched back using a dry etching method so that the insulating film 208 is sandwiched between the side walls of the gate electrode 203. Floating gates 210 and 211 are formed in a sidewall shape.

  At this time, as shown in the schematic view seen from the upper part of FIG. 7A, the side surface and the upper surface of the gate electrode 203 are covered with the insulating film 208, and the periphery of the side surface of the insulating film 208 is Floating gates 210 and 211 are surrounded. The insulating film is also present on the surface of the active region 231.

  Here, in FIG. 7A, the gate electrode 203 is illustrated as a simplified square, but in practice, an appropriate shape can be selected as necessary. For simplification, only one pair of the active regions 231 (regions in which source and drain will be formed later) are shown. However, in an actual memory cell array, a plurality of active regions 231 are provided for one gate electrode (so-called word line). A pair of source / drain is arranged.

  Next, as shown in FIG. 7B, at least a portion where the active region 231 and the floating gates 210 and 211 are close to each other is covered with a protective film 232 such as a photoresist (shown by phantom lines), and then dry etching is performed. Do.

  By this step, the floating gates 210 and 211 in the region close to the active region 231 are left, and the floating gates 210 and 211 in other portions are removed.

  Since the gate electrode 203 and the active region 231 are protected by the insulating film as described above, the gate electrode 203 and the active region 231 are not etched, and eventually only the floating gate at a portion not covered by the protective film 232 can be removed. it can. Thereafter, the protective film 232 is removed using a method such as ashing. Here, the dry etching method is used for the etching of the floating gate, but a wet etching method can also be used. In short, in the region between the active region 231 and the gate electrode 203, the floating gates 210 and 211 are arranged in a sidewall shape, and the active region 231, the gate electrode 203 and the floating gates 210 and 211 are mutually connected. It is only necessary to obtain a structure that is insulated. Thereafter, if necessary, the insulating film on the active region 231 is removed by a method such as wet etching.

  Next, as shown in FIG. 8, a silicon oxide film 233 having a thickness of, for example, 2 nm is formed on the surface by thermal oxidation or CVD, and further, for regulating a silicon nitride film having a thickness of 2 nm by the CVD method. An insulating film 234 is deposited. The material of the regulation insulating film 234 is not limited to the silicon nitride film, and a material whose etching rate for the hydrofluoric acid solution is sufficiently smaller than that of the silicon oxide film may be selected. Further, a material whose electron tunnel barrier is lower than that of the silicon oxide film is more preferable. In view of satisfying these conditions and being easily used in a silicon device process, a silicon nitride film is used here as a representative example. In addition, a material such as aluminum oxide or hafnium oxide may be used. Note that the silicon oxide film 233 may be omitted.

  Thereafter, high-concentration arsenic or phosphorus is implanted by ion implantation, and annealing is performed in a nitrogen atmosphere to form source / drain regions 204 and 205. In addition to this, boron having a concentration lower than that of the arsenic or phosphorus implantation may be implanted at an angle of 15 to 45 degrees to form a so-called halo region in accordance with the desired device characteristics.

In the second embodiment, these implantation steps are performed after the formation of the silicon nitride film 234. However, it is not always necessary at this timing, and the gate is formed before the formation of the silicon nitride film 234. It may be performed at an appropriate timing after the electrode 203 is formed.

However, the source / drain regions 204 and 205 overlap a part of the floating gates 210 and 211 and do not overlap the gate electrode 203. In particular, it is desirable that a part of the portion immediately below the floating gates 210 and 211 is in a carrier depletion state, and a large window for writing and erasing can be taken at the time of reading. In the second embodiment, as an appropriate means for obtaining this structure, implantation and annealing are performed after the silicon nitride film 234 is deposited.

  Next, as shown in FIG. 9, an interlayer insulating film 212 mainly composed of a silicon oxide film is deposited on the entire surface, and contact holes 235 for contact plugs connected to the source / drain regions 204 and 205 are well known. The lithography and etching techniques are used. At this time, the opening position of the contact hole 235 is close to the floating gates 210 and 211 and is not in direct contact with the silicon nitride film 234 on the side surfaces of the floating gates 210 and 211.

  In this etching method for forming the contact hole 235, first, the silicon nitride film (interlayer insulating film 212) is etched at a higher etch rate than the silicon nitride film (regulating insulating film 234), and the silicon nitride film ( Etching is performed until the regulation insulating film 234) is reached, and then etching is performed under a condition where the etching rate for the silicon nitride film is higher than that of the silicon oxide film, so that the silicon nitride film (regulation insulating film) at the bottom of the contact hole 235 234). This method is a preferable method with little damage to the surface of the source / drain regions 204 and 205 at the bottom of the contact hole 235.

  Since the diameter of the contact hole 235 is expanded later by wet etching, the inner diameter of the contact hole 235 at this stage may be smaller than the diameter of the contact plug that is finally desired, and the subsequent wet etching process is taken into consideration. And design.

  Next, as described above, the inner diameter of the contact hole 235 is expanded by wet etching using a solution containing hydrofluoric acid, and at the same time, the oxide film at the bottom of the contact hole 235 is removed. This wet etching is performed to such an extent that the silicon nitride film (regulating insulating film 234) on the side surfaces of the floating gates 210 and 211 is exposed inside the contact hole 235. At this time, since the silicon nitride film is hardly dissolved in hydrofluoric acid, the floating gates 210 and 211 are not exposed.

  Thereafter, as shown in FIG. 10, a contact material 213 and 214 connected to the source / drain regions 204 and 205 are formed by embedding a plug material such as tungsten in the contact hole 235 having the opening widened by a known method. To do.

  Thereafter, the metal wiring (not shown) is appropriately formed. Although other contact plugs to the gate electrode 203 are not shown, the formation of the other contact plugs is performed simultaneously with the step of forming the contact plugs 213 and 214 to the source / drain regions 204 and 205. It is clear from the well-known contact plug formation technique that it can be formed.

Next, writing, erasing, and reading of the semiconductor memory device of the second embodiment obtained through the above steps can be performed in the same manner as the first embodiment and the reference example described above.

FIG. 11 shows a write operation of the semiconductor memory device of the second embodiment based on the write method described in the first embodiment. For example, a voltage such as 0 V is applied to the source / drain regions 204 and 205 and the semiconductor substrate 201, and a voltage of 7 V is applied to the gate electrode 203. The inversion layer generated at this time is not shown.

  At this time, due to the electric field between the contact plugs 213 and 214 and the gate electrode 203, electrons tunnel from the contact plugs 213 and 214 to the floating gates 210 and 211, and charges 215 and 216 are injected. , Writing is done.

  Thus, since the tunnel region is on the side surface of the floating gates 210 and 211, the tunnel region can be made large without increasing the device area, and writing can be performed at high speed.

  On the other hand, the erasing is the same as in the first embodiment. For example, if the semiconductor substrate 201 is 0V, the gate electrode 203 is −4V, one of the source / drain regions 204 and 205 is 4V, and the other of the source / drain regions 204 and 205 is 0V, the 4V application side The charge in the floating gate can be erased. If 4 V is applied to both the source / drain regions 204 and 205, the charges in the floating gates on both sides can be erased simultaneously.

Further, the second embodiment has the following advantages in addition to the advantages of the first embodiment. That is, the tunnel distance between the floating gate 210 (211) and the contact plug 213 (214) is defined by the film thickness of the silicon oxide film 233 and the silicon nitride film 234.

  According to this manufacturing method, even if misalignment occurs in the lithography process at the time of contact hole formation, the distance between the contact plugs 213 and 214 to be finally formed and the floating gates 210 and 211 is constant. In particular, the left and right floating gates 210 and 211 do not become unbalanced.

  Since this tunnel distance greatly influences the tunnel efficiency, the method of making the tunnel distance constant in the self-alignment shown in this embodiment is the variation between lots in the writing and erasing speed and between the left and right floating gates. This is a very effective means for preventing variation.

  In this embodiment, the silicon nitride film 234 is used as a part of the tunnel insulating film. However, since this silicon nitride film has a lower tunnel barrier for electrons than the silicon oxide film, it efficiently emits electrons. Tunneling can be performed, and writing / erasing can be accelerated.

As in the above reference example , the write operation can use hot carrier injection, and electron tunneling can be used only for the erase operation. In this case, in the writing operation, writing can be performed individually for the left and right floating gates, and in erasing, electron tunneling can be used with low power consumption.

  Further, it is preferable to use a material having a tunnel barrier lower than that of the gate sidewall insulating film 208 as the regulating insulating film 234. As described above, the regulation insulating film 234 acting as at least a part of the tunnel insulating film has a high tunneling efficiency, so that a semiconductor memory device capable of writing and erasing at high speed can be obtained.

  Further, it is preferable that the distance between at least a part of the floating gates 210 and 211 and the contact plugs 213 and 214 is less than 10 nm. As described above, since the distance between the floating gates 210 and 211 and the contact plugs 213 and 214 is short, the tunnel efficiency between the two becomes high, and a semiconductor memory device capable of writing or erasing at high speed is obtained.

  In addition, this invention is not limited to the above-mentioned embodiment. For example, the film type, film thickness, and applied voltage shown in this embodiment are merely examples, and may be appropriately designed according to the purpose of use of the device.

1 is a schematic cross-sectional view of a main part of a semiconductor memory device according to a first embodiment of the present invention. FIG. 4 is a schematic cross-sectional view for explaining the write operation of the semiconductor memory device in the first embodiment of the present invention. FIG. 3 is a schematic cross-sectional view for explaining an erasing operation of the semiconductor memory device in the first embodiment of the present invention. It is a schematic sectional drawing explaining the 1st read-out method of the semiconductor memory device in the 1st Embodiment of this invention. It is a schematic sectional drawing explaining the 2nd read-out method of the semiconductor memory device in the 1st Embodiment of this invention. It is a schematic sectional drawing explaining the write-in operation | movement of the semiconductor memory device in the reference example of this invention. It is a schematic process sectional drawing explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic process sectional drawing explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic process bird's-eye view explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic process bird's-eye view explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic process sectional drawing explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic process sectional drawing explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic process sectional drawing explaining the manufacturing method of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic sectional drawing explaining the write-in operation | movement of the semiconductor memory device in the 2nd Embodiment of this invention. It is a schematic sectional drawing of the principal part of the conventional semiconductor memory device. It is a schematic process sectional drawing explaining the manufacturing method of the conventional semiconductor memory device. It is a schematic process sectional drawing explaining the manufacturing method of the conventional semiconductor memory device. It is a schematic sectional drawing explaining the write-in operation | movement of the conventional semiconductor memory device. It is a schematic sectional drawing explaining the read-out operation | movement of the conventional semiconductor memory device. It is a schematic sectional drawing explaining the erasing operation | movement of the conventional semiconductor memory device.

101, 201 Semiconductor substrate 102, 202 Gate insulating film 103, 203 (Control) Gate electrode 104, 105, 204, 205 Source / drain region 106, 107, 206, 207 Floating gate insulating film 108, 109, 208 Gate sidewall insulating film 110, 111, 210, 211 Floating gate 112, 212 Interlayer insulating film 113, 114, 213, 214 Contact plug 115, 116, 215, 216 Charge 117 Inversion layer 118 Electron flow 119 Hot electron 231 Active region 232 Protective film (Photo Resist)
233 Silicon oxide film 234 Regulation insulating film (silicon nitride film)
235 contact hole

Claims (11)

A semiconductor layer;
A gate electrode formed on the semiconductor layer via a gate insulating film;
A floating gate formed on both sides of the gate electrode via a gate sidewall insulating film;
A channel region provided in the semiconductor layer and disposed under the gate electrode;
A diffusion region provided in the semiconductor layer and disposed on both sides of the channel region;
A contact plug connected to the diffusion region,
The diffusion region overlaps a part of the floating gate,
The side surface of the floating gate has a shape substantially parallel to the contact plug,
The distance between the floating gate and the contact plug is smaller than the distance between the gate electrode and the floating gate,
A semiconductor memory device , wherein writing and erasing operations are performed by electron tunneling between the contact plug and the side surface of the floating gate . The semiconductor memory device according to claim 1,
The height dimension of the side surface of the floating gate having a shape substantially along the contact plug is larger than the length dimension of the part of the channel direction overlapping the diffusion region in the lower surface of the floating gate. A semiconductor memory device characterized by being large. The semiconductor memory device according to claim 1,
An interlayer insulating film on the gate electrode and the diffusion region;
A regulating insulating film that is made of a material different from the material of the interlayer insulating film and that regulates the distance between the contact plug and the floating gate to be constant is provided between the floating gate and the contact plug. A semiconductor memory device. The semiconductor memory device according to claim 3 .
The semiconductor memory device, wherein the regulating insulating film is made of a material having a tunnel barrier lower than that of the gate sidewall insulating film. The semiconductor memory device according to claim 3 .
2. The semiconductor memory device according to claim 1, wherein the interlayer insulating film is made of silicon oxide, and the regulating insulating film is made of silicon nitride. The semiconductor memory device according to claim 1,
A distance between the side surface of the floating gate and the contact plug is less than 10 nm. Forming a gate electrode on the semiconductor layer via a gate insulating film;
Forming a floating gate on both sides of the gate electrode through a gate sidewall insulating film;
Forming a diffusion region overlapping with a part of the floating gate in the semiconductor layer;
Forming a regulation insulating film that regulates a constant distance between the contact plug and the floating gate so as to cover the diffusion region and the floating gate;
Forming an interlayer insulating film made of a material different from the material of the regulatory insulating film so as to cover the regulatory insulating film;
Forming a contact hole on the diffusion region by anisotropic etching;
Expanding the inner diameter of the contact hole so that the regulation insulating film is exposed by wet etching;
And a step of forming the contact plug in the contact hole,
A method of manufacturing a semiconductor memory device, wherein write and erase operations are performed by electron tunneling between the contact plug and the side surface of the floating gate . The method of manufacturing a semiconductor memory device according to claim 7 .
A method of manufacturing a semiconductor memory device, characterized in that a material having a tunnel barrier lower than that of the gate sidewall insulating film is used as the regulating insulating film. The method of manufacturing a semiconductor memory device according to claim 7 .
A method of manufacturing a semiconductor memory device, wherein a material made of silicon oxide is used for the interlayer insulating film, and a material made of silicon nitride is used for the regulating insulating film. The method of manufacturing a semiconductor memory device according to claim 7 .
A method of manufacturing a semiconductor memory device, wherein a distance between at least a part of the floating gate and the contact plug is less than 10 nm. An operation method of the semiconductor memory device according to claim 1,
A method of operating a semiconductor memory device, wherein write and erase operations are performed by electron tunneling between the contact plug and the side surface of the floating gate.

Images