JP2007081255A - Manufacturing method of semiconductor laminate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a gallium nitride semiconductor layer in which generation of cracks is suppressed.
A first step of forming, on a surface of the silicon substrate, a wall portion that extends in a substantially vertical direction from the surface of the silicon substrate and divides the surface of the silicon substrate into a plurality of regions; A second step of forming a semiconductor layer 42 by crystal growth of gallium nitride of a semiconductor material different from that of the silicon substrate 10 from each region of the surface of the silicon substrate 10 partitioned by the wall portion 22; A third step of forming a plurality of semiconductor stacked bodies in which the semiconductor layer 42 is stacked on the silicon substrate 10 is performed by dicing along at least a part of the planar pattern.
[Selection] Figure 4

Description

  The present invention relates to a method for manufacturing a semiconductor stacked body in which a semiconductor layer made of a material different from a semiconductor substrate is stacked on the surface of a semiconductor substrate.

  Gallium nitride has a high breakdown field strength and a high saturation electron mobility. For this reason, a semiconductor device using gallium nitride is expected to realize high breakdown voltage, high frequency, and high temperature operation. However, gallium nitride is extremely expensive compared to, for example, general-purpose silicon. For this reason, the development of a technique for growing a gallium nitride semiconductor layer having a thickness necessary for crystal growth of gallium nitride on an inexpensive silicon substrate and making a semiconductor device is underway.

The thermal expansion coefficients of gallium nitride and silicon are very different. For this reason, when a gallium nitride semiconductor layer having a predetermined thickness is formed on the entire surface of the silicon substrate, a difference in thermal expansion occurs between the two due to a temperature change or the like. When excessive stress based on this thermal expansion difference is applied to the semiconductor layer, cracks are generated in the semiconductor layer.
Patent Document 1 discloses a technique in which a silicon oxide layer having openings dispersed therein is formed on the surface of a silicon substrate, and gallium nitride is crystal-grown from the silicon substrate exposed in the openings. According to Patent Document 1, a wide distance between the openings is ensured. For this reason, the gallium nitride crystal grown from the silicon substrate exposed in the opening cannot crystal grow laterally on the surface of the silicon oxide layer between the openings. According to Patent Document 1, the gallium nitride semiconductor layer is selectively formed only above the opening. The gallium nitride semiconductor layer is spatially separated above the silicon oxide layer. The spatial separation of the gallium nitride semiconductor layer reduces stress based on the difference in thermal expansion between the silicon substrate and the gallium nitride semiconductor layer, and prevents the semiconductor layer from cracking.

JP-A-11-186178

However, in Patent Document 1, since the distance between the openings is widely secured, the total area of the gallium nitride semiconductor layers obtained from one silicon substrate is small. For this reason, a gallium nitride semiconductor layer cannot be manufactured efficiently.
Note that this type of problem may occur in other than the combination of a silicon substrate and gallium nitride. For example, a semiconductor substrate such as a sapphire substrate or a SiC substrate and a III-V group compound semiconductor (typically, Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1 and 0 ≦ 1-X−Y ≦ 1)), which may also occur. That is, the problem to be solved by the present invention can generally occur in a semiconductor stacked body in which a semiconductor layer made of a material different from the semiconductor substrate is stacked on the surface of the semiconductor substrate.
The present invention proposes a method of suppressing the generation of cracks based on the difference in thermal expansion between a semiconductor substrate and a semiconductor layer and contributing to a reduction in manufacturing cost.

In the present invention, the semiconductor layer and the semiconductor layer are not spatially separated. The semiconductor layer and the semiconductor layer are separated via a wall portion. The wall is not required to have an area enough to use the space disclosed in Patent Document 1. Since the wall portion is interposed between the semiconductor layers, the semiconductor layer is divided into a plurality of parts. Since the semiconductor layer is divided into a plurality of parts, the area of each semiconductor layer is limited to be small. When the area of each semiconductor layer is small, even if a stress is applied to the semiconductor layer according to a difference in thermal expansion between the semiconductor layer and the semiconductor substrate, the semiconductor layer can withstand the stress. In addition, the stress applied to the semiconductor layer can be relaxed by contracting and expanding the intervening wall portion. Thereby, the occurrence of cracks in the semiconductor layer is suppressed. In the present invention, the area of each semiconductor layer is limited to be small, but the total area of the semiconductor layers formed on one semiconductor substrate is large. For this reason, the area of the semiconductor layer obtained from one semiconductor substrate is large, and the manufacturing cost can be suppressed.
Note that the silicon oxide layer of Patent Document 1 may be present as a “wall portion” between the openings if viewed in a broad sense. However, the silicon oxide layer of Patent Document 1 is formed so that the area of the silicon oxide layer is extremely larger than the area of the opening, and this cannot be considered as a wall portion. The silicon oxide layer of Patent Document 1 is completely different from the wall portion referred to in this specification. Therefore, it is clear that the silicon oxide layer of Patent Document 1 is not a motivation for conceiving the wall portion of the present invention.
Here, the “semiconductor functional structure” used in this specification will be described. The “semiconductor functional structure” refers to a structure that can exhibit a specific function by a combination of a plurality of semiconductor regions into which impurities are introduced, for example. Typically, switching MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), IGBTs (Insulated Gate Bipolar Transistors), and the like are included. In addition, a structure such as a micromachine is also included.

The manufacturing method created in the present invention is embodied in a method for manufacturing a semiconductor stacked body in which a semiconductor layer of a material different from that of a semiconductor substrate is stacked on the surface of the semiconductor substrate. The production method of the present invention comprises at least the following three steps. In the first step, a wall portion that extends in a substantially vertical direction from the surface of the semiconductor substrate and divides the surface of the semiconductor substrate into a plurality of regions is formed on the surface of the semiconductor substrate. In the second step, a semiconductor layer is formed by crystal growth of a semiconductor material different from the semiconductor substrate from each region on the surface of the semiconductor substrate partitioned by the wall portion. In the third step, dicing is performed along at least a part of the planar pattern of the wall portion to form a plurality of semiconductor stacked bodies in which semiconductor layers are stacked on a semiconductor substrate.
When implemented up to the second step, a semiconductor layer divided into a plurality of walls by the wall is formed on the semiconductor substrate. A wall portion is interposed between the semiconductor layers. Note that a part of the semiconductor layer may be continuous beyond the wall. Also in this case, most of the semiconductor layer is separated by the wall portion, and it can be evaluated that the semiconductor layer is substantially divided into a plurality of portions by the wall portion. When the semiconductor layer is divided into a plurality of parts, the area of each semiconductor layer is limited to be small. When the area of each semiconductor layer is small, even if a stress is applied to the semiconductor layer according to the difference in thermal expansion between the semiconductor layer and the semiconductor substrate, the semiconductor layer can withstand the stress. In addition, the stress applied to the semiconductor layer can be relaxed by contracting and expanding the intervening wall portion. Thereby, the occurrence of cracks in the semiconductor layer is suppressed.
Moreover, the semiconductor laminated body by which the semiconductor layer is laminated | stacked on the semiconductor substrate can be obtained by implementing a 3rd process. As the area of the semiconductor stacked body, an area finally required as a chip is secured. That is, according to the present invention, the semiconductor layer is divided into the chip size by the wall portion in advance, instead of dividing into the chip size after forming the semiconductor layer having a large area where cracks are likely to occur. Thereby, a good quality semiconductor layer with reduced cracks can be obtained. Further, dicing is performed along at least a part of the planar pattern of the wall portion. That is, since the wall portion is formed along the scribe line for dicing, even if the wall portion is provided, a substantial decrease in the area of the obtained semiconductor layer can be suppressed. The present invention can efficiently form a semiconductor layer on a semiconductor substrate. Many semiconductor layers can be obtained from one semiconductor substrate.
Regarding dicing, “along at least part of the planar pattern of the wall” includes not only cutting out a plurality of semiconductor layers individually but also including cutting out a part of a plurality of semiconductor layers. Means. Moreover, dicing should just be performed along the plane pattern of a wall part, and it does not become a problem whether the wall part actually exists in the case of dicing.

The first step preferably includes a step of forming a silicon oxide layer on the semiconductor substrate and a step of forming a plurality of grooves reaching the semiconductor substrate from the surface of the silicon oxide layer.
When a plurality of grooves are formed in the silicon oxide layer, the remaining silicon oxide layer can be used as a wall portion.

It is preferable to stop the second step before the crystal-grown semiconductor layer exceeds the height of the wall.
Thereby, the state by which the semiconductor layer was divided | segmented into plurality by the wall part can be obtained. The effects of the present invention can be obtained effectively.

It is preferable that the material of the wall portion is a material from which the semiconductor layer does not grow from the surface. In this case, the second step is characterized in that the semiconductor layer is crystal-grown only from the surface of the semiconductor substrate.
When the semiconductor layer is crystal-grown from the surface of the wall, most of the semiconductor layer continues beyond the wall. In this case, it may be difficult to obtain a semiconductor layer divided into a plurality of parts. For this reason, it is preferable to use a material that does not allow crystal growth of the semiconductor layer from the surface of the wall portion. A state where the semiconductor layer is divided into a plurality of portions by the wall portion can be obtained. The effects of the present invention can be obtained effectively.

In the third step, it is preferable that dicing is performed along at least a part of the planar pattern of the space formed by the wall portion to form a plurality of semiconductor stacked bodies in which semiconductor layers are stacked on a semiconductor substrate. Moreover, it is more preferable to form a space by removing the wall portion before dicing, and to perform dicing along at least a part of the plane pattern of the space.
In this case, by removing the wall portion, the dicing blade (cutting blade) enters the space and cuts the semiconductor substrate (or forms a split groove). Therefore, the semiconductor layer is prevented from being damaged during dicing, and the yield can be improved.

It is preferable to further include a step of forming a semiconductor functional structure in the semiconductor layer between the second step and the third step.
In this case, the lamination of the semiconductor substrate and the semiconductor layer is before dicing, and a semiconductor functional structure can be formed in the semiconductor layer in a state where it is easy to handle.

It is preferable that the thickness of the wall portion separating the semiconductor layer and the semiconductor layer substantially matches the width of the dicing scribe line. The width of the scribe line varies depending on the type of dicing blade (cutting blade) to be used. In this case, the thickness of the wall portion may be adjusted according to the type. That is, the thickness of the wall portion only needs to have at least a thickness that can relieve stress based on the difference in thermal expansion, and the upper limit of the thickness may be adjusted depending on the type of dicing blade (cutting blade) to be used. .
The part corresponding to the width of the scribe line is a part that is eventually wasted. Therefore, when the thickness of the wall portion substantially matches the width of the scribe line, even if the wall portion is provided, a substantial decrease in the area of the obtained semiconductor layer can be suppressed. The present invention can efficiently form a semiconductor layer on a semiconductor substrate. Many semiconductor layers can be obtained from one semiconductor substrate.

The semiconductor substrate is preferably a silicon substrate.
By using an inexpensive silicon substrate, the manufacturing cost can be suppressed.

The semiconductor layer is preferably gallium nitride.
By using the production method of the present invention, gallium nitride having useful characteristics can be obtained in a good quality state.

  According to the manufacturing method of the present invention, the generation of cracks based on the difference in thermal expansion between the semiconductor substrate and the semiconductor layer can be suppressed, and the manufacturing cost can be reduced.

The features of the present invention are listed.
(First Embodiment) The semiconductor substrate and the semiconductor layer are different semiconductor materials. There is a difference in thermal expansion coefficient between the two. The larger the difference in thermal expansion coefficient, the more preferably the semiconductor layer is divided more finely by the wall portion. However, it is preferable to secure the area required for the chip as the area of the semiconductor layer.
(2nd form) A sapphire substrate, a SiC substrate, etc. can be utilized for a semiconductor substrate.
(3rd form) A III-V group compound semiconductor can be utilized for a semiconductor layer. Typically, a semiconductor material having a general formula of Al _X Ga _Y In _1-XY N (where 0 ≦ X ≦ 1, 0 ≦ Y ≦ 1, 0 ≦ 1-X−Y ≦ 1) is used. can do. A large difference in thermal expansion coefficient exists between these semiconductor layers and the semiconductor substrate of the second form.
(4th form) A silicon oxide and silicon nitride can be utilized for a wall part.

A method for manufacturing a semiconductor stacked body in which a gallium nitride semiconductor layer is stacked on a silicon substrate will be described below with reference to FIGS.
First, as shown in FIG. 1, a silicon substrate 10 is prepared, and a silicon oxide layer 20 is formed on the silicon semiconductor substrate 10 by using a CVD (Chemical Vapor Deposition) method. A sputtering method may be used instead of the CVD method. Note that the thickness of the silicon oxide layer 20 is appropriately adjusted according to the characteristics of the semiconductor functional structure formed in the semiconductor layer, as will be described later.
Next, as shown in FIG. 2, a resist 30 is patterned on the surface of the silicon oxide layer 20 by using a lithography technique. The resist 30 is patterned in a lattice pattern on the surface of the silicon oxide layer 20 when viewed in plan.

  Next, as shown in FIG. 3, a groove 40 reaching the silicon substrate 10 from the surface of the silicon oxide layer 20 exposed from the resist 30 is formed using an anisotropic etching technique. The groove 40 is formed in accordance with the window portion of the resist 30 patterned in a lattice shape. The shape of the groove 40 is a substantially rectangular parallelepiped shape, and the plurality of grooves 40 are repeatedly formed in parallel in the vertical and horizontal directions. When the plurality of grooves 40 are formed, the remaining silicon oxide layer 20 becomes the wall portion 22. The wall portion 22 extends from the surface of the silicon substrate 10 in a substantially vertical direction, and divides the surface of the semiconductor substrate 10 into a plurality of regions. The wall portion 22 extends linearly continuously in the vertical and horizontal directions. As will be described later, since the wall portion 22 becomes a dicing scribe line, it is preferable that the wall portion 22 continuously extends linearly in the vertical and horizontal directions.

  Next, as shown in FIG. 4, gallium nitride is crystal-grown from each region of the surface of the silicon substrate 10 partitioned by the wall 22 using, for example, MOCVD (Metal-Organic Chemical Vapor Deposition). Thus, a plurality of semiconductor layers 42 are formed. At this time, a growth condition in which gallium nitride does not grow from the surface of the wall portion 22 is applied. If necessary, aluminum nitride (AlN) or the like may be formed as a buffer layer before crystal growth. Crystal growth of the semiconductor layer 42 is stopped before the upper surface of the semiconductor layer 42 exceeds the height of the wall portion 22. Thereby, the semiconductor layer 42 is accommodated in the groove 40, and a state in which the semiconductor layer 42 is divided into a plurality of portions by the wall portion 22 is obtained. When crystal growth of the semiconductor layer 42 (1) does not exceed the height of the wall portion 22 and (2) occurs only from the surface of the silicon substrate 10, the semiconductor layer 42 is formed by the wall portion 22. It is completely divided into multiple parts.

  At this stage, the semiconductor layer 42 divided into a plurality by the wall portion 22 is formed on the silicon substrate 10. The wall 22 is interposed between the semiconductor layer 42 and the semiconductor layer 42. When the semiconductor layer 42 is divided into a plurality of parts, the area of each semiconductor layer 42 is limited to be small. If the area of each semiconductor layer 42 is small, even if a stress is applied to the semiconductor layer 42 according to the difference in thermal expansion between the semiconductor layer 42 and the semiconductor substrate 42, the semiconductor layer 42 can withstand the stress. Moreover, the stress which generate | occur | produces in the semiconductor layer 42 can be relieve | moderated when the intervening wall part 22 contracts and expands. Thereby, the occurrence of cracks in the semiconductor layer 42 is suppressed.

At this stage, it is preferable to build a semiconductor functional structure in the semiconductor layer 42. At this stage, the silicon substrate 10 and the plurality of semiconductor layers 42 remain in a large area. The plurality of semiconductor layers 42 are given mechanical strength by the silicon substrate 10. For this reason, it is easy to handle a stacked body of the silicon substrate 10 and the plurality of semiconductor layers 42. Therefore, a semiconductor functional structure can be formed in the semiconductor layer 42 in a stable state. Also, the process of creating a semiconductor functional structure often involves a heat treatment process. In many cases, the heat treatment process greatly changes the ambient temperature. However, as described above, in the stacked body of the silicon substrate 10 and the semiconductor layer 42 divided into a plurality, even if a temperature change occurs, the generation of cracks in the semiconductor layer 42 is suppressed. Therefore, if a semiconductor functional structure is formed in the semiconductor layer 42 at this stage, the semiconductor functional structure can be formed in the semiconductor layer 42 with a high yield.
Further, the area required when the semiconductor layer 42 is viewed in a plan view is secured to a size required for a chip having a semiconductor functional structure. For example, when the semiconductor functional structure is a MOSFET, the area of the semiconductor layer 42 needs to be 7 to 10 mm □ to obtain a current capacity of 100 A. Therefore, it can be said that the semiconductor layer 42 is partitioned by the wall portion 22 according to the size required for the chip in advance. That is, the semiconductor layer 42 is not divided into chip sizes after the formation of the large-area semiconductor layer 42 where cracks are likely to occur, but is divided into chip sizes in advance using the wall portion 22. As a result, a chip having a desired size can be obtained while obtaining a high-quality semiconductor layer 42 with reduced cracks.

Next, as shown in FIG. 5, the wall portion 22 is removed using a hydrofluoric acid solution or the like. A space 24 is formed in the portion where the wall portion 22 is removed. This space 24 coincides with the existence range of the wall portion 22.
Next, as shown in FIG. 6, dicing is performed along the plane pattern of the space 24 to form a plurality of semiconductor stacked bodies 50 in which the semiconductor layers 42 are stacked on the silicon substrate 10. At this time, the dicing blade (cutting blade) enters the space 24 and cuts the silicon substrate 10. Since the dicing blade (cutting edge) and the semiconductor layer 42 are not in direct contact with each other, the semiconductor layer 42 is prevented from being damaged.
Dicing is performed along the plane pattern of the space 24. That is, the space 24 corresponds to a dicing scribe line. For this reason, even if the space 24 is provided, the area of the obtained semiconductor layer 42 does not decrease. For example, the width of the flange 22 (space 24) separating the semiconductor layer 42 and the semiconductor layer 42 is about 100 μm, and this width substantially matches the width of the scribe line. For this reason, the semiconductor layer 42 can be efficiently formed on the silicon substrate 10. Many semiconductor layers 42 can be obtained from one silicon substrate 10.

(Modification of wall)
FIG. 7 shows a modification of the wall portion.
This wall portion includes a silicon wall 125 and silicon oxide films 126 and 127 covering the silicon wall 125. The silicon wall 125 extends from the surface of the silicon substrate 100 in a substantially vertical direction, and divides the surface of the semiconductor substrate 100 into a plurality of regions. The silicon oxide films 126 and 127 include a side-surface silicon oxide film 126 that covers the side surface of the silicon wall 125 and an upper-surface silicon oxide film 127 that covers the upper surface of the silicon wall 125. Note that it can be evaluated that the silicon wall 125 and the silicon substrate 100 are substantially integrated.
This wall can be formed, for example, by the following procedure.
A plurality of grooves having a predetermined depth are formed from the surface of the silicon substrate 100, and the remainder is formed as a silicon wall 125. Thereafter, it can be obtained by selectively forming silicon oxide films 126 and 127 on the surface of the silicon wall 125.
In the same manner as in the above embodiment, a gallium nitride semiconductor layer is formed on the wall portion in the portion surrounded by the wall portion, whereby a high-quality semiconductor layer can be obtained.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

A process of manufacturing a semiconductor stack is shown (1). A process of manufacturing a semiconductor stack is shown (2). A process of manufacturing a semiconductor stack is shown (3). A process of manufacturing a semiconductor stack is shown (4). A process of manufacturing a semiconductor stack is shown (5). A process of manufacturing a semiconductor stack is shown (6). The modification of a wall part is shown.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10, 100: Silicon substrate 20: Silicon oxide layer 22: Wall part 24: Space 30: Resist 40: Groove 42: Semiconductor layer 50: Semiconductor laminated body 125: Silicon wall 126: Side surface silicon oxide film 127: Upper surface silicon oxide film

Claims (9)

A method of manufacturing a semiconductor laminate in which a semiconductor layer of a material different from a semiconductor substrate is laminated on the surface of a semiconductor substrate,
A first step of forming, on the surface of the semiconductor substrate, a wall portion extending in a substantially vertical direction from the surface of the semiconductor substrate and dividing the surface of the semiconductor substrate into a plurality of regions;
A second step of forming a semiconductor layer by crystal growth of a semiconductor material different from the semiconductor substrate from each region of the surface of the semiconductor substrate partitioned by the wall;
A third step of dicing along at least a part of the planar pattern of the wall and forming a plurality of semiconductor laminates in which semiconductor layers are laminated on a semiconductor substrate;
A method for producing a semiconductor laminate, comprising: The first step includes
Forming a silicon oxide layer on a semiconductor substrate;
Forming a plurality of grooves reaching the semiconductor substrate from the surface of the silicon oxide layer;
The manufacturing method of Claim 1 characterized by the above-mentioned. The second step,
3. The method according to claim 1, wherein the crystal grown semiconductor layer is stopped before the height of the wall is exceeded. The material of the wall is a material from which the semiconductor layer does not grow from the surface,
4. The method according to claim 1, wherein in the second step, the semiconductor layer is crystal-grown only from the surface of the semiconductor substrate. The third step includes
A dicing along at least a part of a planar pattern of a space formed by removing the wall portion to form a plurality of semiconductor stacked bodies in which semiconductor layers are stacked on a semiconductor substrate. The manufacturing method in any one of 1-4.   6. The method according to claim 1, further comprising a step of forming a semiconductor functional structure in the semiconductor layer between the second step and the third step.   The manufacturing method according to claim 1, wherein the thickness of the wall portion separating the semiconductor layer and the semiconductor layer substantially matches the width of the scribe line for dicing.   The manufacturing method according to claim 1, wherein the semiconductor substrate is a silicon substrate. The manufacturing method according to claim 1, wherein the semiconductor layer is gallium nitride.

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