JP2007043892A - Overboosting prevention circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent malfunction in an overboosting prevention circuit which prevents a boosting circuit from being overboosted by removing ripples occurring in the boosting circuit. <P>SOLUTION: The overboosting prevention circuit controls the output voltage Vout (<0V) of a charge pump circuit so that a difference (Vdd-Vout) between the power supply voltage Vdd and the output voltage Vout (<0V) of the charge pump circuit 2 does not exceed a predetermined value VMAX. That is, the charge pump circuit 2 performs boosting operation when Vdd-Vout<VMAX, and stops the boosting operation when Vdd-Vout>VMAX. An influence of the ripples caused in the charge pump circuit 2 is removed because the reference voltage Vref to an operational amplifier is determined relative to a ground voltage Vss. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an over-boosting prevention circuit that prevents over-boosting of a boosting circuit that generates a negative output voltage with respect to a ground voltage in accordance with a boosting clock.

  Conventionally, a charge pump circuit is known as a kind of booster circuit that boosts the power supply voltage several times. The charge pump circuit is widely used as a power supply circuit for portable electronic devices, for example. A general charge pump circuit is a power supply input by connecting a plurality of switching elements in series, supplying a boost clock to each connection node of the switching elements via a capacitor, and transferring charges through the switching elements. Boost the voltage.

  However, as a result of boosting, a high voltage is applied to the transistors used as switching elements of the charge pump circuit and the transistors constituting the circuit receiving the supply of the output voltage Vout of the charge pump circuit.

  For example, as shown in FIG. 6A, when the output voltage Vout is applied to the gate G of the MOS transistor and the ground voltage Vss is applied to the source S, a high voltage Vout is applied between the gate and source. Become. As shown in FIG. 6B, when the output voltage Vout is applied to the drain D of the MOS transistor and the ground voltage Vss is applied to the source S, a high voltage Vout is applied between the source and drain. Become.

  Therefore, a high breakdown voltage structure has been adopted as the device structure of such a MOS transistor. However, the MOS transistor having a high breakdown voltage structure has a problem that the current drive capability is low because the gate insulating film is thick or the concentration of the source / drain diffusion layer is low.

  Therefore, a circuit for limiting the output voltage Vout of the charge pump circuit has been considered in order to reduce the breakdown voltage of the MOS transistor and improve the current driving capability. For example, if the power supply voltage Vdd = 4V is doubled to obtain 8V, a MOS transistor that can withstand 8V is required. However, if the output voltage Vout of the charge pump circuit is limited to 5.5V, a 5V system Since MOS transistors can be used, current drive capability can be improved and chip size can be reduced.

  FIG. 7 is a circuit diagram of such an over-boosting prevention circuit. A voltage V0 is generated by dividing the output voltage Vout (> 0V) of the charge pump circuit 50 that performs positive boosting by resistors R1 and R2, and a reference voltage Vref based on the voltage V0 and the ground voltage Vss (= 0V) Are compared by the comparator 51, and the supply of the boost clock φ to the charge pump circuit 50 is controlled by the output of the comparator 51. That is, when V0 <Vref, the output of the comparator 51 is at the H (high) level, and the boost clock φ is supplied to the charge pump circuit 50, so that the charge pump circuit 50 performs a normal operation. When V0 rises and V0> Vref, the output of the comparator 51 becomes L (low) level, and the supply of the boost clock φ to the charge pump circuit 50 is stopped. Then, the boosting operation of the charge pump circuit 50 is stopped. Here, V0 = Vout × R2 / (R1 + R2).

  That is, the boosting operation of the charge pump circuit 50 is stopped when Vout> Vref × (R1 + R2) / R2.

  On the other hand, in a charge pump circuit that performs negative boosting, the output voltage Vout is a negative voltage equal to or lower than the ground voltage Vss (= 0 V). For example, in the case of a circuit that generates Vout = −0.5 Vdd based on the power supply voltage Vdd, the value of Vout varies according to Vdd, as shown in FIG. That is, as Vdd increases, the absolute value of Vout also increases. From the viewpoint of the ground voltage Vss, Vdd increases in the positive direction and Vout increases in the negative direction.

The maximum voltage applied to the transistor used as the switching element of the charge pump circuit and the transistor constituting the circuit receiving the supply of the output voltage Vout of the charge pump circuit is Vdd−Vout (= 1.5 Vdd), It cannot be expressed by an absolute value from the ground voltage Vss as in the case of plus boosting. For example, as shown in FIG. 9, when Vdd is applied to the gate G of the MOS transistor and Vout is applied to the drain D, a voltage of Vdd−Vout (= 1.5 Vdd) is applied between the gate and drain. .
JP 2001-112239 A JP 2001-231249 A

  Therefore, in providing an over-boost prevention circuit for a charge pump circuit that performs negative boosting, in this circuit system, the reference voltage input to the comparator is not Vref based on the ground voltage Vss, but the output voltage of the charge pump circuit. It is necessary to use Vout as a reference. That is, the reference voltage is Vref + Vout.

  However, when the output current of the charge pump circuit increases, the reference voltage (Vref + Vout) varies greatly due to the influence of ripples generated in the charge pump circuit. For this reason, the over-boosting prevention circuit malfunctions.

  Further, in addition to the reference voltage (Vref + Vout) used in the over-boost prevention circuit, when a reference voltage Vref based on Vss is required, the reference voltage cannot be shared, so that the reference voltage Vref must be created separately. There is also the problem of having to.

  Therefore, the present invention provides a new type over-boost prevention circuit that can use a reference voltage Vref with the ground voltage Vss as a reference.

  According to the present invention, in an over-boosting prevention circuit for preventing an over-boosting of a boosting circuit that generates a negative output voltage with respect to a ground voltage in accordance with a boosting clock, a first difference is obtained by dividing a difference between a power supply voltage and the output voltage. A first resistor and a second resistor for generating a first voltage; a third resistor and a first transistor connected in series between the power supply voltage and the output voltage; and the third resistor and the first transistor. An operational amplifier that outputs a control voltage to the gate of the first transistor so that a second voltage at the connection point is equal to the first voltage, and a second that has the control voltage of the operational amplifier applied to the gate. A transistor having a first end grounded, a current mirror circuit for passing a current equal to a current flowing through the second transistor through the fourth resistor, and the other end of the fourth resistor. The third that occurs A clock control circuit that compares a voltage with a reference voltage based on the ground voltage and controls the supply of the boosting clock to the boosting circuit according to the comparison result. .

  According to another aspect of the present invention, there is provided an over-boosting prevention circuit for preventing over-boosting of a boosting circuit that generates a negative output voltage with respect to a ground voltage in accordance with the boosting clock, and is connected in series between a power supply voltage and the ground voltage. The first transistor and the first resistor, and the first voltage at the connection point of the first transistor and the first resistor are equal to a reference voltage based on the ground voltage. An operational amplifier that outputs a control voltage to the gate of the transistor, a second resistor to which the output voltage is applied at one end, and a current that is equal to the current flowing through the first resistor is passed through the second resistor. A current mirror circuit for generating a second voltage at the other end of the second resistor, and third and fourth resistors for dividing the difference between the power supply voltage and the output voltage to generate a third voltage; , The second voltage and the third voltage Compared to pressure, is for a clock control circuit for controlling the supply of the boost clock to the booster circuit according to the comparison result, characterized in that it comprises a.

  Further, the present invention provides an over-boosting prevention circuit for preventing an over-boosting of a boosting circuit that generates a negative output voltage with respect to a ground voltage in accordance with the boosting clock, and is connected in series between the power supply voltage and the ground voltage. A first transistor for generating a first voltage at the connection point, a first resistor, and a first voltage for generating a second voltage at the connection point, connected in series between the power supply voltage and the output voltage. A control voltage is output to the gate of the first transistor and the gate of the second transistor so that the first voltage is equal to a reference voltage based on the ground voltage. The operational amplifier, the third and fourth resistors for dividing the difference between the power supply voltage and the output voltage to generate a third voltage, the second voltage and the third voltage are compared, and the comparison Depending on the result A clock control circuit for controlling the supply of the boost clock to, characterized in that it comprises a.

  According to the over-boost prevention circuit of the present invention, the reference voltage Vref based on the ground voltage Vss can be used, so that the influence of ripples generated in the boost circuit can be removed and malfunction can be prevented. Therefore, the over-boost prevention circuit of the present invention is suitable for use in a high-current output boost circuit.

  Further, when the reference voltage Vref based on the ground voltage Vss is used in another circuit, the reference voltage can be shared with that circuit.

  Before describing an embodiment of the present invention, an over-boosting prevention circuit according to a reference example will be described. FIG. 10 is a circuit diagram of such an over-boosting prevention circuit. Resistors R1 and R2 are connected in series between the output voltage Vout (<0V) and Vdd of the charge pump circuit 60 that performs negative boosting, and a voltage V0 ′ is generated at the connection point, and the voltages V0 ′ and Vout are generated. A reference voltage (Vref + Vout) as a reference is compared by the comparator 61, and the supply of the boost clock φ to the charge pump circuit 60 is controlled by the output of the comparator 61.

  That is, when V0 ′> Vref + Vout, the output of the comparator 61 is H (high) and the boost clock φ is supplied to the charge pump circuit 60, so that the charge pump circuit 60 performs a boost operation.

  When V0 ′ <Vref + Vout is satisfied by the boost operation of the charge pump circuit 60, the output of the comparator 61 becomes L (low), and the supply of the boost clock φ to the charge pump circuit 60 is stopped. For example, to set so that the output of the comparator 61 is inverted when Vref = 1.2V and Vdd−Vout = 5.5V,

Therefore, from Equation 1 and Equation 2,

  That is, the ratio of R2 and R1 may be set as shown in Equation 3.

  However, when a reference voltage (Vref + Vout) based on the output voltage Vout is used, the value fluctuates greatly under the influence of ripples generated in the charge pump circuit. For this reason, the over-boosting prevention circuit malfunctions.

  Therefore, the present invention provides a novel over-boost prevention circuit that eliminates the influence of ripple generated in the booster circuit by using the reference voltage Vref with the ground voltage Vss as a reference.

  Next, the over-boosting prevention circuit according to the first embodiment of the present invention will be described in detail with reference to FIGS. FIG. 1 is a circuit diagram of the over-boost prevention circuit, FIG. 2 is a circuit diagram of the charge pump circuit 2 having a negative boost, and FIG. 3 is an operation timing diagram of the charge pump circuit 2 having a negative boost.

  This over-boost prevention circuit is a circuit that controls so that (Vdd−Vout), which is the difference between the power supply voltage Vdd and the output voltage Vout (<0 V) of the charge pump circuit 2, does not exceed a predetermined value VMAX. That is, when Vdd−Vout <VMAX, the charge pump circuit 2 performs a boost operation, and when Vdd−Vout> VMAX, the charge pump circuit 2 stops the boost operation.

  As shown in FIG. 1, a first resistor R1 and a second resistor R2 are connected in series between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit 2, and the power supply voltage Vdd is applied to the first resistor R1. The output voltage Vout is applied to the second resistor R2. The first voltage V1 at the connection point between the first resistor R1 and the second resistor R2 is expressed by the following equation. The resistance value of the first resistor R1 is R1, and the resistance value of the second resistor R2 is R2.

For simplicity, assuming that R1 = R2, V1 is as follows.

  A third resistor R3 and an N-channel first MOS transistor M10 are connected in series between the power supply voltage Vdd and the output voltage Vout. The power supply voltage Vdd is applied to the third resistor R3, and the output voltage Vout is applied to the source of the first MOS transistor M10.

  The first voltage V1 is input to the negative input terminal (−) of the operational amplifier 1, and the second voltage at the connection point between the third resistor R3 and the first MOS transistor M10 is input to the positive input terminal (+). V2 is input. The operational amplifier 1 outputs a control voltage to the gate of the first MOS transistor M10 so that the second voltage V2 is equal to the first voltage V1.

  That is, the following equation is established by an imaginary short of the operational amplifier 1.

  The control voltage output from the operational amplifier 1 is applied to the gate of the N-channel type second MOS transistor M11. The output voltage Vout is applied to the source of the second MOS transistor M11. The drain of the third MOS transistor M12 is connected to the drain of the second MOS transistor M11. A power supply voltage Vdd is applied to the source of the third MOS transistor M12. The gate of the third MOS transistor M12 is connected in common with the gate of the fourth MOS transistor M13, and these two transistors constitute a current mirror circuit. The fourth MOS transistor M13 and the fourth resistor R4 are connected in series, and the fourth resistor R4 is grounded. If the current flowing through the first MOS transistor M10 is I1, I1 is expressed by the following equation. The resistance value of the third resistor R3 is R3.

Substituting Equations 5 and 6 into Equation 7, the current I1 is expressed by the following equation.

When the current flowing through the second MOS transistor M11 is I2 and the current flowing through the fourth resistor R4 is I3,
I1 = I2 = I3 holds.

  Therefore, the third voltage V3 at the connection point between the fourth MOS transistor M13 and the fourth resistor R4 is given by the following equation. The resistance value of the fourth resistor R4 is R4.

  The third voltage V3 is input to the positive input terminal (+) of the comparator 3. A reference voltage Vref with the ground voltage Vss as a reference is input to the negative input terminal (−) of the comparator 3. The result of comparing the third voltage V3 and the reference voltage Vref is the output signal Cout of the comparator 3. The output Cout of the comparator 3 is input to the NOR circuit 5. A clock output from the oscillator 4 is also input to the NOR circuit 5.

  Since Cout is at L level when V3 <Vref, the clock output from the oscillator 4 is input to the charge pump circuit 2 through the NOR circuit 5 as the boost clock φ. Actually, various clocks for controlling on / off of the switching MOS transistor of the charge pump circuit 2 are generated by a control circuit (not shown) based on the boost clock φ. Thereby, the charge pump circuit 2 performs a boosting operation.

  On the other hand, when V3> Vref by the boosting operation of the charge pump circuit 2, Cout changes from L level to H level. Then, since the output of the NOR circuit 5 is fixed at the L level, the boost clock φ is not supplied to the charge pump circuit 2, and the boost operation of the charge pump circuit 2 is stopped.

  Therefore, the determination condition for preventing over-boosting is that V3> Vref is satisfied. Substituting V3 of Equation 9 into this determination conditional expression, the following determination conditional expression is obtained.

  For example, when Vref = 1.2V, R3 = 110 kΩ, and R4 = 48 kΩ, Vdd−Vout> 5.5V, and when the difference between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit 2 is 5.5V. The boosting operation can be stopped.

  That is, according to the over-boosting prevention circuit of the present embodiment, when R1 = R2, Vdd−Vout is set to a desired value by setting the values of R3 and R4 so as to satisfy the determination condition formula of Formula 10. At this time, the boosting operation of the charge pump circuit 2 can be stopped. Of course, the value of Vdd−Vout can also be set by following the same calculation process even when R1 ≠ R2. Further, since the reference voltage Vref based on the ground voltage Vss is used, the influence of the ripple appearing in the output voltage Vout of the charge pump circuit 2 can be removed, and malfunction can be prevented.

  The present invention can be applied to the charge pump circuit 2 as long as it is a circuit that performs boosting according to the boosting clock and generates a negative output voltage Vout (<0 V). For example, Vout = −0.5 Vdd or Vout = −Vdd may be used. Next, a circuit for outputting −0.5 Vdd as Vout as an example of the charge pump circuit 2 will be described with reference to FIGS.

  FIG. 2 is a circuit diagram of the charge pump circuit 2. FIG. 2A shows a case where the boost clock φ input to the clock driver CD is L level (Vss), and FIG. The case of H level (Vdd) is shown. The ground voltage Vss (0 V) is applied to the source of the first switching MOS transistor M1, and the drain of the first switching MOS transistor M1 is connected to the source of the second switching MOS transistor M2. The first switching MOS transistor M1 and the second switching MOS transistor M2 function as charge transfer elements.

  Here, both the first switching MOS transistor M1 and the second switching MOS transistor M2 are N-channel type. This is because a voltage for turning on and off the first switching MOS transistor M1 and the second switching MOS transistor M2 is obtained from the same circuit. In order to turn on the first switching MOS transistor M1 and the second switching MOS transistor M2, the power supply voltage Vdd may be applied to their gates. When they are turned off, the output voltage of this circuit is applied to their gates. Vout (= −0.5 Vdd) may be given.

  The output of the clock driver CD is connected to one terminal of the first capacitor C1. The clock driver CD is configured as a CMOS inverter by connecting a P-channel MOS transistor M6 and an N-channel MOS transistor M7 in series between a power supply voltage Vdd and a ground voltage Vss. The boosted clock φ is input to the clock driver CD, and the boosted clock φ is inverted by the clock driver CD. The inverted clock * φ is applied to one terminal of the first capacitor C1 as the output of the clock driver CD.

  In order to reduce the through current of the clock driver CD, a boost clock φ is applied to the gate of the P-channel MOS transistor M6, and a delay clock φ ′ obtained by delaying the boost clock φ is applied to the gate of the N-channel MOS transistor M7. You may comprise so that it may apply. The second capacitor C2 has one terminal connected to the connection point of the first and second switching MOS transistors M1 and M2. The third switching MOS transistor M3 is connected between the other terminal of the second capacitor C2 and the ground voltage Vss (0 V).

  The fourth switching MOS transistor M4 is connected between the other terminal of the first capacitor C1 and the other terminal of the second capacitor C2. The fifth switching MOS transistor M5 is connected to the other terminal of the first capacitor C1 and the output terminal which is the drain of the second switching MOS transistor M2. This circuit obtains the output voltage Vout (= −0.5 Vdd) from the drain of the second switching MOS transistor M2.

  Here, the third and fifth switching MOS transistors M3 and M5 are N-channel type. This is because, similarly to the first switching MOS transistor M1 and the second switching MOS transistor M2, a voltage for turning on and off these transistors is obtained from the same circuit. That is, in order to turn on the third switching MOS transistor M3 and the fifth switching MOS transistor M5, the power supply voltage Vdd may be applied to their gates. An output voltage Vout (= −0.5 Vdd) may be given.

  The fourth switching MOS transistor M4 may be either a P-channel type or an N-channel type, but is preferably an N-channel type in order to reduce the pattern area. When the fourth switching MOS transistor M4 is an N-channel type, in order to turn it on, it is only necessary to supply the power supply voltage Vdd to its gate. When it is turned off, the output voltage Vout of this circuit is applied to its gate. (= −0.5 Vdd) may be given. When the fourth switching MOS transistor M4 is a P-channel type, in order to turn it on, a ground voltage Vss or an output voltage Vout may be applied to its gate. A voltage Vdd may be given.

  Further, it is assumed that the first and second capacitors C1 and C2 have the same capacitance value. The first, second, third, fourth, and fifth switching MOS transistors M1, M2, M3, M4, and M5 are gated by a control circuit (not shown) according to the voltage level of the boost clock φ. These are controlled to be turned on (ON) and off (OFF) as will be described later.

  Next, the boosting operation of the charge pump circuit 2 will be described with reference to FIGS. 2 (a), 2 (b) and FIG. FIG. 3 is an operation timing chart of the charge pump circuit 2 in a steady state. First, the operation of the charge pump circuit 2 when the boosting clock φ is at the L level will be described (see FIGS. 2A and 3). At this time, the P-channel MOS transistor M6 of the clock driver CD is turned on and the N-channel MOS transistor M7 is turned off, so that the inverted clock * φ is at the H level (Vdd). Further, the first and fourth switching MOS transistors M1 and M4 are turned on, and the second, third and fifth switching MOS transistors M2, M3 and M5 are turned off.

  Then, as indicated by a thick line in FIG. 2A, the P-channel MOS transistor M6, the first capacitor C1, the fourth switching MOS transistor M4, the second capacitor C2, and the first capacitor of the clock driver CD. The first capacitor C1 and the second capacitor C2 are connected in series and charged through a path passing through the switching MOS transistor M1 and the ground voltage Vss.

  As a result, one terminal of the first capacitor C1 is charged to Vdd, the voltage V51 of the other terminal is charged to +0.5 Vdd, and the voltage V53 of the other terminal of the second capacitor C2 is also +0.5 Vdd. Charged.

  Next, the circuit operation when the boosting clock φ is at the H level will be described (see FIGS. 2B and 3). At this time, since the N-channel MOS transistor M7 of the clock driver CD is turned on and the P-channel MOS transistor M6 is turned off, the inverted clock * φ is at the L level. (Vss level) The first and fourth switching MOS transistors M1 and M4 are turned off, and the second, third and fifth switching MOS transistors M2, M3 and M5 are turned on.

  Then, as shown by the thick broken line in FIG. 2B, −0.5 Vdd is supplied from the two paths to the output terminal. One path is that the electric charge of the second capacitor C2 is discharged from the ground voltage Vss through the third switching MOS transistor M3, the second capacitor C2, and the second switching MOS transistor M2, and − 0.5Vdd is supplied. This is because the voltage V53 at the other terminal of the second capacitor C2 is charged to +0.5 Vdd when the boost clock φ is at the L level, so that the third switching MOS transistor M3 is turned on. As V53 changes from +0.5 Vdd to Vss, the voltage V52 at one terminal of the second capacitor C2 changes from Vss (0 V) to −0.5 Vdd due to capacitive coupling of the second capacitor C2. Because.

  The other path is that the charge of the first capacitor C1 is discharged from the ground voltage Vss through the N-channel MOS transistor M7 of the clock driver CD, the first capacitor C1, and the fifth switching MOS transistor M5. -0.5 Vdd is supplied to the terminal.

  This is because the voltage V51 at the other terminal of the first capacitor C1 is charged to +0.5 Vdd when the boost clock φ is at L level, but when the boost clock φ changes to H level, the N-channel MOS transistor M7. Is turned on, and the voltage at one terminal of the first capacitor C1 changes from Vdd to Vss. As a result, the voltage V51 at the other terminal of the first capacitor C1 is caused by capacitive coupling of the first capacitor C1. This is because the voltage changes from +0.5 Vdd to -0.5 Vdd. At this time, paying attention to the second switching MOS transistor M2 and the fifth switching MOS transistor M5, Vdd is applied to the gates of these transistors and Vout = −0.5 Vdd is applied to the drains thereof. Thus, a voltage of Vdd−Vout = 1.5Vdd is applied between the gate and drain. The present invention intends to limit this Vdd-Vout.

  By alternately repeating the operation when the boosting clock φ is at the L level and the operation when the boosting clock φ is at the H level, −0.5 Vdd obtained by multiplying the power supply voltage Vdd by −0.5 is obtained as the output voltage Vout. As described above, when V3> Vref, the output signal Cout of the comparator 3 changes from the L level to the H level, and the boost clock φ that is the output of the NOR circuit 5 is fixed to the L level. Thereby, the operation of the charge pump circuit 2 is stopped.

  Next, an over-boosting prevention circuit according to the second embodiment of the present invention will be described in detail with reference to FIG.

  A reference voltage Vref based on the ground voltage Vss is applied to the positive input terminal (+) of the operational amplifier 1. The first MOS transistor M20 and the first resistor R11 are connected in series, and the first resistor R11 is grounded. The negative input terminal (−) of the operational amplifier 1 is supplied with the first voltage V11 at the connection point between the N-channel first MOS transistor M20 and the first resistor R11. The operational amplifier 1 outputs a control voltage to the gate of the N-channel first MOS transistor M20 so that the first voltage V11 is equal to the reference voltage Vref.

  The drain of the P-channel type second MOS transistor M21 is connected to the drain of the first MOS transistor M20. A power supply voltage Vdd is applied to the source of the second MOS transistor M21. The gate of the second MOS transistor M21 is connected in common with the gate of the P-channel type third MOS transistor M22, and these transistors constitute a current mirror circuit. The third MOS transistor M22 and the second resistor R12 are connected in series, and the output voltage Vout of the charge pump circuit 2 is applied to the second resistor R12.

  Assuming that the current flowing through the first MOS transistor M20 and the first resistor R11 is I1, I1 is expressed by the following equation. The resistance value of the first resistor R11 is R11.

  When the current flowing through the second resistor R12 is I2, I1 = I2 is set by the current mirror circuit. Therefore, the second voltage V12 at the connection point between the third MOS transistor M22 and the second resistor R12 is expressed by the following equation. The resistance value of the second resistor R12 is R12.

  On the other hand, a third resistor R13 and a fourth resistor R14 are connected in series between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit 2, and the power supply voltage Vdd is applied to the third resistor R13. An output voltage Vout is applied to the resistor R14. The third voltage V13 at the connection point between the third resistor R13 and the fourth resistor R14 is expressed by the following equation. The resistance value of the third resistor R13 is R13, and the resistance value of the fourth resistor R14 is R14.

  The second voltage V12 is input to the negative input terminal (−) of the comparator 3, and the third voltage V13 is input to the positive input terminal (+) of the comparator 3. Therefore, when V13 <V12, the output signal Cout of the comparator 3 is at the L level, so that the clock φ output from the oscillator 4 is input to the charge pump circuit 2 through the NOR circuit 5 as the boost clock φ. Thereby, the charge pump circuit 2 performs a boosting operation. On the other hand, when V13> V12 by the boosting operation of the charge pump circuit 2, Cout changes from L level to H level. Then, since the output of the NOR circuit 5 is fixed at the L level, the boost clock φ is not supplied to the charge pump circuit 2, and the boost operation of the charge pump circuit 2 is stopped.

  Therefore, the determination condition for preventing over-boosting is that V13> V12 holds.

  Substituting equations (12) and (13) into this determination condition equation gives the following equation.

  When the difference between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit 2 reaches a predetermined value (the value on the right side of Equation 14), the boosting operation can be stopped. As in the first embodiment, the charge pump circuit 2 is any circuit that performs boosting according to the boosting clock and generates a negative output voltage Vout (<0 V). Can be applied. For example, Vout = −0.5 Vdd or Vout = −Vdd may be used.

  Next, an over-boosting prevention circuit according to a third embodiment of the present invention will be described in detail with reference to FIG. In the second embodiment, the output of the operational amplifier 1 is applied to the gate of the N-channel type first MOS transistor M20, and the current I1 flowing through the first MOS transistor M20 is changed to the P-channel type second and second types. In this configuration, the current is transmitted to the next stage by a current mirror circuit using three MOS transistors M21 and M22. On the other hand, the circuit of the present embodiment performs current mirror driving by applying the output of the operational amplifier 1 to the gates of a pair of P-channel MOS transistors.

  That is, as shown in FIG. 5, a P-channel first MOS transistor M23 and a first resistor R11 are connected in series between the power supply voltage Vdd and the ground voltage Vss. A power supply voltage Vdd is applied to the source of the first MOS transistor M23, and the first resistor R11 is grounded.

  A reference voltage Vref based on the ground voltage Vss is applied to the negative input terminal (−) of the operational amplifier 1. The first voltage V11 at the connection point between the first MOS transistor M23 and the first resistor R11 is input to the positive input terminal (+) of the operational amplifier 1. The operational amplifier 1 outputs a control voltage to the gate of the first MOS transistor M23 so that the first voltage V11 is equal to the reference voltage Vref.

  Further, between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit 2, a P-channel type second MOS transistor M24 and a second resistor R12 are connected in series. The power supply voltage Vdd is applied to the source of the second MOS transistor M24, and the output voltage Vout is applied to the second resistor R12. A second voltage V12 is generated at the connection point between the second MOS transistor M24 and the second resistor R12. The output of the operational amplifier 1 is applied to the gate of the second MOS transistor M24.

  Therefore, since the first MOS transistor M23 and the second MOS transistor 24 constitute a current mirror circuit, the current I1 flowing through the first MOS transistor M23 and the first resistor R11, the second MOS transistor M24, and the second MOS transistor M24 The current I2 flowing through the second resistor R12 is set to be equal. That is, I1 = I2.

  Other circuit configurations are the same as those of the second embodiment. Therefore, also in the circuit of the present embodiment, the mathematical formulas of Equation 11, Equation 12, Equation 13, and Equation 14 hold as in the second embodiment. Therefore, the boosting operation can be stopped when the difference between the power supply voltage Vdd and the output voltage Vout of the charge pump circuit 2 reaches a predetermined value (the value on the right side of Equation 14). Similarly to the first embodiment, the charge pump circuit 2 may be any circuit as long as it boosts in accordance with the boost clock and generates a negative output voltage Vout (<0 V). The present invention can be applied. For example, Vout = −0.5 Vdd or Vout = −Vdd may be used.

1 is a circuit diagram of an over-boosting prevention circuit according to a first embodiment of the present invention. It is a circuit diagram of a charge pump circuit. FIG. 6 is an operation timing chart of the charge pump circuit. It is a circuit diagram of the over-boosting prevention circuit which concerns on the 2nd Embodiment of this invention. It is a circuit diagram of the over-boost prevention circuit which concerns on the 3rd Embodiment of this invention. It is a figure which shows the bias state of a MOS transistor. It is a circuit diagram of the over-boost prevention circuit which concerns on a prior art example. It is a figure which shows the output voltage of the charge pump circuit which performs minus pressure | voltage rise. It is a figure which shows the bias state of a MOS transistor. It is a circuit diagram of the over-boosting prevention circuit which concerns on a reference example.

Explanation of symbols

1 operational amplifier, 2 charge pump circuit, 3 comparator, 4 oscillator, 5 NOR circuit, R1 first resistor, R2 second resistor, R3 third resistor,
R4 4th resistor, M10 1st MOS transistor, M11 2nd MOS transistor, M12 3rd MOS transistor, M13 4th MOS transistor

Claims (6)

In the over-boosting prevention circuit that prevents over-boosting of the boosting circuit that generates a negative output voltage with respect to the ground voltage according to the boosting clock,
First and second resistors for dividing a difference between a power supply voltage and the output voltage to generate a first voltage;
A third resistor and a first transistor connected in series between the power supply voltage and the output voltage;
An operational amplifier that outputs a control voltage to the gate of the first transistor so that a second voltage at a connection point of the third resistor and the first transistor is equal to the first voltage;
A second transistor in which the control voltage of the operational amplifier is applied to a gate;
A fourth resistor with one end grounded;
A current mirror circuit for passing a current equal to a current flowing through the second transistor through the fourth resistor;
The third voltage generated at the other end of the fourth resistor is compared with a reference voltage based on the ground voltage, and the supply of the boosting clock to the boosting circuit is controlled according to the comparison result. An over-boosting prevention circuit comprising: a clock control circuit. The clock control circuit includes a comparator for comparing the third voltage with the reference voltage;
A clock generation circuit for generating the boost clock;
2. The over-boosting prevention circuit according to claim 1, further comprising a gate circuit that cuts off a boosting clock generated from the clock generation circuit in accordance with an output of the comparator. 2. The over-boost prevention circuit according to claim 1, wherein a resistance value of the first resistor is equal to a resistance value of the second resistor. In the over-boosting prevention circuit that prevents over-boosting of the boosting circuit that generates a negative output voltage with respect to the ground voltage according to the boosting clock,
A first transistor and a first resistor connected in series between a power supply voltage and the ground voltage;
An operational amplifier that outputs a control voltage to the gate of the first transistor so that a first voltage at a connection point between the first transistor and the first resistor is equal to a reference voltage based on the ground voltage; ,
A second resistor having the output voltage applied to one end thereof;
A current mirror circuit for generating a second voltage at the other end of the second resistor by causing a current equal to the current flowing through the first resistor to flow through the second resistor;
Third and fourth resistors for dividing the difference between the power supply voltage and the output voltage to generate a third voltage;
An over-boosting prevention circuit comprising: a clock control circuit that compares the second voltage with the third voltage and controls the supply of the boosting clock to the boosting circuit according to the comparison result. . In the over-boosting prevention circuit that prevents over-boosting of the boosting circuit that generates a negative output voltage with respect to the ground voltage according to the boosting clock,
A first transistor and a first resistor connected in series between a power supply voltage and the ground voltage, and generating a first voltage at the connection point;
A second transistor and a second resistor connected in series between the power supply voltage and the output voltage, and generating a second voltage at the connection point;
An operational amplifier that outputs a control voltage to the gate of the first transistor and the gate of the second transistor so that the first voltage is equal to a reference voltage based on the ground voltage;
Third and fourth resistors for dividing the difference between the power supply voltage and the output voltage to generate a third voltage;
An over-boosting prevention circuit comprising: a clock control circuit that compares the second voltage with the third voltage and controls the supply of the boosting clock to the boosting circuit according to the comparison result. . The clock control circuit includes a comparator that compares the second voltage with the third voltage;
A clock generation circuit for generating a boost clock; and
6. The over-boosting prevention circuit according to claim 4, further comprising a gate circuit that cuts off the boosting clock generated from the clock generation circuit in accordance with an output of the comparator.