JP2006296119A - Drive circuit of semiconductor switching element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress a drive fluctuation in an arm short circuit preventing circuit, and prevent a malfunction due to an external noise in a drive circuit of semiconductor switching elements. <P>SOLUTION: The drive circuit drives turnon/turnoff by connecting a switch between gates and emitters of the first and second semiconductor switching elements connected in series between output terminals of a DC power supply and inputting a control signal to the element. The drive circuit has a detector for detecting the control signal and a gate input signal in a off-state and short-circuiting between the gates and the emitters of the elements using the switch. The detector comprises a logic circuit, and does not detect a transition mode in which only the gate input signal transits to an on-state from a state that the control signal and the gate input signal are in the off-state. The gates and the emitters are continuously short-circuited in the transition mode. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a drive circuit for turning on or off a semiconductor switching element.

An inverter circuit is known as a power conversion circuit that converts DC power into AC power and supplies it to a load. In the inverter circuit, connect two semiconductor switching elements in series, connect two sets of single-phase inverters in parallel and three sets of three-phase inverters, and connect these parallel circuits to a DC power supply. is doing.
A circuit in which the two semiconductor switching elements are connected in series is referred to as an arm in the following description. For example, in a single-phase inverter, two sets of U-phase and V-phase arms are connected to a DC power supply, and in a three-phase inverter, three sets of U-phase, V-phase, and W-phase arms are connected to a DC power supply. It is connected.
Further, of the two semiconductor switching elements of each phase arm, the switching element connected to the (+) side of the DC power supply is called the “P side” element, and the switching connected to the (−) side of the DC power supply. The elements are called “N-side” elements to distinguish them.

In the above inverter circuit, if the two semiconductor switching elements of each phase arm are simultaneously turned on, a power supply short circuit is caused. Therefore, it is necessary to control each phase arm not to be turned on simultaneously.
Therefore, when the P-side and N-side switching elements of each phase are switched on and turned on alternately, a dead time is set and a period in which both switching elements are both off is provided so that they do not turn on at the same time. It is controlled.

FIG. 1 shows a general single-phase inverter circuit.
The semiconductor switching element of FIG. 1 uses MOS input type power transistors 3 to 6 (for example, IGBT, FET), and converts the DC power of the DC power source 1 into AC power and supplies it to the load 2.
In this single-phase inverter circuit, the power transistors 3 and 4 constitute a U-phase arm, the power transistors 5 and 6 constitute a V-phase arm, the P-side element of the power transistors 3 and 5 is the (+) terminal of the DC power source 1, the power The N-side elements of the transistors 4 and 6 are connected to the (−) terminal of the DC power supply 1.
Gate drive circuits 7 to 10 are respectively connected between the gates and emitters of the power transistors 3 to 6, and these gate drive circuits control on / off of the power transistors 3 to 6.

FIG. 2 shows a conventional gate drive circuit for a power transistor. As an example, the gate drive circuit 7 of FIG. 1 is shown, but the gate drive circuits 8 to 10 have the same circuit configuration.
In the gate drive circuit 7, an NPN transistor 11 for turning on the power transistor 3 and a PNP transistor 12 for turning off the power transistor 3 are connected in series, and this series circuit is connected to both ends of a power supply 13 for driving the power transistor 3.
The collector of the NPN transistor 11 is connected to the (+) pole side of the driving power supply 13, and the emitter of the PNP transistor 12 is connected to the (−) pole side of the driving power supply 13.
Further, a control signal for turning on or off the power transistor 3 is supplied to the base terminals of the transistors 11 and 12 via the control terminal 14.

Since the upper and lower arms in each phase of the inverter are not allowed to conduct at the same time as described above, the other power transistor is set with the voltage VGE between the gate and the emitter being zero so that one of the power transistors is not turned on. Must be turned on / off.
However, in the single-phase inverter shown in FIG. 1, when the N-side power transistor 4 is turned on / off with the P-side power transistor 3 of the U-phase arm turned off, the P-side power is turned on when the N-side power transistor 4 is turned on. There is a problem in that the gate voltage of the transistor 3 rises transiently, which causes the P-side power transistor 3 to turn on, causing the P-side power transistor 3 and the N-side power transistor 4 to conduct simultaneously and causing a U-phase arm short circuit.

The cause of the arm short circuit due to such a cause can be explained as follows.
As shown in FIG. 1, the series connection circuit of the P-side power transistor 3 and the N-side power transistor 4 is connected to the DC power source 1, and the voltage between the collector and the emitter decreases rapidly when the N-side power transistor 4 is turned on. As a result, the voltage between the collector and the emitter of the P-side power transistor 3 rapidly increases.
At this time, if the resistance between the gate and the emitter of the P-side power transistor 3 is not sufficiently small, a sudden rise in the potential of the collector of the P-side power transistor 3 is caused through the parasitic capacitance between the collector and the gate of the P-side power transistor 3. This is transmitted to the gate, and the potential of the gate is suddenly increased, and the P-side power transistor 3 is instantaneously turned on, causing an arm short circuit.

In order to prevent an arm short circuit due to such a phenomenon, the gate drive circuit 7 includes a switch for short-circuiting the gate and the emitter while the power transistor 3 is turned off as shown in FIG. An arm short circuit prevention circuit 17 including an NMOS input type FET 16 is provided.
As an example of such an arm short circuit prevention circuit 17, a signal delay circuit 18 for delaying the fall of the control signal supplied to the control terminal 14 for a predetermined time is provided, and an FET 16 that short-circuits between the gate and the emitter of the power transistor 3. Has been proposed (see, for example, Patent Document 1).
JP 2000-059189 A

The arm short circuit prevention circuit will be described.
The signal delay circuit 18 shown in FIG. 2 includes a resistor 19, a capacitor 20, and a NOR type logic element 21, and a control signal is supplied to one input terminal IN1 of the NOR type logic element 21, and the other input terminal IN2 is supplied with the control signal. Is supplied with a control signal delayed by a CR time constant circuit comprising a resistor 19 and a capacitor 20.
FIG. 3 is a time chart showing each operation of the gate drive circuit 7 shown in FIG. When a high-level control signal is supplied to the control terminal 14 at time t1, the NPN transistor 11 is turned on, and a voltage is applied from the driving power supply 13 to the gate of the power transistor 3 via the NPN transistor 11 and the resistor 15. As the gate voltage VGE increases, the power transistor 3 is turned on.
At this time, since a high level control signal is also supplied to the input terminal IN1 of the NOR type logic element 21, the NOR type logic element 21 outputs a low level. As a result, the FET 16 is turned off and the power transistor 3 is turned off. Release the gate from the emitter.

Next, when the control signal supplied to the control terminal 14 becomes low level at time t2, the NPN transistor 11 is turned off, and the PNP transistor 12 is turned on instead. As a result, the gate of the power transistor 3 is connected to the emitter of the power transistor 3 via the resistor 15 and the PNP transistor 12, and the gate voltage VGE falls to turn off the power transistor 3.
At this time, the control signal supplied to the input terminal IN1 of the NOR type logic element 21 is also at a low level, but the residual voltage of the signal delay circuit is still applied to the other input terminal IN2, and the NOR type The logic element 21 continues to output a low level signal.
As a result, the FET 16 still maintains the off state.

At time t3, when the terminal voltage of the capacitor 20 of the signal delay circuit 18 becomes lower than the input threshold value Vth of the NOR logic element 21, the NOR logic element 21 outputs a high level control signal. Then, the FET 16 is turned on, and the gate and emitter of the power transistor 3 are short-circuited.
Note that the time from when the control signal changes to low level at time t2 until the terminal voltage of the capacitor 20 drops below the threshold value Vth is a time constant determined by the resistor 19 and the capacitor 20 of the signal delay circuit 18. The time from the end of the turn-off operation of the P-side power transistor 3 to the start of the turn-on operation of the N-side power transistor 4 is adjusted.

Next, when the turn-on operation of the N-side power transistor 4 of the U-phase arm is started, the voltage between the collector and the emitter of the N-side power transistor 4 rapidly decreases, thereby causing the P-side power transistor 3 to turn off at time t4. The voltage between the collector and emitter rises rapidly.
This rapid rise in voltage VCE is transmitted to the gate via the stray capacitance between the collector and gate of the P-side power transistor 3, and attempts to rapidly raise the voltage between the gate and emitter.
However, before the turn-on operation of the N-phase power transistor 4 is started, the FET 16 is turned on to short-circuit the gate and the emitter of the P-side power transistor 3, so that the gate voltage VGE of the P-side power transistor 3 increases. In other words, the P-side power transistor 3 is not turned on. Thereby, an arm short circuit due to simultaneous turn-on of the power transistors 3 and 4 on the P side and the N side of the U-phase arm is prevented.

In the semiconductor switching element drive circuit 7 described above, when the turn-on operation of the N-phase power transistor 4 starts, the voltage VCE between the collector and the emitter of the P-side power transistor 3 suddenly rises (time t4). May be transmitted as noise to the arm short circuit prevention circuit via the above.
At this time, the voltage across the capacitor 20 rises, causing the NOR logic element 21 to malfunction and turn off the FET 16. For this reason, the short circuit between the gate and the emitter of the N-side power transistor 4 is interrupted, the gate voltage VGE rises and the P-side power transistor 3 is turned on, and the P-side and N-side powers of the U-phase arm are turned on. Transistors 3 and 4 are simultaneously turned on, causing a short circuit of the U-phase arm. A circuit for preventing an arm short circuit due to such a phenomenon has been proposed (see, for example, Patent Document 2).
JP 2000-059189 A

  FIG. 4 shows a drive circuit for a semiconductor switching element using the arm short circuit prevention circuit. In the arm short circuit prevention circuit 17 of FIG. 4, the NMOS input FET 22 is connected in parallel with the capacitor 20, and the output terminal of the NOR logic element 21 and the gate of the FET 22 are connected, whereby the N-side power transistor 4 is turned on. When entering, both ends of the capacitor 20 are short-circuited by the FET 22. As a result, the arm short circuit is prevented without increasing the voltage across the capacitor 20 due to noise caused by the sudden rise in the voltage VCE between the collector and emitter of the P-side power transistor 3.

However, the conventional semiconductor switching element driving circuit described above has the following problems.
In the signal delay circuit 18 in the arm short circuit prevention circuit 17 shown in FIG. 4, the resistor 19 and the capacitor 20 that determine the delay time have tolerance variations.
Furthermore, since the capacitance of the capacitor 20 changes depending on the temperature, the signal delay time variation considering the temperature range may reach ± 30 to 40%, which is not preferable in practical use.
In addition, when the P-side and N-side power transistors of each phase are switched on and turned on alternately, a dead time is set and a period in which both the upper and lower arms are turned off is provided. There is a problem that a constraint condition in the control process occurs, for example, it is necessary to set a long dead time for consideration.

  Further, it is desirable that the FET 16 for short-circuiting between the gate and emitter of the power transistor 3 is a short-circuit prevention circuit based on fail-safe so as not to malfunction due to any external noise.

  Due to the problems described above, in the prevention of arm short circuit of the inverter circuit by two semiconductor switching elements connected in series, the drive timing variation of the short circuit prevention circuit is suppressed and the driving of the semiconductor switching element having a fail safe function is performed. A circuit was required.

The present invention solves the above-described problem, and the first and second semiconductor switching elements connected in series between the output terminals of the DC power source and the control signal are input to drive the elements on / off. In the drive circuit of the semiconductor switching element having the drive circuit to
A switch is connected between the gate and emitter of the first and second semiconductor switching elements;
A detector that detects that both the control signal and the gate input signal of the semiconductor switching element are in an OFF state, and shorts the gate and emitter of the first and second semiconductor switching elements by turning on the switch. It is a drive circuit of the semiconductor switching element characterized by having.

  Further, the detector is configured by a logic circuit, and the transition mode in which only the gate input signal shifts from the off state to the on state is not detected from the control signal and the gate input signal. A short circuit between a gate and an emitter of a switching element is continuously performed.

  Further, the detector is connected to a detector for detecting the on / off signal of the control signal and / or the gate input signal, and the detector has a hysteresis function to determine the two input signals. In addition, the semiconductor switching element drive circuit is characterized in that the off signal determination criterion of two input signals is set to zero or more.

A method of short-circuiting between the gate and emitter of a semiconductor switching element by detecting that both the control signal and the gate input signal are off signals in preventing arm short circuit of the inverter circuit by two semiconductor switching elements connected in series Therefore, it is not necessary to set a signal delay time when the gate and the emitter are short-circuited, and the drive timing does not vary.
Also, even if the gate input signal of the semiconductor switching element is turned on due to noise when other switching elements of the common-mode arm start turning on, the detector in the arm short circuit prevention circuit does not detect this and continues. Since the gate and the emitter of the semiconductor switching element are continuously short-circuited, an arm short circuit can be prevented.
Furthermore, it has a determiner that detects the ON / OFF signal of the control signal and / or the gate input signal, the determiner has a hysteresis function, determines the two input signals, and sets the OFF signal determination criterion to zero. By setting to the above values, it becomes possible to make it difficult for malfunction to occur with respect to noise superimposed on the signal line during semiconductor switching.

Embodiments of the present invention will be described below with reference to the drawings.
[Example 1]
FIG. 5 shows a power transistor gate drive circuit according to an embodiment of the present invention. This is a description example of the gate drive circuit 7 of FIG. 1, but the gate drive circuits 8 to 10 have the same circuit configuration.
In the gate drive circuit 7, an NPN transistor 11 for turning on the power transistor 3 and a PNP transistor 12 for turning off the power transistor 3 are connected in series, and this series circuit is connected between outputs of the power supply 13 for driving the power transistor 3. .
The collector of the NPN transistor 11 is connected to the (+) pole output terminal of the driving power supply 13, and the collector of the PNP transistor 12 is connected to the (−) pole output terminal of the driving power supply 13.
Further, a control signal for turning on or off the power transistor 3 is supplied to the base terminals of the transistors 11 and 12 via the control terminal 14.

As shown in FIG. 5, the gate drive circuit 7 is provided with an arm short circuit prevention circuit 17 having an NMOS input type FET 16 as a switch for short-circuiting the gate and the emitter while the power transistor 3 is turned off. It has been.
The arm short circuit prevention circuit 17 will be described. The arm short circuit prevention circuit 17 shown in FIG. 5 includes a NOR logic element 21, a control signal is supplied to one input terminal IN 2 of the NOR logic element 21, and the gate input of the power transistor 3 is connected to the other input terminal IN 1. A signal is supplied.
The output of the NOR type logic element 21 is connected to the gate of the FET 16. The NOR type logic element 21 detects a period in which both the control signal and the gate input signal are at a low level (off state). By short-circuiting between the gate and emitter of the N-side power transistor, a low impedance is prevented, so that the VGE voltage between the gate and the emitter of the P-side power transistor is prevented from rising and turning on when the N-side power transistor is turned on.

FIG. 6 is a time chart showing each operation of the gate drive circuit 7 shown in FIG. 5. When a high-level (on state) control signal is supplied to the control terminal 14 at time t1, the NPN transistor 11 is turned on. A voltage is applied from the driving power supply 13 to the gate of the power transistor 3 via the NPN transistor 11 and the resistor 15, and the power transistor 3 is turned on by the rise of the gate voltage VGE.
At this time, since a high level control signal is also supplied to the input terminal IN2 of the NOR type logic element 21, the NOR type logic element 21 outputs a low level signal. As a result, the FET 16 is turned off and the power transistor is turned off. Release the gate of 3 from the emitter.

Next, when the control signal supplied to the control terminal 14 becomes low level at time t2, the NPN transistor 11 is turned off and the PNP transistor 12 is turned on. As a result, the gate of the power transistor 3 is conducted to the emitter of the power transistor 3 via the resistor 15 and the PNP transistor 12, and the gate voltage VGE is lowered to turn off the power transistor 3.
At this time, the control signal supplied to the input terminal IN2 of the NOR type logic element 21 is also at a low level, but the remaining voltage of the gate input signal of the power transistor 3 is still applied to the other input terminal IN1. Thus, the NOR type logic element 21 continues to output a low level signal.
As a result, the FET 16 still maintains the off state.

  At time t3, when the gate signal of the power transistor 3 becomes lower than the input threshold value Vth of the NOR type logic element 21, the NOR type logic element 21 outputs a high level signal, turns on the FET 16, and turns on the power transistor 3. Short circuit between gate and emitter.

Next, when the turn-on operation of the U-phase N-side power transistor 4 is started, the voltage between the collector and the emitter of the N-side power transistor 4 rapidly decreases, thereby causing the P-side switching element 3 to turn off at time t4. The voltage between the collector and emitter rises rapidly.
This rapid rise in voltage VCE is transmitted to the gate via the stray capacitance between the collector and gate of the P-side power transistor 3 and tries to rapidly increase the voltage between the gate and emitter. Before starting the turn-on operation, the FET 16 is turned on to short-circuit the gate and the emitter of the P-side power transistor 3, so that the gate voltage VGE of the P-side power transistor 3 does not rise and the P-side power transistor 3 does not turn on.
Thereby, an arm short circuit due to simultaneous turn-on of the power transistors 3 and 4 on the P side and the N side of the U-phase arm is prevented.

FIG. 7 is a state transition table in the arm short-circuit prevention circuit 17. It is the output signal of the NOR logic element 21 that determines the gate signal of the FET 16.
Since the gate input signal of the power transistor 3 is supplied to one input terminal IN1 of the NOR type logic element 21 and the control signal is supplied to the other input terminal IN2, the output of the NOR type logic element 21 is output. The high level signal (that is, the gate and emitter of the power transistor 3 are short-circuited) is only between the low level signal and the control signal and the gate input signal of the power transistor 3.
Furthermore, in the states 1 to 4, the control signal changes from L → L → H → H, whereas the gate input signal of the power transistor 3 changes from L → H → H → L one state at a time. This is because the switching of the gate driving circuit is slightly delayed with respect to the control signal.

[Example 2]
FIG. 8 shows a gate drive circuit of a power transistor according to another embodiment of the present invention.
The gate drive circuit 7 of FIG. 8 has a circuit configuration with further improved noise resistance compared to FIG. In the arm short circuit prevention circuit 17 of FIG. 8, an AND type logic element 22 and an INV type logic element 23 are added.
The gate input signal of the power transistor 3 is connected to the input terminal IN3 of the AND type logic element 22, and the output signal of the NOR type logic element 21 is connected to the other input terminal IN4 via the INV type logic element 23. is doing.
Further, the output signal of the AND logic element 22 is connected to the input terminal IN 1 of the NOR logic element 21.

FIG. 9 is a time chart showing each operation of the gate drive circuit 7 in FIG.
At time t 1, when a high level (ON state) control signal is supplied to the control terminal 14, the NPN transistor 11 is turned on, and the drive power supply 13 passes through the NPN transistor 11 and the resistor 15 to the gate of the power transistor 3. A voltage is applied, and the power transistor 3 is turned on by the rise of the gate voltage VGE.
At this time, since a high level control signal is also supplied to the input terminal IN2 of the NOR type logic element 21, the NOR type logic element 21 outputs a low level signal (off state), and as a result, the FET 16 is turned off. Thus, the gate of the power transistor 3 is released from the emitter.

Next, when the control signal supplied to the control terminal 14 becomes low level at time t2, the NPN transistor 11 is turned off, and the PNP transistor 12 is turned on instead.
As a result, the gate of the power transistor 3 is conducted to the emitter of the power transistor 3 via the resistor 15 and the PNP transistor 12, and the gate voltage VGE is lowered to turn off the power transistor 3.
At this time, the control signal supplied to the input terminal IN2 of the NOR logic element 21 is at a low level, but the output signal of the AND logic element 22 is applied as a high level signal to the other input terminal IN1. Therefore, the NOR type logic element 21 continues to output a low level signal.
As a result, the FET 16 still maintains the off state.

  When the gate input signal of the power transistor 3 becomes lower than the input threshold value Vth of the AND type logic element 21 at time t3, the AND type logic element 22 outputs a low level signal and the NOR type logic element 21 is input. Since the signal is input to the terminal IN1, the output of the NOR logic element 21 is inverted to a high level signal to turn on the FET 16, and the gate and emitter of the power transistor 3 are short-circuited.

Next, when the turn-on operation of the U-phase N-side power transistor 4 is started, the voltage between the collector and the emitter of the N-side power transistor 4 rapidly decreases, thereby causing the P-side switching element 3 to turn off at time t4. The voltage between the collector and emitter rises rapidly.
This sudden rise in voltage VCE may be transmitted as noise to the arm short circuit prevention circuit via a printed circuit board on which a drive circuit is mounted. In particular, consideration must be given to the case where noise is transmitted from the gate input terminal directly connected to the power transistor.

Therefore, as shown in FIG. 8, by adding an AND-type logic element 22 and an INV-type logic element 23, the gate of the power transistor 3 is between the control signal and the gate input signal of the power transistor 3 while both are low level signals. Even if the input signal first changes to a high level signal, this is not detected.
That is, while the control signal and the gate input signal of the power transistor 3 are both at the low level signal, the output of the NOR type logic element 21 is at the high level. Input to IN4 of the type logic element 22.
Therefore, while the IN4 input signal of the AND-type logic element 22 is at a low level, even if noise is input to the IN3 input signal of the AND-type logic element 22 and exceeds the threshold value Vth, it is accepted by the AND logic operation. Therefore, the output of the AND type logic element 22 does not change from the low level, and the output of the NOR type logic element 21 is not inverted and does not malfunction.
When the IN2 input of the NOR type logic element 21 changes to a high level according to a normal rule, the output of the NOR type logic element 21 is inverted to a low level, the FET 16 is turned off, and the power transistor 3 is connected between the gate and the emitter. Release from short circuit.
That is, in the state transition table of FIG. 7, when the control signal and the gate input signal of the power transistor 3 are both low, the characteristic that the gate input signal of the power transistor 3 does not change to the high level first is used. Thus, the noise resistance is improved.

[Example 3]
FIG. 10 shows a gate drive circuit for a power transistor according to another embodiment of the present invention. 10 further includes a control signal and / or a gate input signal of the semiconductor switching element through a determination unit 24 that has a hysteresis function and detects an on / off signal in addition to the circuit configuration of FIG. By inputting the signal to the short-circuit prevention circuit 17, the circuit configuration is improved in noise resistance. 11A and 11B show an internal configuration diagram of the determiner 24. FIG.
12 (a) and 12 (b) are time charts showing the input / output operations of FIGS. 11 (a) and 11 (b), respectively.
In the circuit configuration shown in FIG. 11A, an inverting amplifier 25 having a hysteresis function and an INV type logic element 26 are connected in series, and a resistor 27 is connected between the (+) input terminal and the output terminal of the inverting amplifier 25. A resistor 28 is connected between the (+) input terminal and GND.
When the maximum output voltage of the inverting amplifier 25 is Vom and the resistors 27 and 28 have the same resistance value, the input signal at the (−) input terminal of the inverting amplifier 25 is as shown in the time chart of FIG. When the voltage rises and exceeds Vom / 2 (time t1), the output is inverted from the low level signal (off state) to the high level signal (on state), and conversely, the input signal at the (−) input terminal decreases. When the signal reaches zero (time t2), the output is inverted from the high level signal to the low level signal.
That is, even if noise is superimposed on the (−) input terminal of the inverting amplifier 25, no malfunction occurs within a range not exceeding Vom / 2.
11B, a resistor 27 is connected between the (+) input terminal and the output terminal of the inverting amplifier 25, and a resistor 28 is connected between the (+) input terminal and the Vref voltage.
Similarly to the above, when checking the time chart of FIG. 12B, when the input signal at the (−) input terminal of the inverting amplifier 25 rises and exceeds Vom / 2 (time t1), the low level signal is changed to the high level signal. Threshold value for determining that the control signal or the gate input signal of the semiconductor switching element is low level when the output is inverted to the level signal and the input signal of the (−) input terminal is lower than Vref (time t2). Can be set.

For example, in the case of FIG. 11A in which the resistor 28 is connected between the (+) input terminal and the GND, the output signal of the inverting amplifier 25 is high unless the (−) input terminal of the inverting amplifier 25 is completely reduced to zero. Does not change to level.
Therefore, by taking the circuit configuration of FIG. 11B and setting Vref to a value slightly higher than zero (for example, 0.5 to 1 V), the (−) input terminal of the inverting amplifier 25 is changed to a low level. This can be reliably detected.

  Further, by setting the resistance value (R2) of the resistor 28 to be higher than the resistance value of the resistor 27 (R1), the threshold value (= Vom) at which the output of the inverting amplifier 25 is inverted from the low level to the high level signal. XR2 / (R1 + R2)) can be set higher than Vom / 2, and a voltage range that can prevent malfunction when noise is superimposed on the (−) input terminal of the inverting amplifier 25 can be set high. is there.

[Example 4]
FIG. 13 shows a gate drive circuit for a power transistor according to another embodiment of the present invention.
In the gate drive circuit of FIG. 13, the drive power supply 13 for driving the power transistor is a 15V power supply, and the drive power supply for logic elements such as the control signal and the arm short circuit prevention circuit 17 is a 5V power supply.
The control signal is converted to a 15 V signal level by the FET 31 via the determination unit 24 on the drive power supply 13 side, and the NPN transistor 11 and the PNP transistor 12 are driven.
The gate input signal of the power transistor 3 is divided by resistors 33 and 34 using a level shift circuit 32 and converted to a 5V signal level, and then input to the determiner 24. By converting the signal level in this way, the voltage signal levels of the power transistor drive circuit and the signal processing circuit can be controlled separately.

  In the above embodiment, the IGBT is exemplified as the MOS input type power transistor, but it can be replaced with an FET. In this case, the emitter terminal of the power transistor may be replaced with the source terminal.

The circuit configuration of the arm short-circuit prevention circuit 17 in the above embodiment can be realized by using other logic circuit elements or a circuit configuration using transistors or FETs.
For example, in the above embodiment, the control signal and the gate input signal are input to the NOR type logic element 21, but it is also possible to replace them with the negative logic circuit 35 as shown in FIG.

It is a figure which shows the power converter circuit of a single phase inverter. It is a figure which shows the drive circuit of the semiconductor switching element by a prior art example. 3 is a time chart showing each operation of the drive circuit of FIG. 2. It is a figure which shows the drive circuit of the semiconductor switching element by another prior art example. It is a figure which shows the drive circuit of the semiconductor switching element by the Example of this invention. 6 is a time chart illustrating each operation of the drive circuit of FIG. 5. 6 is a state transition table of the arm short circuit prevention circuit of FIG. 5. It is a figure which shows the drive circuit of the semiconductor switching element by the other Example of this invention. It is a time chart which shows each operation | movement of the drive circuit of FIG. It is a figure which shows the drive circuit of the semiconductor switching element by the other Example of this invention. It is a figure which shows the determination device incorporated in the drive circuit of the semiconductor switching element of FIG. It is a time chart in the determination device of FIG. It is a figure which shows the drive circuit of the semiconductor switching element by the other Example of this invention. It is a figure which shows the other logic circuit of a NOR logic circuit element.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 DC power supply 2 Load 3 Power transistor 4 Power transistor 5 Power transistor 6 Power transistor 7 Gate drive circuit 8 Gate drive circuit 9 Gate drive circuit 10 Gate drive circuit 11 NPN transistor 12 PNP transistor 13 Drive power supply 14 Control terminal 15 Resistor 16 FET
17 Arm short circuit prevention circuit 18 Signal delay circuit 19 Resistor 20 Capacitor 21 NOR type logic element 22 AND type logic element 23 INV type logic element 24 Judgment device 25 Inverting amplifier 26 INV type logic element 27 Resistor 28 Resistor 29 Input terminal 30 Output terminal 31 FET
32 Level shift circuit 33 Resistor 34 Resistor 35 Other application example of NOR type logic circuit element 36 Detector

Claims (3)

In a semiconductor switching element drive circuit comprising first and second semiconductor switching elements connected in series between output terminals of a DC power supply, and a drive circuit for driving the elements on / off by inputting a control signal,
A switch is connected between the gate and emitter of the first and second semiconductor switching elements;
A detector that detects that both the control signal and the gate input signal of the semiconductor switching element are in an OFF state, and shorts the gate and emitter of the first and second semiconductor switching elements by turning on the switch. A drive circuit for a semiconductor switching element, comprising: The detector according to claim 1 is configured by a logic circuit and does not detect a transition mode in which only the gate input signal shifts from the off state to the on state.
In the transition mode, a short circuit between the gate and the emitter of the semiconductor switching element is continuously performed.   A detector for detecting an ON / OFF signal of the control signal and / or the gate input signal is connected to the detector according to claim 1, the detector has a hysteresis function, and the two input signal levels are A driving circuit for a semiconductor switching element, characterized in that the off-signal determination criterion for two input signals is set to zero or more.

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