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JP2006229106A - Semiconductor device mounting method, mounting device, and semiconductor device - Google Patents

Semiconductor device mounting method, mounting device, and semiconductor device Download PDF

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Publication number
JP2006229106A
JP2006229106A JP2005043701A JP2005043701A JP2006229106A JP 2006229106 A JP2006229106 A JP 2006229106A JP 2005043701 A JP2005043701 A JP 2005043701A JP 2005043701 A JP2005043701 A JP 2005043701A JP 2006229106 A JP2006229106 A JP 2006229106A
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Prior art keywords
circuit board
bare chip
semiconductor bare
semiconductor
mounting
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Japanese (ja)
Inventor
Kazumichi Shimizu
一路 清水
Kazuto Nishida
一人 西田
Takahiko Yagi
能彦 八木
Michio Yoshino
道朗 吉野
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Panasonic Holdings Corp
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Matsushita Electric Industrial Co Ltd
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Priority to JP2005043701A priority Critical patent/JP2006229106A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01006—Carbon [C]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)

Abstract

【課題】回路基板５の裏面に後から実装する半導体ベアチップ加圧時の反りを矯正し、半導体ベアチップの破壊を防止し、位置合せ認識時の認識不良及び誤認識を防止すること。
【解決手段】回路基板５の少なくとも１箇所以上を基板矯正ツール１２と基板矯正ガイド１３で挟み込み、押圧して回路基板５の矯正を行いながら、半導体ベアチップ押圧ツール１４にて押圧し、加熱加圧を行うことにより、後から実装する半導体ベアチップの破壊防止、認識不良及び誤認識の防止が可能となる。
【選択図】図３An object of the present invention is to correct a warp when a semiconductor bare chip to be mounted later on a back surface of a circuit board 5 is pressed, prevent destruction of the semiconductor bare chip, and prevent recognition failure and misrecognition during alignment recognition.
At least one part of a circuit board is sandwiched between a substrate correction tool and a substrate correction guide and pressed with a semiconductor bare chip pressing tool while correcting the circuit substrate, and heated and pressed. By performing the above, it becomes possible to prevent destruction of a semiconductor bare chip to be mounted later, and prevent recognition failure and erroneous recognition.
[Selection] Figure 3

Description

本発明は、回路基板の片面もしくは両面の半導体ベアチップ取り付け面に半導体ベアチップがフリップチップ方法にて接続され、上記半導体ベアチップ取り付け面に対向する半導体ベアチップに形成された電極と回路基板上の電極とが電気的に接続される半導体装置の実装方法と実装装置および半導体装置に関するものである。   In the present invention, a semiconductor bare chip is connected to a semiconductor bare chip mounting surface on one or both sides of a circuit board by a flip chip method, and an electrode formed on the semiconductor bare chip facing the semiconductor bare chip mounting surface and an electrode on the circuit board are The present invention relates to a mounting method, a mounting apparatus, and a semiconductor device for electrically connected semiconductor devices.

電子回路基板は、あらゆる製品に使用されるようになり、かつ携帯機器の増加から、回路基板の半導体ベアチップをパッケージでなく裸のまま搭載するフリップチップ実装方法が求められている。さらに電子部品の高集積実装化に伴い、回路基板の両面に半導体ベアチップを実装する必要性が高まっている。   Electronic circuit boards are used in various products, and with the increase in portable devices, there is a demand for a flip chip mounting method in which a semiconductor bare chip on a circuit board is mounted as it is, not in a package. Furthermore, with the high integration mounting of electronic components, the need to mount semiconductor bare chips on both sides of a circuit board is increasing.

従来の電子機器の回路基板に半導体ベアチップを接合する方法について、以下に説明する。図１に示されるように、絶縁性の樹脂のシートもしくはペーストを半導体素子の実装における封止材として使用する半導体素子の実装工法が提案されている。   A method for bonding a semiconductor bare chip to a circuit board of a conventional electronic device will be described below. As shown in FIG. 1, there has been proposed a semiconductor element mounting method using an insulating resin sheet or paste as a sealing material for mounting a semiconductor element.

図１（ａ）において、半導体ベアチップ１上バンプは、半導体ベアチップ１のパッド２上に直径２５μｍのＡｕ線を用いてワイヤボンディング装置に付属するキャピラリ４によりバンプ３として形成される。あるいは、複数の半導体素子から構成されるウエハと呼ばれるシリコン結晶板にメッキを施してバンプを形成する場合もある。   In FIG. 1A, bumps on the semiconductor bare chip 1 are formed as bumps 3 on the pads 2 of the semiconductor bare chip 1 by using capillaries 4 attached to a wire bonding apparatus using Au wires having a diameter of 25 μm. Alternatively, bumps may be formed by plating a silicon crystal plate called a wafer composed of a plurality of semiconductor elements.

図１（ｂ）において、回路基板５に封止シート６を半導体素子実装領域に置き、貼り付けツール７を用いて加熱、加圧を行って貼り付けた。この時の加熱は封止シート６が硬化反応を起こさず、かつ、封止シート６の軟化を起こさせ、回路基板５への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。ペーストの場合は回路基板５へ塗布する。   In FIG. 1 (b), the sealing sheet 6 was placed on the circuit board 5 in the semiconductor element mounting region, and was attached by heating and pressing using the attaching tool 7. The heating at this time requires a temperature at which the encapsulating sheet 6 does not cause a curing reaction, causes the encapsulating sheet 6 to soften, and can be easily attached to the circuit board 5, and is usually 60 to 100 ° C. To do. In the case of paste, it is applied to the circuit board 5.

図１（ｃ）において、回路基板５上の基板電極８と半導体素子１に形成したバンプ３が接するように位置合わせして実装ヘッド９によりマウントする。   In FIG. 1C, the substrate electrode 8 on the circuit board 5 and the bump 3 formed on the semiconductor element 1 are aligned with each other and mounted by the mounting head 9.

図１（ｄ）において、回路基板５上にマウントした半導体素子１の裏面から圧着ツール１０を用いて加圧、加熱を行い、封止シート６樹脂硬化反応を起こさせる。   In FIG.1 (d), it pressurizes and heats using the crimping | compression-bonding tool 10 from the back surface of the semiconductor element 1 mounted on the circuit board 5, and causes sealing sheet 6 resin hardening reaction.

以上の工程を行うことにより、半導体素子の実装を短時間に、かつ、容易に行うことができるようになり、以上の実装工法と関連している封止シート６に導電粒子を混入させた異方性導電フィルムを用いた工法はＡＣＦ工法として広く実用されるようになってきた（例えば、特許文献１参照）。   By performing the above steps, the semiconductor element can be mounted in a short time and easily, and the conductive sheet is mixed into the sealing sheet 6 related to the above mounting method. A construction method using an anisotropic conductive film has come to be widely used as an ACF construction method (for example, see Patent Document 1).

両面に半導体ベアチップを実装する場合、上記貼り付け方法により回路基板５の表面に封止シート６を貼り付け、半導体素子１を位置合わせしてマウントする。その後圧着ツール１０を用いて加圧、加熱を行い、封止シート６の樹脂硬化反応を起こさせる。さらにここまでの工程を繰り返し、一つの回路基板内に複数個、特にその回路基板の両面に半導体ベアチップを実装することが求められている。
特開平１０−８３００７３号公報 When mounting a semiconductor bare chip on both surfaces, the sealing sheet 6 is affixed on the surface of the circuit board 5 by the said affixing method, and the semiconductor element 1 is aligned and mounted. Thereafter, pressurization and heating are performed using the crimping tool 10 to cause a resin curing reaction of the sealing sheet 6. Further, it is required to repeat the steps so far and mount a plurality of semiconductor bare chips on one circuit board, particularly on both sides of the circuit board.
JP-A-10-830073

しかしながら、前記従来の半導体ベアチップを回路基板の片面に複数個もしくは両面に複数個実装するためには、以下のような問題点がある。   However, in order to mount a plurality of the conventional semiconductor bare chips on one side or both sides of the circuit board, there are the following problems.

すなわち、圧着ツールにより加熱するため、前もって片面の他の箇所もしくは両面に樹脂の封止シートを貼り付けておくと、基板の他の箇所もしくは裏面にまで熱が伝わり、樹脂封止シートが反応してしまい、裏面の半導体素子が実装できない。そのため、１箇所目の圧着を完了後、他の箇所もしくは裏面の樹脂封止シートを貼り付け、マウントし、圧着するため実装タクトが長くなってしまう。   In other words, in order to heat with a crimping tool, if a resin sealing sheet is attached in advance to the other part or both sides of one side, heat is transmitted to the other part or the back side of the substrate, and the resin sealing sheet reacts. Therefore, the semiconductor element on the back surface cannot be mounted. For this reason, after completion of crimping at the first location, a mounting tact becomes long because a resin sealing sheet at another location or the back surface is attached, mounted, and crimped.

さらに、従来の技術で一箇所づつ実装する場合、１箇所目の圧着を完了した際に樹脂封止シートもしくはペーストの硬化収縮により回路基板および半導体素子に反りが発生し、他の箇所もしくは裏面に実装する際その反りにより圧着の荷重が先に実装した半導体ベアチップに集中し、その半導体ベアチップを破壊したり、実装装置による位置合わせ認識時に反りを有する基板を認識するために、認識不良および誤認識を発生する場合がある。   Furthermore, when mounting one by one with the conventional technology, the warping of the circuit board and the semiconductor element occurs due to the curing shrinkage of the resin sealing sheet or paste when the first crimping is completed, and other parts or the back surface When mounting, the load of crimping is concentrated on the semiconductor bare chip that was previously mounted, and the semiconductor bare chip is destroyed, or the substrate with the warp is recognized during alignment recognition by the mounting device. May occur.

本発明は、前記従来の課題を解決するもので、圧着回数の減少による実装タクトの短縮が可能で、回路基板および半導体素子に反りが発生せず、これらの位置合わせ認識時に認識不良および誤認識の発生を低減することが可能となる半導体装置の実装方法と実装装置、およびこのような実装方法と実装装置により製造される半導体装置を提供することを目的とする。   The present invention solves the above-mentioned conventional problems, and can reduce the mounting tact by reducing the number of times of crimping, does not cause warping of the circuit board and the semiconductor element, and recognizes misrecognition and misrecognition when recognizing these alignments. An object of the present invention is to provide a mounting method and mounting apparatus for a semiconductor device, and a semiconductor device manufactured by such a mounting method and mounting apparatus.

上記課題を解決するために、本発明の半導体装置の実装方法は第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップを実装するに際し、前記回路基板の他方の面の前記第２の半導体ベアチップ周辺の前記回路基板を、前記第２の半導体ベアチップを押圧するツールとは別のツールを用いて少なくとも１箇所以上押圧しながら、前記第２の半導体ベアチップを前記回路基板に搭載する工程、もしくは搭載された前記第２の半導体ベアチップと前記回路基板の間に介在する熱硬化性樹脂を熱により硬化する工程を有するものである。   In order to solve the above-described problem, a semiconductor device mounting method according to the present invention is configured such that the second surface of the circuit board on which the first semiconductor bare chip is mounted is positioned at a position facing the first semiconductor bare chip on the other surface. When mounting the semiconductor bare chip, at least one place of the circuit board around the second semiconductor bare chip on the other surface of the circuit board is used by using a tool different from the tool for pressing the second semiconductor bare chip. The step of mounting the second semiconductor bare chip on the circuit board while pressing the above, or the step of curing the thermosetting resin interposed between the mounted second semiconductor bare chip and the circuit board by heat. I have it.

また、回路基板の片面に搭載された複数個の半導体ベアチップを同時に押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させ、同時に前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる工程を有し、前記複数個の半導体ベアチップの厚みバラツキが±１０μｍ以内に管理されていることを特徴とするものである。   Further, a plurality of semiconductor bare chips mounted on one side of the circuit board are simultaneously pressed to deform the protruding electrode bumps formed on the semiconductor bare chip on the electrodes formed on the circuit board, and at the same time between the circuit boards And a thickness variation of the plurality of semiconductor bare chips is controlled within ± 10 μm.

また、本発明の半導体装置の実装装置は、上記半導体装置の実装方法における各工程を実施するための各手段を有し、さらに本発明の半導体装置は上記半導体装置の実装方法により製造されるものであることを特徴とする。   The semiconductor device mounting apparatus of the present invention has means for performing each step in the semiconductor device mounting method, and the semiconductor device of the present invention is manufactured by the semiconductor device mounting method. It is characterized by being.

本構成によって、実装タクトの短縮が可能であり、また、回路基板および半導体素子に反りが発生せず、これらの位置合わせ認識時に認識不良および誤認識の発生を低減することができる。   With this configuration, the mounting tact time can be shortened, the circuit board and the semiconductor element are not warped, and the occurrence of recognition failure and misrecognition during the alignment recognition can be reduced.

以上のように、本発明によれば、両面に樹脂の封止シートを貼り付け、マウントし、同時に圧着するため圧着回数が減少し、実装タクトを短縮することができる。   As described above, according to the present invention, the resin sealing sheets are attached to both surfaces, mounted, and simultaneously pressed, so that the number of press bondings can be reduced and the mounting tact time can be shortened.

さらに、圧着前に裏面のマウントを行うため、裏面のマウント時に回路基板および半導体素子に反りが発生せず、実装装置による位置合わせ認識時に認識不良および誤認識を発生する可能性が低くなり、これらの効果により生産性の高い半導体素子実装を実現することができる。   Furthermore, since the back surface is mounted before crimping, the circuit board and the semiconductor element are not warped when the back surface is mounted, and the possibility of recognition failure and misrecognition at the time of alignment recognition by the mounting device is reduced. Due to the above effect, it is possible to realize a highly productive semiconductor element mounting.

以下本発明の実施の形態について、図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

（実施の形態１）
図３は、本発明の実施の形態１における回路基板の片面に半導体ベアチップが実装された回路基板のもう一方の面に半導体ベアチップを実装する半導体装置の製造工程の概略図である。 (Embodiment 1)
FIG. 3 is a schematic diagram of a manufacturing process of a semiconductor device in which a semiconductor bare chip is mounted on the other surface of the circuit board in which the semiconductor bare chip is mounted on one surface of the circuit board in the first embodiment of the present invention.

図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図３（ａ）に示すように、回路基板５の少なくとも一箇所以上をシリンダ１１を有する基板矯正ツール１２と基板矯正ガイド１３で挟み込み、押圧しながら回路基板５を矯正する。図３（ｂ）に示すように、この回路基板５の矯正を行いながら、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識の防止を可能とする半導体装置の実装方法が実現する。   When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 3A, at least one portion of the circuit board 5 is sandwiched between the board correction tool 12 having the cylinder 11 and the board correction guide 13, and the circuit board 5 is corrected while being pressed. As shown in FIG. 3B, while the circuit board 5 is being corrected, it is pressed by the semiconductor bare chip pressing tool 14, and is heated and pressed. As a result, the warpage generated in the circuit board 5 and the semiconductor bare chip 1 prevents the destruction of the semiconductor bare chip that occurs when the semiconductor bare chip to be mounted later is pressed, and prevents the recognition failure and misrecognition during the alignment recognition. A possible semiconductor device mounting method is realized.

（実施の形態２）
図４は、本発明の実施の形態２における回路基板の片面に半導体ベアチップが実装された回路基板のもう一方の面に半導体ベアチップを実装する半導体装置の製造工程の概略図である。 (Embodiment 2)
FIG. 4 is a schematic diagram of a manufacturing process of a semiconductor device in which a semiconductor bare chip is mounted on the other surface of the circuit board in which the semiconductor bare chip is mounted on one surface of the circuit board in Embodiment 2 of the present invention.

図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図４（ａ）に示すように、回路基板５の両面をプレート１５およびプレート１６で挟み込み、回路基板５を矯正する。この回路基板５の矯正を行いながら、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識の防止を可能とする半導体装置の実装方法が実現する。   When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 4A, both sides of the circuit board 5 are sandwiched between the plate 15 and the plate 16 to correct the circuit board 5. While the circuit board 5 is being corrected, it is pressed by the semiconductor bare chip pressing tool 14 to be heated and pressed. As a result, the warpage generated in the circuit board 5 and the semiconductor bare chip 1 prevents the destruction of the semiconductor bare chip that occurs when the semiconductor bare chip to be mounted later is pressed, and prevents the recognition failure and misrecognition during the alignment recognition. A possible semiconductor device mounting method is realized.

（実施の形態３）
図５（ａ）は、本発明の実施の形態３における回路基板５の片面に半導体ベアチップが実装され、回路基板５のもう一方の面に半導体ベアチップ１を実装した半導体装置の概略図である。図５（ｂ）に示すように、シリンダ１１を有する基板矯正ツール１２と基板矯正ガイド１３で矯正された回路基板５に半導体ベアチップを実装、もしくは図５（ｃ）に示す回路基板５の両面をプレート１５およびプレート１６で挟み込み、回路基板５の矯正を行いながら半導体ベアチップ押圧ツール１４にて加熱、加圧し実装すると、半導体ベアチップの破壊が防止され、回路基板５および両面の半導体ベアチップ１の反りは矯正しない場合より大幅に低減される。よって歩留まりが高く、反りの少ない半導体装置が得られる。 (Embodiment 3)
FIG. 5A is a schematic diagram of a semiconductor device in which a semiconductor bare chip is mounted on one side of a circuit board 5 and a semiconductor bare chip 1 is mounted on the other side of the circuit board 5 in Embodiment 3 of the present invention. As shown in FIG. 5B, the semiconductor bare chip is mounted on the circuit board 5 corrected by the board correction tool 12 having the cylinder 11 and the board correction guide 13, or both sides of the circuit board 5 shown in FIG. When it is sandwiched between the plate 15 and the plate 16 and heated and pressed with the semiconductor bare chip pressing tool 14 while correcting the circuit board 5, mounting of the semiconductor bare chip is prevented, and the warpage of the circuit board 5 and the semiconductor bare chip 1 on both sides is prevented. Significant reduction compared with no correction. Therefore, a semiconductor device with high yield and less warpage can be obtained.

（実施の形態４）
図６は、本発明の実施の形態４における回路基板の片面に半導体ベアチップが実装された回路基板のもう一方の面に半導体ベアチップを実装する半導体装置の実装装置の概略図である。図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図６に示すように、回路基板５の少なくとも一箇所以上をシリンダ１１を有する基板矯正ツール１２と基板矯正ガイド１３で挟み込み、押圧して回路基板５の矯正を行いながら、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識の防止を可能とした歩留まりの高い半導体装置の実装装置を得ることができる。 (Embodiment 4)
FIG. 6 is a schematic diagram of a semiconductor device mounting apparatus for mounting a semiconductor bare chip on the other surface of the circuit board in which the semiconductor bare chip is mounted on one side of the circuit board according to the fourth embodiment of the present invention. When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 6, at least one part of the circuit board 5 is sandwiched between the board correction tool 12 having the cylinder 11 and the board correction guide 13 and pressed to correct the circuit board 5, and the semiconductor bare chip pressing tool 14. Press and heat and pressurize. As a result, the warpage generated in the circuit board 5 and the semiconductor bare chip 1 prevents the destruction of the semiconductor bare chip that occurs when the semiconductor bare chip to be mounted later is pressed, and prevents the recognition failure and misrecognition during the alignment recognition. It is possible to obtain a semiconductor device mounting apparatus capable of high yield.

（実施の形態５）
図７は、本発明の実施の形態５における回路基板の片面に半導体ベアチップが実装された回路基板のもう一方の面に半導体ベアチップを実装する半導体装置の製造装置の概略図である。図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図７に示すように、回路基板５の両面をプレート１５およびプレート１６で挟み込み、回路基板５の矯正を行いながら半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識の防止を可能とした歩留まりの高い半導体装置の実装装置を得ることができる。 (Embodiment 5)
FIG. 7 is a schematic diagram of a semiconductor device manufacturing apparatus for mounting a semiconductor bare chip on the other surface of the circuit board on which the semiconductor bare chip is mounted on one side of the circuit board in Embodiment 5 of the present invention. When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 7, both sides of the circuit board 5 are sandwiched between the plate 15 and the plate 16, and the circuit board 5 is pressed with the semiconductor bare chip pressing tool 14 while being corrected, and heated and pressed. As a result, the warpage generated in the circuit board 5 and the semiconductor bare chip 1 prevents the destruction of the semiconductor bare chip that occurs when the semiconductor bare chip to be mounted later is pressed, and prevents the recognition failure and misrecognition during the alignment recognition. It is possible to obtain a semiconductor device mounting apparatus capable of high yield.

（実施の形態６）
図８は、本発明の実施の形態６における回路基板の片面に半導体ベアチップが実装された回路基板のもう一方の面に半導体ベアチップを実装する半導体装置の実装工程の概略図である。図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図８（ａ）に示すように、回路基板５の少なくとも一箇所以上をシリンダ１１を有する基板矯正ツール１２と基板矯正ガイド１３で挟み込み、押圧して回路基板５の矯正を行いながら、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。 (Embodiment 6)
FIG. 8 is a schematic diagram of a semiconductor device mounting process for mounting a semiconductor bare chip on the other surface of the circuit board on which the semiconductor bare chip is mounted on one side of the circuit board in the sixth embodiment of the present invention. When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 8 (a), at least one part of the circuit board 5 is sandwiched between the board correction tool 12 having the cylinder 11 and the board correction guide 13, and pressed to correct the circuit board 5, while correcting the semiconductor bare chip. Pressing with the pressing tool 14 performs heating and pressurization.

この際、図８（ｂ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識を防止し、かつ回路基板５の基板電極８の高さバラツキを吸収し、接続抵抗値が低く、３０秒以下の短時間でバンプ３と基板電極８の電気的接続が得られ、歩留まりの高い半導体装置の実装方法が実現できる。   At this time, as shown in FIG. 8B, the bump 3 is deformed on the substrate electrode 8 and the sealing sheet 6 or the paste is simultaneously cured. This prevents the semiconductor bare chip from being destroyed when the semiconductor bare chip to be mounted later is pressed due to the warp generated in the circuit board 5 and the semiconductor bare chip 1, and the recognition failure and misrecognition at the time of alignment recognition are prevented. In addition, the height variation of the substrate electrode 8 of the circuit board 5 is absorbed, the connection resistance value is low, and the electrical connection between the bump 3 and the substrate electrode 8 can be obtained in a short time of 30 seconds or less. Implementation method can be realized.

（実施の形態７）
図９は、本発明の実施の形態７における回路基板の片面に半導体ベアチップが実装された回路基板のもう一方の面に半導体ベアチップを実装する半導体装置の実装工程の概略図である。図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図９（ａ）に示すように、回路基板５の両面をプレート１５およびプレート１６で挟み込み、回路基板５の矯正を行いながら半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。 (Embodiment 7)
FIG. 9 is a schematic diagram of a semiconductor device mounting process for mounting a semiconductor bare chip on the other side of the circuit board on which the semiconductor bare chip is mounted on one side of the circuit board in the seventh embodiment of the present invention. When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 9A, both sides of the circuit board 5 are sandwiched between the plate 15 and the plate 16 and pressed with the semiconductor bare chip pressing tool 14 while the circuit board 5 is being corrected, and heated and pressed.

この際、図９（ｂ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識を防止し、かつ回路基板５の基板電極８の高さバラツキを吸収し、接続抵抗値が低く、３０秒以下の短時間でバンプ３と基板電極８の電気的接続が得られ、歩留まりの高い半導体装置の実装方法が実現できる。   At this time, as shown in FIG. 9B, the bump 3 is deformed on the substrate electrode 8 and the sealing sheet 6 or paste is simultaneously cured. This prevents the semiconductor bare chip from being destroyed when the semiconductor bare chip to be mounted later is pressed due to the warp generated in the circuit board 5 and the semiconductor bare chip 1, and the recognition failure and misrecognition at the time of alignment recognition are prevented. In addition, the height variation of the substrate electrode 8 of the circuit board 5 is absorbed, the connection resistance value is low, and the electrical connection between the bump 3 and the substrate electrode 8 can be obtained in a short time of 30 seconds or less. Implementation method can be realized.

（実施の形態８）
図１０（ａ）は、本発明の実施の形態８における回路基板５の片面に半導体ベアチップ１が実装され、回路基板５のもう一方の面に半導体ベアチップ１を実装した半導体装置の概略図である。図１０（ｂ）に示すように、シリンダ１１を有する基板矯正ツール１２と基板矯正ガイド１３で矯正された回路基板５に半導体ベアチップを実装、もしくは図１０（ｃ）に示す回路基板５の両面をプレート１５およびプレート１６で挟み込み、回路基板５の矯正を行いながら半導体ベアチップ押圧ツール１４にて加熱、加圧し実装すると、半導体ベアチップの破壊が防止され、回路基板５および両面の半導体ベアチップ１の反りは矯正しない場合より大幅に低減される。 (Embodiment 8)
FIG. 10A is a schematic diagram of a semiconductor device in which the semiconductor bare chip 1 is mounted on one side of the circuit board 5 and the semiconductor bare chip 1 is mounted on the other side of the circuit board 5 in the eighth embodiment of the present invention. . As shown in FIG. 10B, the semiconductor bare chip is mounted on the circuit board 5 corrected with the board correction tool 12 having the cylinder 11 and the board correction guide 13, or both sides of the circuit board 5 shown in FIG. When it is sandwiched between the plate 15 and the plate 16 and heated and pressed with the semiconductor bare chip pressing tool 14 while correcting the circuit board 5, mounting of the semiconductor bare chip is prevented, and the warpage of the circuit board 5 and the semiconductor bare chip 1 on both sides is prevented. Significant reduction compared with no correction.

さらに、図１０（ｂ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。よって回路基板５の基板電極８の高さバラツキを吸収し、接続抵抗値が低く、３０秒以下の短時間でバンプ３と基板電極８の電気的接続が得られ、歩留まりが高く、反りの少ない半導体装置が得られる。   Further, as shown in FIG. 10 (b), the bump 3 is deformed on the substrate electrode 8, and at the same time, the sealing sheet 6 or the paste is cured. Therefore, the height variation of the substrate electrode 8 of the circuit board 5 is absorbed, the connection resistance value is low, the electrical connection between the bump 3 and the substrate electrode 8 can be obtained in a short time of 30 seconds or less, the yield is high, and the warp is small. A semiconductor device is obtained.

（実施の形態９）
図１１は、本発明の実施の形態９における回路基板の片面に半導体ベアチップが実装された回路基板５のもう一方の面に半導体ベアチップを実装する半導体装置の製造装置の概略図である。図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図１１（ａ）に示すように、回路基板５の少なくとも一箇所以上をシリンダ１１を有する基板矯正ツール１２と基板矯正ガイド１３で挟み込み、押圧して回路基板５の矯正を行いながら、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。 (Embodiment 9)
FIG. 11 is a schematic diagram of a semiconductor device manufacturing apparatus in which a semiconductor bare chip is mounted on the other surface of the circuit board 5 in which the semiconductor bare chip is mounted on one surface of the circuit board in Embodiment 9 of the present invention. When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 11A, at least one part of the circuit board 5 is sandwiched between the board correction tool 12 having the cylinder 11 and the board correction guide 13 and pressed to correct the circuit board 5 while correcting the semiconductor bare chip. Pressing with the pressing tool 14 performs heating and pressurization.

この際、図１１（ｂ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識を防止し、かつ回路基板５の基板電極８の高さバラツキを吸収し、接続抵抗値が低く、３０秒以下の短時間でバンプ３と基板電極８の電気的接続が得られ、歩留まりの高い半導体装置の実装装置が得られる。   At this time, as shown in FIG. 11 (b), the bump 3 is deformed on the substrate electrode 8, while the sealing sheet 6 or the paste is simultaneously cured. This prevents the semiconductor bare chip from being destroyed when the semiconductor bare chip to be mounted later is pressed due to the warp generated in the circuit board 5 and the semiconductor bare chip 1, and the recognition failure and misrecognition at the time of alignment recognition are prevented. In addition, the height variation of the substrate electrode 8 of the circuit board 5 is absorbed, the connection resistance value is low, and the electrical connection between the bump 3 and the substrate electrode 8 can be obtained in a short time of 30 seconds or less. A mounting device is obtained.

（実施の形態１０）
図１２は、本発明の実施の形態１０における回路基板の片面に半導体ベアチップが実装された回路基板５のもう一方の面に半導体ベアチップを実装する半導体装置の製造装置の概略図である。図２に示す回路基板５の片面に半導体ベアチップ１が実装されていると、封止シート６もしくはペーストの硬化収縮により回路基板５および半導体ベアチップ１に反りが発生する。そこで図１２（ａ）に示すように、回路基板５の両面をプレート１５およびプレート１６で挟み込み、回路基板５の矯正を行いながら半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。 (Embodiment 10)
FIG. 12 is a schematic diagram of a semiconductor device manufacturing apparatus in which a semiconductor bare chip is mounted on the other surface of the circuit board 5 in which the semiconductor bare chip is mounted on one surface of the circuit board in the tenth embodiment of the present invention. When the semiconductor bare chip 1 is mounted on one side of the circuit board 5 shown in FIG. 2, the circuit board 5 and the semiconductor bare chip 1 are warped due to the curing shrinkage of the sealing sheet 6 or the paste. Therefore, as shown in FIG. 12A, both sides of the circuit board 5 are sandwiched between the plate 15 and the plate 16 and pressed with the semiconductor bare chip pressing tool 14 while the circuit board 5 is being corrected, and heated and pressed.

この際、図１２（ｂ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。このことにより、回路基板５および半導体ベアチップ１に発生した反りにより、後から実装する半導体ベアチップを加圧する際に生じる半導体ベアチップの破壊の防止、および位置合わせ認識時の認識不良および誤認識を防止し、かつ回路基板５の基板電極８の高さバラツキを吸収し、接続抵抗値が低く、３０秒以下の短時間でバンプ３と基板電極８の電気的接続が得られ、歩留まりの高い半導体装置の実装装置が得られる。   At this time, as shown in FIG. 12B, the bump 3 is deformed on the substrate electrode 8, and at the same time, the sealing sheet 6 or the paste is cured. This prevents the semiconductor bare chip from being destroyed when the semiconductor bare chip to be mounted later is pressed due to the warp generated in the circuit board 5 and the semiconductor bare chip 1, and the recognition failure and misrecognition at the time of alignment recognition are prevented. In addition, the height variation of the substrate electrode 8 of the circuit board 5 is absorbed, the connection resistance value is low, and the electrical connection between the bump 3 and the substrate electrode 8 can be obtained in a short time of 30 seconds or less. A mounting device is obtained.

（実施の形態１１）
図１３は、本発明の実施の形態１１における、２チップ以上の半導体ベアチップ１７および１８を回路基板５に実装する半導体装置の製造工程の概略図である。２チップ以上の半導体ベアチップを回路基板５の片面に搭載し、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。この際、図１３（ｂ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。このとき用いる半導体ベアチップ１７および１８は、その厚みバラツキが±１０μｍ以下、好適には±５μｍ以下に管理されていることが望ましい。 (Embodiment 11)
FIG. 13 is a schematic diagram of a manufacturing process of a semiconductor device in which two or more semiconductor bare chips 17 and 18 are mounted on the circuit board 5 in the eleventh embodiment of the present invention. Two or more semiconductor bare chips are mounted on one side of the circuit board 5, pressed by the semiconductor bare chip pressing tool 14, and heated and pressed. At this time, as shown in FIG. 13B, the bump 3 is deformed on the substrate electrode 8, and at the same time, the sealing sheet 6 or the paste is cured. It is desirable that the semiconductor bare chips 17 and 18 used at this time have thickness variations of ± 10 μm or less, preferably ± 5 μm or less.

さらに、図１３（ｂ）に示すように、同一ウエハ１９内の半導体ベアチップを用いれば、その厚みバラツキはほぼ一定に管理される。この場合、同一ウエハ１９内であれば、任意の場所の半導体ベアチップ１７および１８もしくはそれ以上を用いればよい。この半導体ベアチップの厚みバラツキが管理されていることにより、各半導体ベアチップでバンプ３は確実に基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化し、良好な電気的接続が得られ、かつ同時に複数個の半導体ベアチップの実装を完了し、生産時間を少なくとも２倍以上短縮することにつながる半導体装置の実装方法が実現できる。   Further, as shown in FIG. 13B, if the semiconductor bare chip in the same wafer 19 is used, the thickness variation is managed to be almost constant. In this case, as long as it is in the same wafer 19, the semiconductor bare chips 17 and 18 at arbitrary positions or more may be used. By controlling the thickness variation of the semiconductor bare chip, the bump 3 is reliably deformed on the substrate electrode 8 in each semiconductor bare chip, and at the same time, the sealing sheet 6 or the paste is cured, and a good electrical connection is obtained. In addition, it is possible to realize a semiconductor device mounting method that simultaneously completes mounting of a plurality of semiconductor bare chips and leads to a reduction in production time by at least twice.

（実施の形態１２）
図１４（ａ）は、本発明の実施の形態１２における、４チップ以上の半導体ベアチップ２０、２１、２２、および２３を回路基板５に実装する半導体装置の製造工程の概略図である。４チップ以上の半導体ベアチップを回路基板５の両面に搭載し、半導体ベアチップ押圧ツール１４にて押圧し、加熱、加圧を行う。この際、図１４（ａ）に示すように、バンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化する。このとき用いる半導体ベアチップは、その厚みバラツキが±１０μｍ以下、好適には±５μｍ以下に管理されていることが望ましい。 (Embodiment 12)
FIG. 14A is a schematic diagram of a manufacturing process of a semiconductor device in which four or more semiconductor bare chips 20, 21, 22, and 23 are mounted on the circuit board 5 in the twelfth embodiment of the present invention. Four or more semiconductor bare chips are mounted on both sides of the circuit board 5, pressed by the semiconductor bare chip pressing tool 14, and heated and pressed. At this time, as shown in FIG. 14 (a), the bump 3 is deformed on the substrate electrode 8, and at the same time, the sealing sheet 6 or the paste is cured. It is desirable that the semiconductor bare chip used at this time has a thickness variation of ± 10 μm or less, preferably ± 5 μm or less.

さらに、図１４（ｂ）に示すように、同一ウエハ２４内の半導体ベアチップを用いれば、その厚みバラツキはほぼ一定に管理される。この場合、同一ウエハ２４内であれば、任意の場所の半導体ベアチップ１９、２０、２１および２２もしくはそれ以上を用いればよい。この半導体ベアチップの厚みバラツキが管理されていることにより、各半導体ベアチップでバンプ３は確実に基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化し、良好な電気的接続が得られ、かつ同時に複数個の半導体ベアチップの実装を完了し、生産時間を少なくとも４倍以上短縮することにつながる半導体装置の実装方法が実現できる。   Furthermore, as shown in FIG. 14B, if semiconductor bare chips in the same wafer 24 are used, the thickness variation is managed to be substantially constant. In this case, the semiconductor bare chips 19, 20, 21, and 22 at arbitrary locations may be used within the same wafer 24. By controlling the thickness variation of the semiconductor bare chip, the bump 3 is reliably deformed on the substrate electrode 8 in each semiconductor bare chip, and at the same time, the sealing sheet 6 or the paste is cured, and a good electrical connection is obtained. In addition, it is possible to realize a semiconductor device mounting method that simultaneously completes the mounting of a plurality of semiconductor bare chips and reduces the production time by at least four times.

（実施の形態１３）
図１５（ａ）は、本発明の実施の形態１３における回路基板２５の片面に半導体ベアチップ１が実装され、回路基板５のもう一方の面に半導体ベアチップ１を実装した半導体装置の概略図である。メモリ用途の半導体ベアチップ２６及び２７に形成されたバンプ３は基板電極８上で変形しながら、同時に封止シート６もしくはペーストは硬化して接合している。 (Embodiment 13)
FIG. 15A is a schematic diagram of a semiconductor device in which the semiconductor bare chip 1 is mounted on one side of the circuit board 25 and the semiconductor bare chip 1 is mounted on the other side of the circuit board 5 in the thirteenth embodiment of the present invention. . While the bumps 3 formed on the semiconductor bare chips 26 and 27 for memory use are deformed on the substrate electrode 8, the sealing sheet 6 or the paste is simultaneously cured and bonded.

図１５（ｂ）に示すように、このメモリ用半導体ベアチップ２６およびメモリ用半導体ベアチップのデータライン部のパッドレイアウトを、回路基板２５の両面で面対称にすることにより、この半導体装置の回路基板２５の電極は両面で同じ配置になっており、その回路基板２５の両面の電極はスルーホール２８で結ばれ、回路基板２５内でデータライン２８を共通化している。このことにより、基板内部の配線を半減しデータ転送を速めることが可能となる半導体装置を得ることができる。   As shown in FIG. 15B, the pad layout of the memory semiconductor bare chip 26 and the data line portion of the memory semiconductor bare chip is made plane-symmetrical on both sides of the circuit board 25, whereby the circuit board 25 of this semiconductor device is obtained. The electrodes on both sides of the circuit board 25 are connected to each other by a through hole 28, and the data line 28 is shared in the circuit board 25. As a result, a semiconductor device capable of halving the wiring inside the substrate and speeding up data transfer can be obtained.

（実施の形態１４）
図１６（ａ）は、本発明の実施の形態１４における回路基板の両面に半導体ベアチップを実装する実装工法の概略図である。 (Embodiment 14)
FIG. 16A is a schematic diagram of a mounting method for mounting a semiconductor bare chip on both surfaces of a circuit board in Embodiment 14 of the present invention.

図１６（ｂ）の回路基板２９に、封止シート３０を半導体素子実装領域に置き、貼り付けツール３１を用いて加熱、加圧を行って貼り付ける。この時の加熱は封止シート３０が硬化反応を起こさず、かつ、封止シートの軟化を起こさせ、回路基板２９への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。表面貼り付け後、裏面の貼り付けを同様に行う。   The sealing sheet 30 is placed in the semiconductor element mounting region on the circuit board 29 in FIG. 16B, and is attached by heating and pressurizing using the attaching tool 31. The heating at this time requires a temperature at which the encapsulating sheet 30 does not cause a curing reaction, and the encapsulating sheet is softened and easily attached to the circuit board 29. Do. After the front surface is pasted, the back surface is pasted in the same manner.

図１６（ｃ）において、回路基板２９上の基板電極３２と半導体ベアチップ３３および半導体ベアチップ３４に形成したバンプ電極３５が接するように位置合わせして、実装ヘッド３６により片面づつ両面にマウントする。   In FIG. 16 (c), the substrate electrode 32 on the circuit board 29 and the bump electrodes 35 formed on the semiconductor bare chip 33 and the semiconductor bare chip 34 are aligned so that they are in contact with each other and mounted on both sides by the mounting head 36.

図１６（ｄ）において、回路基板２９の両面にマウントした半導体ベアチップ３３および半導体ベアチップ３４に対し、下方は断熱性の高いガラスもしくは石英からなるステージ３８を配置し、上方から加熱可能な圧着ツール３７を用いて加圧する。この圧着工程において両面に熱及び加圧力が加わり、基板電極３２上でバンプ電極３５が変形しながら同時に樹脂シートが硬化し、電気的接合を行う。このことにより、両面同時に圧着を行うことで圧着工程の時間短縮が可能な半導体装置の実装装置が得られる。   In FIG. 16D, with respect to the semiconductor bare chip 33 and the semiconductor bare chip 34 mounted on both surfaces of the circuit board 29, a lower pressure stage 37 made of glass or quartz having a high heat insulating property is disposed, and a crimping tool 37 that can be heated from above. Press to apply pressure. In this crimping process, heat and pressure are applied to both surfaces, and the bump electrode 35 is deformed on the substrate electrode 32, and at the same time, the resin sheet is cured and electrical bonding is performed. As a result, a semiconductor device mounting apparatus capable of shortening the time of the crimping process by simultaneously crimping both surfaces is obtained.

（実施の形態１５）
図１７（ａ）は、本発明の実施の形態１５における回路基板の両面に半導体ベアチップを実装する実装工法の概略図である。 (Embodiment 15)
FIG. 17A is a schematic diagram of a mounting method for mounting semiconductor bare chips on both surfaces of a circuit board in Embodiment 15 of the present invention.

図１７（ｂ）の回路基板２９に、封止シート３０を半導体素子実装領域に置き、貼り付けツール３１を用いて加熱、加圧を行って貼り付ける。この時の加熱は封止シート３０が硬化反応を起こさず、かつ、封止シートの軟化を起こさせ、回路基板２９への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。表面貼り付け後、裏面の貼り付けを同様に行う。   The sealing sheet 30 is placed in the semiconductor element mounting region on the circuit board 29 in FIG. 17B and is attached by heating and pressing using the attaching tool 31. The heating at this time requires a temperature at which the encapsulating sheet 30 does not cause a curing reaction, and the encapsulating sheet is softened and easily attached to the circuit board 29. Do. After the front surface is pasted, the back surface is pasted in the same manner.

図１７（ｃ）において、回路基板２９上の基板電極３２と半導体ベアチップ３３および半導体ベアチップ３４に形成したバンプ電極３５が接するように位置合わせして、実装ヘッド３６により片面づつ両面にマウントする。   In FIG. 17 (c), the substrate electrode 32 on the circuit board 29 and the bump electrodes 35 formed on the semiconductor bare chip 33 and the semiconductor bare chip 34 are aligned so that they are in contact with each other and mounted on both sides by the mounting head 36.

図１７（ｄ）において、回路基板２９の両面にマウントした半導体ベアチップ３３および半導体ベアチップ３４に対し、下方は加熱可能なステージ３９を配置し、上方から加熱可能な圧着ツール３７を用いて加圧する。この圧着工程において両面に熱及び加圧力が加わり、基板電極３２上でバンプ電極３５が変形しながら同時に封止シートが硬化し、電気的接合を行う。回路基板の両面から加熱することにより、両面に均一に熱が伝わる。このことにより、両面同時に圧着を行うことで圧着工程の時間が短縮し、半導体装置の反りが少なくかつ接合信頼性の高い半導体装置の製造が可能な半導体実装装置が得られる。   In FIG. 17D, a heatable stage 39 is disposed below the semiconductor bare chip 33 and the semiconductor bare chip 34 mounted on both surfaces of the circuit board 29, and pressure is applied using a crimping tool 37 that can be heated from above. In this crimping process, heat and pressure are applied to both surfaces, and the bump electrode 35 is deformed on the substrate electrode 32, and at the same time, the sealing sheet is cured and electrical bonding is performed. By heating from both sides of the circuit board, heat is uniformly transmitted to both sides. As a result, it is possible to obtain a semiconductor mounting device capable of shortening the time of the crimping process by performing the crimping simultaneously on both sides, producing a semiconductor device with less warpage of the semiconductor device and high bonding reliability.

（実施の形態１６）
図１８（ａ）は、本発明の実施の形態１６における回路基板の両面に半導体ベアチップを実装する実装工法の概略図である。 (Embodiment 16)
FIG. 18A is a schematic diagram of a mounting method for mounting a semiconductor bare chip on both surfaces of a circuit board in Embodiment 16 of the present invention.

図１８（ｂ）の回路基板２９に、封止シート３０を半導体素子実装領域に置き、貼り付けツール３１を用いて加熱、加圧を行って貼り付ける。この時の加熱は封止シート３０が硬化反応を起こさず、かつ、封止シートの軟化を起こさせ、回路基板２９への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。表面貼り付け後、裏面の貼り付けを同様に行う。   The sealing sheet 30 is placed in the semiconductor element mounting region on the circuit board 29 in FIG. 18B, and is attached by heating and pressing using the attaching tool 31. The heating at this time requires a temperature at which the encapsulating sheet 30 does not cause a curing reaction, and the encapsulating sheet is softened and easily attached to the circuit board 29. Do. After the front surface is pasted, the back surface is pasted in the same manner.

図１８（ｃ）において、回路基板２９上の基板電極３２と半導体ベアチップ３３および半導体ベアチップ３４に形成したバンプ電極３５が接するように位置合わせして、実装ヘッド３６により片面づつ両面にマウントする。   In FIG. 18C, the substrate electrode 32 on the circuit board 29 is aligned with the bump electrodes 35 formed on the semiconductor bare chip 33 and the semiconductor bare chip 34 and mounted on both sides by the mounting head 36.

図１８（ｄ）において、回路基板２９の両面にマウントした半導体ベアチップ３３および半導体ベアチップ３４に対し、下方はセラミックスヒータまたはパルスヒータで加熱可能なステージ４０を配置し、上方から加熱可能な圧着ツール３７を用いて加圧する。この圧着工程において両面に熱及び加圧力が加わり、基板電極３２上でバンプ電極３５が変形しながら同時に封止シートが硬化し、電気的接合を行う。回路基板の両面から加熱することにより、両面に均一に熱が伝わる。さらに、回路基板をステージ上に配置する際は、ステージにセラミックスヒータまたはパルスヒータを用いているために加熱しないことが可能であり、回路基板をステージ上に配置する間の封止シートの反応を抑制することができる。このことにより、両面同時に圧着を行うことで圧着工程の時間が短縮し、半導体装置の反りが少なくかつ接合信頼性の高い半導体装置の製造が可能な半導体実装装置が得られる。   In FIG. 18D, with respect to the semiconductor bare chip 33 and the semiconductor bare chip 34 mounted on both surfaces of the circuit board 29, a stage 40 that can be heated by a ceramic heater or a pulse heater is disposed below, and a crimping tool 37 that can be heated from above. Press to apply pressure. In this crimping process, heat and pressure are applied to both surfaces, and the bump electrode 35 is deformed on the substrate electrode 32, and at the same time, the sealing sheet is cured and electrical bonding is performed. By heating from both sides of the circuit board, heat is uniformly transmitted to both sides. Furthermore, when the circuit board is placed on the stage, it is possible to avoid heating because a ceramic heater or a pulse heater is used for the stage, and the reaction of the sealing sheet during the placement of the circuit board on the stage is prevented. Can be suppressed. As a result, it is possible to obtain a semiconductor mounting device capable of shortening the time of the crimping process by performing the crimping simultaneously on both sides, producing a semiconductor device with less warpage of the semiconductor device and high bonding reliability.

（実施の形態１７）
図１９（ａ）は、本発明の実施の形態１７における回路基板の両面に半導体ベアチップを実装する実装工法の概略図である。 (Embodiment 17)
FIG. 19A is a schematic diagram of a mounting method for mounting semiconductor bare chips on both surfaces of a circuit board in Embodiment 17 of the present invention.

図１９（ｂ）の回路基板２９に、封止シート３０を半導体素子実装領域に置き、貼り付けツール３１を用いて加熱、加圧を行って貼り付ける。この時の加熱は封止シート３０が硬化反応を起こさず、かつ、封止シートの軟化を起こさせ、回路基板２９への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。表面貼り付け後、裏面の貼り付けを同様に行う。   A sealing sheet 30 is placed in the semiconductor element mounting region on the circuit board 29 in FIG. 19B and is attached by heating and pressurizing using the attaching tool 31. The heating at this time requires a temperature at which the encapsulating sheet 30 does not cause a curing reaction, and the encapsulating sheet is softened and easily attached to the circuit board 29. Do. After the front surface is pasted, the back surface is pasted in the same manner.

図１９（ｃ）において、回路基板２９上の基板電極３２と半導体ベアチップ３３および半導体ベアチップ３４に形成したバンプ電極３５が接するように位置合わせして、実装ヘッド３６により片面づつ両面にマウントする。   In FIG. 19 (c), the substrate electrodes 32 on the circuit board 29 are aligned with the bump electrodes 35 formed on the semiconductor bare chip 33 and the semiconductor bare chip 34, and are mounted on both sides by the mounting head 36.

図１９（ｄ）において、回路基板２９の両面にマウントした半導体ベアチップ３３および半導体ベアチップ３４に対し、下方はセラミックスヒータまたはパルスヒータで加熱可能なステージ４０を配置し、上方からはセラミックスヒータまたはパルスヒータで加熱可能な圧着ツール４１を用いて加圧する。この圧着工程において両面に熱及び加圧力が加わり、基板電極３２上でバンプ電極３５が変形しながら同時に封止シートが硬化し、電気的接合を行う。回路基板の両面から加熱することにより、両面に均一に熱が伝わる。さらに、回路基板をステージ上に配置する際は、ステージにセラミックスヒータまたはパルスヒータを用いているために加熱しないことが可能であり、回路基板をステージ上に配置する間の封止シートの反応を抑制することができる。圧着ツールにセラミックスヒータまたはパルスヒータを用いているために加圧と同時に圧着ツールを昇温することができる。加熱された状態の圧着ツールを用いると、この半導体装置を加熱するまでの間に輻射熱を受け、封止シートの反応が始まってしまうが、セラミックスヒータまたはパルスヒータを用いた圧着ツールで加圧すると、輻射熱による封止シートの反応を抑制することができる。このことにより、両面同時に圧着を行うことで圧着工程の時間が短縮し、半導体装置の反りが少なくかつ接合信頼性の高い半導体装置の製造が可能な半導体実装装置が得られる。   In FIG. 19D, a stage 40 that can be heated by a ceramic heater or a pulse heater is disposed below the semiconductor bare chip 33 and the semiconductor bare chip 34 mounted on both surfaces of the circuit board 29, and the ceramic heater or pulse heater is disposed from above. The pressure is applied by using a crimping tool 41 that can be heated in the above. In this crimping process, heat and pressure are applied to both surfaces, and the bump electrode 35 is deformed on the substrate electrode 32, and at the same time, the sealing sheet is cured and electrical bonding is performed. By heating from both sides of the circuit board, heat is uniformly transmitted to both sides. Furthermore, when the circuit board is placed on the stage, it is possible to avoid heating because a ceramic heater or a pulse heater is used for the stage, and the reaction of the sealing sheet during the placement of the circuit board on the stage is prevented. Can be suppressed. Since a ceramic heater or a pulse heater is used for the crimping tool, the temperature of the crimping tool can be raised simultaneously with pressurization. If a crimping tool in a heated state is used, it will receive radiant heat until the semiconductor device is heated, and the reaction of the sealing sheet will start. If pressure is applied with a crimping tool using a ceramic heater or pulse heater, The reaction of the sealing sheet due to radiant heat can be suppressed. As a result, it is possible to obtain a semiconductor mounting device capable of shortening the time of the crimping process by performing the crimping simultaneously on both sides, producing a semiconductor device with less warpage of the semiconductor device and high bonding reliability.

（実施の形態１８）
図２０（ａ）は、本発明の実施の形態１８における回路基板の両面に半導体ベアチップを実装する実装工法の概略図である。 (Embodiment 18)
FIG. 20A is a schematic diagram of a mounting method for mounting a semiconductor bare chip on both surfaces of a circuit board according to the eighteenth embodiment of the present invention.

図２０（ｂ）の回路基板２９に、封止シート３０を半導体素子実装領域に置き、貼り付けツール３１を用いて加熱、加圧を行って貼り付ける。この時の加熱は封止シート３０が硬化反応を起こさず、かつ、封止シートの軟化を起こさせ、回路基板２９への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。表面貼り付け後、裏面の貼り付けを同様に行う。   A sealing sheet 30 is placed in the semiconductor element mounting region on the circuit board 29 in FIG. 20B and is attached by heating and pressurizing using the attaching tool 31. The heating at this time requires a temperature at which the encapsulating sheet 30 does not cause a curing reaction, and the encapsulating sheet is softened and easily attached to the circuit board 29. Do. After the front surface is pasted, the back surface is pasted in the same manner.

図２０（ｃ）において、回路基板２９上の基板電極３２と半導体ベアチップ３３および半導体ベアチップ３４に形成したバンプ電極３５が接するように位置合わせして、実装ヘッド３６により片面づつ両面にマウントする。   In FIG. 20 (c), the substrate electrode 32 on the circuit board 29 is aligned with the bump electrodes 35 formed on the semiconductor bare chip 33 and the semiconductor bare chip 34, and mounted on both sides by the mounting head 36.

図２０（ｄ）において、回路基板２９の両面にマウントした半導体ベアチップ３３および半導体ベアチップ３４に対し、下方はコンスタントヒータで加熱可能なステージ４２を配置し、上方からはコンスタントヒータで加熱可能な圧着ツール４３を用いて加圧する。この圧着工程において両面に熱及び加圧力が加わり、基板電極３２上でバンプ電極３５が変形しながら同時に封止シートが硬化し、電気的接合を行う。回路基板の両面から加熱することにより、両面に均一に熱が伝わる。さらに、圧着ツールとステージにセラミックスヒータまたはパルスヒータを用いる場合より、昇温、降温に時間がかからず、かつ温度が一定に保たれているため、一度圧着ツールとステージの平行度を出せば、その平行度は安定して保たれ続けた状態で圧着を繰り返すことができる。このことにより、両面同時に圧着を行うことで圧着工程の時間が短縮し、半導体装置の反りが少なくかつ接合信頼性の高い半導体装置の製造が可能な半導体実装装置が得られる。   In FIG. 20 (d), with respect to the semiconductor bare chip 33 and the semiconductor bare chip 34 mounted on both surfaces of the circuit board 29, a stage 42 that can be heated by a constant heater is disposed below, and a crimping tool that can be heated by a constant heater from above. Pressurize using 43. In this crimping process, heat and pressure are applied to both surfaces, and the bump electrode 35 is deformed on the substrate electrode 32, and at the same time, the sealing sheet is cured and electrical bonding is performed. By heating from both sides of the circuit board, heat is uniformly transmitted to both sides. Furthermore, it takes less time to raise and lower the temperature than when a ceramic heater or pulse heater is used for the crimping tool and stage, and the temperature is kept constant. The pressure bonding can be repeated in a state where the parallelism is kept stably. As a result, it is possible to obtain a semiconductor mounting device capable of shortening the time of the crimping process by performing the crimping simultaneously on both sides, producing a semiconductor device with less warpage of the semiconductor device and high bonding reliability.

（実施の形態１９）
図２１（ａ）は、本発明の実施の形態１９における回路基板の両面に半導体ベアチップを実装する実装工法の概略図である。 (Embodiment 19)
FIG. 21A is a schematic diagram of a mounting method for mounting semiconductor bare chips on both surfaces of a circuit board in Embodiment 19 of the present invention.

図２１（ｂ）の回路基板２９に、封止シート３０を半導体素子実装領域に置き、貼り付けツール３１を用いて加熱、加圧を行って。この時の加熱は封止シート３０が硬化反応を起こさず、かつ、封止シートの軟化を起こさせ、回路基板２９への貼り付けを容易にする温度が必要であり、通常６０〜１００℃で行う。表面貼り付け後、裏面の貼り付けを同様に行う。   A sealing sheet 30 is placed on the circuit board 29 of FIG. 21B in the semiconductor element mounting region, and heated and pressurized using the attaching tool 31. The heating at this time requires a temperature at which the encapsulating sheet 30 does not cause a curing reaction, and the encapsulating sheet is softened and easily attached to the circuit board 29. Do. After the front surface is pasted, the back surface is pasted in the same manner.

図２１（ｃ）において、回路基板２９上の基板電極３２と半導体ベアチップ３３および半導体ベアチップ３４に形成したバンプ電極３５が接するように位置合わせして、実装ヘッド３６により片面づつ両面にマウントする。   In FIG. 21 (c), the substrate electrode 32 on the circuit board 29 and the bump electrodes 35 formed on the semiconductor bare chip 33 and the semiconductor bare chip 34 are aligned so that they are mounted on both sides by the mounting head 36.

図２１（ｄ）において、回路基板２９の両面にマウントした半導体ベアチップ３３および半導体ベアチップ３４に対し、上方及び下方の両方から加熱可能な圧着ツール４４を用いて加圧する。この圧着工程において両面から熱及び加圧力が加わり、基板電極３２上でバンプ電極３５が変形しながら同時に封止シートが硬化し、電気的接合を行う。回路基板の両面から加圧加熱することにより、両面に均一に加圧力と熱が伝わる。このことにより、両面同時に圧着を行うことで圧着工程の時間が短縮し、半導体装置の反りが少なく、両面での接合状態がほぼ等しくなり、接合信頼性の高い半導体装置の製造が可能な半導体実装装置が得られる。   In FIG. 21D, the semiconductor bare chip 33 and the semiconductor bare chip 34 mounted on both surfaces of the circuit board 29 are pressed using a crimping tool 44 that can be heated from both above and below. In this crimping process, heat and pressure are applied from both sides, and the bump sheet 35 is deformed on the substrate electrode 32, and at the same time, the sealing sheet is cured and electrical bonding is performed. By applying pressure and heating from both sides of the circuit board, pressure and heat are uniformly transmitted to both sides. As a result, the time required for the crimping process can be shortened by performing crimping simultaneously on both sides, there is little warpage of the semiconductor device, the joining state on both sides is almost equal, and the semiconductor packaging that can manufacture a semiconductor device with high joining reliability A device is obtained.

本発明の半導体装置の実装方法と実装装置、およびこれにより製造される半導体装置においては、圧着回数の減少による実装タクトの短縮が可能で、回路基板および半導体素子に反りが発生せず、これらの位置合わせ認識時に認識不良および誤認識の発生を低減することが可能となり、様々なタイプの半導体素子の回路基板への実装に汎用的に適用できる。   In the semiconductor device mounting method and the mounting device of the present invention, and the semiconductor device manufactured thereby, the mounting tact can be shortened by reducing the number of times of crimping, and the circuit board and the semiconductor element are not warped. It is possible to reduce the occurrence of recognition failure and misrecognition at the time of alignment recognition, and it can be generally applied to mounting various types of semiconductor elements on a circuit board.

従来の電子機器の回路基板に半導体ベアチップを接合する方法を説明する図であり（ａ）は半導体ベアチップにバンプを形成する状態を示す図（ｂ）は回路基板にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板に半導体ベアチップをマウントする状態を示す図（ｄ）は本圧着の状態を示す図It is a figure explaining the method to join a semiconductor bare chip to the circuit board of the conventional electronic equipment, (a) shows the state where bump is formed in a semiconductor bare chip, and (b) shows the state where sheet resin is stuck on a circuit board Figure (c) is a diagram showing a state where a semiconductor bare chip is mounted on a circuit board. 図１に示す従来の接合方法による半導体ベアチップの反り発生を示す図The figure which shows the curvature generation | occurrence | production of the semiconductor bare chip by the conventional joining method shown in FIG. 本発明の実施の形態１における半導体装置の製造工程の概略図であり（ａ）は回路基板の反りを矯正する状態を示す図（ｂ）は回路基板の反りを矯正しながら本圧着する状態を示す図BRIEF DESCRIPTION OF THE DRAWINGS It is the schematic of the manufacturing process of the semiconductor device in Embodiment 1 of this invention, (a) is a figure which shows the state which corrects the curvature of a circuit board, (b) is the state which carries out this pressure bonding, correcting the curvature of a circuit board. Illustration 本発明の実施の形態２における半導体装置の製造工程の概略図であり（ａ）はプレートによって回路基板の反りを矯正する状態を示す図（ｂ）は回路基板の反りを矯正しながら本圧着する状態を示す図It is the schematic of the manufacturing process of the semiconductor device in Embodiment 2 of this invention, (a) is a figure which shows the state which corrects the curvature of a circuit board with a plate, (b) is this crimping | bonding, correcting the curvature of a circuit board. Diagram showing the state 本発明の実施の形態３における半導体装置の構成を示す概略図であり（ａ）は、基板矯正ツールと基板矯正ガイドまたはプレートにより回路基板の反りを矯正して実装された半導体装置の概略図（ｂ）は基板矯正ツールと基板矯正ガイドにより、回路基板の反りを矯正しながら本圧着する状態を示す図（ｃ）はプレートにより回路基板の反りを矯正しながら本圧着する状態を示す図FIG. 7A is a schematic diagram illustrating a configuration of a semiconductor device according to a third embodiment of the present invention. FIG. 5A is a schematic diagram of a semiconductor device mounted by correcting a warp of a circuit board using a substrate correction tool and a substrate correction guide or plate ( FIG. 5B is a diagram showing a state where the main press-bonding is performed while correcting the warp of the circuit board by the substrate correction tool and the substrate correction guide. FIG. 本発明の実施の形態４における半導体装置の実装装置の概略図Schematic of a semiconductor device mounting apparatus according to a fourth embodiment of the present invention. 本発明の実施の形態５における半導体装置の製造装置の概略図Schematic of a semiconductor device manufacturing apparatus according to Embodiment 5 of the present invention. 本発明の実施の形態６における半導体装置の実装工程の概略図であり（ａ）は、基板矯正ツールと基板矯正ガイドにより回路基板の反りを矯正して実装する状態を示す図（ｂ）は回路基板の反りを矯正して本圧着される半導体装置の概略図FIG. 10A is a schematic diagram of a semiconductor device mounting process according to a sixth embodiment of the present invention. FIG. 7A is a circuit diagram illustrating a state in which a circuit board is warped and mounted using a board correction tool and a board correction guide. Schematic diagram of a semiconductor device that is permanently crimped by correcting substrate warpage 本発明の実施の形態７における半導体装置の実装工程の概略図であり（ａ）はプレートにより回路基板の反りを矯正して実装する状態を示す図（ｂ）はプレートにより回路基板の反りを矯正して実装された半導体装置の概略図It is the schematic of the mounting process of the semiconductor device in Embodiment 7 of this invention, (a) is a figure which shows the state which correct | amends the curvature of a circuit board with a plate, and (b) corrects the curvature of a circuit board with a plate. Schematic diagram of the semiconductor device mounted 本発明の実施の形態８における半導体装置の概略図であり（ａ）は基板矯正ツールと基板矯正ガイドまたはプレートにより回路基板の反りを矯正して実装された半導体装置の概略図（ｂ）は基板矯正ツールと基板矯正ガイドにより、回路基板の反りを矯正しながら本圧着する実装装置の概略図（ｃ）はプレートにより回路基板の反りを矯正しながら本圧着する実装装置の概略図（ｄ）は基板矯正ツールと基板矯正ガイドまたはプレートにより回路基板の反りを矯正して実装される半導体装置の本圧着時の状態を示す概略図FIG. 9A is a schematic diagram of a semiconductor device according to an eighth embodiment of the present invention. FIG. 9A is a schematic diagram of a semiconductor device mounted by correcting a warp of a circuit board using a substrate correction tool and a substrate correction guide or plate. A schematic diagram (c) of a mounting apparatus that performs final press-bonding while correcting the warping of the circuit board by using a correction tool and a board correction guide. Schematic diagram showing the state of the semiconductor device that is mounted by correcting the warping of the circuit board with the substrate correction tool and substrate correction guide or plate at the time of final compression bonding 本発明の実施の形態９における半導体装置の製造装置の概略図であり（ａ）は基板矯正ツールと基板矯正ガイドにより、回路基板の反りを矯正して実装する実装装置の概略図（ｂ）は本図（ａ）における本圧着の状態を示す図FIG. 16A is a schematic diagram of a semiconductor device manufacturing apparatus according to a ninth embodiment of the present invention. FIG. 10A is a schematic diagram of a mounting apparatus that corrects and warps a circuit board using a board correction tool and a board correction guide. The figure which shows the state of this crimping in this figure (a) 本発明の実施の形態１０における半導体装置の製造装置の概略図であり（ａ）はプレートにより回路基板の反りを矯正して実装する実装装置の概略図（ｂ）は本図（ａ）に示す実装装置による半導体装置の本圧着の状態を示す図It is the schematic of the manufacturing apparatus of the semiconductor device in Embodiment 10 of this invention, (a) is the schematic diagram (b) of the mounting apparatus which correct | amends the curvature of a circuit board with a plate, and shows this figure (a). The figure which shows the state of this crimping of the semiconductor device with the mounting equipment 本発明の実施の形態１１における半導体装置の製造工程の概略図であり（ａ）は回路基板の片面に実装された複数個の半導体ベアチップを同時に本圧着する状態を示す図（ｂ）は同一ウエハ内の複数個の半導体ベアチップを示す図It is the schematic of the manufacturing process of the semiconductor device in Embodiment 11 of this invention, (a) is the figure which shows the state which carries out this press-bonding of the several semiconductor bare chip mounted on the single side | surface of a circuit board simultaneously (b) is the same wafer Diagram showing multiple semiconductor bare chips 本発明の実施の形態１２における４チップ以上の半導体ベアチップを回路基板に実装する半導体装置の製造工程の概略図であり（ａ）は回路基板の両面に実装された複数個の半導体ベアチップを同時に本圧着する状態を示す図（ｂ）は同一ウエハ内の複数個の半導体ベアチップを示す図It is the schematic of the manufacturing process of the semiconductor device which mounts the semiconductor bare chip | tip of 4 chips or more in Embodiment 12 of this invention on a circuit board, (a) is a plurality of semiconductor bare chips mounted on both surfaces of a circuit board simultaneously. The figure which shows the state which crimps | bonds is a figure which shows the several semiconductor bare chip in the same wafer. 本発明の実施の形態１３における半導体装置の概略図であり（ａ）は回路基板の両面に半導体ベアチップが実装された半導体装置を示す図（ｂ）は本図（ａ）に示す半導体装置において回路基板の内部でスルーホールによりデータラインが共通化されている半導体装置を示す図It is the schematic of the semiconductor device in Embodiment 13 of this invention, (a) is a figure which shows the semiconductor device by which the semiconductor bare chip was mounted on both surfaces of the circuit board, (b) is a circuit in the semiconductor device shown to this figure (a) The figure which shows the semiconductor device where the data line is made common by the through hole inside the substrate 本発明の実施の形態１４における半導体ベアチップの実装工法の概略図であり（ａ）は回路基板の両面に半導体ベアチップを実装する状態を示す図（ｂ）は回路基板の両面にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板の両面に半導体ベアチップをマウントする状態を示す図（ｄ）は断熱性の高いガラスもしくは石英ステージを用いて両面同時に本圧着する状態を示す概略図It is the schematic of the mounting method of the semiconductor bare chip in Embodiment 14 of this invention, (a) is a figure which shows the state which mounts a semiconductor bare chip on both surfaces of a circuit board, (b) affixes sheet resin on both surfaces of a circuit board Figure (c) showing the state shows a state where the semiconductor bare chip is mounted on both sides of the circuit board. 本発明の実施の形態１５における半導体ベアチップの実装工法の概略図であり（ａ）は回路基板の両面に半導体ベアチップを実装する状態を示す図（ｂ）は回路基板の両面にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板の両面に半導体ベアチップをマウントする状態を示す図（ｄ）は加熱可能なステージを用いて両面同時に本圧着する状態を示す図It is the schematic of the mounting method of the semiconductor bare chip in Embodiment 15 of this invention, (a) is a figure which shows the state which mounts a semiconductor bare chip on both surfaces of a circuit board, (b) affixes sheet resin on both surfaces of a circuit board Figure (c) showing the state shows a state where the semiconductor bare chip is mounted on both sides of the circuit board. (D) shows a state where the main pressing is performed simultaneously on both sides using a heatable stage. 本発明の実施の形態１６における半導体ベアチップの実装工法の概略図であり（ａ）は回路基板の両面に半導体ベアチップを実装する状態を示す図（ｂ）は回路基板の両面にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板の両面に半導体ベアチップをマウントする状態を示す図（ｄ）はセラミックスヒータまたはパルスヒータで加熱可能なステージを用いて両面同時に本圧着する状態を示す概略図It is the schematic of the mounting method of the semiconductor bare chip in Embodiment 16 of this invention, (a) is a figure which shows the state which mounts a semiconductor bare chip on both surfaces of a circuit board, (b) affixes sheet resin on both surfaces of a circuit board (C) is a diagram showing a state where semiconductor bare chips are mounted on both sides of a circuit board. (D) is a schematic diagram showing a state where main pressing is simultaneously performed on both sides using a stage that can be heated by a ceramic heater or a pulse heater. 本発明の実施の形態１７における半導体ベアチップの実装工法の概略図であり（ａ）は回路基板の両面に半導体ベアチップを実装する状態を示す図（ｂ）は回路基板の両面にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板の両面に半導体ベアチップをマウントする状態を示す図（ｄ）はセラミックスヒータまたはパルスヒータで加熱可能なステージとセラミックスヒータまたはパルスヒータで加熱可能な圧着ツールを用いて両面同時に本圧着する状態を示す概略図It is the schematic of the mounting method of the semiconductor bare chip in Embodiment 17 of this invention, (a) is a figure which shows the state which mounts a semiconductor bare chip on both surfaces of a circuit board, (b) affixes sheet resin on both surfaces of a circuit board Figure (c) shows a state where semiconductor bare chips are mounted on both sides of a circuit board. (D) shows a stage that can be heated by a ceramic heater or a pulse heater and a crimping tool that can be heated by a ceramic heater or a pulse heater. Schematic showing the state where both sides are fully crimped simultaneously 本発明の実施の形態１８における半導体ベアチップの実装工法の概略図であり（ａ）は回路基板の両面に半導体ベアチップを実装する状態を示す図（ｂ）は回路基板の両面にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板の両面に半導体ベアチップをマウントする状態を示す図（ｄ）はコンスタントヒータで加熱可能なステージとコンスタントヒータで加熱可能な圧着ツールを用いて両面同時に本圧着する状態を示す図It is the schematic of the mounting method of the semiconductor bare chip in Embodiment 18 of this invention, (a) is a figure which shows the state which mounts a semiconductor bare chip on both surfaces of a circuit board, (b) affixes sheet resin on both surfaces of a circuit board Figure (c) showing the state shows a state where the semiconductor bare chip is mounted on both sides of the circuit board. Figure (d) shows a state where both sides of the circuit board are subjected to final pressure bonding simultaneously using a stage that can be heated by a constant heater and a pressure tool that can be heated by a constant heater. Diagram showing the state 本発明の実施の形態１９における半導体ベアチップの実装工法の概略図であり（ａ）は回路基板の両面に半導体ベアチップを実装する状態を示す図（ｂ）は回路基板の両面にシート樹脂を貼り付ける状態を示す図（ｃ）は回路基板の両面に半導体ベアチップをマウントする状態を示す図（ｄ）は両面から加熱可能な圧着ツールを用いて両面同時に本圧着する状態を示す図It is the schematic of the mounting method of the semiconductor bare chip in Embodiment 19 of this invention, (a) is a figure which shows the state which mounts a semiconductor bare chip on both surfaces of a circuit board, (b) affixes sheet resin on both surfaces of a circuit board (C) is a diagram showing a state in which a semiconductor bare chip is mounted on both sides of a circuit board. (D) is a diagram showing a state in which main pressing is simultaneously performed on both sides using a crimping tool that can be heated from both sides.

符号の説明Explanation of symbols

１、１７、１８、２０、２１、２２、２３、２６、２７、３３、３４ 半導体ベアチップ
２ パッド
３ バンプ
５、２５、２９ 回路基板
６、３０ 封止シート
７、３１ 貼り付けツール
８、３２ 基板電極
９、３６ 実装ヘッド
１０、３７、４１、４３、４４ 圧着ツール
１１ シリンダ
１２ 基板矯正ツール
１３ 基板矯正ガイド
１４ 半導体ベアチップ押圧ツール
１５、１６ プレート
３５ バンプ電極
３８、３９、４０、４２ ステージ 1, 17, 18, 20, 21, 22, 23, 26, 27, 33, 34 Semiconductor bare chip 2 Pad 3 Bump 5, 25, 29 Circuit board 6, 30 Sealing sheet 7, 31 Pasting tool 8, 32 Substrate Electrode 9, 36 Mounting head 10, 37, 41, 43, 44 Crimping tool 11 Cylinder 12 Substrate correction tool 13 Substrate correction guide 14 Semiconductor bare chip pressing tool 15, 16 Plate 35 Bump electrode 38, 39, 40, 42 Stage

Claims (19)

第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップを実装するに際し、前記回路基板の他方の面の前記第２の半導体ベアチップ周辺の前記回路基板を、前記第２の半導体ベアチップを押圧するツールとは別のツールを用いて少なくとも１箇所以上押圧しながら、前記第２の半導体ベアチップを前記回路基板に搭載する工程、もしくは搭載された前記第２の半導体ベアチップと前記回路基板の間に介在する熱硬化性樹脂を熱により硬化する工程を有することを特徴とする半導体装置の実装方法。 When mounting the second semiconductor bare chip at a position facing the first semiconductor bare chip on the other side of the circuit board on which the first semiconductor bare chip is mounted, the other side of the circuit board is The second semiconductor bare chip is mounted on the circuit board while pressing the circuit board around the second semiconductor bare chip using at least one place using a tool different from the tool for pressing the second semiconductor bare chip. Or a step of curing the thermosetting resin interposed between the mounted second semiconductor bare chip and the circuit board by heat. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップを実装するに際し、前記回路基板の両面をプレートにて挟み込む工程と、前記第２の半導体ベアチップを前記回路基板に搭載する工程もしくは搭載された前記第２の半導体ベアチップと前記回路基板の間に介在する熱硬化性樹脂を熱により硬化する工程とを有することを特徴とする半導体装置の実装方法。 When mounting the second semiconductor bare chip at a position facing the first semiconductor bare chip on the other side of the circuit board on which the first semiconductor bare chip is mounted, both surfaces of the circuit board are plated A step of sandwiching, and a step of mounting the second semiconductor bare chip on the circuit board, or a step of curing the thermosetting resin interposed between the mounted second semiconductor bare chip and the circuit board by heat. A method for mounting a semiconductor device. 請求項１または２いずれかに記載の半導体装置の実装方法により、回路基板の両面にそれぞれ第１および第２の半導体ベアチップが実装された半導体装置。 3. A semiconductor device in which the first and second semiconductor bare chips are mounted on both sides of the circuit board by the semiconductor device mounting method according to claim 1. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に実装される第２の半導体ベアチップを押圧する第１のツールと、前記第２の半導体ベアチップ周辺の前記回路基板を少なくとも１箇所以上押圧する第２のツールと、前記第２の半導体ベアチップを前記回路基板に搭載する手段、もしくは搭載された前記第２の半導体ベアチップと前記回路基板の間に介在する熱硬化性樹脂を熱により硬化する手段とを有することを特徴とする半導体装置の実装装置。 A first tool for pressing a second semiconductor bare chip mounted at a position facing the first semiconductor bare chip on the other surface of the circuit board on which the first semiconductor bare chip is mounted; A second tool that presses at least one circuit board around the semiconductor bare chip of 2; means for mounting the second semiconductor bare chip on the circuit board; or the mounted second semiconductor bare chip and the circuit And a means for curing the thermosetting resin interposed between the substrates by heat. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップが実装される前記回路基板の両面を挟み込むプレートと、前記第２の半導体ベアチップを前記回路基板に搭載する手段もしくは搭載された前記第２の半導体ベアチップと前記回路基板の間に介在する熱硬化性樹脂を熱により硬化する手段とを有することを特徴とする半導体装置の実装装置。 A plate for sandwiching both surfaces of the circuit board on which the second semiconductor bare chip is mounted at a position facing the first semiconductor bare chip on the other surface of the circuit board on which the first semiconductor bare chip is mounted; Means for mounting the second semiconductor bare chip on the circuit board, or means for curing the thermosetting resin interposed between the mounted second semiconductor bare chip and the circuit board by heat. A semiconductor device mounting apparatus. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップを実装するに際し、前記回路基板の他方の面の前記第２の半導体ベアチップ周辺の前記回路基板を、前記第２の半導体ベアチップを押圧するツールとは別のツールを用いて少なくとも１箇所以上押圧しながら、前記第２の半導体ベアチップを押圧し前記第２の半導体ベアチップに形成された突起電極バンプを前記回路基板上に形成された電極上で変形させ、同時に前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる工程を有することを特徴とする半導体装置の実装方法。 When mounting the second semiconductor bare chip on the other surface of the circuit board on which the first semiconductor bare chip is mounted at a position facing the first semiconductor bare chip, the other surface of the circuit board is The second semiconductor bare chip is pressed by pressing the second semiconductor bare chip while pressing the circuit board around the second semiconductor bare chip using at least one place using a tool different from the tool for pressing the second semiconductor bare chip. A step of deforming bump electrode bumps formed on the semiconductor bare chip on the electrode formed on the circuit board and simultaneously curing the thermosetting resin interposed between the circuit board and the circuit board by heat. A method for mounting a semiconductor device. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップを実装するに際し、前記回路基板の両面をプレートにて挟み込む工程と、前記第２の半導体ベアチップを押圧し前記第２の半導体ベアチップに形成された突起電極バンプを前記回路基板上に形成された電極上で変形させ、同時に前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる工程を有することを特徴とする半導体装置の実装方法。 When mounting the second semiconductor bare chip at a position facing the first semiconductor bare chip on the other side of the circuit board on which the first semiconductor bare chip is mounted, both surfaces of the circuit board are plated A step of sandwiching and projecting electrode bumps formed on the second semiconductor bare chip by pressing the second semiconductor bare chip and deforming on the electrodes formed on the circuit board, and intervening between the circuit board at the same time A method for mounting a semiconductor device, comprising: a step of curing a thermosetting resin to be heated. 請求項６または７いずれかに記載の半導体装置の実装方法により、回路基板に半導体ベアチップが実装された半導体装置。 A semiconductor device in which a semiconductor bare chip is mounted on a circuit board by the method for mounting a semiconductor device according to claim 6. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に実装される第２の半導体ベアチップを押圧し、前記第２の半導体ベアチップに形成された突起電極バンプを前記回路基板上に形成された電極上で変形させる第１のツールと、前記第２の半導体ベアチップ周辺の前記回路基板を少なくとも１箇所以上押圧する第２のツールと、前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる手段とを有することを特徴とする半導体装置の実装装置。 A second semiconductor bare chip mounted on a surface opposite to the first semiconductor bare chip on one side of the circuit board on which the first semiconductor bare chip is mounted is pressed to the second semiconductor bare chip. A first tool for deforming the formed bump electrode bump on the electrode formed on the circuit board; a second tool for pressing at least one place on the circuit board around the second semiconductor bare chip; A mounting device for a semiconductor device, comprising: means for curing a thermosetting resin interposed between the circuit board and the circuit board by heat. 第１の半導体ベアチップが実装された回路基板の一方の面に対する他方の面の前記第１の半導体ベアチップと対向する位置に第２の半導体ベアチップが実装される前記回路基板の両面を挟み込むプレートと、前記第２の半導体ベアチップに形成された突起電極バンプを前記回路基板上に形成された電極上で変形させるのツールと、前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる手段とを有することを特徴とする半導体装置の実装装置。 A plate for sandwiching both surfaces of the circuit board on which the second semiconductor bare chip is mounted at a position facing the first semiconductor bare chip on the other surface of the circuit board on which the first semiconductor bare chip is mounted; A tool for deforming the protruding electrode bump formed on the second semiconductor bare chip on the electrode formed on the circuit board and a thermosetting resin interposed between the circuit board by heat A mounting device for a semiconductor device, comprising: 回路基板の片面に搭載された複数個の半導体ベアチップを同時に押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させ、同時に前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる工程を有し、前記複数個の半導体ベアチップの厚みバラツキが±１０μｍ以内に管理されていることを特徴とする半導体装置の実装方法。 Simultaneously pressing a plurality of semiconductor bare chips mounted on one side of a circuit board to deform projecting electrode bumps formed on the semiconductor bare chip on the electrodes formed on the circuit board and simultaneously interposing between the circuit boards A method of mounting a semiconductor device, comprising: a step of curing the thermosetting resin by heat, wherein a thickness variation of the plurality of semiconductor bare chips is controlled within ± 10 μm. 回路基板の一方の面に複数個の半導体ベアチップを搭載しかつ前記回路基板の他方の面に半導体ベアチップを搭載し、前記回路基板両面の半導体ベアチップを同時に押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させ、同時に前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる工程を有し、前記回路基板に実装される複数個の前記半導体ベアチップの厚みバラツキが前記回路基板の片面ごとに±１０μｍ以内に管理されていることを特徴とする半導体装置の実装方法。 A plurality of semiconductor bare chips mounted on one side of the circuit board and a semiconductor bare chip mounted on the other side of the circuit board, and the semiconductor bare chips on both sides of the circuit board are pressed simultaneously to form protruding electrodes formed on the semiconductor bare chip A step of deforming the bumps on the electrodes formed on the circuit board and simultaneously curing the thermosetting resin interposed between the circuit boards by heat, and a plurality of the mountings mounted on the circuit board A method for mounting a semiconductor device, characterized in that the thickness variation of the semiconductor bare chip is controlled within ± 10 μm for each side of the circuit board. 回路基板の両面にメモリ用途の半導体ベアチップを押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させ、同時に前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させて構成された前記メモリ用半導体ベアチップのデータライン部のパッドレイアウトを前記回路基板の両面で面対称にすることにより、前記回路基板の両面に搭載された前記メモリ用半導体ベアチップのデータラインを前記回路基板内で共通化していることを特徴とする半導体装置。 A thermosetting that presses a semiconductor bare chip for memory use on both sides of a circuit board and deforms bump electrode bumps formed on the semiconductor bare chip on the electrodes formed on the circuit board, and intervenes between the circuit boards at the same time. The memory semiconductor bare chip mounted on both sides of the circuit board by making the pad layout of the data line portion of the memory semiconductor bare chip configured by curing resin by heat symmetrical on both sides of the circuit board The data line is shared in the circuit board. 両面に半導体ベアチップが実装される回路基板に搭載された前記半導体ベアチップを押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させるツールと、前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる手段と、前記回路基板の両面を同時に加熱加圧するための加熱ヒータを備えた加熱ツールと、断熱性のガラスもしくは石英からなるステージとを有することを特徴とする半導体装置の実装装置。 A tool that presses the semiconductor bare chip mounted on a circuit board on which both sides of the semiconductor bare chip are mounted and deforms protruding electrode bumps formed on the semiconductor bare chip on the electrodes formed on the circuit board; and Means for curing the thermosetting resin interposed therebetween by heat, a heating tool having a heater for heating and pressurizing both surfaces of the circuit board simultaneously, and a stage made of heat insulating glass or quartz. A semiconductor device mounting apparatus. 両面に半導体ベアチップが実装される回路基板に搭載された前記半導体ベアチップを押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させるツールと、前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる手段と、前記回路基板の両面を同時に加熱加圧するための加熱ヒータを備えた加熱ツールと、加熱ヒータを備えたステージとを有することを特徴とする半導体装置の実装装置。 A tool that presses the semiconductor bare chip mounted on a circuit board on which both sides of the semiconductor bare chip are mounted and deforms protruding electrode bumps formed on the semiconductor bare chip on the electrodes formed on the circuit board; and And a heating tool including a heater for heating and pressurizing both sides of the circuit board simultaneously, and a stage including the heater. A semiconductor device mounting apparatus. ステージに備えた加熱ヒータがセラミックスヒータまたはパルスヒータであることを特徴とする請求項１５記載の半導体装置の実装装置。 16. The semiconductor device mounting apparatus according to claim 15, wherein the heater provided in the stage is a ceramic heater or a pulse heater. ステージに備えた加熱ヒータがセラミックスヒータまたはパルスヒータであることを特徴とする請求項１６記載の半導体装置の実装装置。 17. The semiconductor device mounting apparatus according to claim 16, wherein the heater provided in the stage is a ceramic heater or a pulse heater. 回路基板の両面を同時に加熱加圧するための加熱ツールに備えた加熱ヒータと、ステージに備えた加熱ヒータが共にコンスタントヒータであることを特徴とする請求項１５記載の半導体装置の実装装置。 16. The apparatus for mounting a semiconductor device according to claim 15, wherein the heater provided in the heating tool for simultaneously heating and pressurizing both surfaces of the circuit board and the heater provided in the stage are both constant heaters. 両面に半導体ベアチップが実装される回路基板に搭載された前記半導体ベアチップを押圧し前記半導体ベアチップに形成された突起電極バンプを前記回路基板に形成された電極上で変形させるツールと、前記回路基板との間に介在する熱硬化性樹脂を熱により硬化させる手段と、前記回路基板の両面を同時に加熱加圧するための加熱ヒータを備えた二つの加熱ツールとを有することを特徴とする半導体装置の実装装置。 A tool that presses the semiconductor bare chip mounted on a circuit board on which both sides of the semiconductor bare chip are mounted and deforms protruding electrode bumps formed on the semiconductor bare chip on the electrodes formed on the circuit board; and Mounting a semiconductor device, comprising: a means for curing a thermosetting resin interposed between the two by heating; and two heating tools provided with a heater for simultaneously heating and pressurizing both surfaces of the circuit board. apparatus.
JP2005043701A 2005-02-21 2005-02-21 Semiconductor device mounting method, mounting device, and semiconductor device Pending JP2006229106A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012033885A (en) * 2010-06-28 2012-02-16 Murata Mfg Co Ltd Electronic component module manufacturing method
WO2012147458A1 (en) * 2011-04-27 2012-11-01 ソニーケミカル＆インフォメーションデバイス株式会社 Method for fabricating connection structure

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2012033885A (en) * 2010-06-28 2012-02-16 Murata Mfg Co Ltd Electronic component module manufacturing method
WO2012147458A1 (en) * 2011-04-27 2012-11-01 ソニーケミカル＆インフォメーションデバイス株式会社 Method for fabricating connection structure
JP2012231039A (en) * 2011-04-27 2012-11-22 Sony Chemical & Information Device Corp Manufacturing method of connection structure
TWI494038B (en) * 2011-04-27 2015-07-21 Dexerials Corp Method of manufacturing a connecting structure
US9318353B2 (en) 2011-04-27 2016-04-19 Dexerials Corporation Method of manufacturing connection structure

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