JP2006185483A - Nonvolatile storage apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce a target fraction defective for protrusion from a threshold voltage distribution by shortening a processing time in which a threshold voltage of a nonvolatile memory cell is transited. <P>SOLUTION: A nonvolatile storage apparatus has a memory array and a control circuit, the memory array has a plurality of memory transistors of which the threshold voltages can be changed electrically, the control circuit makes one memory transistor be able to store a logic value of a quaternary or more by the change of the threshold voltage. In the control circuit, when the threshold voltage of the memory transistor is changed from an initial distribution to a target threshold voltage distribution, the threshold voltage is transited from the initial distribution side to the target threshold voltage distribution in terms of a successive threshold voltage distribution unit for all memory transistors to be changed, when the threshold voltage is transited, the product of a pulse width and a voltage level of a write-in voltage applied to a word line of the memory transistor is controlled so as to become maximum in initial pulse application. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a so-called non-volatile storage device capable of storing multiple bits of information in a single memory cell, and relates to a technique effective when applied to, for example, a flash memory.

  The threshold voltage of the non-volatile memory cell before the flash memory changes according to the amount of charge stored in the charge storage region. The threshold voltage of the memory cell is limited to a desired range according to the value of the stored data, and the threshold voltage distribution is called a memory threshold voltage distribution. For example, when one non-volatile memory cell stores 2-bit information, the memory threshold voltage distribution is determined corresponding to the data of 01, 00, 10, 11 respectively. In order to obtain the memory threshold voltage distribution, the write verify voltage applied to the word line during the write operation after erasure is set to three different voltages, and these three types of voltages are sequentially switched three times. The write operation is performed separately. In each of these three write operations, 0 V is applied to the write-selected bit line and 1 V is applied to the non-selected bit line. Although not particularly limited, the voltage applied to the word line is, for example, 17V. As the write high voltage application time is increased, the threshold voltage of the memory cell is increased. The threshold voltage control for writing can be performed by time control in such a high voltage state and further by level control of a high voltage applied to the word line. Patent Document 1 and Patent Document 2 describe a flash memory capable of storing the above four values.

Special table 1996-024138 Special table 2003-73433 gazette

  In the nonvolatile memory that performs multi-level storage, the memory threshold voltage distribution needs to be narrowed in order to ensure reliability. For this reason, the number of times of write verification is increased compared with the binary technology nonvolatile memory, and the write time is increased. Tend to be longer. The present inventor has studied the reduction of the writing time of a flash memory that performs multi-level storage. It is known that the write characteristics of a nonvolatile memory cell to which a write voltage is applied are linear with respect to the logarithm of the cumulative write voltage application time. Therefore, if the write pulse length is constant, the increase amount of the memory threshold voltage every time the write pulse is applied gradually decreases, and the number of write verify times increases. Therefore, in order to make the increase amount of the memory threshold voltage constant and optimize the number of times of write verification, the write bias application time may be extended to the power of the cumulative bias application time for each write pulse. However, in this power pulse method, the number of verifications can be optimized, but the pulse length increases for each write pulse, and therefore the write bias application time increases exponentially. In contrast, there is an ISPP (Incremental Step Pulse Programming) method in which the pulse length is constant for each write pulse. In ISPP, the write bias voltage is increased for each pulse to keep the write pulse length constant. This ideally increases the memory threshold voltage with each pulse application, so that the number of verifications can be optimized in the same way as the power pulse method, and the write time can be shortened.

  However, when the fluctuation amount of the memory threshold voltage for each actual write verification when ISPP is performed is examined, it is found that the higher the word line voltage, the larger the fluctuation amount of the memory threshold voltage in a region where the number of verifications is small. It was done. For this reason, it has been clarified that the write variation becomes large at the initial stage of the write operation, and the write jump defect is likely to occur. The write-out failure is that the threshold voltage of the memory cell falls into a distribution one higher than the target threshold voltage distribution. However, it has been clarified that when the voltage is lowered on the word line as a countermeasure, the number of memory cells that pass the write verify decreases, and there is a problem that the useless write bias application and the number of write verify increase.

  The object of the present invention is to reduce the processing time for transitioning the threshold voltage of a nonvolatile memory cell and to reduce the pop-out defect rate from the target threshold voltage distribution.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  The following is a brief description of an outline of typical inventions disclosed in the present application.

  [1] The nonvolatile memory device (1) includes a memory array (FARY1 to FARY3) and a control circuit (CNT), and the memory array includes a plurality of memory transistors whose threshold voltages can be electrically changed. And the control circuit can store four or more logical values in one memory cell transistor by changing a threshold voltage. Further, when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the control circuit changes the threshold voltage distribution from the initial distribution side to the target threshold voltage distribution for all the memory cell transistors to be changed. The threshold voltage is sequentially changed in units of threshold voltage distribution until the threshold voltage is changed, and the product of the pulse width of the write voltage applied to the word line of the memory cell transistor and the voltage level is maximized by the first pulse application. To control. In a specific mode, in short, (A) writing is performed step by step while synthesizing write data from the low voltage side, and (B) only the first write bias application is written roughly. This case also has a common point in that the memory threshold voltage of the write source is brought close to the write destination.

  According to the above means, when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the target threshold voltage distribution from the initial distribution side to all the memory cell transistors to be changed The threshold voltage is sequentially shifted in units of threshold voltage distribution until the threshold voltage is increased. As represented by the above (A), the threshold voltage is raised step by step while synthesizing the write data from the low voltage side. It is to go. As a result, when the threshold voltage is shifted in units of threshold voltage distribution, the threshold voltage of the transition source and the transition destination are close to each other, so that the threshold voltage can be transitioned in a variation region smaller than the original write characteristic variation of the memory cell. . In short, the variation in write characteristics between memory cells with fast write characteristics and memory cells with slow write characteristics becomes larger as the cumulative application time of the write voltage becomes longer. The characteristic variation is reduced, and the number of write verifications can be suppressed. In particular, it is possible to suppress the number of write verifications of the “01” distribution and the “00” distribution that are separated from the erase distribution toward the high voltage side. For example, the number of times of each verification can be reduced by 2 to 3 times. The write processing time is reduced by about 10%.

  Further, in the above-described means, the threshold voltage is controlled so that the product of the pulse width and the voltage level of the write voltage applied to the word line of the memory cell transistor is maximized by the first pulse application. As represented by (B) above, only the first write bias application is written roughly. By roughly writing only the first write pulse in this way, the amount of change in the memory threshold voltage for each application of the second and subsequent write pulses can be reduced, thereby making it possible to suppress write popping defects. The word voltage can be set higher, which can contribute to shortening the write processing time. In short, the potential difference between the substrate and the charge storage region remains relatively large when the number of electrons stored in the charge storage region of the nonvolatile memory cell at the time after the application of the write pulse is relatively small. Electrons are likely to pass through the tunnel film. It can be understood that the memory cell in this state has the same characteristics as a memory cell having a slow write characteristic. Conversely, in a state where there are many electrons stored in the charge storage region of the nonvolatile memory cell, the potential difference between the substrate and the charge storage region is relatively small, and it is difficult for electrons to pass through the tunnel film. It can be understood that the memory cell in the state is the same as the characteristic of the memory cell having fast write characteristics. Therefore, compared to the latter, the former is more likely to cause a pop-out defect due to the application of the next write pulse. Therefore, the memory threshold voltage is brought as close as possible to the writing destination by applying the first writing pulse voltage (that is, applying the initial pulse voltage) (in other words, the memory threshold potential difference between the writing source and the writing destination after the initial pulse voltage is applied is reduced). By doing so, it is possible to contribute to a reduction in the write-out failure rate and, in turn, a reduction in the write processing time.

  As one specific form of the present invention, the control circuit may change a write voltage pulse applied to the word line of the memory cell transistor when the threshold voltage of the memory cell transistor is changed from an initial distribution to a target threshold voltage distribution. The voltage level is sequentially increased, the pulse width is made constant except for the first pulse, and the first pulse width is made larger than the subsequent pulse width. The application form of the voltage pulse is basically ISPP in consideration of shortening of the write processing time.

  As another specific form of the present invention, when the control circuit changes the threshold voltage of the memory cell transistor from the initial distribution to the target threshold voltage distribution, the write voltage applied to the word line of the memory cell transistor The voltage level of the pulse is sequentially increased except for the first pulse, the pulse width is made constant except for the first pulse, and the first pulse width is made larger than the subsequent pulse width. The application form of the voltage pulse is basically based on ISPP.

  As yet another specific form of the present invention, the control circuit writes data to be applied to a word line of the memory cell transistor when the threshold voltage of the memory cell transistor is changed from an initial distribution to a target threshold voltage distribution. The voltage level of the voltage pulse is sequentially increased, and the pulse width in units of threshold voltage is sequentially decreased from the first pulse. The application form of the voltage pulse is basically based on ISPP.

  [2] The nonvolatile memory device includes a memory array and a control circuit, the memory array includes a plurality of memory cell transistors whose threshold voltage can be electrically changed, and the control circuit includes the threshold voltage This makes it possible to store four or more logical values in one memory cell transistor. Further, when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the control circuit sequentially shifts all the memory cell transistors to be changed to the target threshold voltage distribution. At the same time, the threshold voltage is controlled so that the product of the pulse width and the voltage level of the write voltage applied to the memory cell transistor is maximized by the first pulse application.

  As one specific form of the present invention, the control circuit sequentially increases the voltage level of the write voltage pulse applied to the memory cell transistor when transitioning the threshold voltage, and the pulse width is excluded from the first pulse. The first pulse width is made larger than the subsequent pulse width.

  As another specific form of the present invention, the control circuit sequentially increases the voltage level of the write voltage pulse applied to the memory cell transistor when transitioning the threshold voltage except for the first pulse, The width is constant except for the first pulse, and the first pulse width is made larger than the subsequent pulse width.

  As yet another specific form of the present invention, the control circuit sequentially increases the voltage level of the write voltage pulse applied to the memory cell transistor when transitioning the threshold voltage, and the pulse width of the threshold voltage unit. Are sequentially reduced from the first pulse.

  The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.

  That is, it is possible to shorten the processing time for transitioning the threshold voltage of the nonvolatile memory cell and reduce the pop-out defect rate from the target threshold voltage distribution.

<Flash memory>
FIG. 1 shows a planar layout configuration of a flash memory which is an example of a semiconductor memory device according to the present invention. The flash memory 1 shown in the figure is not particularly limited, but is formed on a single semiconductor substrate (chip) such as single crystal silicon by a known MOS integrated circuit manufacturing method.

  The flash memory 1 includes, for example, four memory banks BNK0 to BNK3 and a control unit CNT. The memory banks BNK0 to BNK3 have flash memory arrays FARY0 to FARY3 as nonvolatile memory units and buffer memories BMRY0 to BMRY3 as buffer units. Corresponding to one flash memory array, the buffer memory is divided into two parts on the left and right. For convenience, the right buffer memory is given a suffix (R), and the left buffer memory is given a suffix (L).

  The external input / output terminals i / o0 to i / o7 of the flash memory 1 are also used as an address input terminal, a data input terminal, a data output terminal, and a command input terminal. The flash memory 1 receives a command latch enable signal CLE, an address latch enable signal ALE, a chip enable signal CEb, a read enable signal REb, and a write enable signal WEb as external control signals such as a strobe signal, and a ready / busy signal R / Bb. Output. The chip enable signal CEb indicates a chip selection state in the flash memory 1, the read enable signal REb instructs a read operation from the external input / output terminals i / o0 to i / o7, and the write enable signal WEb is an external input / output terminal i. The write operation from / o0 to i / o7 is instructed. The command latch enable signal CLE means that a command is supplied from the outside to the external input / output terminals i / o0 to i / o7, and the address latch enable signal ALE is supplied from the outside to the external input / output terminals i / o0 to i / o7. This means that an address signal is supplied. The ready / busy signal R / Bb indicates, by a low level (L), that any of the flash memory arrays FARY0 to FARY3 is being erased, written, or read (busy state). The busy state or ready state for each flash memory array (FARY0 to FARY3) can be recognized from the outside by reading status information described later.

  The control unit CNT controls a signal interface function with the outside according to the state of the strobe signal, and controls an internal operation according to an input command.

  Each of the flash memory arrays FARY0 to FARY3 has a large number of nonvolatile memory cells arranged in a matrix. Although this non-volatile memory cell is not particularly limited, one memory cell is constituted by one known floating gate type transistor. For example, a nonvolatile memory cell has a source and drain formed in a well region, a floating gate formed in a channel region between the source and drain through a tunnel oxide film, and an interlayer insulating film in the floating gate. Consists of stacked control gates. The control gate is connected to the word line, the drain is connected to the bit line, and the source is connected to the source line. FIG. 1 representatively shows one nonvolatile memory cell MC and one bit line G-BL, and one end of the bit line G-BL is connected to a sense launch SL composed of a static latch circuit. The

  In the flash memory 1 of FIG. 1, 512 bytes of stored information is called one sector. The information storage unit for writing and reading is 2048 bytes (= 4 sectors), and this unit is called one page. 1024 bytes are also referred to as 1 kilobyte. One page is specified by a page address. Since the flash memory has field element isolation, the information storage unit for erasure is twice the write unit (= 4096 bytes), which is called one block. The even page address designation in the erase mode is the block designation.

  Although not particularly limited, in the flash memory 1, one non-volatile memory cell stores information of 2 bits. Accordingly, in each flash memory array FARY0 to FARY3, 2048 bytes of nonvolatile memory cells are connected to one word line, and page address information is even-numbered or odd-numbered 1024 connected to one corresponding word line. 1024 bytes of sense latches SL are arranged in parallel so as to correspond to the 1024 memory cells specified by the page address information on a one-to-one basis. Page address information specifies the page address within the entire memory bank, its least significant bit specifies an even or odd number of page address, its upper side specifies a word line, and the most significant 2 bits specify a memory bank To do. The word line selection is performed by a word line selection decoder (not shown), and the bit line selection in even page or odd page units is performed by an even / odd bit line selector (not shown). The 1024 bytes selected by the even / odd bit line selector. One bit line is connected to 1024 bytes of sense latches SL. In the erase mode, even page addresses are regarded as block addresses (addresses for two pages of one word line).

  The data stored in the non-volatile memory cell utilizes the fact that the threshold voltage of the memory cell changes according to the amount of charge stored in the floating gate as a charge holding region. At this time, the threshold voltage of the memory cell is limited to a desired range according to the value of the stored data, and the threshold voltage distribution is called a memory threshold voltage distribution. For example, in this example, one nonvolatile memory cell stores two bits of information, and four types of memory threshold voltage distributions corresponding to data 01, 00, 10, and 11 as stored information are determined. That is, the information storage state of one memory cell is the erase state (“11”) as the fourth threshold voltage (Vth4) state in which the threshold voltage belongs to the fourth threshold voltage distribution, and the threshold voltage is the first threshold voltage distribution. The first write state (“10”) as the first threshold voltage (Vth1) state belonging to, and the second write state (Tth) as the second threshold voltage (Vth2) state where the threshold voltage belongs to the second threshold voltage distribution ( “00”), the threshold voltage is selected from the third write state (“01”) as the third threshold voltage (Vth3) state belonging to the third threshold voltage distribution. Although not particularly limited, the threshold voltage has a relationship of Vth4 <Vth1 <Vth2 <Vth3. A total of four information storage states are determined by 2-bit data. In order to obtain the memory threshold voltage distribution, the write verify voltage applied to the word line during the write operation after erasure is set to three different voltages, and these three types of voltages are sequentially switched three times. The write operation is performed separately. In each of these three write operations, 0 V is applied to the write-selected bit line and 1 V is applied to the non-selected bit line. Although not particularly limited, the write high voltage applied to the word line is set to 17 V, for example. As the write high voltage application time is increased, the threshold voltage of the memory cell is increased. Three kinds of write threshold voltage control can be performed by such time control in a high voltage state, and further by level control of a high voltage applied to the word line. Whether 0V or 1V is applied to the bit line is determined by the logical value of the write control information latched by the sense latch circuit SL. For example, the latch data of the sense latch circuit SL is controlled so that writing is not selected when the logic value is “1” and writing is selected when the logic value is “0”. Whether the sense latch SL is set to “1” or “0” during the write operation is determined by the control unit CNT according to the write data in the buffer memory according to the write threshold voltage state to be written. At the time of block erasure, the selected word line applied voltage is set to -16V, the unselected word line is set to 0V, and the selected bit line is set to 2V. For reading out stored information, three kinds of voltages as word line selection levels to be applied to the word lines are set, and the three kinds of word line selection levels are sequentially changed, and read operation is performed three times at a maximum. The 2-bit storage information is determined based on the binary (1 bit) value read from the memory cell.

  The control unit CNT controls erasing, writing, and reading with respect to the flash memory arrays FARY0 to FARY3. With respect to writing, a technique of bringing the memory threshold voltage of the writing source closer to the writing destination acts to reduce the writing processing time. Details thereof will be described later.

  The buffer memories BMRY0 to BMRY3 are constituted by, for example, SRAM (Static Random Access Memory), and write data input from the outside to the external input / output terminals i / o0 to i / o7 and the external input / output terminals i / o0 to i / o0. Binary read data output from i / o 7 is temporarily stored. The buffer memories BMRY0 to BMRY3 are divided into two for each memory bank, and the buffer memories BMRY0 to BMRY3 for each memory bank have a minimum storage capacity equal to a write unit and a read unit in each corresponding flash memory array. For example, in the case of the flash memory 1, since the write information unit and the read information unit are one page (= 2K bytes), each of the buffer memories BMRY0 to BMRY3 as on-chip buffers has a storage capacity of 2K bytes. As described above, one set of buffer memories BMRY0 to BMRY3 is arranged in each memory bank, and the buffer memories arranged in the same memory bank are preferentially used for the same flash memory array. Depending on the operation mode, a buffer memory that is not preferentially supported may be used. The control is performed by the control unit CNT according to a command and an address signal.

  Data input / output between the flash memory array and the buffer memory is performed in units of 8 bits. In the flash memory arrays FARY0 to FARY3, selection of the sense latch SL in units of 8 bits is performed by a sense latch selection circuit not shown. The buffer memories BMRY0 to BMRY3 are made accessible in units of 8 bits. The control unit CNT performs data transfer between the flash memory arrays FARY0 to FARY3 and the buffer memories BMRY0 to BMRY3 and access control to the buffer memories BMRY0 to BMRY3 based on externally applied commands and access address information.

<Write method>
For writing, a technique of bringing the memory threshold voltage of the writing source closer to the writing destination is adopted. In the method adopted here, the application form of the voltage pulse is basically ISPP in consideration of shortening of the write processing time. First, this point will be described. The write characteristics of nonvolatile memory cells vary from memory cell to memory cell. As shown in FIG. 2, a memory threshold voltage (memory Vth) has a fast transition characteristic (fast write characteristic) and a threshold voltage has a slow transition characteristic (slow write characteristic) with respect to the write voltage application time. is there. Therefore, in order to align the write memory threshold voltage distribution width within the desired range (that is, to narrow the memory threshold voltage distribution), the write process increases the memory threshold voltage by adding a write bias as shown in FIG. “Write bias application” to be performed and “write verify” to determine whether the memory threshold voltage has increased to a desired voltage value are repeated. The write operation is continuously repeated until all memory cells pass the write verify. Therefore, in order to shorten the write operation time, it is effective to reduce the number of repetitions.

  It is known that the write characteristics of the flash memory when an arbitrary write word voltage (VWW) is applied are linear with respect to the logarithm of the cumulative write bias application time as shown in FIG. Therefore, if the write pulse length is constant, there is a problem that the increase amount ΔVth of the memory threshold voltage (memory Vth) every time the write pulse is applied gradually decreases and the number of write verifications increases. Therefore, in order to make ΔVth constant and optimize the number of write verifications, there is a “power pulse method” in which the write bias application time is extended to the power of the cumulative bias application time for each write pulse as shown in FIG. In this power pulse method, the number of verifications can be optimized. However, since the pulse length (= tWP) increases for each write pulse, there is a problem that the write bias application time (= ΣtWP) increases exponentially.

  In contrast to the power pulse method in which the word voltage VWW should be constant for each write pulse, there is an ISPP method in which the pulse length is constant for each write pulse. In the ISPP method, as shown in FIG. 6, the write bias is increased by ΔVww for each pulse (VWWn + 1 = VWWn + ΔVww), and the write pulse length is kept constant. Thus, ideally, the memory threshold voltage increases by ΔVww every time the pulse is applied, so that the number of verifications can be optimized in the same way as in the power pulse method. The ideal number of times of write verification Nverify is given by Nverify = ΔVthw / ΔVww, where the variation in write characteristics is ΔVthw.

  FIG. 7 shows a variation amount ΔVth of the memory threshold voltage for each actual write verify when ISPP is performed. As shown in FIG. 7, as the word voltage VWW is higher, ΔVth is larger in a region where the number of verifications is smaller. For this reason, in the initial stage of the write operation, the write variation becomes large and a write jump defect is likely to occur. However, if the word voltage VWW is lowered as a countermeasure, there is a problem that it is difficult to pass the write verification, and the useless application of the write bias voltage and the number of write verifications are increased.

  Therefore, based on the above recognition, a method of bringing the memory threshold voltage of the writing source closer to the writing destination is adopted. This method is (1) a mixed program (Mix Program) method in which write data is synthesized step by step while synthesizing write data from the low voltage side, and (2) an initial pulse for coarsely writing only the first write bias application. It is roughly divided into application methods. In any case, there is a common point in that the memory threshold voltage of the writing source is brought close to the writing destination.

《Mix Program method》
The mixed program method is a method of sequentially writing from the memory threshold voltage of the erase distribution (11 data distribution) to the write distribution on the low voltage side. In the mixed program method, when writing each threshold voltage distribution, the method of writing for each memory threshold voltage to be written as in the comparative example of FIG. Writing is also performed in accordance with the writing distribution on the side. In the comparative example of FIG. 8 and the mixed program method of FIG. 9, the write processing target for the write data has the difference shown in FIG. When the mixed program method is employed, the memory threshold voltage distribution of the writing source is always one distribution on the low voltage side of the memory threshold voltage distribution of the writing destination. For example, even if the interval (potential difference) between the memory threshold voltage distributions is 1 V or less, the variation in the write characteristic with respect to this is at most about 1.5 times the interval of the threshold voltage distribution. By writing from the low voltage side, it is possible to perform writing in a region where the variation is smaller than the original variation in write characteristics. In short, as shown in FIG. 2, the variation in the write characteristic between the memory cell having the fast write characteristic and the memory cell having the slow write characteristic becomes larger as the cumulative application time of the write voltage becomes longer. As the threshold voltage of the transition destination approaches VL with respect to VH with respect to (distribution), the write characteristic variation decreases from DH to DL, and the number of write verifications can be suppressed. In particular, it is possible to suppress the number of write verifications of the “01” distribution and the “00” distribution that are separated from the erase distribution toward the high voltage side. For example, the number of times of each verification can be reduced by 2 to 3 times. The write processing time is reduced by about 10%. Reducing the number of times of write verification contributes to shortening of the write processing time. FIG. 11 shows the contents of FIG. 2 with different expressions.

<Initial pulse application method>
In order to reduce the potential difference between the memory threshold voltage of the write source and the write destination, it is preferable to bring the memory threshold voltage as close as possible to the write destination by applying the first write bias (initial pulse application). For this purpose, it is effective to increase the pulse width of ISPP, but if all the pulse widths are extended, there is a problem that the total write bias time increases. Therefore, as shown in FIG. 12, the write bias application time is extended for only the initial pulse and other write pulses. That is, writing is performed roughly only in the first write bias application in the writing process in each threshold voltage distribution. By roughly writing only the first write pulse in this way, the amount of change in the memory threshold voltage for each application of the second and subsequent write pulses can be reduced, thereby making it possible to suppress write popping defects. The word voltage can be set higher, which can contribute to shortening the write processing time. The reason will be explained. FIG. 13 illustrates a cross-sectional structure of the nonvolatile memory cell MC. CG is a control gate, FG is a floating gate, VTN is a tunnel oxide film potential at the time of writing, and VWW is a writing gate voltage. In writing, electrons (electrons) are injected into the floating gate FG. When the number of electrons accumulated in the floating gate of the nonvolatile memory cell at the time after applying the write pulse is small, the potential difference between the substrate and the floating gate remains relatively large, and the electrons still remain in the tunnel film. As shown in FIG. 14, the tunnel oxide film potential VTN is in a large state. It can be understood that the memory cell in this state has the same characteristics as a memory cell having a slow write characteristic. Conversely, in a state where there are many electrons accumulated in the floating gate FG of the nonvolatile memory cell, the potential difference between the substrate and the floating gate FG becomes relatively small, and it is difficult for the electrons to pass through the tunnel film. As shown in FIG. 14, the tunnel oxide film potential VTN is in a small state. It can be understood that the memory cell in this state has the same characteristics as a memory cell having a fast write characteristic. Therefore, compared to the latter, the former is more likely to cause a pop-out defect due to the application of the next write pulse. Therefore, the memory threshold voltage is brought as close as possible to the writing destination by applying the first writing pulse voltage (that is, applying the initial pulse voltage) (in other words, the memory threshold potential difference between the writing source and the writing destination after the initial pulse voltage is applied is reduced). Thus, after the second pulse, writing can be performed in an area where the memory threshold voltages of the writing source and the writing destination are close to each other, which can contribute to the reduction of the write-out failure rate and hence the writing processing time. FIG. 15 illustrates the concept of pop-out failure. For example, INI-DSB is an initial distribution, REG-DSB1 is a normal threshold voltage distribution above it, and REG-DSB2 is a normal threshold voltage distribution above it. VRini is a read word line voltage for a memory cell having an initial distribution threshold voltage, and VRdsb1 is a read word line voltage for a memory cell having a threshold voltage of threshold voltage distribution REG-DSB1. For example, the pop-out defect in the write processing intended to be included in the threshold voltage distribution REG-DSB1 is that the threshold voltage of the memory cell exceeds the read word line voltage VRdsb1. IREG-DSB1 is an example of a pop-out defect distribution with respect to the normal threshold voltage distribution REG-DSB1.

  The mixed program method relates to the determination of the memory threshold voltage distribution of the write destination, and the initial pulse application method relates to the method of applying the write bias. Since the specific means are different, they are used in combination with each other. I can do things. FIG. 16 illustrates the relationship between the write gate voltage VWW, the pop-out defect rate, and the write verify count when they are used in combination. The number of times of verification is smaller in the mixed program method than in the comparative example method, and the pop-out failure rate is lower in the case of using the initial pulse method than in the case without the initial pulse. For example, when the initial pulse method is not adopted and the pop-out defect is desired to be zero, the write gate voltage VWW must be set to V1. At this time, if the comparative example method is not used, the number of write verify times is N1. If the mix program method is adopted, N2 is obtained. If both the initial pulse method and the mixed program method are employed, even if the write gate voltage VWW is increased to V2, the number of write verify operations can be reduced to N3 while maintaining the write defect rate at zero.

  According to the mix program method, the so-called source floating effect can be further expected. That is, in the read operation, voltage sensing is performed by charging / discharging the bit line. Therefore, paying attention to the memory threshold voltage of a memory cell in a small area that shares a source line, if writing is performed to another memory cell in such a small area by additional writing or the like, The read current flowing as a whole decreases, and the memory threshold voltage appears to decrease due to the decrease in floating of the source potential due to the read memory cell current. For the same reason, the memory threshold voltage of the memory cell that has passed the write operation at the beginning of the write operation appears to gradually decrease as the write operation proceeds. Furthermore, writing from the memory threshold voltage distribution on the low voltage side is considered to increase this effect as compared to writing from the high voltage side. The memory threshold voltage of the memory cell that has passed the write verify in the region where the number of write pulses is small and is likely to jump out of the memory shifts to the low voltage side due to the effect of the floating source. This means that the effect of the source floating acts in a direction to suppress the pop-out defect.

  FIG. 17 shows another example of the initial pulse application method. Here, when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the voltage level of the write voltage pulse applied to the word line of the memory cell transistor is sequentially increased except for the first pulse, In addition, the pulse width is constant except for the first pulse, and the first pulse width is made larger than the subsequent pulse width. The application form of the voltage pulse is basically based on ISPP. More specifically, instead of extending the bias time of the initial pulse, only the VWW of the initial pulse is removed from the ISPP and set to an arbitrary high voltage. This is suitable for speeding up the write operation because the pulse time can be shortened.

  FIG. 18 shows still another example of the initial pulse application method. Here, when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the voltage level of the write voltage pulse applied to the word line of the memory cell transistor is sequentially increased, and the threshold voltage unit. The pulse width is sequentially reduced from the first pulse. The application form of the voltage pulse is basically based on ISPP. In short, by extending the bias time of the initial pulse and gradually shortening the bias application time for each second and subsequent write bias application, it becomes more difficult to cause pop-out defects.

  Although the invention made by the present inventor has been specifically described based on the embodiments, it is needless to say that the present invention is not limited thereto and can be variously modified without departing from the gist thereof.

  For example, in the above, the write control is performed by the control unit CNT, but may be performed by an external logic of a memory such as a data processor. In the above description, the case where the present invention is applied to a memory cell using a floating gate has been described. However, the present invention can also be applied to a memory cell using a silicon nitride film for a charge storage region. Further, multi-value storage is not limited to four values, and the present invention can be applied to more eight-value storage. The present invention can be widely applied not only to a single nonvolatile memory but also to an on-chip nonvolatile memory such as a microcomputer.

1 is a block diagram showing a planar layout configuration of a flash memory which is an example of a semiconductor memory device according to the present invention. FIG. It is explanatory drawing which saves and shows the characteristic with a quick transition of a threshold voltage with respect to the application time of a write voltage, and a slow characteristic. 6 is a flowchart illustrating a write processing procedure in which write bias application and write verify are repeated. It is explanatory drawing which shows that the write-in characteristic of the flash memory at the time of applying arbitrary write word voltages is linear with respect to the logarithm of accumulated write bias application time. It is explanatory drawing which shows the exponentiation pulse system for making (DELTA) Vth constant and optimizing the number of times of write-verify. It is explanatory drawing which shows the ISPP system which makes a pulse length constant for every write pulse. It is explanatory drawing which shows the variation | change_quantity (DELTA) Vth of the memory threshold voltage for every actual write verification at the time of performing ISPP. It is explanatory drawing which illustrates the writing method regarding the comparative example which writes in for every memory threshold voltage of writing object. It is explanatory drawing which illustrates the write method by the mix program system which writes in also the write distribution by the side of a high voltage rather than write object distribution. FIG. 10 is an explanatory diagram illustrating a write process target for write data in each of the comparative example in FIG. 8 and the mixed program method in FIG. 9; It is explanatory drawing which changed and expressed the content of FIG. It is a wave form diagram which shows an example of the pulse voltage waveform by an initial stage pulse application system. 2 is a cross-sectional view illustrating a cross-sectional structure of a flash memory cell. FIG. When writing, there are few electrons stored in the floating gate of the non-volatile memory cell, and it is difficult for electrons to pass through the tunnel film when there are many electrons stored in the floating gate of the non-volatile memory cell. It is explanatory drawing which shows the difference with a shape. It is explanatory drawing which illustrates the concept of a pop-out defect. It is explanatory drawing which illustrates the relationship between the write gate voltage VWW, the pop-out defect rate, and the number of times of write verify when the mixed program method and the initial pulse application method are used in combination. It is explanatory drawing which shows another pulse voltage application form of an initial stage pulse application system. It is explanatory drawing which shows another pulse voltage application form of an initial stage pulse application system.

Explanation of symbols

1 Flash memory FARY0 to FARY3 Flash memory array CNT control unit MC Nonvolatile memory cell

Claims (8)

A memory array and a control circuit;
The memory array includes a plurality of memory transistors whose threshold voltage can be electrically changed,
The control circuit can store four or more logic values in one memory cell transistor by changing a threshold voltage;
When the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the control circuit reaches the target threshold voltage distribution from the initial distribution side for all the memory cell transistors to be changed. The threshold voltage is sequentially changed in units of threshold voltage distribution until the threshold voltage is changed, and the product of the pulse width of the write voltage applied to the word line of the memory cell transistor and the voltage level is maximized by the first pulse application. Nonvolatile storage device to control.   The control circuit sequentially increases the voltage level of the write voltage pulse applied to the word line of the memory cell transistor and changes the pulse width when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution. 2. The nonvolatile memory device according to claim 1, wherein the first pulse width is constant except for the first pulse, and the first pulse width is made larger than the subsequent pulse width.   When the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, the control circuit sequentially increases the voltage level of the write voltage pulse applied to the word line of the memory cell transistor except for the first pulse. The nonvolatile memory device according to claim 1, wherein the pulse width is constant except for the first pulse, and the first pulse width is made larger than the subsequent pulse width.   The control circuit sequentially increases the voltage level of the write voltage pulse applied to the word line of the memory cell transistor when the threshold voltage of the memory cell transistor is changed from the initial distribution to the target threshold voltage distribution, and the threshold voltage The nonvolatile memory device according to claim 1, wherein the unit pulse width is sequentially reduced from the first pulse. A memory array and a control circuit;
The memory array includes a plurality of memory transistors whose threshold voltage can be electrically changed,
The control circuit can store four or more logic values in one memory cell transistor by changing a threshold voltage;
When the control circuit changes the threshold voltage of the memory cell transistor from the initial distribution to the target threshold voltage distribution, the control circuit sequentially makes a transition to the target threshold voltage distribution for all the memory cell transistors to be changed, and A non-volatile memory device that controls a product of a pulse width and a voltage level of a write voltage to be applied to a memory cell transistor when a threshold voltage is changed to be maximized by the first pulse application.   The control circuit sequentially increases the voltage level of the write voltage pulse applied to the memory cell transistor when transitioning the threshold voltage, makes the pulse width constant except for the first pulse, and sets the first pulse width to the subsequent pulse width. The nonvolatile memory device according to claim 5, wherein the nonvolatile memory device is larger than the pulse width.   The control circuit sequentially increases the voltage level of the write voltage pulse applied to the memory cell transistor when transitioning the threshold voltage except for the first pulse, and makes the pulse width constant except for the first pulse. 6. The nonvolatile memory device according to claim 5, wherein the pulse width is made larger than the subsequent pulse width.   6. The nonvolatile circuit according to claim 5, wherein the control circuit sequentially increases the voltage level of the write voltage pulse applied to the memory cell transistor when transitioning the threshold voltage, and sequentially decreases the pulse width of the threshold voltage unit from the first pulse. Sex memory device.

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