JP2011233209A - Semiconductor storage - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor storage in which the threshold voltage distribution of a memory cell is made narrower than a conventional one, without altering the ability of an ECC to correct.SOLUTION: A memory includes cells, a word line driver for driving the voltage of a word line, and a sense amplifier for detecting the data of the cells. The memory stores a multi-valued data into a selected cell by performing a first writing stage in which a writing loop is repeated more than one time, thereby bringing the selected cell into a first state, and a second writing stage in which a writing loop is repeated more than one time, thereby bringing the selected cell into a second state from the first state, the writing loop being composed of a writing operation in which data is written in the selected cell of a cell string, and a verification read operation in which the writing of data in the selected cell is verified. When the second writing stage is performed in the selected cell, the word line driver increases a voltage for the verification read operation, which is to be applied to one of non-selected cells other than the selected cell, compared to the case where the first writing stage is performed in the selected cell.

Description

  Embodiments described herein relate generally to a semiconductor memory device.

  Nonvolatile semiconductor memory devices such as NAND flash memories have been increasingly miniaturized in order to increase memory capacity. As miniaturization progresses, the interval between adjacent memory cells becomes narrower, so that interference between memory cells (hereinafter referred to as proximity effect) cannot be ignored. Due to the proximity effect, the width of the threshold voltage distribution of the memory cell into which data is written is widened.

  On the other hand, it is preferable to reduce the voltage applied at the time of writing and reading as the memory becomes finer. However, if the width of the threshold voltage distribution of the memory cell becomes wider, the interval between the data (voltage difference) must be increased, so that the voltage applied at the time of writing and reading becomes rather high. Therefore, the difference between the threshold voltage of the memory cell after data writing and the threshold voltage of the memory cell after data erasing becomes large. As a result, interference (proximity effect) between adjacent memory cells is increased, and the width of the threshold voltage distribution is further increased.

  Even if the width of the threshold voltage distribution is widened, it is possible to suppress an increase in write or read voltage by using ECC (Error Correcting Code). However, ECC with a high correction capability requires many redundant columns, and the number of gates of the ECC circuit increases. This increases the memory chip size and increases the cost.

  Further, in a multi-value storage memory in which each memory cell stores data of 2 bits or more, one data write is divided into two stages (two stages) or more in order to reduce the proximity effect. In this case, the write stage is executed on the memory cells MCn−1 and MCn + 1 adjacent to the memory cell MCn between the first write stage and the second write stage of the memory cell MCn connected to the word line WLn. May be. Therefore, the threshold voltages of the memory cells MCn−1 and MCn + 1 in the second write stage for the memory cell MCn are larger than the threshold voltages of the memory cells MCn−1 and MCn + 1 in the first write stage for the memory cell MCn. May be higher. In this case, in the verify read in the second write stage for the memory cell MCn, the resistance values of the memory cells MCn−1 and MCn + 1 are higher than in the verify read in the first write stage. Therefore, the current (cell current) flowing through the selected memory cell MCn changes due to the influence of the adjacent memory cells MCn−1 and MCn + 1. This is also a cause of widening the threshold voltage distribution.

JP 2007-157315 A JP 2006-228394 A

  Provided is a semiconductor memory device capable of making the threshold voltage distribution of memory cells narrower than before without changing the ECC correction capability.

A semiconductor memory device according to an embodiment of the present invention includes a plurality of word lines, a plurality of bit lines, a plurality of memory cells whose gates are connected to any one of the word lines, and the plurality of word lines. A word line driver that drives a voltage; and a sense amplifier that detects data of the memory cell via the plurality of bit lines;
A plurality of the memory cells are connected in series between the bit line and the source to form a cell string,
A write loop consisting of a write operation for writing data to a selected memory cell in the cell string and a verify read operation for verifying that data has been written to the selected memory cell is repeated a plurality of times, and the selected memory cell is moved to the first memory cell. A plurality of bit data by executing a first write stage that enters a state and a second write stage that repeats the write loop a plurality of times to bring the selected memory cell from the first state to the second state Is stored in the selected memory cell,
When the second write stage is executed on the selected memory cell, the word line driver is not selected memory other than the selected memory cell than when the first write stage is executed on the selected memory cell. The voltage during the verify read operation applied to one of the cells is increased.

1 is a block diagram showing a configuration of a NAND flash memory according to a first embodiment. The conceptual diagram which shows the verify read voltage applied to the word line of a certain NAND string NS. FIG. 5 is a threshold distribution diagram showing a state when 2-bit data is written to each memory cell MC in two write stages. The table | surface which shows the order which performs the 1st and 2nd write stage with respect to the memory cell connected to each word line. The conceptual diagram which shows the verify read voltage applied to the word line of a certain NAND string NS of the NAND type flash memory according to the second embodiment. The threshold value distribution figure which shows a mode when 2-bit data is written in each memory cell MC according to 2nd Embodiment. The table | surface which shows the order which performs the 1st-3rd write stage with respect to the memory cell connected to each word line. The graph which expressed the data write operation as a comparative example by transition of the threshold voltage distribution of a memory cell. The graph which shows transition of the voltage of the word line in the 1st write stage according to a 3rd embodiment. The graph which expressed data write operation (program operation) with transition of threshold voltage distribution of a memory cell. The graph which shows transition of the voltage of the word line in the 2nd write stage of 3rd Embodiment.

  Embodiments according to the present invention will be described below with reference to the drawings. This embodiment does not limit the present invention.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a NAND flash memory according to the first embodiment of the present invention. In the memory cell array 11, a plurality of memory cells are two-dimensionally arranged in a matrix. The gate of the memory cell is connected to the word line, and the source or drain of the memory cell is connected to the bit line. The plurality of word lines are wired so as to cross each other in the row direction and the bit lines cross each other in the column direction. A sense amplifier 12 is disposed at one end of the memory cell array 11 in the bit line direction. A sense amplifier 12 is also arranged at the other end of the memory cell array 11 opposite to one end in the bit line direction. The sense amplifier 12 is connected to the bit line, and detects data stored in the memory cell by detecting a cell current flowing through the bit line in the memory cell connected to the selected word line. At both ends of the memory cell array 11 in the word line direction, a row decoder 13 and a word line driver 21 are arranged. The word line driver 21 is connected to the word line and is configured to apply a voltage to the word line when data is written to the memory cell.

  In a NAND flash memory, a plurality of memory cells are connected in series to form a NAND string. One end of the NAND string is connected to the bit line BL via a selection transistor, and the other end is connected to the source S via a selection transistor. Therefore, the memory cell is connected to the bit line BL via another memory cell interposed between the memory cell and the bit line BL. An interval between adjacent memory cells in the NAND string is, for example, 30 nm or less.

  Data exchange between the sense amplifier 12 and the external input / output terminal I / O is performed via the data bus 14 and the I / O buffer 15.

  Various external control signals such as a chip enable signal / CE, an address latch enable signal ALE, a command latch enable signal CLE, a write enable signal / WE, and a read enable signal / RE are input to the controller 16. Based on these control signals, the controller 16 identifies the address Add and the command Com supplied from the input / output terminal I / O. Then, the controller 16 transfers the address Add to the row decoder 13 and the column decoder 18 via the address register 17. Further, the controller 16 decodes the command Com. The sense amplifier 12 is configured to apply a voltage to the bit line according to the column address decoded by the column decoder 18. The word line driver 21 is configured to apply a voltage to the word line according to the row address decoded by the row decoder 13.

  The controller 16 performs sequence control of data reading, data writing, and erasing in accordance with an external control signal and a command. The internal voltage generation circuit 19 is provided to generate an internal voltage (for example, a voltage boosted from the power supply voltage) necessary for each operation. The internal voltage generation circuit 19 is also controlled by the controller 16 and performs a boosting operation to generate a necessary voltage.

  FIG. 2 shows the verification applied to the word lines WL0 to WLn, WLDS, WLDD of the NAND string NS of the NAND flash memory according to the first embodiment, and the gates SGS, SGD of the selection transistors Tsels, Tseld. It is a conceptual diagram which shows a read voltage. Note that n is an integer. As shown in FIG. 2, the NAND string NS as the cell string includes a plurality of memory cells MC connected in series between the bit line BL and the source S. One end of the NAND string NS is connected to the bit line BL via the selection transistor Tseld, and the other end is connected to the source S via the selection transistor Tsels.

  Each memory cell MC includes a source layer, a drain layer, a floating gate FG, and a control gate CG. Two adjacent memory cells MC in the NAND string NS share a source layer or a drain layer. Thus, the plurality of memory cells MC are connected in series in the NAND string NS.

  In FIG. 2, the word line WLk (0 ≦ k ≦ n) functions as a selected word line. When 1 ≦ k ≦ n−1, the word lines WL0 to WLk−1 and WLk + 1 to WLn are unselected word lines. When k = 0, WL1 to WLn function as non-selected word lines, and when k = n, WL0 to WLn-1 function as non-selected word lines. The word line driver 21 applies the same voltage as the other unselected word lines WL0 to WLk−1 and WLk + 1 to WLn to the word lines WLDS and WLDD closest to the selection transistors Tsels and Tseld. The memory cells connected to the word lines WL0 to WLn are indicated as MC0 to MCn, respectively. Memory cells connected to the word lines WLDS and WLDD are denoted as MCds and MCdd. Here, the word lines WLDS and WLDS are dummy word lines, and the cells MCds and MCdd are dummy cells that are not used for data storage. In this embodiment, a NAND string having dummy word lines WLDS and WLDD is taken as an example. However, this embodiment can also be applied to a NAND string having no dummy word line. In this case, the same effect as this embodiment can be obtained.

  FIGS. 3A to 3C are threshold value distribution diagrams showing a state when 2-bit data is written to each memory cell MC in two write stages. In FIG. 3A, Er indicates a threshold distribution of memory cells in the erased state. Er and LM in FIG. 3B indicate threshold distributions of the memory cells after the first write stage. Er, A, B, and C in FIG. 3C indicate the threshold distribution of the memory cell after the second write stage. In the second write stage, the memory cells MC having the distribution LM become memory cells having the distribution B or C, and the memory cells MC having the distribution Er become memory cells having the distribution Er or A.

  Please refer to FIG. 2 again. In each write loop of the first write stage (FIGS. 3A to 3B), the memory performs a verify read operation after writing data to the memory cell. When WLk is a selected word line, in the verify read operation, the word line driver 21 applies a gate voltage VCG as a selection voltage to the selected word line WLk. The word line driver 21 applies the first verify read voltage VREAD1_1 to unselected word lines WLk-1 and WLk + 1 adjacent to both sides of the selected word line WLk. Further, the word line driver 21 applies the second verify read voltage VREAD2_1 to the unselected word lines WLk-2 and WLk + 2 that are the second closest to the selected word line WLk. Further, the word line driver 21 applies the third verify read voltage VREAD3_1 to unselected word lines WL0 to WLk-3, WLk + 3 to WLn, WLDS, and WLDD that are separated from the selected word line WLk by three or more word lines.

  The voltage increases in the order of VCG, VREAD1_1, VREAD3_1, and VREAD2_1.

  The word line driver 21 sets the gate voltages of the selection transistors Tsels and Tseld to VSG. The gate voltage VSG is a voltage that is lower than the verify read voltage VREAD3_1 and higher than the electrode VCG, and makes the select transistors Tsels and Tseld having a low threshold voltage conductive. As a result, the non-selected memory cells MC0 to MCk−1, MCk + 1 to MCn, MCds and MCdd are turned on, and the selection transistors Tsels and Tseld are also turned on. As a result, the selected memory cell MCk in the non-conductive state is connected between the bit line BL and the source S. By applying a voltage to the selected memory cell MCk via the bit line BL, the sense amplifier S / A can detect data in the selected memory cell MCk.

  Next, in each write loop of the second write stage (FIGS. 3B to 3C), the memory performs a verify read operation after writing data to the memory cell. In the verify read operation in the second write stage, the word line driver 21 changes the voltages VREAD3_1, VREAD2_1, and VREAD1_1 to voltages VREAD3_2, VREAD2_2, and VREAD1_2. The voltages VREAD3_2, VREAD2_2, and VREAD1_2 are voltages higher than the voltages VREAD3_1, VREAD2_1, and VREAD1_1, respectively. The voltages VREAD3_2, VREAD2_2, and VREAD1_2 may be higher than the original voltages VREAD3_1, VREAD2_1, and VREAD1_1 by a certain voltage, respectively, or may be higher than the original voltages VREAD3_1, VREAD2_1, and VREAD1_1 by a certain ratio.

  The voltage indicated by the solid line in FIG. 2 is the voltage of each word line in the first write stage, and the voltage indicated by the broken line is the voltage of each word line in the second write stage.

  As described above, in this embodiment, the verify read voltage of the non-selected word line in the second write stage is higher than the verify read voltage of the non-selected word line in the first write stage. With reference to FIG. 4, the reason why the verify read voltages of the unselected word lines are made different between the first write stage and the second write stage will be described.

  FIG. 4 is a table showing the order in which the first and second write stages are performed on the memory cells connected to each word line. “0” to “2n + 2” in this table indicate the execution order of the first and second write stages. According to this table, for example, after executing the first write stage on WL0, WL1, the second write stage is executed on WL0, the first write stage is executed on WL2, and the second write stage is executed on WL1. Run the stage. Continuing, as indicated by the arrow in FIG. 4, the first write stage is performed on WLk-1, then the second write stage is performed on WLk-2, and then the first write stage on WLk. Execute the write stage. Here, k is an integer from 0 to n. As described above, the reason why the first write stage and the second write stage are alternately executed while changing the selected word line is to reduce the proximity effect.

  For example, when the word line driver 21 selects the word line WLk and executes the first write stage, the memory cell MCk−1 connected to the word line WLk−1 adjacent to the word line WLk is already in the first cell stage. The write stage has been executed. Therefore, the memory cell MCk-1 may be in the distribution LM in FIG. Further, the first and second write stages are not executed in the memory cell MCk + 1 connected to the word line WLk + 1 adjacent to the word line WLk. Therefore, the memory cell MCk + 1 is in the erased state Er of FIG. 3A, and its threshold voltage remains low.

  When the word line driver 21 selects the word line WLk and executes the second write stage, the memory cell MCk−1 connected to the word line WLk−1 adjacent to the word line WLk is already in the second cell stage. The write stage has been executed. Accordingly, the memory cell MCk-1 may be included in any of the distributions B and C in FIG. In this case, the threshold voltage of the memory cell MCk-1 is higher than the threshold voltage in the LM state. The first write stage has been executed for the memory cell MCk + 1 connected to the word line WLk + 1 adjacent to the word line WLk. Therefore, the memory cell MCk + 1 may be in the erased state LM in FIG. In this case, the threshold voltage of the memory cell MCk + 1 is high.

  As described above, at the time when the first write stage is performed on the memory cells MCk connected to the word line WLk, the memory cells MCk−1 and MCk + 1 adjacent to the memory cell MCk can be included in the distributions LM and Er, respectively. . Further, at the time when the second write stage is executed on the memory cell MCk, the memory cells MCk−1 and MCk + 1 can be included in the distributions C (or B) and LM, respectively. This means that the threshold voltages of the adjacent memory cells MCk−1 and MCk + 1 in the second write stage are higher than the threshold voltages of the adjacent memory cells MCk−1 and MCk + 1 in the first write stage.

  If the threshold voltage of the non-selected memory cells MCk−1 and MCk + 1 increases while the verify read voltage is kept constant, the current (cell current) flowing through the selected memory cell MCk in the verify read of the selected memory cell MCk decreases. As described above, this is a cause of widening the width of the threshold voltage distribution (that is, a cause of variation in threshold voltage of the memory cell after writing).

  Therefore, in the present embodiment, in the second write stage in which the threshold voltages of the unselected memory cells MCk−1 and MCk + 1 are increased, the verify read voltages VREAD3_1, VREAD2_1, and VREAD1_1 of the unselected word lines are set to VREAD3_2, VREAD2_2, and VREAD1_2, respectively. To rise. As a result, during the verify read of the selected memory cell MCk in the second write stage, the resistance values of the unselected memory cells MCk−1 and MCk + 1 are sufficiently lowered, so that a decrease in cell current is suppressed. As a result, the threshold voltage distribution can be narrowed after the memory cell is written.

  In this embodiment, in order to facilitate the control of the verify read voltage of the unselected word line, the word line driver 21 increases the verify read voltage of all the unselected word lines in the second write stage. Yes. In this case, the resistance values of the unselected memory cells MCk−1 and MCk + 1 mainly decrease, and the resistance values of the other unselected memory cells MC0 to MCk−2 and MCk + 2 to MCn slightly decrease, but do not change much. This is because the resistance values of the non-selected memory cells MC0 to MCk-2 and MCk + 2 to MCn are sufficiently lowered by the verify read voltages VREAD3_1 and VREAD2_1.

  Therefore, in order to reduce the resistance value of only the non-selected memory cells MCk−1 and MCk + 1, the word line driver 21 does not change the verify read voltages VREAD3_1 and VREAD2_1 as they are in the second write stage. Only VREAD1_1 may be raised to VREAD1_2. Even in this case, since the resistance values of the non-selected memory cells MCk−1 and MCk + 1 can be lowered, the effect of the present embodiment can be obtained.

  In the present embodiment, the word line driver 21 does not depend on the state (Er, LM, A, B, or C) of data stored in the unselected memory cells MCk−1, MCk + 1 adjacent to the selected memory cell MCk. In the second write stage, the verify read voltage of the unselected word lines WLk−1 and WLk + 1 is increased. In the verify read operation, the verify read voltage may be increased regardless of the state of the data stored in the non-selected memory cells in order to make the non-selected memory cells MCk−1 and MCk + 1 have a sufficiently low resistance state. .

  On the other hand, the word line driver 21 determines whether the unselected word line WLk−1, in the second write stage, according to the state of data stored in the unselected memory cells MCk−1 and MCk + 1 adjacent to the selected memory cell MCk. It may be determined whether the verify read voltage of WLk + 1 is raised or maintained without being raised. For example, in the second write stage of the selected memory cell MCk, when the non-selected memory cell MCk−1 or MCk + 1 is in the erased state Er shown in FIG. 3B, the word line driver 21 is in the second write stage. It is not necessary to increase the verify read voltage of the unselected memory cell MCk−1 or MCk + 1 or the verify read voltage of all the unselected memory cells.

  On the other hand, when the non-selected memory cell MCk−1 or MCk + 1 belongs to the distribution LM shown in FIG. 3B in the second write stage of the selected memory cell MCk, the word line driver 21 selects the unselected memory cell MCk− The verify read voltage of 1 or MCk + 1 or the verify read voltage of all unselected memory cells is increased. Even if it is such a form, the effect of this embodiment is not lost.

  During the verify read operation, the word line driver 21 applies the first verify read voltage VREAD1_1 (or VREAD1_2) higher than VCG to the first non-selected memory cells MCk-1 and MCk + 1 adjacent to the selected memory cell MCk. Apply. During the verify read operation, the word line driver 21 applies the second verify voltage VREAD1_1 (or VREAD1_2) higher than the first verify read voltage VREAD1_1 to the second non-selected memory cells MCk-2 and MCk + 2 that are second closest to the selected memory cell MCk. A verify read voltage VREAD2_1 (or VREAD2_2) is applied. Further, the word line driver 21 is higher than the first verify read voltage VREAD1_1 (or VREAD1_2) in the third non-selected memory cells MCk-3 and MCk + 3 that are third closest to the selected memory cell MCk during the verify read operation. A third verify read voltage VREAD3_1 (or VREAD3_2) lower than the second verify read voltage VREAD2_1 (or VREAD2_2) is applied. The reason why the verify read voltage applied to the non-selected memory cells MCk-1, MCk + 1, MCk-2, MCk + 2 is closer to the VCG as it is closer to the selected memory cell is as follows. As the memory becomes finer, the interval between the word lines becomes narrower, and the breakdown voltage between the floating gate of the memory cell and the word line adjacent to the word line connected to the memory cell decreases. For this reason, the closer to the selected memory cell, the closer the verify read voltage is to VCG, and the potential difference between the floating gate and the adjacent word line needs to be relaxed. That is, the gradient of the electric field from VCG to VREAD2_1 (or VREAD2_2) is relaxed to prevent the electric field from concentrating between the floating gate of the memory cell MCk and the adjacent word lines WLk−1 and WLk + 1.

  When the word line WL0 is selected, the word line driver 21 may set the verify read voltage of the dummy word line WLDS to VREAD1_1 or VREAD1_2. When the word line WLn is selected, the word line driver 21 may set the verify read voltage of the dummy word line WLDD to VREAD1_1 or VREAD1_2.

(Second Embodiment)
FIG. 5 shows the verification applied to the word lines WL0 to WLn, WLDS, WLDD of the NAND string NS of the NAND flash memory according to the second embodiment, and the gates SGS, SGD of the selection transistors Tsels, Tseld. It is a conceptual diagram which shows a read voltage. The configuration of the memory according to the second embodiment may be the same as that of the first embodiment. In the second embodiment, 2-bit data is written to each memory cell MC in three write stages.

  In FIG. 5, a word line WLk (0 ≦ k ≦ n) functions as a selected word line. When 1 ≦ k ≦ n−1, the word lines WL0 to WLk−1 and WLk + 1 to WLn are unselected word lines. When k = 0, WL1 to WLn function as non-selected word lines, and when k = n, WL0 to WLn-1 function as non-selected word lines. The word line driver 21 applies the same voltage as the other unselected word lines WL0 to WLk−1 and WLk + 1 to WLn to the word lines WLDS and WLDD closest to the selection transistors Tsels and Tseld.

  In the second embodiment, a NAND string having dummy word lines WLDS and WLDD is taken as an example. However, the second embodiment can also be applied to a NAND string having no dummy word line. In this case, the same effect as in the second embodiment can be obtained.

  FIGS. 6A to 6D are threshold value distribution diagrams showing a state when 2-bit data is written to each memory cell MC according to the second embodiment of the present invention. In FIG. 6A, Er indicates a threshold distribution of memory cells in the erased state. Er and LM in FIG. 6B indicate the threshold distribution of the memory cell after the first write stage. Er, Af, Bf, and Cf in FIG. 6C indicate the threshold distribution of the memory cell after the second write stage. The states of distributions Af, Bf, and Cf are also referred to as foggy states. Er, A, B, and C in FIG. 6D indicate threshold distributions of the memory cells after the third write stage. The states of distributions A, B, and C are also referred to as fine states.

  In the second write stage, the memory cells MC having the distribution LM become memory cells having the distribution Bf or Cf. The memory cells MC having the distribution Er become memory cells having the distribution Er or Af, respectively. In the third write stage, the memory cells with distributions Af, Bf, and Cf become memory cells with distributions A, B, and C, respectively.

  Please refer to FIG. 5 again. In the verify read operation of each write loop of the first write stage, the word line driver 21 applies the gate voltage VCG as the selection voltage to the selected word line WLk, similarly to the first write stage in the first embodiment. The first verify read voltage VREAD1_1 is applied to the unselected word lines WLk-1 and WLk + 1, the second verify read voltage VREAD2_1 is applied to the unselected word lines WLk-2 and WLk + 2, and the other non-selected word lines WLk-1 and WLk + 1 are applied. A third verify read voltage VREAD3_1 is applied to the selected word lines WL0 to WLk-3 and WLk + 3 to WLn. Accordingly, the distribution LM in FIG. 6B is the same as the distribution LM in FIG.

  Next, in each write loop of the second write stage (FIGS. 6B to 6C), the memory performs a verify read operation after writing data to the memory cell. In the verify read operation in the second write stage, the word line driver 21 changes the voltages VREAD3_1, VREAD2_1, and VREAD1_1 to voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a. The voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a are higher than the voltages VREAD3_1, VREAD2_1, and VREAD1_1, respectively. The voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a may be higher than the original voltages VREAD3_1, VREAD2_1, and VREAD1_1 by a certain voltage, respectively, or may be higher than the original voltages VREAD3_1, VREAD2_1, and VREAD1_1 by a certain ratio.

  Next, in each write loop of the third write stage (FIG. 6C to FIG. 6D), the memory performs a verify read operation after writing data to the memory cell. In the verify read operation in the third write stage, the word line driver 21 changes the voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a to voltages VREAD3_3, VREAD2_3, and VREAD1_3. The voltages VREAD3_3, VREAD2_3, and VREAD1_3 are higher than the voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a, respectively. The voltages VREAD3_3, VREAD2_3, and VREAD1_3 may be higher than the original voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a by a certain voltage, respectively, or may be higher than the original voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a by a certain ratio.

  The voltage indicated by the solid line in FIG. 5 is the voltage of each word line in the first write stage, the voltage indicated by the broken line is the voltage of each word line in the second write stage, and the voltage indicated by the alternate long and short dash line is the third voltage This is the voltage of each word line in the write stage.

  As described above, in the second embodiment, the verify read voltage of the non-selected word line in the second write stage is higher than the verify read voltage of the non-selected word line in the first write stage. The verify read voltage of the unselected word line at is higher than the verify read voltage of the unselected word line in the second write stage.

  FIG. 7 is a table showing the order in which the first to third write stages are executed on the memory cells connected to each word line. “0” to “3n + 3” in this table indicate the execution order of the first to third write stages. According to this table, for example, after executing the first write stage on WL0, WL1, the second write stage is executed on WL0, the first write stage is executed on WL2, and the second write stage is executed on WL1. A stage is executed, and further a third write stage is executed for WL0. This is continued and the first to third write stages are executed as indicated by the arrows in FIG. Thus, the reason why the first to third write stages are sequentially executed while changing the selected word line is to reduce the proximity effect.

  For example, when the word line driver 21 selects the word line WLk and executes the first write stage, the first write stage is the memory cell MCk− connected to the word line WLk−1 adjacent to the word line WLk. 1 has already been executed. Therefore, the memory cell MCk-1 may be in the distribution LM in FIG. In addition, none of the first to third write stages is executed on the memory cell MCk + 1 connected to the word line WLk + 1 adjacent to the word line WLk. Accordingly, the memory cell MCk + 1 is in the erased state Er of FIG. 6A, and its threshold voltage remains low.

  When the word line driver 21 selects the word line WLk and executes the second write stage, the second write stage has already been executed for the memory cell MCk-1. Therefore, the memory cell MCk-1 may be in the foggy state of either the distribution Bf or Cf in FIG. In this case, the threshold voltage of the memory cell MCk-1 is higher than the threshold voltage in the LM state. The first write stage has been executed for the memory cell MCk + 1 connected to the word line WLk + 1 adjacent to the word line WLk. Therefore, the memory cell MCk + 1 may be in the erased state LM in FIG. In this case, the threshold voltage of the memory cell MCk + 1 is high.

  Furthermore, when the word line driver 21 selects the word line WLk and executes the third write stage, the third write stage has already been executed for the memory cell MCk-1. Therefore, the memory cell MCk-1 may be in the fine state of either the distribution B or C in FIG. In this case, the threshold voltage of the memory cell MCk-1 is further higher than the threshold voltage of the memory cell MCk-1 in the foggy state. The second write stage has been executed for the memory cell MCk + 1 connected to the word line WLk + 1 adjacent to the word line WLk. Therefore, the memory cell MCk + 1 may be in the foggy state of either the distribution Bf or Cf in FIG. In this case, the threshold voltage of the memory cell MCk + 1 is further increased.

  As described above, at the time when the first write stage is performed on the memory cells MCk connected to the word line WLk, the memory cells MCk−1 and MCk + 1 adjacent to the memory cell MCk can be included in the distributions LM and Er, respectively. . Further, at the time of executing the second write stage on the memory cell MCk, the memory cells MCk−1 and MCk + 1 can be included in the distributions Bf, Cf (foggy state) and LM, respectively. This means that the threshold voltages of the adjacent memory cells MCk−1 and MCk + 1 in the second write stage are higher than the threshold voltages of the adjacent memory cells MCk−1 and MCk + 1 in the first write stage.

  Further, at the time when the third write stage is performed on the memory cell MCk, the memory cells MCk−1 and MCk + 1 can be included in the distributions B and C (fine state) and the distributions Bf and Cf (foggy state), respectively. This means that the threshold voltages of the adjacent memory cells MCk−1 and MCk + 1 in the third write stage are higher than the threshold voltages of the adjacent memory cells MCk−1 and MCk + 1 in the second write stage.

  In the second embodiment, the verify read voltages VREAD3_1, VREAD2_1, and VREAD1_1 of the unselected word lines are set to VREAD3_2a, VREAD2_2a, and VREAD1_2a, respectively, in the second write stage in which the threshold voltages of the unselected memory cells MCk-1 and MCk + 1 are increased. To rise. Note that VREAD3_2a> VREAD3_1, VREAD2_2a> VREAD1_2, and VREAD2_1a> VREAD1_1. As a result, during the verify read of the selected memory cell MCk in the second write stage, the resistance values of the unselected memory cells MCk−1 and MCk + 1 are sufficiently lowered, so that a decrease in cell current is suppressed. As a result, the threshold voltage distribution can be narrowed after the memory cell is written.

  Further, in the second embodiment, the verify read voltages VREAD3_2a, VREAD2_2a, and VREAD1_2a of the unselected word lines are set to VREAD3_3 and VREAD2_3, respectively, in the third write stage in which the threshold voltages of the unselected memory cells MCk−1 and MCk + 1 are increased. , VREAD1_3. Note that VREAD3_3> VREAD3_2a, VREAD1_3> VREAD2_2a, and VREAD1_3> VREAD2_1a. As a result, during the verify read of the selected memory cell MCk in the third write stage, the resistance values of the unselected memory cells MCk−1 and MCk + 1 are sufficiently lowered, so that a decrease in cell current is suppressed. As a result, the threshold voltage distribution can be narrowed after the memory cell is written.

  In the second embodiment, as in the first embodiment, the word line driver 21 may reduce the resistance values of only the non-selected memory cells MCk−1 and MCk + 1. That is, the word line driver 21 does not change the verify read voltages VREAD3_1 and VREAD2_1 as they are in the second write stage, but raises only the verify read voltage VREAD1_1 to VREAD1_2, and in the third write stage, the verify read voltage VREAD1_2a May be raised to VREAD1_3. Even in this case, since the resistance values of the non-selected memory cells MCk−1 and MCk + 1 can be lowered, the effect of the second embodiment can be obtained.

  Also in the second embodiment, as in the first embodiment, the word line driver 21 determines whether the data stored in the unselected memory cells MCk−1 and MCk + 1 adjacent to the selected memory cell MCk. Whether to increase the verify read voltage of the unselected word lines WLk−1 and WLk + 1 may be determined. For example, after the first write stage, when the non-selected memory cell MCk−1 or MCk + 1 is in the erased state Er shown in FIG. 6B, the word line driver 21 determines that the non-selected memory cell MCk in the second write stage. The verify read voltage of −1 or MCk + 1 or the verify read voltage of all unselected memory cells is not increased. On the other hand, after the first write stage, when the non-selected memory cell MCk−1 or MCk + 1 belongs to the distribution LM shown in FIG. 6B, the word line driver 21 determines that the non-selected memory cell in the second write stage. The verify read voltage of MCk-1 or MCk + 1 or the verify read voltage of all unselected memory cells is increased.

  When the non-selected memory cell MCk−1 or MCk + 1 belongs to the distribution Er shown in FIG. 6C after the second write stage, the word line driver 21 determines that the non-selected memory cell in the third write stage. The verify read voltage of MCk-1 or MCk + 1 or the verify read voltage of all unselected memory cells is not increased. On the other hand, if the non-selected memory cell MCk−1 or MCk + 1 belongs to the distributions Af to Cf shown in FIG. 6C after the second write stage, the word line driver 21 is not selected in the third write stage. The verify read voltage of memory cell MCk-1 or MCk + 1 or the verify read voltage of all unselected memory cells is increased. Even in such an operation, the effect of the second embodiment is not lost.

  As described above, the present embodiment can also be applied to a method of writing data in each memory cell in the first to third write stages.

(Third embodiment)
FIGS. 8A to 8D are graphs representing typical data write operations (program operations) as comparative examples by transitions of threshold voltage distributions of memory cells. The horizontal axis of the graph is the threshold voltage of the memory cell. The vertical axis of the graph is the number of memory cells. FIG. 8A shows the erase state distribution De, and all the memory cells are in the erased state. 8A to 8D show a write stage for writing data to a selected memory cell of each column connected to a certain selected word line.

  A memory cell MC of the NAND flash memory includes a floating gate FG and a control gate CG as shown in FIG. The control gate CG is connected to the word line WL, and the word line driver 21 applies a voltage to the control gate CG via the word line WL. As a result, the threshold voltage of the memory cell MC changes by injecting charges (for example, electrons) into the floating gate FG or by extracting charges from the floating gate FG. For example, if all the memory cells MC are composed of N-type FETs (Field-Effect Transistors), the threshold voltage is increased by injecting electrons into the floating gate FG. Conversely, the threshold voltage is lowered by extracting electrons from the floating gate FG. Here, a state where the threshold voltage of the memory cell MC is high is referred to as data “0”, and a state where the threshold voltage of the memory cell MC is low is referred to as data “1”. That is, the erase state shown in FIG. 8A shows data “1”, and FIGS. 8A to 8D show memory cells MC storing data “1” (hereinafter referred to as “1” cells). The operation of writing data “0” to any one of the above is also shown.

  The NAND flash memory writes data to the memory cell MC by repeating a write loop including a write operation for writing data to the selected memory cell and a verify operation for verifying that the data has been written to the selected memory cell a plurality of times. . For example, FIGS. 8A to 8D may each indicate a threshold voltage distribution indicating a result of executing the write loop. Hereinafter, a series of write sequences including a plurality of write loops is referred to as a write stage.

  The selected memory cell that has reached a predetermined threshold voltage in one write verify operation is disconnected from the bit line by the select transistors Tsel and Tsels (see FIG. 2) in the next write operation, and writing is not executed. The selected memory cell that has not reached the predetermined threshold voltage in the verify operation is also written in the next write operation.

  FIG. 8B shows the threshold voltage distribution of the memory cell after the first write loop is executed. Dp1 indicates the threshold voltage distribution of all the memory cells to which data has been written. Among the memory cells having the distribution Dp1, the distribution Dpa1 indicates a memory cell having a relatively high threshold voltage, that is, a memory cell having a relatively high writing speed. Among the memory cells having the distribution Dp1, the distribution Dpb1 indicates a memory cell having a relatively low threshold voltage, that is, a memory cell having a relatively low writing speed.

  A verify operation is performed after each write operation. VL indicates a verify level. When the threshold voltage of the selected memory cell reaches the verify level VL, it is considered that data is written in the selected memory cell. That is, it is determined that the selected memory cell has passed (passed) verification. Therefore, subsequent writing in the writing stage is not executed for the selected memory cell.

  On the other hand, when the threshold voltage of the selected memory cell is lower than the verify level VL, it is considered that data has not yet been written in the selected memory cell. That is, it is determined that the selected memory cell has failed verify. Therefore, the selected memory cell is further written in the next write loop.

  FIG. 8C shows the threshold voltage distribution of the memory cell after the second write loop is executed. Dp2 represents the threshold voltage distribution of all the memory cells that have been written for the second time. Among the memory cells having the distribution Dp2, the distribution Dpa2 indicates a memory cell having a relatively high threshold voltage, that is, a memory cell having a relatively high writing speed. Among the memory cells having the distribution Dp2, the distribution Dpb2 indicates a memory cell having a relatively low threshold voltage, that is, a memory cell having a relatively low writing speed. Generally, the memory cells belonging to the distribution Dpa1 shift to the distribution Dpa2 by the second writing, and the memory cells belonging to the distribution Dpb1 shift to the distribution Dpb2 by the second writing.

  At the time of the second writing, the threshold voltages of most memory cells belonging to the distribution Dpa2 having a high writing speed reach the verify level VL. The threshold voltages of most memory cells belonging to the distribution Dpb2 whose write speed is slow have not yet reached the verify level VL. A memory cell that has reached the verify level VL is considered to have been written, and is not subject to the next write loop. Therefore, hereinafter, a selected memory cell in a column for which writing has been completed is referred to as a writing completed memory cell, and a selected memory cell in a column for which writing has not yet been completed is referred to as a writing incomplete memory cell.

  Since the NAND string including the write completion memory cell is disconnected from the bit line BL and the source S, the body region (channel portion) of the write completion memory cell is in an electrically floating state.

  FIG. 8D shows the threshold voltage distribution of the memory cell after the third write loop is executed. Distribution Dp3 shows the threshold voltage distribution of all the memory cells that have been written for the third time. Among the memory cells having the distribution Dp3, the distribution Dpa3 indicates a memory cell having a relatively high threshold voltage, that is, a memory cell having a relatively high writing speed. Among the memory cells having the distribution Dp3, the distribution Dpb3 indicates a memory cell having a relatively low threshold voltage, that is, a memory cell having a relatively low writing speed. Generally, the memory cells belonging to the distribution Dpa2 in FIG. 8C shift to the distribution Dpa3 by the third writing, and the memory cells belonging to the distribution Dpb2 shift to the distribution Dpb3 by the third writing.

  The NAND string including the write completion memory cell shares the word line WL with the NAND string including the write incomplete memory cell. For this reason, even after the completion of programming, the gate voltage is applied to the gate of the programming completed memory cell. At this time, the potential of the body region of the write-completed memory cell is boosted according to the gate voltage by capacitive coupling with the control gate CG, and writing hardly occurs. However, since the potential of the body region does not transition to a voltage equal to the gate voltage, a certain electric field is applied to the floating gate FG. Due to this electric field, a small amount of charge is quantum-injected into the write completion memory cell. That is, the write completion memory cells belonging to the distribution Dpa2 in FIG. 8C are prohibited from being written thereafter, but the threshold voltage of the write completion memory cell is as shown in the distribution Dpa3 in FIG. The quantum rises slightly slightly due to the writing loop after the writing is completed.

  Accordingly, the distribution Dpa3 having a relatively high threshold voltage among the threshold voltage distribution Dp3 in FIG. 8D is configured by memory cells having a high write speed and having been written in a small write loop. The distribution Dpb3 having a relatively low threshold voltage is composed of memory cells having a low write speed and having been written in many write loops.

  As described above, the threshold voltage of the write completion memory cell gradually increases due to the write loop after the write is completed, so that the threshold voltage distribution Dp3 is widened at the end of the write stage in which the writing of all the memory cells is completed.

  Therefore, in the NAND flash memory according to the third embodiment, the word line driver 21 verifies one of the word lines connected to the non-selected memory cell in the NAND string at a certain point in each write stage. Voltage VREAD is increased.

  The configuration of the memory in the third embodiment may be the same as the configuration of the first or second embodiment. Further, the initial verify read voltage in each write stage may be the same as VREAD1_1, VREAD2_1, etc. in the first or second embodiment.

  FIG. 9A to FIG. 9D are graphs showing the transition of the voltage of the word line in the first write stage according to the third embodiment. FIG. 9A shows the voltage of the selected word line WLk. FIG. 9B shows voltages applied to the non-selected word lines WLk−1 and WLk + 1 adjacent to the selected word line WLk. FIG. 9C shows voltages applied to unselected word lines WLk−2 and WLk + 2 that are second closest to the selected word line WLk. FIG. 9D shows voltages applied to the other non-selected word lines WL0 to WLk-3, WLk + 3 to WLn, WLDD, and WLDS.

  First, the operation of the selected word line WLk shown in FIG. 9A will be described. The word line driver 21 steps up the program voltages VPGM (1) to VPGM (M) of the selected word line WLk in the write operation in each of the write loops Loop1 to LoopM. Thus, the program voltage increases as the number of write loops increases. That is, even in a memory cell that did not pass verification in the initial write loop of the write stage, data (charge) is sufficiently written in the subsequent write loop by passing up the program voltage, and passes verification. be able to.

  In the verify operation in each of the write loops Loop1 to LoopM, the voltage applied to the selected word line WLk is VCG and is constant. That is, in each of the write loops Loop1 to LoopM, the gate voltage VCG of the selected memory cell MCk in the verify operation is constant.

  On the other hand, the voltages of the unselected word lines WLk−1 and WLk + 1 shown in FIG. 9B are VPASS and constant in the write operations of the write loops Loop1 to LoopM. However, in the verify operation of each of the write loops Loop1 to LoopM, the voltages of the unselected word lines WLk−1 and WLk + 1 are VREAD1_1 or VREAD1_1b. Here, VREAD1_1b is a voltage higher than VREAD1_1. In the initial write loop of the write stage, the word line driver 21 applies a relatively low verify read voltage VREAD1_1 to the unselected word lines WLk−1 and WLk + 1. At some point in the write stage, the word line driver 21 applies a relatively high verify read voltage VREAD1_1b to the unselected word lines WLk−1 and WLk + 1.

  The reason for changing the verify read voltage applied to the unselected word line during the first write stage will be described below with reference to FIGS. 10 (A) to 10 (C).

  FIG. 10A to FIG. 10C are graphs representing the data write operation (program operation) according to the third embodiment as transitions of the threshold voltage distribution of the memory cells. Since the threshold voltage distribution in the erased state is the same as that in FIG. 8A, the illustration thereof is omitted.

  When the verify read voltage is constant in each write loop as in the prior art, as described with reference to FIG. 8C and FIG. 8D, the threshold voltage of the write completion memory cell is Gradually increases by the write loop, and the threshold voltage distribution Dp3 is widened at the end of the write stage.

  On the other hand, in the memory according to the present embodiment, the low verify read voltage VREAD1_1 is used for the unselected word line at the initial stage of the write stage. Although the unselected memory cells MCk−1 and MCk + 1 are turned on when the refine read voltage VREAD1_1 is applied to the gates, their on-resistances are relatively high. For this reason, the resistance between the bit line BL and the source S is apparently increased. That is, when viewed from the sense amplifier 12, the resistance of the selected memory cell MCk looks high. In other words, the verify level VL is apparently lowered. As a result, the selected memory cell is likely to pass (pass) in the verify operation. The apparent verify level at this time is displayed as VL0 in FIG.

  The selected memory cell with fast writing belonging to the distribution Dpai (i = 1 to 3) in FIGS. 10A to 10C passes the verification with a small number of writings. At this time, as shown in FIG. 10B, some of the slow-selected memory cells belonging to the distribution Dpbi also pass the verification with a small number of writings, but many of the selected memory cells belonging to the distribution Dpbi are still in the verifying state. Has not passed.

  The word line driver 21 raises the verify read voltage to a relatively high VREAD1_1b at some point during the write stage. As a result, the on-resistances of the unselected memory cells MCk−1 and MCk + 1 are lowered. For this reason, the resistance between the bit line BL and the source S is apparently lowered. That is, when viewed from the sense amplifier 12, the resistance of the selected memory cell MCk looks relatively low. In other words, the verify level is apparently increased. As a result, the selected memory cell is difficult to pass in the verify operation. The apparent verify level at this time is displayed as VL1 in FIG.

  As shown in FIG. 10B, many of the fast-writing selected memory cells belonging to the distribution Dpa2 have already passed verification in the write loop using the verify read voltage VREAD1_1. These selected memory cells that are written quickly pass the verification with a low verification level VL0. Accordingly, the distribution Dpa2 in FIG. 10B is shifted to the lower threshold voltage side as compared with the distribution Dpa2 in FIG. 8C of the comparative example. Thus, even if the apparent verify level is changed, the selected memory cell that has once passed verification is prohibited from being written in the subsequent write loop. On the other hand, as described above, even if writing is prohibited, the threshold voltage of the selected memory cell in which writing has been completed slightly increases by driving the word line WLk in the subsequent writing loop. In other words, in the present embodiment, the threshold voltage of the selected memory cell with fast writing that has passed verification is originally shifted to the low voltage side. Can be substantially canceled. Here, in order to cancel the increase in the threshold voltage after the completion of writing, the difference between the verify read voltages VL0 and VL1 is preferably substantially equal to the shift amount of the threshold voltage by the writing loop after the writing is completed.

  Further, when the verify read voltage is stepped up to VREAD1_1b at a certain point in the write stage, as shown in FIG. 10C, the select memory cell with slow write belonging to the distribution Dpb3 uses the verify read voltage VREAD1_1b. Verify is performed in the write loop. These selected memory cells that are written slowly apparently pass verify when the high verify level VL1 is exceeded. As a result, an overlapping region between the threshold voltage distribution Dpb3 of the selected memory cell with slow writing and the threshold voltage distribution Dpa3 of the selected memory cell with fast writing becomes large, and the width of the entire threshold voltage distribution Dp3 becomes narrow.

  The above description can be similarly applied to the other non-selected word lines 0 to WLk−2, WLk + 2 to WLn, WLDD, and WLDS shown in FIGS. 9C and 9D.

  That is, the voltages of the unselected word lines WLk−2 and WLk + 2 shown in FIG. 9C are VREAD2_1 or VREAD2_1b in the verify operation of each of the write loops Loop1 to LoopM. Here, VVREAD2_1b is a voltage higher than READ2_1. In the initial write loop of the write stage, the word line driver 21 applies a relatively low verify read voltage VREAD2_1 to the unselected word lines WLk-2 and WLk + 2. At some point in the write stage, the word line driver 21 applies a relatively high verify read voltage VREAD2_1b to the unselected word lines WLk-2 and WLk + 2.

  As described above, at a certain point in the first write stage, the verify read voltages of the unselected word lines WLk−2 and WLk + 2 step up from VREAD2_1 to VREAD2_1b. As a result, many of the selected memory cells that are quickly written already pass verification in the write loop using the verify read voltage VREAD2_1. These selected memory cells that are fast to write apparently pass verify with a low verify level VL0 '.

  On the other hand, the selected memory cell which is slow in writing is verified in the write loop using the verify read voltage VREAD2_1b. These selected memory cells that are slow to write apparently pass verify when the high verify level VL1 'is exceeded. As a result, as shown in FIG. 10C, the overlapping region between the threshold voltage distribution Dpb3 of the selected memory cell with slow writing and the threshold voltage distribution Dpa3 of the selected memory cell with fast writing becomes large, and the entire threshold voltage distribution Dp3 The width of becomes narrower.

  The voltages of the unselected word lines 0 to WLk−3, 0 to WLk + 3, WLDD, and WLDS shown in FIG. 9D are VREAD3_1 or VREAD3_1b in the verify operation of each of the write loops Loop1 to LoopM. Here, VVREAD3_1b is a voltage higher than READ3_1. In the initial write loop of the write stage, the word line driver 21 applies a relatively low verify read voltage VREAD3_1 to the unselected word lines 0 to WLk-3, 0 to WLk + 3, WLDD, and WLDS. At some point in the write stage, the word line driver 21 applies a relatively high verify read voltage VREAD3_1b to the unselected word lines 0 to WLk-3, 0 to WLk + 3, WLDD, and WLDS.

  In this way, at some point during the first write stage, the verify read voltages of the unselected word lines 0 to WLk−3, 0 to WLk + 3, WLDD, and WLDS step up from VREAD3_1 to VREAD3_1b. As a result, many of the selected memory cells with fast writing already pass verification in the write loop using the verify read voltage VREAD3_1. These selected memory cells that are fast to write apparently pass verification with a low verify level VL0 ″.

  On the other hand, the selected memory cell which is slow in writing is verified in the write loop using the verify read voltage VREAD3_1b. These slow-programmed selected memory cells apparently pass verify when the high verify level VL1 ″ is exceeded. As a result, as shown in FIG. 10C, the threshold voltage of the slow-programmed selected memory cell The overlapping region between the distribution Dpb3 and the threshold voltage distribution Dpa3 of the selected memory cell with fast writing becomes large, and the width of the entire threshold voltage distribution Dp3 becomes narrow.

  As described above, the NAND flash memory according to the third embodiment apparently lowers the verify level in the initial write loop of the write stage, and increases the verify level in the write loop in the middle of the write stage. The threshold voltage distribution of the subsequent memory cell can be narrowed. By narrowing the threshold voltage distribution of the memory cell after writing, the third embodiment can suppress an increase in the writing voltage or the reading voltage without changing the ECC correction capability. Therefore, the third embodiment can suppress an increase in chip size.

  With the recent miniaturization of memory cells and increase in memory capacity, the number of memory cells MC included in each NAND string NS is increasing. In such a situation, the ON resistance of the entire NAND string NS has more unselected memory cells MC0 to MCk−1, MCk + 1 to MCn, MCDD than the verify read voltage VCG applied to a single selected memory cell MCk. , And may vary greatly depending on the verify read voltage VREAD applied to the MCDS. Therefore, the threshold voltage distribution Dp3 can be effectively narrowed by changing the verify read voltage VREAD in the middle of the write stage.

  The voltage differences ΔVREAD1_1 to ΔVREAD1_3 depend on the gate interval between adjacent memory cells MC. For example, in the generation where the interval between adjacent gates is about 30 nm, the voltage differences ΔVREAD1_1 to ΔVREAD1_3 are preferably 0.4V to 0.6V. In the generation in which the distance between adjacent gates is about 25 nm, the voltage differences ΔVREAD1_1 to ΔVREAD1_3 are preferably 0.3V to 0.4V. In the generation in which the distance between adjacent gates is about 20 nm, the voltage differences ΔVREAD1_1 to ΔVREAD1_3 are preferably 0.2V to 0.3V. The voltage differences ΔVREAD1_1 to ΔVREAD1_3 may be equal to each other.

  The write loop Loopj (1 ≦ j ≦ M) for changing the verify read voltages VREAD1_1 to VREAD3_1 is preferably an intermediate write loop among all the write loops. That is, j is preferably an integer around M / 2. However, when the data writing stage and erasing are repeated in the memory cell, charges trapped in the tunnel insulating film between the floating gate FG and the body region are generated, so that the number of write loops in the write stage tends to decrease. There is. Considering this charge trapping, the write loop Loopj for changing the verify read voltages VREAD1_1 to VREAD3_1 is preferably a write loop slightly before the middle of all the write loops. That is, j is preferably an integer smaller than M / 2.

  In the present embodiment, the word line driver 21 steps up the verify read voltages VREAD1_1 to VREAD3_1 only once during the write stage. However, the number of times each of the refinement voltages VREAD1_1 to VREAD3_1 is changed in each write stage is not limited. The word line driver 21 may increase the verify read voltages VREAD1_1 to VREAD3_1 twice or more during the write stage. For example, the word line driver 21 may increase the verify read voltages VREAD1_1 to VREAD3_1 in each of the write loops Loop1 to LoopM. In this case, it is necessary to set the verify read voltages VREAD1_1 to VREAD3_1 finely in multiple stages. However, the width of the threshold voltage distribution Dp3 of the selected memory cell can be narrowed more effectively, and variations in threshold voltage can be further suppressed. . The step-up widths of the verify read voltages VREAD1_1 to VREAD3_1 are preferably equal in each write loop. For example, if the verify read voltage rising in a certain write stage is ΔVREADL, the step-up width of the verify read voltages VREAD1_1 to VREAD3_1 in each of the write loops Loop1 to LoopM may be ΔVREADL / (M−1).

  Although the first write stage has been described above, the verify read voltage may be similarly raised during the write stage for the second write stage. That is, in the third embodiment, the verify read voltage of the non-selected word line is increased in the second write stage as compared with the first write stage, and the verify read voltage is set in the middle of the first and second write stages. Step up.

  FIG. 11A to FIG. 11D are graphs showing the transition of the voltage of the word line in the second write stage of the third embodiment. Since FIG. 11A is the same as FIG. 9A, description thereof is omitted.

  In FIG. 11B, the voltages of the non-selected word lines WLk−1 and WLk + 1 adjacent to the nearest selected word line WLk are raised from VREAD2_1 to VREAD2_1b in the middle of the second write stage. VREAD2_1 is a higher voltage than VREAD1_1, and VREAD2_1b is a higher voltage than VREAD1_1b. ΔREAD2-1 is the difference between VREAD2_1 and VREAD2_1b.

  In FIG. 11C, the voltages of the non-selected word lines WLk-2 and WLk + 2 that are the second closest to the selected word line WLk are raised from VREAD2_2 to VREAD2_2b in the middle of the second write stage. VREAD2_2 is a voltage higher than VREAD1_2, and VREAD2_2b is a voltage higher than VREAD1_2b. Note that ΔREAD2-2 is the difference between VREAD2_2 and VREAD2_2b.

  In FIG. 11D, the voltages of the other non-selected word lines WL0 to WLk-3, WLk + 3 to WLn, WLDD, and WLDS are raised from VREAD2_3 to VREAD2_3b in the middle of the second write stage. VREAD2_3 is a voltage higher than VREAD1_3, and VREAD2_3b is a voltage higher than VREAD1_3b. ΔREAD2-3 is the difference between VREAD2_3 and VREAD2_3b.

  Thereby, the third embodiment can obtain the effects of the first embodiment, and can further narrow the threshold distribution of the memory cell MC after writing as described above.

  The third embodiment can be applied not only to the first embodiment but also to the second embodiment. That is, in the third embodiment, data may be written to the memory cell MC by executing the first to third write stages. In this case, the verify read voltage may be raised even during the third write stage. Thereby, 3rd Embodiment can also acquire the effect of 2nd Embodiment.

  Note that also in the third embodiment, the word line driver 21 may decrease the resistance values of only the non-selected memory cells MCk−1 and MCk + 1. Further, the word line driver 21 determines whether or not to increase the verify read voltage of the unselected word lines WLk−1 and WLk + 1 according to the state of the data stored in the unselected memory cells MCk−1 and MCk + 1. Also good.

  The word line driver 21 may increase the verify read voltage after executing the write loop the same number of times in the first to third write stages. However, the word line driver 21 increases the verify read voltage after executing the write loop a different number of times. May be high.

BL ... bit line, WL0 to WLn ... word line, MC0 to MCn ... memory cell, WLDD, WLDS ... dummy word line, Tsel, Rsels ... select transistor, NS ... NAND string, select voltage (control gate voltage) ... VCG, VREAD1_1 ~ VREAD3_3 ... Verify read voltage

Claims (6)

Multiple word lines,
Multiple bit lines,
A plurality of memory cells having gates connected to any of the word lines;
A word line driver for driving voltages of the plurality of word lines;
A sense amplifier that detects data of the memory cell via the plurality of bit lines;
A plurality of the memory cells are connected in series between the bit line and the source to form a cell string,
A write loop consisting of a write operation for writing data to a selected memory cell in the cell string and a verify read operation for verifying that data has been written to the selected memory cell is repeated a plurality of times to cause the selected memory cell to A plurality of bit data by executing a first write stage that enters a state and a second write stage that repeats the write loop a plurality of times to bring the selected memory cell from the first state to the second state Is stored in the selected memory cell,
When the second write stage is executed on the selected memory cell, the word line driver is not selected memory other than the selected memory cell than when the first write stage is executed on the selected memory cell. A semiconductor memory device characterized in that a voltage at the time of the verify read operation applied to any one of the cells is increased.   The word line driver applies a selection voltage to the selected memory cell during the verify read operation, and applies a first voltage higher than the selection voltage to a first non-selected memory cell adjacent to the selected memory cell. A verify read voltage is applied, a second verify read voltage higher than the first verify read voltage is applied to a second non-selected memory cell that is the second closest to the selected memory cell, and 3 second from the selected memory cell. 2. The third verify read voltage that is higher than the first verify read voltage and lower than the second verify read voltage is applied to the third non-selected memory cell that is closest to the second. Semiconductor memory device. Executing a third write stage after the first and second write stages, by repeating the write loop a plurality of times to bring the selected memory cell from the second state to the third state; Storing bit data in the selected memory cell;
When the third write stage is executed on the selected memory cell, the word line driver is not selected memory other than the selected memory cell than when the second write stage is executed on the selected memory cell. 3. The semiconductor memory device according to claim 1, wherein a voltage during the verify read operation applied to any one of the cells is increased.   At the time of a verify operation in a certain write loop in the write stage, the word line driver increases the voltage at the time of the verify read operation of any non-selected word line connected to the non-selected memory cell. The semiconductor memory device according to claim 1, wherein:   The word line driver is applied to all the unselected memory cells when the second write stage is performed on the selected memory cell, rather than when the first write stage is performed on the selected memory cell. 5. The semiconductor memory device according to claim 1, wherein a voltage during the verify read operation is increased. 6.   The word line driver raises the first verify read voltage when the second write stage is executed on the selected memory cell than when the first write stage is executed on the selected memory cell. 5. The semiconductor memory device according to claim 2, wherein the second and third verify read voltages are not changed. 6.

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