JP2006172240A - Data processing system and memory control method for the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress delay in the processing of a microprocessor and complication in the structure of a memory controller, in burst transfer in mixed different operation modes. <P>SOLUTION: A data processing system 10 comprises the microprocessor 11 for executing burst transfer in mixed different operation modes, a synchronous burst memory 13 having a mode register 14 for a setting of the operation mode of the burst transfer, and the memory controller 12 for arbitrating access between the synchronous burst memory 13 and the microprocessor 11. The memory controller 12 has a function of outputting a wrap switch signal 21 via an output terminal 22. The synchronous burst memory 13 has a function of inputting the wrap switch signal 21 via an input terminal 23 from the memory controller 12 and setting an operation mode depending on the wrap switch signal 21 in the mode register 14. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a data processing system that executes burst transfer in which increment burst transfer and wrap burst transfer are mixed, and a memory control method therefor.

  In recent years, since microprocessors have been operating faster than externally connected memories, it has become necessary to reduce the latency of the microprocessor as much as possible. In response to this, there is known a microprocessor that efficiently performs burst transfer by mixing two types of increment burst transfer and wrap burst transfer in order to increase data transfer speed (for example, patents). Reference 1). Incrementing burst transfer is a burst transfer method in which an address is incremented from a start address and burst transfer is performed. Wrapped burst transfer is a burst transfer method in which burst transfer is started from an intermediate address regardless of the burst transfer boundary, and wraparound operation is performed at the burst transfer boundary.

  FIG. 3 is a block diagram showing a conventional example of a data processing system using such a microprocessor. Hereinafter, description will be given based on this drawing.

  The conventional data processing system 50 includes a microprocessor 51, a synchronous burst memory 53, and a memory controller 52 that arbitrates access therebetween. Each interface includes control buses 55 and 56, address buses 57 and 58, data buses 59 and 60, and the like, which are used for burst transfer.

  The synchronous burst memory 53 includes a mode register 54 for setting an operation mode of burst transfer. In the mode register 54, as shown in the burst sequence correspondence table of FIG. 4, there are a BST bit for setting a burst length and a WP bit for setting a wraparound operation. By setting these bits, the burst transfer method can be set. In this case, when burst access is made from the microprocessor 51 to the synchronous burst memory 53, it is necessary to set the burst transfer operation mode in advance for the synchronous burst memory 53 before the burst transfer is started.

  At this time, in the data processing system 50 in which the increment burst transfer and the wrap burst transfer are mixed, the following two memory control methods can be considered depending on whether or not the setting of the mode register 54 is changed during the burst transfer.

  As a first memory control method, in order to change the setting of the mode register 54 during burst transfer, the burst transfer operation mode of the synchronous burst memory 53 is changed from the microprocessor 51 for each transfer according to the burst transfer method. It is possible to do.

  However, it is necessary to set the operation mode of burst transfer from the microprocessor 51 to both the memory controller 52 and the synchronous burst memory 53. If these modes are not set at the same time, normal access cannot be made. Therefore, since the burst transfer operation mode must be changed for both the memory controller 52 and the synchronous burst memory 53 in a state where the burst transfer is temporarily stopped, there arises a problem that the processing of the microprocessor 51 is delayed. .

  As a second memory control method, without changing the setting of the mode register 54 during the burst transfer, the memory controller 52 arbitrates the increment burst transfer or the wrap burst transfer output from the microprocessor 51, and the synchronous type It is conceivable to control an access signal to the burst memory 53. The memory controller 52 inputs each access signal from the microprocessor 51 via the control bus 55, the address bus 57 and the data bus 59, and adjusts the access timing according to the operation timing of the synchronous burst memory 53, while controlling the control bus. 56, each access signal is output to the synchronous burst memory 53 via the address bus 58 and the data bus 60. At this time, one of the burst transfer methods of increment burst transfer or wrap burst transfer is transmitted to the memory controller 52 by the control signal of the control bus 55 output from the microprocessor 51.

  However, in the conventional synchronous burst memory 53, the presence or absence of the wrap-around operation needs to be set in advance for the mode register 54 before the burst transfer is started. Therefore, since the operation mode on the side of the synchronous burst memory 53 is fixed in advance, the increment burst transfer or the wrap burst transfer output from the microprocessor 10 is adjusted by the memory controller 52, and the synchronous burst memory 53 is adjusted. It is necessary to output an access signal to the memory 53.

  For example, as shown in FIG. 4, before starting data transfer, the wraparound setting bit of the mode register 54 of the synchronous burst memory 53 is set to wraparound operation (WP = 1), and the burst length setting is set to 8 burst. Assume that the mode (BST = 1) is set. In this case, when the increment burst transfer is generated from the microprocessor 51, the synchronous burst memory 53 side is set to 0-1-2-3-4-5-6-7, 1-2-3-4 by the burst start address. -5-6-7-0, 2-3-4-5-6-7-0-1, 3-4-5-6-7-0-1-2, 4-5-6-7-0 -1-2-3, 5-6-7-0-1-2-3-4, 6-7-0-1-2-3-4-5, 7-0-1-2-3-4 Wrap around like -5-6.

  Therefore, when the start address for the synchronous burst memory 53 is 1 to 7, the memory controller 52 is 1-2-3-4-5-6-7 → stop → 8, 2-3-4- 5-6-7 → Stop → 8-9, 3-4-5-6-7 → Stop → 8-9-10, 4-5-6-7 → Stop → 8-9-10-11, 5- 6-7 → Stop → 8-9-10-11-12, 6-7 → Stop → 8-9-10-11-12-13, 7 → Stop → 8-9-10-11-12-13- As shown in FIG. 14, it is necessary to perform an arbitration operation divided into two burst transfers, in which burst transfer is temporarily stopped at the burst transfer boundary, the increment start address is output, and the remaining burst transfer is executed.

  As described above, even in the second memory control method, access time from the memory controller 52 to the synchronous burst memory 53 is wasted along with this arbitration operation, and thus, an access waiting time of the microprocessor 51 is generated. .

  Further, as described above, in the memory controller 52 having the arbitration operation function, there arises a problem that the circuit scale increases because the control becomes complicated. Further, when a plurality of synchronous burst memories 53 having different burst lengths are connected, the memory controller 52 needs to perform an arbitration operation corresponding to the combination of the burst length type and the burst transfer type, so that the arbitration circuit is complicated. This causes a problem that the circuit scale further increases.

JP 2000-29775 A

  In the conventional synchronous burst memory 53, a burst length, a wrap operation mode, and the like are set by setting a mode register 54 that is an internal register thereof. Since the setting of the mode register 54 is executed by the mode register setting sequence, the burst transfer method must be determined in advance before the start of the burst transfer, so the burst transfer method cannot be changed during the burst transfer. . That is, the burst transfer method cannot be changed unless the burst transfer is temporarily stopped.

  Therefore, in the data processing system 50 in which the increment burst transfer and the wrap burst transfer are mixed, the memory controller 52 having the function of arbitrating the burst transfer between the microprocessor 51 and the synchronous burst memory 53 is required. . In the memory controller 52, when the synchronous burst memory 53 is set to the incremental burst transfer system before the burst transfer, when the microprocessor 51 receives a wrap burst transfer access, it wraps at the burst transfer boundary on the microprocessor 51 side. It is necessary to execute an arbitration operation that operates around. On the other hand, when the synchronous burst memory 53 is set to the wrap / burst transfer method before the burst transfer, when the microprocessor 51 receives an increment burst transfer, the wraparound is performed at the burst transfer boundary on the synchronous burst memory 53 side. Instead, an arbitration operation to access the increment address must be performed. During these access arbitration operations, the microprocessor 51 has to wait for processing, so that the processing of the microprocessor 51 is delayed.

  Further, the memory controller 52 requires complicated control in order to realize this access arbitration operation function, and there is a problem that the circuit scale increases.

  That is, in the conventional data processing system 50, if the setting of the mode register 54 and the operation mode from the microprocessor 51 are different, an arbitration operation by the memory controller 52 is required, so that the processing of the microprocessor 51 is delayed. There is a problem that the configuration of the memory controller 52 becomes complicated in order to realize the arbitration operation function.

  Accordingly, an object of the present invention is to provide a data processing system or the like that can suppress delay in processing of the microprocessor and complication of the configuration of the memory controller in burst transfer in which increment burst transfer and wrap burst transfer are mixed. There is to do.

  A data processing system according to the present invention includes a microprocessor that performs burst transfer in which different operation modes of increment burst transfer and wrap burst transfer are mixed, and a synchronization having a mode register in which the operation mode of burst transfer is set And a memory controller that arbitrates access between the synchronous burst memory and the microprocessor. The memory controller has a function of outputting a lap switching signal. The synchronous burst memory has a function of inputting a lap switching signal from a memory controller and setting an operation mode in a mode register in accordance with the wrap switching signal. At this time, the memory controller may have an output terminal for outputting a wrap switching signal. The synchronous burst memory may have an input terminal for inputting a wrap switching signal.

  For example, when an access signal for increment burst transfer is input from the microprocessor, the memory controller outputs a wrap switching signal for setting increment burst transfer to the mode register, and an access signal for wrap burst transfer from the microprocessor. When input, a wrap switching signal for setting wrap / burst transfer is output to the mode register.

  Conventionally, setting of a mode register of a synchronous burst memory is executed by a mode register setting sequence. According to this mode register setting sequence, the mode register must be set in advance before the start of burst transfer. Therefore, when burst transfer is performed from the microprocessor in an operation mode different from the mode register setting, an arbitration operation by the memory controller is required. As a result, the processing of the microprocessor is delayed and the configuration of the memory controller is complicated.

  Therefore, in the present invention, the lap switching signal is output from the memory controller without using the conventional mode register setting sequence, and the mode register is set according to the wrap switching signal. Therefore, the arbitration operation by the memory controller becomes unnecessary, so that the processing delay of the microprocessor and the complexity of the configuration of the memory controller can be suppressed.

  The data processing system according to the present invention may be as follows. The synchronous burst memory includes a plurality of synchronous burst memories having different burst lengths. Each of the plurality of synchronous burst memories is connected to a memory controller. In each mode register of the plurality of synchronous burst memories, an operation mode is set by a wrap switching signal and a burst length is set in advance.

  Conventionally, in a memory controller, when a plurality of synchronous burst memories having different burst lengths are connected, burst transfer control has become extremely complicated due to an increase in combinations of operation modes and burst lengths. Therefore, the present invention uses a synchronous burst memory in which a burst length is set in advance in the mode register and the operation mode of the mode register is switched every burst transfer. This simplifies the configuration because the memory controller only needs to arbitrate memory access in accordance with the burst length setting.

  The memory control method according to the present invention captures the operation of the data processing system according to the present invention as a method.

  Furthermore, the present invention can be paraphrased as follows in a synchronous burst memory having a function of switching a wrapping operation. This is a memory control system characterized in that the lap operation is immediately switched by a control signal from the outside. Specifically, it is characterized by reducing the waiting time of access to the external memory of the microprocessor in a system in which increment burst transfer and wrap burst transfer are mixed by switching the wrap operation immediately by an external control signal. This is a memory control method. Furthermore, the present invention can also be understood as shown below.

  1. In a system in which increment burst transfer and wrap burst transfer from a microprocessor to an external memory coexist, burst can be achieved by using a system that connects a synchronous burst memory with an external terminal that switches the wrap operation for each burst transfer. The waste of memory access time due to divided transfer at the transfer boundary may be eliminated, and the waiting time for accessing the external memory of the microprocessor may be reduced.

  2. In a system in which increment burst transfer and wrap burst transfer from a microprocessor to an external memory coexist, by using a system that connects a synchronous burst memory having an external terminal that switches the wrap operation for each burst transfer, the memory The burst transfer control circuit of the controller may be simplified to reduce the circuit scale.

  3. Burst transfer complicated by combination of burst length and burst transfer operation in a system where multiple external memories with different burst lengths are connected and increment burst transfer and wrap burst transfer from the microprocessor to the external memory coexist The control circuit may be simplified by using a system that connects a synchronous burst memory having an external terminal for switching the wrapping operation for each burst transfer, and the circuit scale may be reduced.

  According to the present invention, the memory controller outputs a lap switching signal from the memory controller without using the conventional mode register setting sequence, and sets the mode register of the synchronous burst memory in accordance with the wrap switching signal. Since the arbitration operation is unnecessary, it is possible to achieve a high-speed processing of the microprocessor and a simple configuration of the memory controller. In other words, the present invention has the following effects.

  1. In a system in which increment burst transfer and wrap burst transfer are mixed from the microprocessor to the memory, a synchronous burst memory with an external terminal that switches the wrap operation for each burst transfer can be connected to each burst transfer. The lap operation can be switched immediately. In addition, in the burst transfer arbitration circuit of the memory controller that performs arbitration between increment burst transfer and wrap burst transfer from the microprocessor, control for interrupting burst transfer at the burst transfer boundary and performing divided transfer becomes unnecessary. It is possible to reduce the waiting time of the microprocessor due to the increase in the memory access time due to the divided transfer.

  2. Since a complicated wraparound control circuit for arbitrating the increment burst transfer and the wrap burst transfer from the microprocessor and outputting them to the synchronous burst memory becomes unnecessary, the circuit scale of the memory controller can be reduced.

  3. Conventionally, when a plurality of external memories having different burst lengths are connected, the memory controller becomes complicated in circuit and increases in scale. This is because a circuit that arbitrates increment burst transfer and wrap burst transfer from a microprocessor to multiple external memories requires arbitration operation in the amount of a combination of burst length type and burst transfer type. is there. In contrast, in the present invention, since the burst transfer wraparound control can be immediately transmitted from the microprocessor to the external memory, the memory controller only has to arbitrate the memory access in accordance with the burst length setting. The control circuit can be simplified. In addition, since the memory controller can be used for a general purpose, a plurality of memories having different burst lengths can be used in the memory access arbitration circuit in which the wraparound control circuit is simplified.

  FIG. 1 is a block diagram showing a first embodiment of a data processing system according to the present invention. Hereinafter, description will be given based on this drawing.

  The data processing system 10 of this embodiment includes a microprocessor 11 that executes burst transfer in which different operation modes of increment burst transfer and wrap burst transfer are mixed, and a mode register 14 in which the operation mode of burst transfer is set. And a memory controller 12 that arbitrates access between the synchronous burst memory 13 and the microprocessor 11. The memory controller 12 has a function of outputting the lap switching signal 21 via the output terminal 22. The synchronous burst memory 13 has a function of inputting a lap switching signal 21 from the memory controller 12 via the input terminal 23 and setting an operation mode in the mode register 14 in accordance with the lap switching signal 21.

  When the memory controller 12 receives the increment burst transfer access signal from the microprocessor 11, the memory controller 12 outputs a wrap switching signal 21 for setting the increment burst transfer to the mode register 14, and the microprocessor 11 outputs the wrap burst transfer signal. When an access signal is input, a wrap switching signal 21 for setting wrap / burst transfer is output to the mode register 14.

  Between the memory controller 12 and the synchronous burst memory 13, a line of the wrap switching signal 21 is connected so that the wraparound setting bit (WR bit: FIG. 4) of the mode register 14 can be input from the outside as a control signal. A book has been added. Each interface is provided with control buses 15 and 16, address buses 17 and 18, and data buses 19 and 20, and a wrap switching signal 21 causes the memory controller 12 to perform a burst transfer operation of the synchronous burst memory 13 for each burst transfer. To control.

  Here, referring to FIG. 3, the setting of the mode register 54 of the synchronous burst memory 53 is conventionally performed by a mode register setting sequence. According to this mode register setting sequence, the mode register 54 must be set in advance before the start of burst transfer. Therefore, when burst transfer is performed from the microprocessor 51 in an operation mode different from the setting of the mode register 54, an arbitration operation by the memory controller 52 is required. As a result, the processing of the microprocessor 51 is delayed and the configuration of the memory controller 52 is complicated.

  Therefore, in the present invention, the lap switching signal 21 is output from the memory controller 12 without using the conventional mode register setting sequence, and the mode register 14 is set according to the wrap switching signal 21. Therefore, since the arbitration operation by the memory controller 12 is not necessary, processing delay of the microprocessor 11 and complication of the configuration of the memory controller 12 can be suppressed.

  Next, the data processing system 10 will be described in more detail.

  By setting the mode register 14 of the synchronous burst memory 13 before the start of burst transfer, only the burst length (BST bit) is set. When a memory access occurs from the microprocessor 11, the memory controller 12 determines whether it is an increment burst transfer or a wrap burst transfer based on a control signal input from the control bus 15, and wraps around according to the operation mode for each burst transfer. A lap switching signal 21 is output as a control signal for switching the operation. The memory controller 12 inputs an access signal from the microprocessor 11 via the control bus 15, the address bus 17 and the data bus 19, and controls the access timing in accordance with the operation timing of the synchronous burst memory 13. Each access signal is output to the synchronous burst memory 13 via the bus 16, address bus 18, data bus 20, and wrap switching signal 21 lines. The synchronous burst memory 13 captures the burst start address at the same time when burst transfer is started, and simultaneously captures the wrap switch signal 21, discriminates the operation mode for each burst transfer, and switches the wraparound operation.

  According to the present embodiment, in the data processing system 10 that employs a data transfer method in which increment burst transfer and wrap burst transfer are mixed from the microprocessor 11 to the synchronous burst memory 13, a wrap operation is performed for each burst transfer. By using the synchronous burst memory 13 having the input terminal 23 for switching the wrapping operation, it is possible to immediately switch the wrap operation for each burst transfer. The burst transfer arbitration circuit of the memory controller 12 that arbitrates between increment burst transfer and wrap burst transfer from the microprocessor 11 does not require control for interrupting burst transfer at the burst transfer boundary and performing divided transfer. Therefore, it is possible to reduce the waiting time of the microprocessor 11 due to the increase in the memory access time due to the divided transfer. Further, since a complicated wraparound control circuit for arbitrating increment burst transfer and wrap burst transfer from the microprocessor 11 and outputting the same to the synchronous burst memory 13 is not required, the circuit scale of the memory controller 12 is reduced. It becomes possible.

  FIG. 2 is a block diagram showing a second embodiment of the data processing system according to the present invention. Hereinafter, description will be given based on this drawing. However, the same parts as those in FIG.

  The data processing system 30 of this embodiment has the following features. The synchronous burst memories 13 and 33 have different burst lengths and are connected to the memory controller 12. In each of the mode registers 14 and 34 of the synchronous burst memories 13 and 33, an operation mode is set by a lap switching signal 21 and a burst length is set in advance.

  Conventionally, in a memory controller, when a plurality of synchronous burst memories having different burst lengths are connected, burst transfer control has become extremely complicated due to an increase in combinations of operation modes and burst lengths. Therefore, in the present embodiment, the synchronous burst memories 13 and 33 are used in which the burst length is set in the mode registers 14 and 34 in advance, and the operation mode of the mode registers 14 and 34 is switched every burst transfer. As a result, the memory controller 12 only has to arbitrate memory access in accordance with the burst length setting, so that the configuration is simplified.

  Needless to say, the present invention is not limited to the first and second embodiments. For example, in the second embodiment, two synchronous burst memories are used, but three or more synchronous burst memories may be used.

1 is a block diagram showing a first embodiment of a data processing system according to the present invention. It is a block diagram which shows 2nd embodiment of the data processing system which concerns on this invention. It is a block diagram which shows the conventional data processing system. It is a chart which shows burst sequence correspondence.

Explanation of symbols

10, 30 Data processing system 11 Microprocessor 12 Memory controller 13, 33 Synchronous burst memory 14, 34 Mode register 15, 16 Control bus 17, 18 Address bus 19, 20 Data bus 21 Lap switching signal

Claims (6)

A microprocessor that performs burst transfer in which different operation modes of increment burst transfer and wrap burst transfer are mixed, a synchronous burst memory having a mode register in which the operation mode of the burst transfer is set, and this synchronization In a data processing system comprising: a memory controller that arbitrates access between a burst memory and the microprocessor;
The memory controller has a function of outputting a wrap switching signal. The synchronous burst memory receives the wrap switching signal from the memory controller and sets the operation mode in the mode register according to the wrap switching signal. Have the ability to
A data processing system characterized by that. The memory controller has an output terminal for outputting the wrap switching signal.The synchronous burst memory has an input terminal for inputting the wrap switching signal.
The data processing system according to claim 1. When the memory controller inputs an access signal for increment burst transfer from the microprocessor, the memory controller outputs the wrap switching signal for setting increment burst transfer to the mode register, and the wrap burst transfer from the microprocessor. When an access signal is input, the wrap switching signal for setting wrap burst transfer is output to the mode register.
The data processing system according to claim 1 or 2. The synchronous burst memory includes a plurality of synchronous burst memories having different burst lengths, and each of the plurality of synchronous burst memories is connected to the memory controller,
In each mode register of the plurality of synchronous burst memories, an operation mode is set by the wrap switching signal, and the burst length is preset.
The data processing system according to claim 1.
A microprocessor that performs burst transfer in which different operation modes of increment burst transfer and wrap burst transfer are mixed, a synchronous burst memory having a mode register in which the operation mode of the burst transfer is set, and this synchronization In a memory control method used in a data processing system, comprising: a memory controller that arbitrates access between a burst memory and the microprocessor;
The memory controller outputs a lap switching signal,
The synchronous burst memory receives a lap switching signal from the memory controller, and sets the operation mode in the mode register according to the wrap switching signal.
And a memory control method. When an access signal for increment burst transfer is input from the microprocessor, the memory controller outputs the wrap switching signal for setting increment burst transfer to the mode register, and the wrap burst transfer from the microprocessor. When an access signal is input, the wrap switching signal for setting wrap burst transfer is output to the mode register.
The memory control method according to claim 5.

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