JP2006133258A - Electro-optical device substrate, electro-optical device, electronic apparatus, and electro-optical device substrate inspection method - Google Patents

Abstract

A substrate for an electro-optical device and an inspection method thereof that can realize an inspection with sufficient measurement accuracy without requiring contact with an external probe.
A substrate according to the present invention has a first region and a second region, and a signal line for supplying a first potential signal to a plurality of pixels via each of a plurality of switching elements in each region. A video line 7 and a transmission gate portion 6 for writing through. Each signal line in the first and second regions is electrically disconnected. Further, the substrate 1 is written to the pixel and the display data reading circuit section 4 including the differential amplifier 4a that outputs the lower potential lower and the higher potential higher to the signal line. The transmission gate unit 6 and the video line 7 for reading out the first potential signal and the reference second potential signal.
[Selection] Figure 1

Description

  The present invention relates to a substrate for an electro-optical device, an electro-optical device, an electronic apparatus, and a method for inspecting a substrate for an electro-optical device, and in particular, includes a plurality of switching elements respectively provided in a plurality of pixels and two signal lines. The present invention relates to a method for inspecting a substrate for an electro-optical device, an electro-optical device, an electronic apparatus, and a substrate for an electro-optical device that are divided into two.

Conventionally, display devices such as liquid crystal devices have been widely used in devices such as mobile phones and projectors. 2. Description of the Related Art A liquid crystal display device using a TFT (Thin Film Transistor) or the like is configured by bonding a TFT substrate and a counter substrate and enclosing liquid crystal between the substrates. In general, an inspection of whether a manufactured liquid crystal device operates normally is performed on a finished product. For example, a predetermined image signal is input to the liquid crystal device as display data, and projected, displayed, etc., to check whether the data is correctly displayed or whether there is a defective pixel.
However, the method of inspecting a finished product is not preferable from the viewpoint of management of the manufacturing process. The reason is that a defective product is found after the substrate manufacturing process, so that the detection of the defective product is delayed.

For this reason, the time until defect detection is fed back to the process management becomes longer. As a result, the yield reduction period becomes longer and the manufacturing cost increases. Also, in the case of a prototype, since the period from the evaluation of the prototype to the feedback to the design is prolonged, the development period is prolonged and the development cost is increased. Furthermore, after the product is completed, so-called repair, that is, repair of a defective portion is difficult.
Therefore, it is desired to find a defect, particularly a defective pixel of a display device, in the manufacturing process of the substrate.

  As one of such inspection methods, there has been proposed a technique for inspecting a liquid crystal display device by bringing a test probe into contact with an electrode pad of the liquid crystal display device and supplying a predetermined current (for example, a patent). Reference 1). Similarly, a technique has been proposed in which a predetermined voltage is applied to each pixel of the TFT substrate based on the capacitor capacitance characteristics of the pixel, and the function of the TFT is inspected based on the waveforms of the discharge current and the discharge voltage (for example, Patent Documents). 2).

In addition, a technique has been proposed in which an operation inspection of each pixel electrode is performed by detecting the amount of change in the potential of the pixel electrode using a counter electrode for inspection corresponding to the pixel electrode of the TFT substrate (for example, Patent Literature 3).
JP-A-5-341302 Japanese Unexamined Patent Publication No. 7-333278 Japanese Patent Laid-Open No. 10-104563

  However, in the case of the techniques described in Patent Document 1 and Patent Document 3 described above, in the inspection apparatus, mechanical positional accuracy is required to bring a predetermined probe or the like into contact with or close to an electrode pad or the like from the outside of the substrate. . As a result, there is a problem that the inspection time becomes long in order to ensure mechanical alignment accuracy. Furthermore, in the case of a high-definition liquid crystal display device, a thin probe or the like must be brought into contact with many electrode pads by performing mechanical control, and these methods may not be applied.

  Further, in the method described in Patent Document 2 described above, various capacitance components between the liquid crystal display device and the measurement device, for example, the capacitance in the source line, the video line, the electrode pad terminal, and the like are affected, so that the capacitance of the pixel itself is relatively low. If it is small, there is a problem that sufficient measurement accuracy cannot be obtained.

  The present invention has been made in view of the above points, and provides an electro-optical device substrate that does not require contact with an external probe and that can realize inspection with sufficient measurement accuracy. With the goal.

The electro-optical device substrate of the present invention includes a plurality of scanning lines, a plurality of first signal lines intersecting with the plurality of scanning lines, and the plurality of scanning lines intersecting with the first signal lines. A matrix shape corresponding to intersections of the plurality of second signal lines that are electrically disconnected, the plurality of scanning lines, the plurality of first signal lines, and the plurality of second signal lines. A plurality of pixels arranged in correspondence with the plurality of pixels, a plurality of switching elements respectively provided corresponding to the plurality of pixels, and a plurality of first signal lines. A plurality of first amplifying means for inputting a first potential signal of the signal line and a second potential signal as a reference potential; and provided corresponding to each of the plurality of second signal lines, A third potential signal of a plurality of second signal lines and a fourth potential signal as a reference potential; A plurality of second amplifying means for outputting, a first data reading means for reading out a first output potential signal output from each of the plurality of first amplifying means to each of the plurality of first signal lines; Second data reading means for reading a second output potential signal output from the plurality of second amplifying means to each of the plurality of second signal lines; and the plurality of first amplifying means. Each of the first potential signal and the second potential signal are compared, and when the first potential signal is low, the potential of the first signal line is made lower. The lowered first output potential signal is output to the first signal line, and when the first potential signal is high, the potential of the first signal line is made higher and higher. Outputting the first output potential signal to the first signal line; Each of the width means compares the third potential signal with the fourth potential signal, and when the third potential signal is low, lowers the potential of the second signal line, The lower second output potential signal is output to the second signal line, and when the third potential signal is high, the potential of the second signal line is increased to The increased second output potential signal is output to the second signal line.
According to such a configuration, it is not necessary to contact an external probe, and an electro-optical device substrate that can be inspected with sufficient measurement accuracy can be realized. Further, since each signal line is electrically disconnected, the capacity of the signal line is halved, so that the read potential can be increased.

In the electro-optical device substrate of the present invention, each of the first potential signal and the third potential signal is written to all or a part of the plurality of pixels through the plurality of switching elements. Preferably, each of the second potential signal and the fourth potential signal is a potential supplied from the outside.
According to such a configuration, a pixel defect can be detected as a defect for each pixel.

In the electro-optical device substrate according to the aspect of the invention, each of the first, second, third, and fourth potential signals may include all or one of the plurality of pixels via the plurality of switching elements. Each of the first, the second, the third, and the fourth potential signals has a corresponding plurality of the first and the plurality of second signal lines. It is preferable that the plurality of first amplifying units and the plurality of second amplifying units are supplied.
According to such a configuration, since the potentials of the two pixels are compared, if any of the two pixels is defective, the defect can be detected.

In the electro-optical device substrate of the present invention, it is preferable that each of the plurality of first and the plurality of second amplifying units is a differential amplifier.
In the electro-optical device substrate of the present invention, it is preferable that each of the first and second data reading units includes a differential amplifier for outputting the read potential signal.
According to such a configuration, the potential difference between the two signal lines can be clearly output.

In the electro-optical device substrate according to the aspect of the invention, it is preferable that an additional capacitor is provided for each of the plurality of pixels.
According to such a configuration, it is possible to detect a defect in the additional capacity.

In the electro-optical device substrate according to the aspect of the invention, the plurality of first and second pixels connected to the plurality of first and plurality of second signal lines, respectively, and precharge the plurality of pixels. It is desirable to have a precharge circuit.
According to such a structure, it can utilize in the test | inspection of various characteristics.

In the electro-optical device substrate according to the aspect of the invention, the first and second videos may be connected to the plurality of first and second signal lines and may supply image signals to be written to the pixels. A signal line; and a plurality of first and second transmission gates that supply the first and second signal lines with the image signals supplied from the first and second video signal lines, It is preferable that the first and second data reading means include the first and second video signal lines, respectively.
According to such a configuration, it is possible to supply an image signal to a video signal line or read an image signal by controlling a plurality of transmission gates.

In the electro-optical device of the present invention, the electro-optical device substrate of the present invention is used for one of the pair of substrates in an electro-optical device in which an electro-optical material is sandwiched between the pair of substrates.
The electronic apparatus of the present invention uses the electro-optical device of the present invention.
According to such a configuration, it is possible to realize an electro-optical device or an electronic apparatus using an electro-optical device substrate that can be inspected with sufficient measurement accuracy without requiring contact with an external probe.

  The inspection method for a substrate for an electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of first signal lines intersecting with the first scanning line among the plurality of scanning lines, and the plurality of scanning lines. The first signal line intersects with the second scanning line, is electrically disconnected from the first signal line, and is divided with respect to the dividing line extending in the direction of the scanning line. A plurality of second signal lines extending in a line symmetric direction, the plurality of scanning lines, and a plurality of first signal lines and a plurality of second signal lines in a matrix form corresponding to intersections An inspection method for a substrate for an electro-optical device, comprising: a plurality of arranged pixels; and a plurality of switching elements respectively provided corresponding to the plurality of pixels, the pixels corresponding to the first signal line The first potential signal is applied to the pixel corresponding to the second signal line, and the third potential signal is applied to the pixel corresponding to the second signal line. Each of the writing step, the step of reading the first potential signal written to the pixel, the read out first potential signal, and the first potential signal as a reference signal having a different potential. When the first potential signal is low, the potential of the first signal line is made lower and the lower first output potential signal is compared with the first potential signal. When the first potential signal is output to the signal line and the first potential signal is high, the potential of the first signal line is made higher, and the first output potential signal that is made higher is supplied to the first signal line. A first output step for outputting; a first comparison step for comparing the first potential signal written in the writing step with the first output potential signal outputted in the first output step; A step of reading the third potential signal written in the pixel; and The third potential signal is compared with a fourth potential signal as a reference signal having a potential different from that of the third potential signal, and when the third potential signal is low, the third signal If the potential of the line is made lower and the lower third output potential signal is outputted to the second signal line, and the third potential signal is high, the potential of the second signal line And a second output step for outputting the higher second output potential signal to the second signal line, the third potential signal written in the writing step, and the second potential signal. And a second comparison step of comparing the second output potential signal output in the output step.

  According to such a configuration, it is possible to realize a method for inspecting a substrate for an electro-optical device that does not require contact with an external probe and can perform inspection with sufficient measurement accuracy.

Embodiments of the present invention will be described below with reference to the drawings.
Here, as an example of the electro-optical device substrate of the present invention, an active matrix display device substrate used in a liquid crystal display device will be described as an example.

(First embodiment)
FIG. 1 is a diagram showing an arrangement of circuit elements on an element substrate of a liquid crystal display device according to a first embodiment of the present invention. The element substrate 1 of the liquid crystal display device is a TFT substrate that is a substrate for an active matrix display device. Each circuit element of the element substrate 1 is arranged on the substrate in a mirror-inverted manner with respect to a dividing line AC that divides a display element array portion 2 described later into two.
Specifically, as shown in FIG. 1, the element substrate 1 has a display element array section 2 that becomes a liquid crystal display section. The display element array unit 2 has a plurality of pixels in a matrix shape, and an image can be displayed by supplying display pixel data to each pixel. The display element array unit 2 formed in the substantially central part of the element substrate 1 is arranged in one direction of the matrix, here, in the central part of a plurality of pixels arranged in the Y direction so as to divide the display region in half. Each signal line S is electrically disconnected, and is divided so as to be driven independently in image display and inspection described later. Accordingly, the display element array section 2 is composed of two display element array sections 2A and 2B that are independent of each other. Therefore, the element substrate 1 has a plurality of separate circuit elements for independently driving the two display element array portions 2A and 2B.

As shown in FIG. 1, a region 1T on which various circuits and the like are formed on the element substrate 1 is divided into a first region 1A including the first display element array portion 2A and a second region with the dividing line AC as a boundary. It is divided into a second region 1B including the display element array portion 2B. In the first region 1A, a first display element array section 2A and a plurality of circuit elements for driving the first display element array section 2A are formed. In the second region 1B, a second display element array unit 2B and a plurality of circuit elements for driving the second display element array unit 2B are formed. In the following description, a circuit element formed in the first region 1A will be described as an upper stage circuit portion, and a circuit element formed in the second region 1B will be described as a lower stage circuit portion.
In the present embodiment, the display element array unit 2 is divided in the middle in one direction of the two-dimensional matrix, here the Y direction, that is, the signal line is electrically non-conductive, but divided in the middle. You don't have to. For example, the display area does not have to be halved. For example, the display area may be divided up and down by a ratio of 51:49, or by a ratio of 40:60. Here, the display element array section 2 is divided so as to be 50:50 in the Y direction, and the first display element array section 2A and the second display element array section 2B are divided into lines with respect to the dividing line AC. It is symmetrical.
As will be described later, in the first display element array unit 2A and the second display element array unit 2B, a plurality of scanning lines and a plurality of signal lines intersect, respectively. The plurality of signal lines and the plurality of signal lines of the second display element array portion 2B are electrically disconnected. In addition, the plurality of signal lines of the first display element array section 2A and the plurality of signal lines of the second display element array section 2B are symmetrical with respect to the dividing line AC extending in the scanning line direction. Stretch in the direction of.

  As will be described later, the display element array section 2 is divided at a dividing line AC that is a boundary line, and is divided into a first display element array section 2A and a second display element array section 2B. The plurality of pixels in the array unit 2 have a constant distance between each other in the X direction and the Y direction. As a result, the two images displayed on the first and second display element array units 2A and 2B of the display element array unit 2 driven by the respective drive circuits are separated or close to the dividing line AC. As it is, it is not visible, so it does not give the viewer a sense of incongruity.

  Conversely, the plurality of pixels in the first display element array section 2A and the second display element array section 2B have a constant distance between each other in the X direction and the Y direction, but the dividing line AC. You may make it the distance between the pixels which pinch | interpose differ from the said mutual distance.

  A plurality of circuit elements for driving the first display element array section 2A in the first region 1A are a precharge circuit section 3A, a display data read circuit section 4A, an X driver section 5A, and a Y driver section. 5A1, a transmission gate portion 6A, a video signal line 7A, and a connection gate portion 9A. In the present embodiment, as shown in FIG. 1, on the element substrate 1, a plurality of circuit elements are arranged in the first display element array section 2A and the precharge circuit section 3A in the direction D1 away from the dividing line AC. The transmission gate portion 6A, the video signal line 7A, the X driver portion 5A, the connection gate portion 9A, and the display data reading circuit portion 4A are formed in this order. The Y driver section 5B is formed on one side of the first display element array section 2A along the Y direction of the first display element array section 2A. The first display element array section 2A is driven by these multiple circuit elements.

  In FIG. 2, two video signal lines 7A are shown. However, when the image signal is phase-expanded, the number of video signal lines 7A may be as many as the number of phase expansion of the image signal. . For example, when the image signal is developed in 6 phases (six series), the number of video signal lines 7A is 6, and when the image signal is developed in 12 phases, the number of video signal lines 7A is 12.

  A plurality of circuit elements for driving the second display element array unit 2B in the second region 1B are a precharge circuit unit 3B, a display data read circuit unit 4B, an X driver unit 5B, and a Y driver unit. 5B1, a transmission gate portion 6B, a video signal line 7B, and a connection gate portion 9B. In the present embodiment, as shown in FIG. 1, on the element substrate 1, the plurality of circuit elements are in a direction opposite to the direction D <b> 1 and the first display toward the direction D <b> 2 away from the dividing line AC. The element array section 2B, precharge circuit section 3B, transmission gate section 6B, video signal line 7B, X driver section 5B, connection gate section 9B, and display data readout circuit section 4B are formed in this order. The Y driver section 5B1 is formed on one side of the second display element array section 2B along the Y direction of the second display element array section 2B. The second display element array section 2B is driven by these circuit elements. Accordingly, the arrangement of the circuit elements in the first region 1A and the arrangement of the circuit elements in the second region 1B are in a line-symmetric relationship with respect to the dividing line AC.

Next, the display element array unit 2 and a plurality of circuit elements for driving the display element array unit 2 will be described in detail with reference to FIG.
FIG. 2 is a circuit diagram showing the circuit configuration of the element substrate 1, mainly the circuit configuration of the upper circuit portion. The display element array section 2A serving as a display section is composed of cells of a plurality of pixels of m rows × n columns arranged two-dimensionally in a matrix. Here, m and n are integers. Accordingly, the display element array section 2 is composed of a plurality of pixel cells of 2m rows × n columns. In order to drive the plurality of pixels 2a arranged in the X direction (horizontal direction) and the Y direction (vertical direction) of the display element array unit 2A, the upper stage side circuit unit includes an X driver unit 5A, a Y driver unit 5A1, It also includes a transmission gate portion 6A and a video signal line 7A. The X driver unit 5A, the Y driver unit 5A1, the transmission gate unit 6A, and the video signal line 7A constitute a data writing unit and a data reading unit, respectively. The transmission gate unit 6A supplies the pixel data signal input from the video signal line 7A according to the output timing signal from the X driver unit 5A. The video signal line 7A has a signal line for supplying a signal to the odd-numbered columns of the matrix-shaped display element array section 2A and a signal line for supplying a signal to the even-numbered columns, and is connected to the respective terminals ino and ine. ing.

  The display data read circuit unit 4A is connected to the source line S output from the precharge circuit unit 3A via the connection gate unit 9A. The gate terminal of each transistor 9a of the transmission gate portion 9A is connected to the connection gate terminal 9b via a signal line 9c. Normally, since the gate terminal of the transistor 9d is HIGH because the potential of the connection gate terminal 9b is LOW, the signal line 9c is LOW, and the display data reading circuit unit 4A is disconnected from the source line. Therefore, according to the configuration of FIG. 2, when the display data reading circuit unit 4A is not used, there is an advantage that it can be completely separated so as not to be affected by the unstable operation state of the differential amplifier 4a. is there.

  As will be described later, by controlling the potential of the connection gate terminal 9b so that the potential of the signal line 9c is HIGH, the signal of the signal line S can be supplied to the display data reading circuit unit 4A.

  Further, a differential amplifier 10 including a current mirror amplifier is provided on the video signal line 7A. The purpose of this is to prevent the difference between the HIGH and LOW signals from becoming smaller due to the capacitive component of the video signal line 7A itself. The output signals outo and oute are made faster by further clarifying the HIGH and LOW signals. Output with high accuracy.

The display element array section 2A is a matrix of the first column, the second column,..., The nth column from the right and the first row, the second row,... The mth row from the top. In order to simplify the above, an example of a circuit including pixels of a matrix of 4 (rows) × 6 (columns) is shown.
As will be described later, the precharge circuit unit 3A can be used by changing the voltage at the time of precharging each pixel in order to inspect various characteristics.

  The display data read circuit unit 4A includes one differential amplifier 4a connected to a pair of source lines of an odd-numbered source line S (odd) and an even-numbered source line S (even) in a two-dimensional matrix. Are provided. A display data reading circuit portion 4A as a test circuit used at the time of inspection is formed on an element substrate of an active matrix drive type liquid crystal display panel.

  The plurality of signal lines S in the first region 1A and the plurality of signal lines S in the second region 1B are electrically disconnected. As shown in FIG. 2, the end portions STA of the plurality of signal lines S in the first region 1A and the end portions STB of the plurality of signal lines S in the second region 1B sandwich the dividing line AC. It is formed in a disconnected state.

Next, the pixel 2a that is a unit display element of the display element array unit 2A will be described. FIG. 3 is an equivalent circuit diagram of one pixel which is one memory cell according to this embodiment.
Each pixel 2a includes a thin film transistor (hereinafter referred to as TFT) 11 as a switching element, a liquid crystal capacitor Clc, and an additional capacitor Cs connected in parallel to the liquid crystal capacitor Clc. One end of each of the liquid crystal capacitor Clc and the additional capacitor Cs is connected to the drain terminal of the TFT 11. The other end of the additional capacitor Cs is connected to a common fixed potential CsCOM. The gate terminal g of the TFT 11 is connected to the scanning line G from the Y driver 5b. When a predetermined voltage signal is input to the gate terminal g of the TFT 11 and the TFT 11 is turned on, the voltage applied to the source terminal s of the TFT 11 connected to the source line S is applied to the liquid crystal capacitor Clc and the additional capacitor Cs for supply. The predetermined potential is maintained.

  FIG. 4 is a circuit diagram of the differential amplifier 4 a of the display data reading circuit unit 4. The differential amplifier 4a shown in FIG. 4 is provided (n / 2) for n pixels (n is an integer and an even number) in one direction of the two-dimensional matrix, here, the X direction. Therefore, (n / 2) differential amplifiers 4a are connected to a plurality of corresponding source lines for n columns of pixels.

  Each differential amplifier 4 a includes two P-channel transistors 21 and 22 and two N-channel transistors 23 and 24. A first series circuit composed of transistors 21 and 23 and a second series circuit composed of transistors 22 and 24 are connected in parallel. The gate terminal of the transistor 21 and the connection point so of the transistors 22 and 24 are connected. The gate terminal of the transistor 22 and the connection point se between the transistors 21 and 23 are connected. The gate terminal of the transistor 23 and the connection point so of the transistors 22 and 24 are connected. The gate terminal of the transistor 24 and the connection point se between the transistors 21 and 23 are connected. The connection point so is connected to the source lines S1, S3, S5,. The connection point se is connected to the source lines S2, S4, S6,. A connection point sp between the transistors 21 and 22 of each differential amplifier 4a is connected to a terminal 4b that supplies the first drive power source SAp-ch of the display data read circuit unit 4. A connection point sn between the transistors 23 and 24 of each differential amplifier 4a is connected to a terminal 4c that supplies the second drive power source SAn-ch of the display data read circuit unit 4.

  As will be described later, the differential amplifier 4a which is a cross-coupled amplifier as an amplifying means includes two source lines S connected to the connection points so and se, that is, an odd-numbered source line S (odd) and an even-numbered column. In the source line S (even), when a high voltage is supplied to one side and a low voltage is supplied to the other, the differential amplifier 4a has two source lines S (odd) and S ( In accordance with each voltage difference appearing in (even), the operation is performed so that the source line voltage of the lower voltage is lowered and the source line voltage of the higher voltage is further raised.

  In the differential amplifier 4a of FIG. 4, a connection point sp connected to the terminal 4b is a terminal to which a timing signal for setting the output level to a HIGH signal (hereinafter simply referred to as HIGH) is input. The connection point sn connected to the terminal 4c is a terminal to which a timing signal for setting the output level to a LOW signal (hereinafter simply referred to as LOW) is input.

  As an operation, for example, when the connection point se has a slightly higher potential than the connection point so, the transistor 24 is turned on first. As a result, since the transistor 24 is turned on, the connection point so falls to the low ground potential of the terminal 4c. Since the connection point so drops to the low ground potential of the terminal 4c, the transistor 21 whose gate end is connected to the connection point so is turned on. As a result, the connection point se rises to the high power supply voltage Vdd at the terminal 4b.

Thus, the differential amplifier 4a functions to increase the potential of the higher potential source line of two adjacent source lines and lower the potential of the lower potential source line.
In the present embodiment, one differential amplifier 4a is provided for two adjacent source lines. This is because it is easy to form the differential amplifier 4a on the element substrate 1, and when there is an external noise, both source lines are affected in the same way. Alternatively, one differential amplifier may be provided.

  According to the present embodiment, when the element substrate of the liquid crystal display device which is an active matrix display device having the above-described configuration is manufactured in the manufacturing process, the element substrate before being bonded to the counter substrate and encapsulating the liquid crystal The electrical characteristics of itself can be evaluated or inspected. Defective electrical characteristics to be inspected include LOW fixing failure due to leakage of data holding capacitor (additional capacitance Cs) of each pixel on the element substrate, and HIGH fixing failure due to leakage between TFT and source of switching element. There is.

In the second region 1B, as shown in FIG. 1, circuit elements having the same configuration as that of the first region 1A are formed in a symmetrical arrangement with respect to the dividing line AC, that is, in a so-called mirror-inverted arrangement. As described above, each signal line S is divided at the dividing line AC, and the signal line S in the display element array section 2A and the signal line S in the display element array section 2B are electrically connected. Not.
Accordingly, in order to display one image as a whole on one display unit including the display element array units 2A and 2B, each of the various circuit elements serving as drive circuits in the display element array units 2A and 2B includes: Separately, two image data obtained by dividing the one image corresponding to the display element array units 2A and 2B are supplied. That is, the image display of the first display element array unit 2A and the second display element array unit 2B is controlled separately, but the display element array unit 2 is controlled by the same display timing. Two images are displayed.

  As described above, the upper stage circuit and the lower stage circuit of the active matrix display device substrate are identical in configuration. In the inspection of the substrate for an active matrix display device configured as described above, the upper stage circuit and the lower stage circuit are separately and independently performed. Therefore, in the following description, the inspection of the upper circuit is described, and the description of the inspection of the lower circuit is omitted.

  First, before explaining the inspection of the element substrate 1 in the manufacturing process, when the TFT substrate shown in FIG. 2 is bonded to the counter substrate and the liquid crystal is sealed to complete normal image display Will be described. At this time, the potential of the connection gate terminal 9b is LOW, and the display data reading circuit unit 4A is disconnected from the source line. First, pixel data signals, which are pixel signals in odd columns and even columns, are input to the input terminals ine and ino of the video signal line 7A in the two video signal lines 7A, respectively. Each pixel data signal is supplied to each source line S via each transistor of the transmission gate portion 6A in accordance with a column selection signal from the X driver 5A.

  The pixel signal supplied to each source line S is written to each pixel 2a in the selected row when the scanning line G from the Y driver 5A1 becomes HIGH. Accordingly, in the selected scanning line G, the pixel data signal supplied to the source line S is supplied to the corresponding pixel 2a as a pixel data signal for display and held. By performing this operation in row order, a desired image is displayed on the display element array portion 2A of the liquid crystal display device. Similarly, a desired image is displayed on the display element array section 2B by performing the same display control in the lower circuit.

The precharge circuit unit 3A is a circuit for applying a precharge voltage Vpc to each source line S before the scanning line G becomes HIGH. The precharge voltage Vpc is supplied to the terminal 3a of the precharge circuit unit 3A. The timing for supplying the precharge voltage Vpc is determined by the voltage applied to the precharge gate terminal 3b.
Therefore, when an image is displayed as a liquid crystal display device as a product or a prototype, the display data reading circuit unit 4A of the element substrate 1 does not operate and is not used.

Next, an inspection procedure performed in the state of the element substrate 1 after the circuit portion shown in FIG. 2 is manufactured in the element substrate 1 by the process of the semiconductor process will be described. In the inspection of the element substrate 1, the display data reading circuit unit 4A operates and is used. At this time, the potential of the connection gate terminal 9b is HIGH, and the display data read circuit unit 4A is connected to the source line S.
First, an inspection system for realizing the inspection method will be described. FIG. 5 is a configuration diagram of the inspection system according to the present embodiment. The element substrate 1 and a test apparatus 31 capable of writing and reading pixel data are connected via a connection cable 32. The connection cable 32 includes terminals ino and ine of the data line 7A of the element substrate 1, terminals 4b and 4c of the signal line of the display data reading circuit unit 4A, terminals 3a and 3b of the precharge circuit unit 3A, and terminals of the connection gate unit 9A. 9b and the like are electrically connected to the test apparatus 31.

  The electrical characteristics of the element substrate 1 can be inspected by supplying a predetermined voltage from the test apparatus 31 to each terminal in a predetermined order described later. The procedure for inspecting the presence / absence of the above-described LOW fixing defect and HIGH fixing defect will be described below as the contents of the inspection.

Next, the overall flow of inspection will be described. FIG. 6 is a flowchart showing an example of the inspection flow.
The differential amplifiers 4a of the display data reading circuit unit 4A are brought into a non-operating state. Specifically, the first drive power supply SAp-ch and the second drive power supply SAn-ch are set to an intermediate potential (Vdd / 2) between the power supply voltage Vdd and the ground potential, respectively. In this state, a predetermined pixel data signal is input to each pixel which is a cell from the input terminals ino and ine of the video signal line 7A, that is, written (step (hereinafter abbreviated as S) 1). Specifically, HIGH is written to the odd-numbered pixels in the selected row by supplying HIGH to the odd-numbered source line S (odd) and LOW to the even-numbered source line S (even). , LOW is written to even-numbered pixels. This writing step is performed for each row, and is performed for all rows. FIG. 7 is a diagram illustrating a state of LOW (L) and HIGH (H) of pixel data written in each pixel of 4 (rows) × 6 (columns). As shown in FIG. 7, each pixel data of the display element array section 2A is a matrix in which LOW (L) columns and HIGH (H) columns alternately appear.

  Next, the written pixel data is read for each row while operating the display data reading circuit unit 4A (S2). The operation of the display data reading circuit unit 4A will be described later. As will be described later, when the display data read circuit unit 4A operates, the initial precharge period is slightly longer, so that the voltage change due to the current leakage phenomenon is ensured in the data holding capacitor (Cs). It seems to appear. That is, the display data reading circuit unit 4A executes an output process of amplifying and outputting the signal output on the signal line when reading the pixel data.

Then, the test apparatus 31 compares the pixel data read in the reading process with the pixel data written in the writing process (S3). In this comparison step, it is determined whether the pixel data written for each pixel matches the read pixel data.
The test apparatus 31 identifies a cell in which the written pixel data and the read pixel data do not match, that is, a pixel, and displays data such as a cell number as an abnormal cell on a monitor screen (not shown). Output (S4).

  Next, the reading operation of the pixel data in S2 of FIG. 6 will be described using the timing chart of FIG. FIG. 8 is a timing chart for explaining a read operation in the circuit of FIG. The pixel inspection is performed by determining whether or not the inspection target column is normal with respect to the reference column. First, the reference column is an even column, and the column to be inspected is an odd column. A signal for timing shown in FIG. 8 is generated by the test apparatus 31 and supplied to each terminal.

  First, as shown in FIG. 7, even-numbered pixels are used for writing reference data, LOW is written to even-numbered pixels, and HIGH is written to odd-numbered pixels to be inspected. Each pixel is inspected.

  As shown in FIG. 7, after the predetermined pixel data is written to all the pixels, the precharge gate voltage PCG supplied to the terminal 3b of the precharge circuit unit 3A becomes HIGH and precharge is performed. A read operation is started after a predetermined time in the precharge state. Note that the precharge potential (voltage applied to the precharge voltage application terminal 3a) Vpc of each source line S is an intermediate potential between HIGH and LOW, and the CsCOM potential shown in FIG. 3 is (LOW potential−ΔV). The CsCOM potential is set to (LOW potential−ΔV) because when the data holding capacitor Cs has a leak failure, the CsCOM potential at the leak destination is (Low potential−ΔV), so the read potential is higher than the reference side potential. This is to make it low. Then, a slightly long time is set for the first precharge period so that a voltage change due to a leak failure appears.

  In the read operation of the first row, first, the precharge gate voltage PCG is set to LOW to stop the precharge, and then the potential of the scanning line G1 is set to HIGH to turn on each TFT 11 that is a pixel transistor in the first row. . The TFTs 11 of all the pixels connected to the scanning line G1 are turned on all at once. As a result, the charge written in the capacitor Cs moves to the source line S. The odd-side source line (S (odd)) where HIGH is written rises slightly from the high-side potential near the intermediate potential, and the potential of the even-side source line (S (even)) on the reference side is near the intermediate potential. Decreases slightly from the lower potential. The display data read circuit unit 4A is activated by setting the SAn-ch drive power supply to LOW and then the SAp-ch drive power supply to HIGH.

  However, in the case where the leakage of the data holding capacitor Cs of the odd-numbered pixel occurs, as shown by the dotted line L1 in FIG. 8, the odd-numbered source line (S) from the potential of the even-numbered source line (S (even)). (odd)) potential is lower. As a result, as indicated by the dotted line L2, the even-side potential increases.

When the SAn-ch drive power supply goes LOW, the potential slightly lower than the intermediate potential changes to LOW, and when the SAp-ch drive power supply goes HIGH, the potential slightly higher than the intermediate potential changes to HIGH. To do. This is because, as described above, the high and low potential levels appearing on the two source lines S are clarified by the operation of each differential amplifier 4a of the display data read circuit unit 4A. This operation is performed simultaneously for all the pixels connected to the scanning line G1.
Then, the gates TG1 to TGn of the transistors in the transmission gate section 6A are opened in order (set to HIGH), and the pixel data of each pixel in the first row is read in order from the video signal line 7A.

  After opening up to the last transmission gate TGn, it moves to precharge operation again. The precharge operation, that is, the precharge time after the second time does not need to be as long as the first time.

  Therefore, as described above, the written pixel data is compared with the read pixel data (S3). When the HIGH of the odd-numbered pixel to be inspected is LOW at the time of reading, the odd-numbered side It can be determined that the pixel of LOW has a fixed LOW defect. Such a LOW fixed defective pixel, that is, an abnormal cell is output to a display device or the like (not shown) in the inspection device 31 (S4).

  After stopping the precharge operation, the TFT 11 of each pixel in the second row is turned on by setting the potential of the second scanning line G2 to HIGH. Thereafter, the same operation is read up to the pixel connected to the last scanning line Gm, that is, the pixel data of each pixel in the m-th row.

By comparing the read pixel data with the written pixel data, it is possible to check whether or not each pixel in the odd column to be inspected has a LOW fixing defect.
Next, the relationship between the even-numbered columns and the odd-numbered columns is reversed, that is, the odd-numbered pixels are used for writing reference data, LOW is written to the odd-numbered pixels, and HIGH is written to the even-numbered pixels to be inspected. By performing processing similar to the processing shown in FIG. 8, it is checked whether or not the even-numbered pixel has a LOW fixing defect with respect to the reference odd-numbered pixel.

  As described above, by checking whether there is a LOW fixed defect in the other pixel with respect to one of the odd and even columns, the LOW fixed defect is detected for all the pixels. You can check for it.

Next, with reference to FIG. 9, the inspection for the presence or absence of HIGH fixation failure will be described. FIG. 9 is a timing chart for explaining the reading operation in the inspection for the presence / absence of a HIGH fixing defect.
As in the case of the LOW fixed defect described above, the even-numbered pixels are first used for writing reference data. However, when writing pixel data, HIGH is set for even-numbered pixels and LOW is set for odd-numbered pixels to be inspected. Write.

  After writing pixel data as shown in FIG. 7 to all the pixels (a state in which the relationship between HIGH and LOW in FIG. 7 is reversed), a read operation is started after a predetermined time in the precharge state. At this time, the precharge potential (voltage applied to the precharge voltage application terminal 3a) Vpc of each source line S is set to (HIGH potential + ΔV) potential. The precharge potential Vpc is set to the (HIGH potential + ΔV) potential when the leak between the source and the drain of the TFT 11 is because the potential of the source line S to be leaked is (HIGH potential + ΔV), and the read potential is the reference This is because the potential is higher than the potential on the side.

  In the read operation, first, precharging is stopped, and then the potential of the scanning line G1 is set to HIGH to turn on each TFT 11. The TFTs 11 are turned on all at once in all the pixels in the first row connected to the scanning line G1. The potential of the even-side source line S (even) on the reference side where HIGH is written slightly decreases (changes to HIGH potential) from the precharge potential Vpc, and the potential of the odd-side source line S (odd) where LOW is written. Further falls below the precharge potential Vpc. Therefore, the differential amplifier 4a lowers the potential of the odd-numbered source line S (odd) in which LOW is written, and the potential of the even-numbered source line S (even) in which HIGH is written maintains the HIGH potential. To do.

  However, if a leak occurs between the source and drain of the TFT 11 of the odd-numbered pixel to be inspected, the potential of the capacitor Cs of the pixel to be leaked becomes a precharge potential (HIGH potential + ΔV), and the even-side of the reference side Higher than the pixel potential. Therefore, when pixel data is read, as indicated by the dotted line L3 in FIG. 9, the potential of the odd-numbered source line S (odd) remains almost unchanged at the precharge potential (HIGH potential + ΔV). That is, the potential of the odd-numbered source line S (odd) is higher than the potential of the even-numbered source line S (even). When the SAn-ch drive power supply goes LOW, the low-side potential changes to LOW, and when the SAp-ch drive power supply goes HIGH, the high-side potential changes to HIGH. As a result, the potential of the even-numbered source line S (even) becomes LOW and the potential of the odd-numbered source line S (odd) becomes HIGH, as indicated by the dotted line L4.

Therefore, in the cell of the pixel to be inspected, the written pixel data and the read pixel data are different, so that an abnormal cell can be detected.
The subsequent operation of the differential amplifier is the same as that at the time of detecting the LOW fixing failure described above. By performing the above operation with the reference side as the odd side and the inspection target as the even side, it is possible to inspect all pixels for high fixation defects.

  As described above, the LOW fixed defect is inspected by exchanging the even and odd columns on the reference side, and in the same manner, all the fixed defects are inspected by exchanging the even and odd columns on the reference side. A pixel can be inspected for the presence of a LOW fixing defect and a HIGH fixing defect.

In the above-described example, the reference pixel is inspected as HIGH or LOW, but an intermediate potential signal may be written in the reference pixel.
A method for performing inspection by writing an intermediate potential between HIGH and LOW to a reference pixel will be described with reference to FIG.
As in the case of the detection of the LOW fixing defect described above, the even-numbered pixel is first used for writing the reference data, the intermediate potential between HIGH and LOW is set to the even-numbered pixel, and the HIGH or LOW is set to the odd-numbered pixel to be inspected. Write LOW. For example, as shown in FIG. 11, HIGH is first written to odd-numbered pixels, and an intermediate potential (M) between HIGH and LOW is written to even-numbered pixels.

  After writing to all pixels, a read operation is started after a predetermined time in the precharge state. At this time, the precharge potential of the source line S (voltage applied to the precharge voltage application terminal 3a) is set to an intermediate potential between HIGH and LOW.

  In the reading operation, first, precharging is stopped, and then the potential of the scanning line G1 is set to HIGH to turn on each TFT 11. The TFTs 11 are turned on all at once for all the pixels connected to the scanning line G1. The potential of the even-numbered source line on the reference side remains unchanged between the precharge potentials. The potential of the odd-numbered source line S rises slightly from the intermediate potential because HIGH is written. Accordingly, the differential amplifier 4a causes the even side to be LOW and the odd side to be HIGH, so that the pixel data written to the odd side remains HIGH.

  However, when a leak occurs in the capacitance Cs of the pixel to be inspected, the potential of the odd-numbered source line S (odd) is slightly lower than the intermediate potential. Therefore, the differential amplifier 4a causes the odd side to become LOW as shown by the dotted line L5 in FIG. 10 and the even side to become HIGH as shown by the dotted line L6. Therefore, the pixel data written to the odd side becomes LOW instead of HIGH. Become.

  The subsequent operation is the same as that at the time of detecting the LOW fixing failure described above. In the same manner, pixel data is read out for all rows.

  Next, LOW is written to the odd side (the state in which H in FIG. 11 is changed to L), and the intermediate potential is written to the even side serving as a reference. Then, the same operation as that when writing HIGH to the odd-numbered side and reading out the pixel data is performed in a row sequential manner for all the pixels.

  As a result, the test apparatus 31 can obtain data in which the intermediate potential is written on the reference side, HIGH and LOW are written on the inspection target side, and pixel data in each case is read. The pixel data written with HIGH and LOW is compared with the pixel data read in each case. At this time, in both cases where LOW is written to a certain pixel and HIGH is written, when LOW is read, it is first considered that the pixel has a leakage defect in the capacitance Cs.

  Furthermore, the source line potential on the inspection target side always becomes the precharge potential due to the capacitance or high resistance of the TFT, or leakage between the source and drain of the TFT, that is, the read amplification operation becomes a potential comparison between the precharge potentials, It can be determined that there is a possibility that the inspection target side always leans to LOW due to the inherent characteristics.

  Further, in any case, when HIGH is read out, the possibility of a leak failure is only eliminated in the capacitance Cs, and the same failure as in the case of LOW can be considered.

  That is, by writing an intermediate potential on the reference side, writing LOW and HIGH on the inspection target side (whichever can be done first), reading out the pixel data in each case and comparing them, Cell capacitance Cs and TFT defects can be detected.

  Then, when the same inspection is performed with the odd-numbered column as the reference side and the even-numbered side as the inspection target side, it is possible to inspect all the pixels for the presence or absence of capacitance Cs and TFT.

  As described above, according to the operation shown in FIG. 10, if the data in which HIGH and LOW are written is fixed to LOW or HIGH at the time of reading, it is determined that there is some defect in the capacitance Cs or TFT. Can do.

As described above, all the pixels on the element substrate 1 can be inspected by inspecting the upper stage circuit and performing the same inspection on the lower stage circuit at the same time or thereafter.
In the above embodiment, the display data reading circuit unit is provided for all the pixels of the display element array unit. However, the display data reading circuit unit may be provided for only some of the pixels used as the display unit. It may be.

  As described above, according to the embodiment and the modification of the present invention described above, since the defect of the element substrate can be detected after the element substrate process in the product or the prototype is completed, the yield reduction period is shortened, and the defective product is reduced. As a result, it is less likely to assemble the product, resulting in cost reduction. In particular, in the case of a prototype, the development period is shortened and the development cost is reduced.

In addition, since a defect can be detected at the stage of the element substrate, so-called repair is facilitated.
Furthermore, since the display data readout circuit unit can convert the charge of the capacitor, which is analog information, into digital information (voltage logic), the detection sensitivity in the inspection is high.

  Furthermore, in the above example, differential amplifiers are connected to adjacent source lines so that they are not easily affected by external noise, but a differential amplifier connected to source lines that are not adjacent to each other is provided. May be. By doing so, it is possible to eliminate the influence of the possibility of leakage between adjacent source lines.

Further, according to the present embodiment, each signal line S is electrically separated at the dividing line AC, and the signal line S in the display element array unit 2A and the signal line S in the display element array unit 2B are separated from each other. Is not connected. Accordingly, the wiring length of the signal line S is halved, that is, the capacitance of the source line S with the ground is halved, so that the potential appearing on the signal line S rises. For example, when a LOW or HIGH signal is written to the pixel to be inspected and an intermediate potential between HIGH and LOW is written to the reference pixel, the potential ΔV read by the differential amplifier 4a is expressed by the following equation. The precharge potential is an intermediate potential between LOW and HIGH. When the capacity is CS and the capacity of each signal line S is CL,
ΔV = (Vdd / 2) ・ CS / (CS + CL) ・ ・ Expression (1)
It becomes. Therefore, according to the present embodiment, each signal line S is divided at the dividing line AC and is electrically disconnected, and the capacitance CL is halved, so that the read potential ΔV can be increased. it can. More specifically, when Vdd is 10 V and CL: CS = 10: 1, ΔV = 0.45 V in the formula (1), but according to the present embodiment, CL: CS = 5: 1 In this case, ΔV = 0.83V.

  If ΔV is small, malfunction may occur if the sensitivity of the differential amplifier 4a is not sufficient. Even if the differential amplifier 4a is sufficient, if ΔV is small, the value of ΔV itself may fluctuate due to the influence of noise on the signal line S, which may cause malfunction. In contrast, in the present embodiment, since the signal line S is divided and the differential amplifier 4a is connected to each of them, the value of ΔV can be increased. Therefore, stable circuit operation can be obtained during substrate inspection. In addition, since the differential amplifier 4a having low sensitivity can be used, the circuit area of the differential amplifier 4a can be reduced (transistor gate length can be reduced), or the Vth variation management conditions of the transistor can be relaxed. it can.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 12 is a circuit diagram of an element substrate of a liquid crystal display device according to the second embodiment of the present invention. In FIG. 12, the same components as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. Also in the second embodiment, similarly to the first embodiment, the element substrate 1 has an upper stage circuit and a lower stage circuit. The display element array unit 2 formed in the substantially central part of the element substrate 1 is arranged in one direction of the matrix, here, in the central part of a plurality of pixels arranged in the Y direction so as to divide the display region in half. It is divided. Accordingly, the display element array section 2 is composed of two display element array sections 2A and 2B that are independent of each other. Therefore, the element substrate 1 has a plurality of separate circuit elements for independently driving the two display element array portions 2A and 2B.

  The first region 1A of the liquid crystal display device according to the present embodiment also includes a display element array unit 2A, a display data read circuit unit 4A, an X driver unit 5A, a Y driver unit 5A1, a transmission gate unit 6A, A video signal line 7A and a differential amplifier 10 are included. Further, in the present embodiment, it includes a precharge circuit unit 16A, a connection gate unit 17A, and a reference voltage supply unit 18A.

In the second region 1B, as shown in FIG. 1, circuit elements having the same configuration as that of the first region 1A are formed in a symmetrical arrangement with respect to the dividing line AC, that is, in a so-called mirror-inverted arrangement. Specifically, the first region 1B also includes the display element array unit 2B, the display data read circuit unit 4B, the X driver unit 5B, the Y driver unit 5B1, the transmission gate unit 6B, and the video signal line 7B. The differential amplifier 10 further includes a precharge circuit portion 16B, a connection gate portion 17B, and a reference voltage supply portion 18B. Each signal line S is divided at the dividing line AC, and the signal line S in the display element array section 2A and the signal line S in the display element array section 2B are not connected.
The precharge circuit unit 16A according to the second embodiment includes a pair of transistors 16b and 16c with respect to a pair of source lines of an odd-numbered source line S (odd) and an even-numbered source line S (even). have. The sources and drains of the transistors 16b and 16c connected in series with the source and drain connected are connected to the respective differential amplifiers via the odd-numbered source line S (odd) and the even-numbered source line S (even), respectively. 4a is connected to a connection point so and a connection point se. The gates of the transistors 16b and 16c are connected to a precharge gate terminal 16a. A connection point between the transistors 16b and 16c is connected to a terminal 18a of the reference voltage supply unit 18A. A reference voltage Vref is supplied to the terminal 18a. Therefore, by controlling the gate voltages of the transistors 16b and 16c, the transistors 16b and 16c are simultaneously turned on so that the reference voltage Vref supplied from the outside can be applied to each source line S via the transistors 16b and 16c. It has become. The reference voltage Vref is an intermediate potential voltage between HIGH and LOW.

  In the connection gate portion 17A, as shown in FIG. 12, one connection point so of each differential amplifier 4a is connected to the odd-numbered column source line S (odd) via one transistor 17b of the connection gate portion 17A. ing. The other connection point se of each differential amplifier 4a is connected to the even column source line S (even) via the other transistor 17c of the connection gate portion 17A. The gates of the transistors 17b and 17c are connected to a gate terminal 17a1 for connecting an odd-numbered column test circuit and a gate terminal 17a2 for connecting an even-numbered column test circuit, respectively. Test circuit connection signals TEo and TEe described later are respectively supplied to the gate terminals 17a1 and 17a2.

  Therefore, by setting one of the test circuit connection signals TEo and TEe to HIGH, the pixels of the odd-numbered column source line S (odd) and the pixels of the even-numbered column source line S (even) are detected by one differential amplifier 4a. Only one of the data can be read. The potential that appears on the source line S and is read out (a slight potential change) is transmitted to the differential amplifier 4a through one of the transistors 17b and 17c. The potential of the transistor is turned on and closed once, then amplified in the differential amplifier 4a, and then the transistor closed once is opened again and written back to the source line, and output via the video line 7.

  Next, details of the operation of the circuit shown in FIG. 12 will be described with reference to the timing chart of FIG. A reading operation of the pixel data in S2 of FIG. 6 will be described. FIG. 13 is a timing chart for explaining a read operation in the circuit of FIG. The pixel inspection is performed by determining whether each pixel is normal by dividing into an odd column and an even column here. Signals for timing shown in FIG. 13 are generated by the test apparatus 31 and supplied to each terminal.

  First, all the scanning lines G in the element array section 2A are turned on, and HIGH is written to all the pixels in the odd-numbered columns. Note that HIGH may be written in all pixels. In the present embodiment, the inspection of the pixels of the odd column source line S (odd) and the inspection of the even column source line S (even) pixels are performed separately. Furthermore, here, a case where HIGH is written to each pixel will be described, but LOW may be written. In the following, an example in which HIGH is written to all pixels in the odd-numbered column and the substrate 1A is inspected will be described. However, only some pixels may be inspected. After writing, the gate of the scanning line G is turned off. The even column source S (even) sets the test circuit connection signal TEe to LOW, so that the influence of the potential from the display element array section 2A is not transmitted to the differential amplifier 4a on the even column source line S (even). .

As shown in FIG. 13, after the predetermined pixel data (in this case, HIGH) is written to the odd-numbered columns of pixels, the precharge circuit supplied to the terminal 16a of the precharge circuit section 16A in order to secure the data holding time t1. The charge gate voltage PCG becomes HIGH, and the transistors 16b and 16c are turned on for a predetermined time. Further, the test circuit connection signal TEo at the gate terminal 17a1 for connecting the test circuit is also HIGH. After the data holding time t1 has elapsed, reading of pixel data is started.
Since the transistors 16b and 16c are turned on for a predetermined time so that the reference voltage Vref appears at both the connection point so and the connection point se of each differential amplifier 4a, the gate line G is turned off. In this case, it is not always necessary to enter the precharge state. Furthermore, when the transistors 16b and 16c are turned on, the test circuit connection signal TEo of the test circuit connection gate terminal 17a1 may not yet be HIGH. Therefore, data retention time t1
If the precharge gate voltage PCG is LOW after the lapse, precharge is performed as HIGH.

  From the reference voltage supply unit 18A, a reference voltage Vref having an intermediate potential between HIGH and LOW is applied as a precharge potential to the terminal 18a. Therefore, after writing predetermined pixel data, the source line S (odd), the connection point se, and the connection point so are in an intermediate potential state.

  Then, after the data holding time t1, elapses, the precharge gate voltage PCG is set to LOW to release the precharge state. At this time, the test circuit connection signal TEo is HIGH and the first drive power supply By setting the potentials of SAp-ch and the second drive power supply SAn-ch to an intermediate potential, the differential amplifiers 4a are not operated.

  Immediately after the precharge gate voltage PCG is set to LOW, when the gate line G1 is turned on, data is simultaneously output from each pixel connected to the gate line G1. Specifically, the charges written and held in the capacitor Cs move all at once to the corresponding source line S (odd). As shown in FIG. 13, the potential of each source line S (odd) slightly increases. If there is a leak in the capacitor Cs and the data of each pixel changes to LOW, the potential of each source line S (odd) slightly decreases as shown by the dotted line. At this time, since the test circuit connection signal TEe is LOW, the potential of the even column source line S (even) can be ignored.

  In order to operate each differential amplifier 4a after a predetermined time has elapsed after opening the gate line G1, first, the potential of the second drive power source SAn-ch is changed from the intermediate potential to LOW. The test circuit connection signal TEo is set to LOW at the same time as or before or after the moment when the potential of the second drive power supply SAn-ch changes to LOW, and the transistor 17b of the connection gate portion 17A is turned off to slightly increase the voltage. The information on the potential of the odd-numbered column source line S (odd) is confined in the differential amplifier 4a.

  When the SAn-ch drive power supply goes LOW, the slightly lower potential of the connection point so and the connection point se changes to LOW. Accordingly, each differential amplifier 4a compares the reference voltage Vref, which is an intermediate potential applied from the outside, with the voltage of each odd column source line S (odd). If the pixel is normal, the potential of the odd-numbered column source line S (odd) is slightly higher than the intermediate potential, so that the connection point se of each differential amplifier 4a has a lower potential than the connection point so. Become. Therefore, as shown in FIG. 13, the potential at the connection point se is lowered. At this time, the potential of the connection point so is maintained as it is.

Next, when the SAp-ch drive power supply becomes HIGH, the P-channel transistors 21 and 22 of the differential amplifier 4a are operated. That is, when the SAp-ch drive power supply becomes HIGH, the slightly higher potential of the connection point so and the connection point se changes to HIGH. If the pixel is normal, the potential of the odd-numbered column source line S (odd) is slightly higher than the intermediate potential, so that the connection point so of each differential amplifier 4a is higher than the connection point se. Become. Therefore, as shown in FIG. 13, the potential at the connection point so increases.
If the pixel is defective, for example, if the capacitor Cs leaks and the data of each pixel changes to LOW, the potential of each odd-numbered column source line S (odd) is indicated by a dotted line in FIG. So as to descend slightly. In this case, when the SAn-ch drive power supply goes low, the potential at the connection point se drops as shown by the dotted line in FIG. Further, when the SAp-ch drive power supply becomes HIGH, the potential at the connection point so increases as shown by a dotted line in FIG.
In this case, since the test circuit connection signals TEo and TEe are turned off, it is not affected by the capacity of the source line S serving as a load, and high-speed operation is possible. Further, since the reference voltage Vref is not a write potential, a defect of a certain pixel is detected as a defect of the pixel, and detailed defect characteristic classification is possible.

  When the logic at the connection point se and the connection point so of the differential amplifier 4a is determined to be either HIGH or LOW, the test circuit connection signal TEo is set to HIGH, and the determined logic data is written to the odd-numbered column source line S (odd). return. Since the potential of each pixel connected to the gate line G1 is read to the corresponding odd-numbered column source line S (odd), the odd-side gate of each transistor of the transmission gate unit 6 is set to TGn (TG1 to TG3, TG5 in order). Alternatively, TGn-1) is opened (set to HIGH), the pixel data of each pixel in the first row is read in order from the video signal line 7 and output to the output terminals outo and oute.

  When the data of all the pixels connected to the gate line G1 is read, the gate line G1 is set to LOW, the SAn-ch drive power supply and the SAp-ch drive power supply are set to the intermediate potential, and the differential amplifier 4a is stopped. Subsequently, the precharge gate voltage PCG is set to HIGH to precharge all the source lines S.

  Thereafter, by repeating the above-described operation, the gate lines G2 to Gm are inspected in order.

As described above, when the inspection operation performed by writing HIGH data to all the pixels in the odd-numbered column is completed, next, all the pixels in the odd-numbered column are written by writing the LOW data to all the pixels in the odd-numbered column and performing the same inspection. All inspections about are complete.
Subsequently, the inspection target pixel is changed to an even-numbered column. That is, when the test circuit connection signal TEo is fixed to LOW and the same test as the test performed on the odd column pixels is performed while HIGH data is written to the even column pixels while changing the test circuit connection signal TEe. This is done when LOW data is written.

  Similarly to the first embodiment, in the second embodiment, one differential amplifier 4a is sufficient for two source lines, so that the circuit scale on the substrate is reduced. The size of the transistor in the dynamic amplifier 4a can be increased. As a result, it is possible to reduce the asymmetry of the transistors in the differential amplifier 4a, improve the driving capability, and the like, so that the differential amplifier 4a having a stable and high sensitivity can be realized.

  As described above, in the first embodiment, even if one pixel is defective, two pixels are detected as defective, whereas according to the second embodiment, one pixel is defective. 1 pixel is detected as defective. Therefore, according to the circuit configuration according to the second embodiment, the defect characteristic classification can be performed in more detail than the circuit configuration according to the first embodiment.

  Further, according to the second embodiment, by using the test circuit connection signals TEo and TEe, the load during operation of the differential amplifier is lightened so as not to be affected by the capacitance of the source line S serving as a load. Therefore, the circuit can be operated at high speed.

  Furthermore, according to the second embodiment, since the reference voltage is applied from the outside, the reference voltage can be externally controlled, so that inspection for detailed evaluation such as investigation of the holding potential is possible. .

  Furthermore, also in this embodiment, each signal line S is divided at the dividing line AC, and the signal line S in the display element array section 2A and the signal line S in the display element array section 2B are connected. Absent. Therefore, as in the first embodiment, according to the present embodiment, each signal line S is divided at the dividing line AC and the capacitance CL is halved, so that the read potential ΔV is increased. Can do. Therefore, stable circuit operation can be obtained during substrate inspection. In addition, since the differential amplifier 4a having low sensitivity can be used, the circuit area of the differential amplifier 4a can be reduced (transistor gate length can be reduced), or the Vth variation management conditions of the transistor can be relaxed. it can.

  As described above, in the above-described two embodiments, the electro-optic device substrate of the present invention has been described by taking the active matrix display device substrate as an example. However, the present invention is limited to the above-described embodiment. However, various changes and modifications can be made without departing from the scope of the present invention.

  For example, by providing an optical sensor in the display portion, it can be applied to a display device substrate having an input function.

  In the above-described embodiment, the active matrix type substrate including the configuration necessary for the inspection of the display data reading circuit units 4A and 4B and the connection gate units 9A and 9B has been described. In an active matrix type substrate that does not include the display element array, the display element array unit 2 can be divided into two parts and mirror-inverted as in the present invention.

  That is, by dividing the display element array section 2 into two, the length of the source line can be shortened as compared with a normal active matrix substrate (for example, if the source line is divided at 50:50 up and down, Half the length).

  For this reason, the resistance of the source line can be reduced, and the capacity of the source line can be reduced. When the capacity of the source line is reduced, the time for writing the image signal voltage can be reduced.

  As a result, the time during which each of the transmission gates TG1, 2,... Is opened can be shortened as compared with the prior art, so that the image signal that is originally written to the next selected source line may be erroneously written. As a result, the effect of reducing the occurrence of ghosts can be obtained.

In this configuration, since it is necessary to match the driving phases of the parts divided vertically, it is desirable to provide means for adjusting the phase of the clock signal that is the driving reference.
An electro-optical device using the substrate for an electro-optical device of the present invention is also included in the present invention.
For example, an electro-optical device in which an electro-optical material is sandwiched between a pair of substrates, and the substrate for an electro-optical device of the present invention is used for one of the pair of substrates.

Further, an electronic apparatus using the above electro-optical device is also included in the present invention. 14 and 15 are diagrams illustrating examples of electronic devices. FIG. 14 is an external view of a personal computer according to one example. FIG. 15 is an external view of a mobile phone according to one example. As shown in FIG. 14, the above-described electro-optical device, for example, a liquid crystal display device is used for the display unit 101 of a personal computer 100 as an electronic apparatus. As shown in FIG. 15, the above-described electro-optical device, for example, a liquid crystal display device, is used for the display unit 201 of the mobile phone 200 as an electronic device.
In addition, as an electronic device, for example, a projection display device including a light source, a light valve that modulates light emitted from the light source, and an optical system for projecting light modulated by the light valve It is. Furthermore, other electronic devices include televisions, viewfinder type / monitor direct view type video tape recorders, car navigation devices, pagers, electronic notebooks, calculators, word processors, workstations, videophones, POS terminals, digital Examples include a still camera and a device equipped with a touch panel. Needless to say, the display panel according to the present invention is applicable to these various electronic devices.

  The present invention is not limited to the liquid crystal display device including the TFT described above, and can be applied to an active matrix drive display device.

1 is a layout diagram of circuit elements on an element substrate of a liquid crystal display device according to a first embodiment of the present invention. 1 is a circuit diagram of an element substrate of a liquid crystal display device according to a first embodiment of the present invention. FIG. 3 is an equivalent circuit diagram of a pixel according to the first embodiment. The circuit diagram of the differential amplifier concerning a 1st embodiment. The lineblock diagram of the inspection system concerning a 1st embodiment. 5 is a flowchart showing an example of a flow of inspection according to the first embodiment. FIG. 5 is a diagram illustrating a state of pixel data written to each pixel according to the first embodiment. 4 is a timing chart for explaining a read operation according to the first embodiment. 10 is a timing chart of another read operation according to the first embodiment. 12 is a timing chart of still another read operation according to the first embodiment. The figure which shows the example of the state of the pixel data written in each pixel. The circuit diagram of the element substrate of the liquid crystal display device concerning the 2nd Embodiment of this invention. 9 is a timing chart for explaining a read operation according to the second embodiment. 1 is an external view of a personal computer as an example of an electronic apparatus to which the present invention is applied. 1 is an external view of a mobile phone as an example of an electronic apparatus to which the present invention is applied.

Explanation of symbols

1 element substrate, 1A first area, 1B second area, 2 display element array section, 2A first display element array section, 2B second display element array section, 3A, 3B precharge circuit section, 4A, 4B display data reading circuit section, 4a differential amplifier, 6A, 6B transmission gate section, 7A, 7B video signal line

Claims (11)

A plurality of scan lines;
A plurality of first signal lines intersecting a first scanning line of the plurality of scanning lines;
The second scanning line of the plurality of scanning lines intersects the first scanning line and is electrically disconnected from the first signal line, and the dividing line extending in the direction of the scanning line A plurality of second signal lines extending in a line-symmetric direction with respect to one signal line;
A plurality of pixels arranged in a matrix corresponding to intersections of the plurality of scanning lines, the plurality of first signal lines, and the plurality of second signal lines, and corresponding to the plurality of pixels A plurality of switching elements each provided;
A plurality of first signals provided corresponding to each of the plurality of first signal lines and receiving a first potential signal of the plurality of first signal lines and a second potential signal as a reference potential. Amplifying means,
A plurality of second signals provided corresponding to each of the plurality of second signal lines and receiving a third potential signal of the plurality of second signal lines and a fourth potential signal as a reference potential. Amplifying means,
First data reading means for reading a first output potential signal output from the plurality of first amplifying means to each of the plurality of first signal lines;
Second data reading means for reading a second output potential signal output from the plurality of second amplifying means to each of the plurality of second signal lines;
Have
Each of the plurality of first amplifying means compares the first potential signal with the second potential signal, and when the first potential signal is low, the potential of the first signal line is low. When the first output potential signal is output to the first signal line and the first potential signal is high, the potential of the first signal line is further increased. Output the first output potential signal that has been increased to the first signal line,
Each of the plurality of second amplifying means compares the third potential signal with the fourth potential signal, and when the third potential signal is low, the potential of the second signal line is When the second output potential signal is output to the second signal line and the third potential signal is high, the potential of the second signal line is further increased. A substrate for an electro-optical device, wherein the second output potential signal is increased and the higher second output potential signal is output to the second signal line. Each of the first potential signal and the third potential signal is a potential of a signal written to all or a part of the plurality of pixels via the plurality of switching elements,
2. The electro-optical device substrate according to claim 1, wherein each of the second potential signal and the fourth potential signal is a potential supplied from the outside. Each of the first, second, third and fourth potential signals is a potential of a signal written to all or a part of the plurality of pixels via the plurality of switching elements,
Each of the first, second, third and fourth potential signals corresponds to the plurality of first and second corresponding signal lines via the corresponding first and second signal lines. 2. The electro-optical device substrate according to claim 1, wherein the substrate is supplied to the plurality of second amplifying units.   4. The electro-optical device substrate according to claim 1, wherein each of the plurality of first and the plurality of second amplifying units is a differential amplifier. 5.   5. Each of the first and second data reading means includes a differential amplifier for outputting the read potential signal. 6. Electro-optic device substrate.   6. The electro-optical device substrate according to claim 1, wherein each of the plurality of pixels is provided with an additional capacitor.   2. The apparatus according to claim 1, further comprising: a plurality of first and second precharge circuits connected to the plurality of first and second signal lines, respectively, for precharging the plurality of pixels. The substrate for an electro-optical device according to claim 6. First and second video signal lines that supply image signals to be written to the plurality of pixels via the first and second signal lines, and the first and second video signal lines. First and second transmission gates for supplying image signals to the first and second signal lines;
8. The electro-optical device substrate according to claim 1, wherein the first and second data reading units include the first and second video signal lines, respectively. 9. .   9. An electro-optical device comprising an electro-optical material sandwiched between a pair of substrates, wherein the electro-optical device substrate according to claim 1 is used for one of the pair of substrates. Electro-optical device characterized.   An electronic apparatus using the electro-optical device according to claim 9. A plurality of scanning lines; a plurality of first signal lines intersecting with a first scanning line among the plurality of scanning lines; and a second scanning line among the plurality of scanning lines; A plurality of second signals that are electrically disconnected from one signal line and that extend in a direction symmetrical to the first signal line with respect to a dividing line extending in the direction of the scanning line. Lines, a plurality of scanning lines, a plurality of pixels arranged in a matrix corresponding to intersections of the plurality of first signal lines and the plurality of second signal lines, and the plurality of pixels A plurality of switching elements provided correspondingly, and an inspection method for a substrate for an electro-optical device,
Writing a first potential signal to a pixel corresponding to the first signal line and writing a third potential signal to a pixel corresponding to the second signal line;
Reading a first potential signal written to the pixel;
The read first potential signal is compared with a second potential signal as a reference signal having a potential different from that of the first potential signal. When the first potential signal is low, When the potential of the first signal line is made lower and the lower first output potential signal is outputted to the first signal line, and the first potential signal is high, A first output step of increasing the potential of the signal line and outputting the higher first output potential signal to the first signal line;
A first comparison step of comparing the first potential signal written in the writing step with the first output potential signal outputted in the first output step;
Reading a third potential signal written to the pixel;
The read out third potential signal is compared with a fourth potential signal as a reference signal having a potential different from that of the third potential signal. When the third potential signal is low, When the potential of the third signal line is made lower and the lower third output potential signal is outputted to the second signal line, and the third potential signal is high, A second output step of increasing the potential of the signal line and outputting the higher second output potential signal to the second signal line;
A second comparison step of comparing the third potential signal written in the writing step with the second output potential signal outputted in the second output step;
A method for inspecting a substrate for an electro-optical device, comprising:

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