JP2007240667A - Electro-optical device, inspection method thereof, and electronic apparatus - Google Patents

Abstract

A pixel portion is rapidly inspected with a simple circuit configuration.
A data line driving circuit 100 includes a first output signal Ro1,..., And a second output signal Re1,..., And a second output signal Re1,. When reading Rek, sampling signals P1,..., Pk are supplied to the sampling switch 111 constituting the sampling circuit 110, and the sampling switch 111 electrically connected to the data lines constituting each data line group is turned on. Switch to state. When the pixel circuit 70 is inspected, the sampling circuit 110 outputs a plurality of output signals such as the first output signal Ro and the second output signal Re output from the differential amplifier circuit 15 included in the inspection circuit 4 to four data. Each data line group including a line is output to four image signal lines 91, and the first output signal Ro and the second output signal Re are transmitted to the external test circuit via the four image signal lines 91 for each data line group. Read all at once.
[Selection] Figure 8

Description

  The present invention relates to a technical field of, for example, an electro-optical device such as a liquid crystal device, an electronic apparatus such as a liquid crystal projector including the electro-optical device, and an inspection method for inspecting an electro-optical device such as a liquid crystal device.

  An electro-optical device such as a liquid crystal device includes a step of inspecting a substrate for an electro-optical device such as a TFT array substrate on which a thin film transistor (hereinafter referred to as “TFT”) is formed, a TFT array substrate, a liquid crystal, and the like. And a step of enclosing a liquid crystal between opposing substrates on which an opposing electrode for driving the electro-optical element is formed. The inspection of whether or not the finished liquid crystal device operates normally is performed based on whether or not the image displayed by the completed liquid crystal device is correctly displayed. In such an electro-optical device, if a defect of the TFT formed on the TFT array substrate is not detected in the process of inspecting the TFT array substrate, the defect is detected by the inspection performed on the liquid crystal device which is the finished product. Will be.

  As countermeasures when a defect is detected in the finished liquid crystal device, measures such as exchanging the TFT array substrate after repairing the liquid crystal from the liquid crystal device or repairing the defective part can be considered. These measures are practically difficult to adopt in view of a decrease in yield and an increase in cost when manufacturing the product. In addition, the process after forming the TFT array substrate becomes a useless process, and there is a problem in that the yield is reduced and the cost is increased when manufacturing an electro-optical device such as a liquid crystal device.

  As one means for solving such a problem, for example, Patent Document 1 compares potential information supplied via two signal lines electrically connected to a comparator in a pixel array. A technique for inspecting whether or not a pixel is defective is disclosed.

JP 2004-226551 A

  However, according to the technique disclosed in Patent Document 1, potential information reflecting the quality of each pixel is read from all signal lines to each comparator, and output signals simultaneously output from each of the plurality of comparators are parallel-serial. It is read as serial data by conversion, and parallel output signals output in parallel from a plurality of comparators are converted into serial data. Therefore, there is an essential problem from a technical point of view that it is difficult to process data at high speed and inspect the pixel portion quickly.

  In addition, according to Patent Document 1, it is necessary to form a conversion circuit for parallel-serial conversion of a plurality of output signals output from each of a plurality of comparators in a narrow region on a substrate such as a TFT array substrate. is there. Therefore, there are a design problem that it is difficult to lay out various circuits in a limited area on the substrate, and a problem that the cost is increased by providing the conversion circuit.

  Accordingly, the present invention has been made in view of the above problems and the like, and includes an electro-optical device capable of quickly and inspecting the quality of a pixel portion by an inexpensive circuit configuration, and such an electro-optical device. It is an object to provide an electronic device.

  In order to solve the above problems, the electro-optical device according to the present invention corresponds to a plurality of scanning lines and a plurality of data lines intersecting each other on the substrate, and the intersection of the plurality of scanning lines and the plurality of data lines. A plurality of pixel portions arranged in a row and inspection signals held by the plurality of pixel portions are input, and a signal obtained by amplifying the potential of the input inspection signal to a potential higher or lower than a reference potential is output. An inspection circuit that outputs signals, and a reading unit that simultaneously reads N output signals output to N (N is a natural number of 2 or more) data lines among the plurality of output signals. With.

  In the electro-optical device according to the present invention, for example, an electro-optical device is formed by sandwiching an electro-optical material such as liquid crystal between a TFT array substrate and a counter substrate. During the operation of the electro-optical device, a scanning signal is supplied to each pixel unit via the scanning line, and an image signal is supplied to each pixel unit via the data line. More specifically, for example, a pixel switching thin film transistor (hereinafter referred to as “TFT”) provided for each pixel portion has a gate connected to a scanning line, and an image signal is transmitted in accordance with the scanning signal. It is selectively supplied to the pixel electrode via a line. Accordingly, for example, by driving an electro-optical material such as liquid crystal sandwiched between the pixel electrode and the counter electrode in each pixel portion, active matrix driving is possible.

  Such an electro-optical device needs to be inspected to determine whether the pixel portion is good or bad. When the electro-optical device is inspected, for example, the electrical connection between the pixel portion and the data line is turned on for each scanning line, and the data line corresponding to the pixel portion is inspected for the pixel portion to be inspected. The inspection signal is input to the inspection circuit, and the inspection circuit outputs, as an output signal, a signal obtained by amplifying the potential of the input inspection signal to a potential higher or lower than the reference potential. The output signal is a signal including information regarding the quality of the pixel portion. The output signal is a signal supplied according to the quality of the pixel unit based on the test signal supplied to the pixel unit, and has a potential different from the potential of the test signal according to the quality of the pixel unit, for example. . More specifically, the output signal read out from the pixel portion indicates that the inspection signal previously supplied to the plurality of pixel portions at the time of inspection indicates whether there is a defect such as charge leakage in the pixel portion, that is, whether the pixel portion is good or bad. This is a signal obtained as a result of reflection.

  The quality of the pixel portion is determined by comparing the level of the potential of the inspection signal with respect to the reference potential with the level of the potential with respect to the reference potential of the output signal corresponding to the pixel portion. The reference potential is a potential that serves as a reference when evaluating the inspection signal and the output signal output from the pixel portion to be inspected.

  For example, at the time of the above-described inspection, the inspection circuit can read an output signal from the pixel portion to be inspected for each scanning line and accurately output a plurality of output signals to a plurality of data lines. More specifically, for example, when a pixel portion is provided at each of intersections of a plurality of scanning lines and a plurality of data lines, a plurality of pixel portions and data lines are provided for each scanning line at the time of inspection. These electrical connections are turned on, and an inspection signal is supplied to these pixel portions. Note that the reference potential to be compared with the signal read from the pixel portion is read from, for example, a data line electrically connected to the pixel portion adjacent to the pixel portion.

  The reading means simultaneously reads N output signals output to N (N is a natural number of 2 or more) data lines included in the plurality of data lines among the plurality of output signals. As a result, N individual output signals indicating whether the potential is high or low with reference to the reference potential are read simultaneously as N-bit data. Therefore, it is possible to quickly determine the quality of the pixel unit based on N-bit data output via the N data lines without converting parallel data output simultaneously from a plurality of pixel units into serial data. . In addition, since a conversion circuit for parallel-serial conversion of a plurality of output signals output simultaneously corresponding to a plurality of pixel portions is not necessary, the circuit configuration formed on the substrate can be simplified, and electrical An increase in cost required for the optical device can be suppressed. The quality of the pixel portion can be determined by a determination circuit provided separately in the electro-optical device or a determination unit such as an external circuit.

  As described above, according to the electro-optical device according to the present invention, it is possible to provide an electro-optical device such as a liquid crystal device in which a plurality of pixel units are quickly inspected for quality by a simple circuit configuration.

  In one aspect of the electro-optical device according to the present invention, the reading unit is electrically connected to each of the N data lines, and N for supplying serial-parallel converted image signals to N systems. A book image signal line may be included.

  According to this aspect, parallel N-system image signals obtained by serial-parallel conversion of serial image signals into a plurality of series are transferred to N data lines belonging to the data line group for each data line group. Each can be supplied at the same time.

  The serial-parallel conversion is typically performed by an external circuit provided outside the electro-optical device in order to realize high-definition image display while suppressing an increase in drive frequency. In this case, a serial image signal is input to the external circuit, and the serial image signal is converted into a plurality of parallel image signals such as 4-phase, 12-phase, 24-phase,. The Such “serial-parallel conversion” is also called “serial-parallel expansion” or “phase expansion”.

  In this aspect, N output signals are read out simultaneously via N image signal lines. That is, by using N image signal lines used for supplying image signals when displaying an image by the electro-optical device when reading N output signals, the image display and the pixel portion are inspected. N image signal lines can be shared. Therefore, the pixel portion can be inspected quickly and easily without providing a complicated data conversion circuit on a substrate such as a TFT array substrate and without requiring data conversion.

  In this aspect, the reading means includes a sampling circuit including a plurality of sampling switches for supplying each of the N system image signals to each of the N data lines in response to a sampling circuit drive signal, and the plurality of samplings. A data line driving circuit that sequentially supplies the sampling circuit driving signal for each sampling switch corresponding to the N data lines of the switches, and the N output signals are the N output signals When the output signal is read, the data is read for each of the N data lines via the sampling switch corresponding to the N data lines that are turned on by the sampling circuit drive signal output from the data line drive circuit. May be issued.

  According to this aspect, when the electro-optical device is driven, N-system image signals subjected to serial-parallel conversion are supplied to the N image signal lines, and further supplied to the sampling circuit from these image signal lines. The In parallel with the supply of the N system image signals to the sampling circuit, the data line driving circuit for each sampling switch corresponding to the data line group, for example, from the transfer signal sequentially output from the shift register to the sampling signal (ie, sampling) Circuit drive signal) is generated, and the generated sampling signals are sequentially supplied. Then, by each sampling switch in the sampling circuit, N system image signals are sequentially supplied to the plurality of data lines for each data line group in accordance with the sampling signal. Thus, N parallel image signals are supplied to N data lines belonging to the same data line group all at once.

  On the other hand, when N output signals are read during inspection of the electro-optical device, the sampling corresponding to the data line group is performed by the data line driving circuit, contrary to the case where N image signals are supplied. For each switch, a sampling signal (that is, a sampling circuit drive signal) is generated from the transfer signal sequentially output from the shift register, and the generated sampling signal is sequentially supplied. Then, each of the sampling switches in the sampling circuit reads N output signals from a plurality of data lines at a time for each data line group according to the sampling signal.

  Therefore, according to this aspect, it is possible to quickly read N output signals for each data line group by sharing N image signal lines used when displaying an image at the time of inspection. The output speed of the output signal can be increased.

  In another aspect of the electro-optical device according to the invention, the inspection circuit includes a differential amplifier circuit provided corresponding to a set of two data lines out of the N data lines. The differential amplifier circuit reads a first potential signal from the pixel portion via one data line of the two data lines and is electrically connected to another data line of the two data lines. A second potential signal having the reference potential is read from the other pixel portion via the other data line, and a potential higher or lower than the reference potential is applied to each of the one data line and the other data line. You may output the 1st output signal and 2nd output signal which have.

  According to this aspect, the level relationship between the first output potential and the second output potential is determined based on each of the first potential signal and the second potential signal. More specifically, the differential amplifier circuit outputs a first output signal and a second output signal in which the potential difference is amplified by the potential difference between the potential of the first potential signal and the potential of the second potential signal that is the reference potential. Output. According to the first output signal and the second output signal, the quality of the pixel portion can be reliably determined.

  In this aspect, the differential amplifier circuit compares the potential of the first potential signal with the reference potential, and (i) the potential of the first potential signal is greater than the reference potential. A low potential signal having a potential lower than the potential of the first potential signal when the potential is lower; (ii) a potential lower than the reference potential when the potential of the first potential signal is higher than the reference potential; A high potential signal having a high potential may be output to the one data line as the first output signal.

  In this aspect, the differential amplifier circuit amplifies the potential difference between the first potential signal and the second potential signal read from the pixel portion according to the quality of the pixel portion. More specifically, when the first potential signal read from the pixel portion is higher than the reference potential, a first output signal having a higher potential than that of the reference potential is output and is output from the pixel portion. When the read first potential signal is lower than the reference potential, the first output signal whose potential is further lowered as compared with the reference potential is output. According to such an output signal, the potential difference between the first output signal and the second output signal for determining the quality of the pixel portion becomes clear, and the inspection accuracy can be improved.

  In order to solve the above problems, an inspection method for an electro-optical device according to the present invention is held by a plurality of pixel units arranged corresponding to intersections of a plurality of scanning lines and a plurality of data lines intersecting each other on a substrate. An output step of outputting a signal obtained by amplifying the potential of the input inspection signal to a potential higher or lower than a reference potential as an output signal, and the plurality of output signals among the plurality of output signals A readout step of simultaneously reading out N output signals output to N (N is a natural number of 2 or more) data lines included in the data line.

  According to the inspection method for an electro-optical device according to the present invention, similarly to the above-described electro-optical device, it is possible to quickly inspect a plurality of pixel portions with a simple circuit configuration, and the yield is high. An electro-optical device such as a high-quality liquid crystal device can be provided.

  Since the electronic apparatus according to the present invention includes the electro-optical device according to the present invention described above, a projection display device, a television set, a mobile phone, an electronic notebook, a word processor, capable of performing high-quality image display, Various electronic devices such as a viewfinder type or a monitor direct-view type video tape recorder, a workstation, a videophone, a POS terminal, and a touch panel can be realized. According to the electronic apparatus of the present invention, DLP (Digital Light Processing) or the like can be realized as an apparatus using an electrophoresis apparatus or an electron emission apparatus. Since the electronic apparatus according to the present invention includes the electro-optical device described above, the yield is improved.

  Such an operation and other advantages of the present invention will become apparent from the embodiments described below.

  Embodiments of an electro-optical device, an inspection method thereof, and an electronic apparatus according to the invention will be described below with reference to the drawings. In the present embodiment, a liquid crystal device driven by a TFT active matrix system is taken as an example of the electro-optical device according to the invention.

  A liquid crystal device 1 according to the present embodiment will be described with reference to FIGS.

  First, with reference to FIG.1 and FIG.2, the whole structure of the liquid crystal device 1 which concerns on this embodiment is demonstrated. FIG. 1 is a plan view showing the overall configuration of the liquid crystal device 1 according to this embodiment. 2 is a cross-sectional view taken along line HH ′ of FIG.

  1 and 2, in the liquid crystal device 1 according to the present embodiment, a TFT array substrate 10 and a counter substrate 20 are disposed to face each other. A liquid crystal layer 50 is sealed between the TFT array substrate 10 and the counter substrate 20, and the TFT array substrate 10 and the counter substrate 20 are provided with a sealing material 52 provided in a seal region positioned around the image display region 10a. Are bonded to each other.

  In FIG. 1, a light-shielding frame light-shielding film 53 that defines the frame area of the image display region 10a is provided on the counter substrate 20 side in parallel with the inside of the seal region where the sealing material 52 is disposed. A data line driving circuit 101 and an external circuit connection terminal 102 are provided along one side of the TFT array substrate 10 in a region located outside the sealing region in which the sealing material 52 is disposed in the peripheral region. The sampling circuit 110 is provided so as to be covered with the frame light shielding film 53 on the inner side of the seal region along the one side. Further, the scanning line driving circuit 104 is provided so as to be covered with the frame light-shielding film 53 inside the seal region along two sides adjacent to the one side. On the TFT array substrate 10, vertical conduction terminals 106 for connecting the two substrates with the vertical conduction material 107 are arranged in regions facing the four corner portions of the counter substrate 20. Thus, electrical conduction can be established between the TFT array substrate 10 and the counter substrate 20.

  On the TFT array substrate 10, the external connection terminal 102 is electrically connected to the image signal supply circuit 101, the scanning line driving circuit 104, the vertical conduction terminal 106, and the like which are examples of the “reading unit” of the present invention. A routing wire 90 is formed for this purpose.

  In FIG. 2, on the TFT array substrate 10, a laminated structure is formed in which pixel switching TFTs (Thin Film Transistors), which are driving elements, and wirings such as scanning lines and signal lines are formed. In the image display area 10a, a pixel electrode 9a is provided in an upper layer of wiring such as a pixel switching TFT, a scanning line, and a signal line. An alignment film is formed on the pixel electrode 9a. On the other hand, on the counter substrate 20, in addition to the counter electrode 21, a lattice-shaped or striped light-shielding film 23 and an alignment film are formed on the uppermost layer portion. The liquid crystal layer 50 is made of, for example, a liquid crystal in which one or several types of nematic liquid crystals are mixed, and takes a predetermined alignment state between the pair of alignment films.

  Although not shown here, on the TFT array substrate 10, in addition to the image signal supply circuit 101 and the scanning line drive circuit 104, a plurality of differential amplifier circuits, precharge circuits, and transmissions included in an inspection circuit described later are provided. A gate or the like is formed.

  Next, the main circuit configuration of the liquid crystal device 1 according to the present embodiment will be described with reference to FIGS. 3 to 8. FIG. 3 is a block diagram showing the main circuit configuration of the liquid crystal device 1 according to this embodiment. FIG. 4 is a circuit diagram showing an electrical configuration of the pixel portion. FIG. 5 is a circuit diagram showing an electrical configuration of the pull-down circuit. FIG. 6 is a circuit diagram showing an electrical configuration of the pull-up circuit. FIG. 7 is a circuit diagram showing an electrical configuration of the differential amplifier circuit. FIG. 8 is a block diagram showing a circuit configuration of the image signal supply circuit 101.

For convenience of explanation, in FIG. 3, when viewed from the left side in the figure, the odd number (that is, the first) along the direction in which the scanning line Gj (j = 1, 2,..., N; n is an integer of 2 or more) extends. Data lines Soi (i = 1, 2,..., M; m is an integer greater than or equal to 2) wired to the third, fifth,. The data lines are distinguished from the data lines Sei (i = 1, 2,..., M; m is an integer) wired to the (th,...).
In FIG. 3, the liquid crystal device 1 of this embodiment includes a scanning line driving circuit 104, an image signal supply circuit 101, an inspection circuit 4, and a pixel unit 70 on a TFT array substrate 10.

  The scanning line driving circuit 104 sequentially supplies a switching signal for each scanning line 116 when the pixel unit 70 is inspected. Here, the switching signal is a signal different from the scanning signal for image display supplied to the pixel unit 70 when displaying an image, and an inspection signal, which will be described later, supplied in advance to the pixel unit 70 is used as an inspection target. This is a signal for switching a switching element included in the pixel unit 70 to an ON state in order to output the first potential signal from the pixel unit 70.

  The image signal supply circuit 101 supplies image signals VID1 to VID4 to the data lines So and Se when the liquid crystal device 1 is operating, that is, when an image is displayed. As will be described in detail later, the image signal supply circuit 101 determines that the output signal output from the inspection circuit 4 is determined by an external circuit or the like in order to determine the quality of the pixel unit 70 when the pixel unit 70 is inspected. Read to means.

  The pixel unit 70 is provided in the image display area 10a corresponding to the intersection of the data lines Soi and Sei and the scanning line Gj.

  Here, a detailed configuration of the pixel unit 70 will be described with reference to FIG. In FIG. 4, the pixel portion 70 includes a TFT 71, a liquid crystal element 72, and a storage capacitor 73.

  The TFT 71 has a source electrically connected to the data line Soi or Sei and a gate electrically connected to the scanning line Gj. The TFT 71 is switched on and off by a switching signal supplied from the scanning line driving circuit 104.

  The liquid crystal element 72 has a liquid crystal injected between the TFT array substrate 10 and a counter substrate disposed so as to correspond to the TFT array substrate 10 and a pair of electrodes that sandwich the liquid crystal.

  The storage capacitor 73 temporarily holds an image signal supplied to the pixel unit 70 when image display is performed, and enables active matrix driving of the plurality of pixel units 70.

  In FIG. 3 again, the inspection circuit 4 includes a differential amplifier circuit 15, a first drive signal supply circuit 21, a second drive signal supply circuit 22, an equalize circuit 23, a voltage application wiring 24, a preamplifier on the TFT array substrate 10. A charge circuit 25, a connection circuit 26, TFTs 11, 12a, 12b, 13p, and 13n, and a transmission gate 6 electrically connected to the data lines So and Se are provided.

  A plurality of data lines Soi and Sei extend from the image display region 10a to the differential amplifier circuit 15 and are electrically connected to nodes So and Se of the differential amplifier circuit 15, respectively. The data lines Soi and Sei intersect the plurality of scanning lines Gj (j = 1, 2,..., N; n is an integer of 2 or more) provided in the image display area 10a. It extends in the image display area. The pixel portion 70 provided in the image display area 10a is arranged in accordance with the intersection of the data lines Soi and Sei and the plurality of scanning lines Gj, and is electrically connected to the data lines Soi and Sei.

  The connection circuit 26 includes a test signal supply line 45 electrically connected to the test circuit via a test circuit connection gate terminal, and a pull-down circuit 35. The test signal supply line 45 supplies a series of test signals supplied from the test circuit to the transmission gate 6 when the pixel unit 70 is inspected. The pull-down circuit 35 stabilizes the potential of the test signal supply line 45 so that the test signal supplied to the transmission gate 6 via the test signal supply line 45 does not fluctuate.

  Here, a detailed configuration of the pull-down circuit will be described with reference to FIG. As shown in FIG. 5, the pull-down circuit 35 includes a TFT 135 having a gate electrically connected to the power supply VDD, a grounded source, and a drain electrically connected to the test signal supply line 45. This reduces the fluctuation of the potential of the test signal supply line 45 when the test signal is supplied. Note that the pull-down circuits 32, 33 and 34 also have the same circuit configuration as the pull-down circuit 35.

  In FIG. 3 again, the transmission gate 6 is provided in the middle of each of the data lines Soi and Sei. The transmission gate 6 is provided on the side close to the differential amplifier circuit 15 when viewed from the pixel portion 70, and includes a plurality of TFTs 14 electrically connected in the middle of each of the data lines Soi and Sei. The plurality of TFTs 14 are collectively switched on according to a test signal supplied from the test circuit via the test signal supply line 45 when the pixel unit 70 is inspected. As a result, a signal reflecting the quality of each pixel unit 70 can be supplied to each of the nodes Se and So of the differential amplifier circuit 15. More specifically, if the TFT 71 provided in the pixel unit 70 is switched to the on state, each pixel unit 70 is connected from each pixel unit 70 to each differential amplifier circuit 15 via each of the data lines Soi and Sei. The first potential signal and the second potential signal reflecting the quality can be supplied together.

  At the time of inspecting the pixel portion, an inspection signal and a reference signal having a predetermined potential are supplied to the plurality of pixel portions 70 in advance.

  As shown in FIG. 9, the pixel portion 70 provided corresponding to the data line Soi has a potential higher than an intermediate potential (indicated as “M” in the drawing) as a reference potential (hereinafter, “HIGH” as appropriate). An inspection signal of “potential” (shown as “H” in the figure) is supplied, and a reference signal having an intermediate potential which is a reference potential is supplied to the pixel portion 70 provided corresponding to the data line Sei. . In the present embodiment, the intermediate potential is half of the power supply voltage Vdd of the power supply VDD, that is, Vdd / 2. Therefore, in the image display area 10a, the columns of the pixel portions 70 supplied with the intermediate potential signal and the columns of the pixel portions 70 supplied with the HIGH potential signal are alternately arranged.

  The first potential signal is a signal in which the inspection signal previously supplied to the pixel unit 70 is read from the pixel unit 70, and when the pixel unit 70 is defective, the potential of the inspection signal, that is, the HIGH potential. Is output at a different potential. The second potential signal is a signal in which the reference signal previously supplied to the pixel unit 70 is read from the pixel unit 70, and is read to the differential amplifier circuit 15 through the data line Sei simultaneously with the first potential signal. . The intermediate potential is a reference potential that is a comparison target when the differential amplifier circuit 15 determines the level of the potential of the first potential signal, that is, a reference potential. The first potential signal may be a signal supplied to all or a part of the plurality of pixel units 70, and the second potential signal may be a signal supplied from the outside. In this case, since the reference signal can be stably supplied from the outside regardless of the quality of the pixel unit, the quality of the pixel unit 70 can be more reliably determined.

  Here, the potential of the output signal when there is no malfunction in the pixel portion will be described with reference to FIG. FIG. 10 is a diagram schematically showing the state of the potential of the output signal including the first output signal and the second output signal output from the differential amplifier circuit 15.

  As shown in FIG. 10, when there is no malfunction in the pixel portion, the first potential signal that is a HIGH potential is output as a first output signal having a higher HIGH potential (H), and the second potential signal Is output as a second output signal having a LOW potential (L) lower than the reference potential. When a defect occurs in the pixel portion, the first output signal and the second output signal are output with their relative potentials reversed.

  In FIG. 3 again, the equalizing circuit 23 includes an equalizing signal supply line 43 and a pull-down circuit 33, and a precharge signal for switching on / off of the TFT 11 is supplied to the gate of the TFT 11 via the equalizing signal supply line 43. . The pull-down circuit 33 reduces fluctuations in the potential of the equalize signal supply line 43.

  The precharge circuit 25 includes a precharge signal supply line 44 electrically connected to the gates of the TFTs 12 a and 12 b and a pull-down circuit 34 electrically connected to the precharge signal supply line 44. The precharge signal supply line 44 is also electrically connected to the equalize signal supply line 43. The precharge signal supply line 44 supplies a precharge signal supplied from the outside to the gates of the TFTs 11, 12a, and 12b through the precharge terminal in order to switch on and off the TFTs 11, 12a, and 12b. The pull-down circuit 34 reduces fluctuations in the potential of the precharge signal supply line 44.

  The voltage application wiring 24 is electrically connected to the source of the TFT 12a and the drain of the TFT 12b, and applies a precharge voltage to the TFTs 12a and 12b. The precharge voltage is set to an intermediate potential in advance and is supplied to the TFTs 12a and 12b. The precharge voltage is supplied to the TFTs 12a and 12b before the first and second potential signals are supplied to the differential amplifier circuit 15 via the data lines Soi and Sei, respectively.

  The TFTs 11, 12a, and 12b are switched on by the precharge signal, and the data is set so that the potential difference between the data lines Soi and Sei is reduced before the first and second potential signals are supplied to the data lines Soi and Sei, respectively. The potentials of the lines Soi and Sei are set. More specifically, the source and drain of the TFT F11, the drain of the TFT 12a, and the source of the TFT 12b are electrically connected to the data lines Soi and Sei, and a precharge signal is supplied to the gates of the TFTs 11, 12a, and 12b. After that, a precharge voltage is supplied between the source and drain of each of the TFTs 12a and 12b. As a result, a current flows between the source and drain of the TFT 11 and between the source and drain of the TFTs 12a and 12b so that the potential difference between the data lines Soi and Sei is reduced, and the potentials of the data lines Soi and Sei are intermediate potentials. Is equal to Therefore, on the premise that the differential amplifier circuit 15 compares the first and second potential signals, the potentials of the data lines Soi and Sei supplying these signals to the differential amplifier circuit 15 can be made uniform.

  When the first and second potential signals are supplied to the differential amplifier circuit 15 through the data lines Soi and Sei having the same potential, the potential relationship between the potentials of the first and second potential signals is maintained. The first and second potential signals are supplied to the differential amplifier circuit 15 as they are. Therefore, it is possible to reduce the fluctuation of the potential relationship between the potential of the first potential signal and the potential of the second potential signal due to the potential difference between the data lines Soi and Sei, and the potentials of the first potential signal and the second potential signal can be reduced. Reversal of the elevation relationship can be reduced.

  The first drive signal supply circuit 21 includes a first drive signal supply line 41 and a pull-up circuit 31. The first drive signal supply line 41 is electrically connected to the gate of the TFT 13p electrically connected to the differential amplifier circuit 15, and supplies the first drive signal SApE supplied from the outside to the gate of the TFT 13p. . The first drive signal SApE is a drive signal for driving the differential amplifier circuit 15. As will be described later, the differential amplifier circuit 15 has a high potential among signals input to the nodes So and Se. It functions as a sense amplifier that raises the potential of a signal and lowers the potential of a low signal. The TFT 13p is a p-channel TFT, and the TFT 13p is turned on when the first drive signal SApE is supplied to the gate, and supplies the power supply VDD to the node Sp of the differential amplifier circuit 15.

  Here, the configuration of the pull-up circuit 31 will be described with reference to FIG.

  In FIG. 6, the pull-up circuit 31 includes a p-channel TFT 131 whose gate is grounded. The TFT 131 supplies the power VDD to the first drive signal supply line 41.

  In FIG. 3 again, the second drive signal supply circuit 22 includes a second drive signal supply line 42 and a pull-down circuit 32. The second drive signal supply line 42 is electrically connected to the gate of the TFT 13n electrically connected to the differential amplifier circuit 15, and supplies the second drive signal SAnE supplied from the outside to the gate of the TFT 13n. . The TFT 13n is an n-channel TFT and is turned on when the second drive signal SAnE is supplied to the gate, and supplies the power supply VDD to the differential amplifier circuit 15. The pull-down circuit 32 maintains the potential of the second drive signal supply line 42.

  One differential amplifying circuit 15 is provided for each data line set including the data lines Soi and Sei. When the transmission gate 6 is turned on, the first and second potential signals are supplied from the data lines Soi and Sei to the nodes So and Se of the differential amplifier circuit 15, respectively. The differential amplifier circuit 15 compares the first and second potential signals and outputs a first output signal and a second output signal having different potentials to the data lines Soi and Sei, respectively.

  Next, the configuration of the differential amplifier circuit will be described in detail with reference to FIG.

  In FIG. 7, the differential amplifier circuit 15 is a cross-coupled differential amplifier circuit including p-channel TFTs 51 and 52 and n-channel TFTs 53 and 54. More specifically, a series circuit in which the TFTs 51 and 52 are electrically connected in series and a series circuit in which the TFTs 53 and 54 are electrically connected in series are electrically connected in parallel. The gate of the TFT 51 is electrically connected to the node So of the TFTs 52 and 54. The gate of the TFT 52 is electrically connected to the node Se of the TFTs 51 and 53. The gate of the TFT 53 is electrically connected to the node So of the TFTs 52 and 54. The gate of the TFT 54 is electrically connected to the node Se of the TFTs 51 and 53. The node So is electrically connected to the data line Soi, and the node Se is electrically connected to the data line Sei. The node Sp of the TFTs 51 and 52 is electrically connected to the drain of the TFT 13p. The node Sn of the TFTs 53 and 54 is electrically connected to the drain of the TFT 13n.

  When the first potential signal has a slightly higher potential than the second potential signal, the differential amplifier circuit 15 outputs the first output signal whose potential is higher than that of the first potential signal to the data line Soi. And a second output signal whose potential is set lower than that of the second potential signal is output to the data line Sei. As described above, according to the first output signal whose potential is increased and the second output signal whose potential is set low, it can be clearly determined that the potential of the first potential signal is higher than the potential of the second potential signal. When the first potential signal has a slightly lower potential than the second potential signal, the differential amplifier circuit 15 outputs the first output signal whose potential is lower than that of the first potential signal to the data line. In addition to outputting to the Soi, a second output signal having a potential higher than the reference potential is output to the data line Sei.

  According to such a low potential first output signal and a high potential two output signal, it can be clearly determined that the potential of the first potential signal is lower than the potential of the second potential signal. Accordingly, the reference signal and the inspection signal having the reference potential supplied in advance to the pixel portion are the potential relations of the potentials of the first output signal and the second output signal in which the potential difference is amplified compared to the first potential signal and the second potential signal. By discriminating whether or not it matches the level relationship of the potential, the quality of the pixel portion to be inspected can be accurately determined. Note that all pixel portions can be inspected by exchanging the inspection signal and the reference signal supplied to the pixel portion to which the reference signal is supplied and the pixel portion to be inspected, respectively.

  Next, a procedure for the differential amplifier circuit 15 to output the first output signal and the second output signal will be described with reference to FIGS. Here, when the first potential signal having a higher potential than the potential of the second potential signal having the intermediate potential is supplied to the differential amplifier circuit 15, that is, the respective potentials of the data lines Soi and Sei are shown in FIG. The state shown in FIG.

  3 and 7, when the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n, the TFT 13n is turned on, and the potential of the node Sn approaches the ground potential via the TFT 13n. Since the source potential of the TFT 53 is set to an intermediate potential, a current flows between the source and drain of the TFT 53, and the potential of the node Se decreases. At this time, since the gate of the p-channel TFT 52 is electrically connected to the node Se, the TFT 52 is switched to the on state when the potential of the node Se decreases. When the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the TFT 13p is switched on, and the power supply VDD is supplied to the node Sp via the TFT 13p. As a result, the power supply VDD is supplied to the node So through the TFTs 13p and 52, and the potential of the node So is increased.

  In this way, the differential amplifier circuit 15 increases the potential of the first potential signal and decreases the potential of the second potential signal. According to the differential amplifier circuit 15, when the first potential signal is higher than the intermediate potential, a first output signal having a higher potential than the first potential signal is output.

  When the potential of the first potential signal is lower than the potential of the second potential signal, the TFTs 51 and 54 operate in the same manner as the TFTs 52 and 53 described above, and a first output signal having a low potential is output based on the first potential signal. Is done. In this case, the second potential signal set to the intermediate potential is output as a second output signal whose potential is increased, and the first potential signal is a low potential signal having a potential lower than that of the second output signal. Is output as

  Next, with reference to FIG. 3 and FIG. 12, the timing of various signals when the differential amplifier circuit 15 outputs the first output signal and the second output signal via the data lines Soi and Sei will be described. FIG. 12 is a timing chart showing timings for outputting various signals via the data lines Soi and Sei. In FIG. 12, the pixel unit 70 corresponding to the data line Soi is the inspection target. That is, as described with reference to FIG. 9, in the image display region 10a, the columns of the pixel units 70 supplied with the intermediate potential signal and the columns of the pixel units 70 supplied with the HIGH potential signal are alternately arranged. Let's take the case of the

  In FIG. 12, the inspection signal is supplied to the pixel unit 70o and the reference signal is supplied to the pixel unit 70e by timing t1. That is, as described with reference to FIG. 9, in the image display region 10a, the column of the pixel portion to which the intermediate potential signal is supplied and the column of the pixel portion to which the HIGH potential signal is supplied are alternately arranged. It has become. The precharge circuit 25 supplies the precharge signal PCG to the gates of the TFTs 11, 12a and 12b via the precharge signal supply line 44 at timing t1. The TFTs 11, 12 a and 12 b are turned on, and a precharge voltage is applied to the data lines Soi and Sei via the voltage application wiring 24. Thereby, the potentials of the data lines Soi and Sei are set to the intermediate potential. Thereafter, the precharge circuit 25 ends the supply of the precharge signal PCG at the timing t2.

  After the transmission gate 6 is switched on, the scanning line G1 supplies a switching signal to the pixel unit 70 at timing t3, and the first and second potential signals are differentially transmitted via the signal lines Soi and Sei, respectively. This is supplied to the amplifier circuit 15. Note that the scanning line G1 supplies a switching signal to all the pixel portions 70 electrically connected to the scanning line G1, and the TFT 71 included in the pixel portion 70 electrically connected to the scanning line G1 is switched on. It is done. The first and second potential signals are supplied from each of the plurality of pixel portions 70 electrically connected to the scanning line G1 to the differential amplifier circuit 15 corresponding to these pixel portions 70.

  Here, when there is no malfunction in the pixel portion 70o, the first potential signal having a potential higher than the intermediate potential, that is, the HIGH potential, is applied to the data line in the same manner as the potential of the inspection signal previously supplied to the pixel portion 70o. The signal is supplied to the differential amplifier circuit 15 via Soi. At this time, the first potential signal has a potential slightly higher than the intermediate potential. The potential of the data line Sei from which the second potential signal is output is a preset intermediate potential, which is slightly lower than the potential of the first potential signal. As described above, when there is no malfunction in the pixel portion 70o, the level relationship between the potential of the inspection signal and the intermediate potential supplied in advance to the pixel portion 70o is the potential of the first potential signal and the second potential. The signal potential level is maintained as it is.

  When the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n at the timing t4, the differential amplifier circuit 15 lowers the potential of the data line Sei. As a result, the potential of the node Se having a lower potential than the potential of the node So to which the first potential signal is supplied is lowered to a potential lower than that at the time of supplying the second potential signal.

  At timing t5, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the differential amplifier circuit 15 supplies the potential of the node So to which the first potential signal is supplied to the second potential signal. Higher than the current potential

  At each of timings t4 and t5, the potential of the node Se to which the second potential signal having a low potential among the signals supplied to the differential amplifier circuit 15 is supplied is lowered further, and the first potential signal having a high potential is supplied. The potential of the node So supplied with is raised higher. Thereby, the level relationship between the potentials of the nodes So and Se becomes clear. The differential amplifier circuit 15 outputs the first output signal output via the node So to a determination unit such as a test circuit via the data line Soi. At the same time, the differential amplifier circuit 15 outputs the second output signal output via the node Se to a determination means such as a test circuit via the data line Sei.

  The test circuit compares the potential of the first output signal and the potential of the second output signal. Since the potential of the first output signal is higher than that of the first potential signal and the potential of the second output signal is lower than the intermediate potential, the test circuit is slightly less than the second potential signal and the second potential signal. It can be clearly determined that the potential of the first output signal is higher than the potential of the second output signal, as compared with the case where the first potential signal having a higher potential is compared. Here, since the level relationship between the potential of the inspection signal and the intermediate potential matches the level relationship between the potential of the first output signal and the potential of the second output signal, the test circuit has a problem with the pixel unit 70o to be inspected. It is determined that has not occurred.

  Next, in order to determine the quality of the pixel portion electrically connected to the scanning line G2, between the timings t6 and t7, a precharge voltage is supplied to the data lines Soi and Sei, and these data lines are again set to the intermediate potential. Set to

  At timing t8, the scanning line G2 outputs a switching signal, and the switching signal is supplied to the pixel portion 70 that is electrically connected to the scanning line G2. The pixel unit 70o supplied with the switching signal outputs the first potential signal to the differential amplifier circuit 15 through the data line Soi, similarly to the pixel unit 70o electrically connected to the scanning line G1. At this time, the data line Sei supplies the second potential signal to the differential amplifier circuit 15. Accordingly, the first output signal corresponding to the pixel portion 70o electrically connected to the scanning line G2 out of the pixel portion 70o electrically connected to the data line Soi in the same manner as the scanning line G1, and the pixel portion 70e. And the second output signal corresponding to the above are output from the differential amplifier circuit 15 to the test circuit via each data line, and the quality of the pixel unit 70 electrically connected to the scanning line G2 can be determined. In this way, it is possible to sequentially determine the quality of the pixel portion electrically connected to each of the scanning lines G3, G4,..., Gn.

  Next, with reference to FIG. 3 and FIG. 12, a case where a defect occurs in the pixel portion will be described.

  In FIG. 12, as described with reference to FIG. 9, the pixel unit 70 includes a column of pixel units 70 e supplied with an intermediate potential signal and a HIGH potential signal (that is, an inspection signal) in the image display region 10 a. The supplied rows of pixel portions 70o are alternately arranged. At a timing t3 when the switching signal is supplied from the scanning line G1 to the pixel unit 70, the pixel unit 70o supplies a first potential signal having a potential slightly lower than the intermediate potential to the differential amplifier circuit 15. Note that the potential of the node So to which the first potential signal having a potential lower than the intermediate potential is supplied is L0 indicated by a dotted line in the drawing. Here, the first potential signal has a potential lower than the intermediate potential when, for example, the pixel portion 70o includes a TFT in which current leakage occurs or a storage capacitor 73 in which current leakage occurs. Equivalent to.

  At timing t4, when the second drive signal SAnE is supplied from the second drive signal supply circuit 22 to the TFT 13n, the differential amplifier circuit 15 causes the node So to which the first potential signal having a potential lower than the intermediate potential is supplied. The potential is lowered to a lower potential (indicated by a dotted line L1 in the figure). More specifically, since the potential of the first potential signal supplied to the node So of the differential amplifier circuit 15 is slightly lower than the potential of the second potential signal supplied to the node Se of the differential amplifier circuit 15, The differential amplifier circuit 15 compares the potentials of the first potential signal and the second potential signal, and lowers the potential of the signal line Soi to a lower potential. The differential amplifier circuit 15 outputs a low potential first potential signal having a potential equal to the potential of the node So.

  At timing t5, when the first drive signal SApE is supplied from the first drive signal supply circuit 21 to the TFT 13p, the differential amplifier circuit 15 increases the potential of the second potential signal. Since the potential of the node Se is higher than the potential of the node So that has been lowered by the differential amplifier circuit 15, the differential amplifier circuit 15 raises the potential of the node Se to a potential higher than the intermediate potential. The differential amplifier circuit 15 outputs a second output signal having a high potential equal to the potential of the node Se whose potential is higher than the intermediate potential.

  As a result, the test circuit outputs the first output signal and the second output signal in which the relationship between the potential of the first potential signal and the potential of the second potential signal supplied to each of the data lines Soi and Sei is maintained. . The test circuit can clearly detect that the potential of the first potential signal is lower than the intermediate potential by detecting the first output signal whose potential is lower than that of the first potential signal. Here, the level relationship between the potentials of the first output signal and the second output signal is opposite to the level relationship of the potential of the inspection signal with respect to the potential of the intermediate potential. In such a case, the test circuit Determines that a defect has occurred in the pixel portion 70o.

  As the potentials of the first and second output signals, when the first and second potential signals are lower than the intermediate potential, the ground power supply potential (VSS power supply: 0 V) is used, and when higher than the intermediate potential, the potential is high. Power supply potential (VDD power supply; for example, 15 V) may be used.

  Thus, according to the liquid crystal device 1 of the present embodiment, the level relationship between the potential of the inspection signal and the intermediate potential supplied to the pixel unit 70 in advance, the potential of the first output signal that is compared with the potential in the test circuit, and By determining whether or not the potential level of the second output signal matches, it can be determined whether or not a defect has occurred in the pixel portion 70o. Furthermore, the first and second potential signals from the pixel unit 70 located in any region in the image display region 10a can be detected accurately and at high speed, and the quality of the pixel unit 70 can be determined accurately and in a short time. Accordingly, the yield of electro-optical devices such as liquid crystal devices can be increased, and the manufacturing cost can be reduced.

  Next, the electrical connection configuration of the image signal supply circuit 101 will be described with reference to FIG. As will be described later, according to the image signal supply circuit 101, the first output signal and the second output signal can be quickly read out from the test circuit. In the present embodiment, an image is displayed by supplying the image signals VID1 to VID4 expanded in four phases for each data line group including four data lines as a group, and the first output signal and the first output signal The two output signals are characterized in that they are read in a batch for each data line group.

  In FIG. 8, an image signal supply circuit 101 includes a data line driving circuit 100, a sampling circuit 110, and a plurality of image signal lines 91 electrically connected to the data lines.

  When the liquid crystal device 1 operates, that is, when an image is displayed, the data line driving circuit 100 is based on the enable signal ENB, the clock signal CLX, the inverted clock signal CLXinv, and the start pulse DX supplied from the outside. Sampling signals P1,..., Pk (k: integer calculated by m / 4) are sequentially supplied for each data line group from the (1) data line group to the (m) data line group, and the data lines The sampling switch 111 is switched on for each group. More specifically, the data line driving circuit 100 supplies the sampling signal P1 to the (1) data line group and is electrically connected to the data lines Se1, So1, Se2, and So2 in the middle. Switch 111 is turned on. The four-phase image signals VID1, VID2, VID3, and VID4 supplied to the four image signal lines 91a, 91b, 91c, and 91d, respectively, are the four image signal lines 91a, 91b, 91c, and 91d, respectively. Is supplied to each pixel unit 70 via data lines Se1, So1, Se2, and So2 electrically connected to the pixel line 70. Thereafter, a sampling signal is supplied to each data line group in order up to the (k) th data line group, and the image signals VID1, VID2, and the like are electrically connected to the data lines included in each data line group. Each of VID3 and VID4 is supplied.

  On the other hand, the data line driving circuit 100 receives the first output signals Ro1, ..., Rok and the second output signals Re1, ..., Rek from the differential amplifier circuit 15 via the data lines Se and So, respectively. When reading, sampling signals P1,..., Pk are supplied to the sampling switch 111 constituting the sampling circuit 110, and the sampling switch 111 electrically connected to the data lines constituting each data line group is turned on. Switch to. The “sampling signal” here is different from a signal supplied from the data line driving circuit 101 to the sampling circuit 110 when displaying an image, and a first output signal output from the differential amplifier circuit 15 described later, This is a signal for switching the sampling switch for reading the second output signal for each data line group to the ON state.

  When the pixel circuit 70 is inspected, the sampling circuit 110 outputs a plurality of output signals such as the first output signal Ro and the second output signal Re output from the differential amplifier circuit 15 included in the inspection circuit 4 to four data. Each data line group including a line is output to four image signal lines 91, and the first output signal Ro and the second output signal Re are transmitted to the external test circuit via the four image signal lines 91 for each data line group. Read all at once.

  More specifically, in the liquid crystal device 1 according to the present embodiment, at the time of inspection, four (system) output signals from each data line group, that is, two first output signals Ro and two second output signals. Re is read out simultaneously, that is, in parallel, via the four image signal lines 91. The four output signals read out in parallel for each data line group in this way become 4-bit data as a whole. Therefore, according to the liquid crystal device 1 according to the present embodiment, the four data lines and the four image signal lines are converted without converting parallel output signals output in parallel from the plurality of pixel units into serial data. The quality of the pixel portion can be quickly determined for each data line group based on the 4-bit data output via the. In addition, according to the liquid crystal device 1 according to the present embodiment, a conversion circuit for parallel-serial conversion of a plurality of output signals simultaneously output corresponding to a plurality of pixel units is not necessary, and therefore, on the substrate. The circuit configuration to be formed can be simplified and an increase in cost required for the liquid crystal device can be suppressed.

  Further, since the four output signals are simultaneously read out via the four image signal lines, the four image signal lines 91 used for supplying the image signal when displaying the image have four pieces. Used when reading the output signal. Therefore, four image signal lines can be shared during image display and pixel portion inspection. According to the liquid crystal device 1 having such a configuration, the pixel portion can be inspected quickly and easily without providing a complicated data conversion circuit on the TFT array substrate 10 and without requiring data conversion. is there.

  The 4-bit digital data read through the image signal line 91 is stored in a storage device 200 including a memory provided separately from the liquid crystal device 1 as shown in FIG. More specifically, the image signal supply circuit 101 sequentially supplies 4-bit digital data to the storage device 200 for each data line group, and the supplied digital data is sequentially stored in the storage device 200. Note that such digital data is composed of binary digital data indicating that the potential of the output signal is lower (LOW) or higher (HIGH) than the reference potential corresponding to each output signal.

  The determination apparatus 300 including the test circuit includes the relationship between the level of the inspection signal and the reference potential supplied to each pixel unit prior to the inspection, and the digital data read for each data line group, that is, the number of bits equal to the number of pixel units. Thus, the quality of the pixel portion is determined by reading out from the storage device 200 and comparing the digital data including the information on the level of each potential of the first output signal and the second output signal with each other.

  As described above, according to the liquid crystal device 1 according to the present embodiment, it is possible to quickly inspect a plurality of pixel portions with a simple circuit configuration. Therefore, by determining the quality of the pixel portion in advance before completing the liquid crystal device, it is possible to provide an electro-optical device such as a high-quality liquid crystal device with a high yield.

  Next, an inspection method for the electro-optical device according to the present embodiment will be described with reference to FIGS. 13 and 14. As an inspection method for the electro-optical device according to the present embodiment, the above-described inspection method for the liquid crystal device 1 is taken as an example. FIG. 13 is a flowchart of the inspection method of the liquid crystal device according to the present embodiment, and FIG. 14 is a timing chart when reading the output signal.

  In FIG. 13, an inspection signal is supplied to the pixel portion 70o (S10a), and a reference signal having a reference potential is supplied to the pixel portion 70e (S10b). Next, the image signal line 91 is precharged to an intermediate potential (S20). Next, the inspection circuit 4 is driven, and the first potential signal and the second potential signal are read into the differential amplifier circuit 15 via the data lines So and Se, and the first output signal and the data lines So and Se are respectively read. A second output signal is output (S30), and the potential of each data line is determined (S40). Next, an output sampling signal for reading out the first output signal and the second output signal for each data line group is supplied to the sampling switch 111 corresponding to each data line group (S50). Next, the first output signal and the second output signal are read out to the image signal line 91 for each data line group (S60). In the present embodiment, as already described, four output signals composed of two first output signals and two second output signals via four data lines constituting one data line group. Are collectively read for each data line group and sequentially stored in the storage device 200.

  Here, the procedure for reading the first output signal and the second output signal will be described with reference to FIG. Here, in order to simplify the description, an example in which output signals are read from the (1) data line group and the (2) data line group will be described as an example.

  In FIG. 14, when the first drive signal SApE is supplied to the node sp at the timing t10, the differential amplifier circuit 15 is driven. Next, when the sampling signal P1 is supplied to the sampling switch 111 corresponding to the first (1) data line group at the timing 20, the first output signals Ro1 (1) and Ro1 (2) and the second output signal Re1 ( 1) and Re1 (2) are read out to the four image signal lines 91, respectively. Next, when the supply of the sampling signal P1 is terminated at the timing 30, and the sampling signal P2 is supplied to the sampling switch 111 corresponding to the (2) th data line group at the subsequent timing 40, the first output signal Ro2 (1). And Ro2 (2) and the second output signals Re2 (1) and Re2 (2) are read out to the four image signal lines 91, respectively. The supply of the sampling signal P2 is finished at the timing 50, and similarly, the output signal composed of the first output signal and the second output signal is read up to the (k) th data line group.

  Next, in FIG. 13 again, the image signal line 91 is precharged again to the intermediate potential to prepare for reading of the next output signal (S70). Next, it is determined whether or not the output signal has been read up to the (k) th data line group (S80). Returning to the step of supplying the sampling signal (S50), the first output signal and the second output signal are read for all the pixel portions. Next, the quality of each pixel unit is inspected by comparing the height relationship between the digital data stored in the storage device 200 and the potentials of the inspection signal and the reference signal stored in advance (S90).

  As described above, according to the inspection method of the electro-optical device according to the present embodiment, as already described in the liquid crystal device 1, the output signal for determining the quality of the pixel unit can be read quickly and reliably. Is possible.

<Electronic equipment>
Next, the case where the liquid crystal device which is the above-described electro-optical device is applied to various electronic devices will be described.

  First, a projector using this liquid crystal device as a light valve will be described. FIG. 15 is a plan view showing a configuration example of a projector which is an example of the electronic apparatus of the invention. As shown in FIG. 15, a projector 1100 includes a lamp unit 1102 made up of a white light source such as a halogen lamp. The projection light emitted from the lamp unit 1102 is separated into three primary colors of RGB by four mirrors 1106 and two dichroic mirrors 1108 arranged in the light guide 1104, and serves as a light valve corresponding to each primary color. The light enters the liquid crystal panels 1110R, 1110B, and 1110G.

  The configurations of the liquid crystal panels 1110R, 1110B, and 1110G are the same as those of the liquid crystal device described above, and are driven by R, G, and B primary color signals supplied from the image signal processing circuit. The light modulated by these liquid crystal panels enters the dichroic prism 1112 from three directions. In this dichroic prism 1112, R and B light is refracted at 90 degrees, while G light travels straight. Accordingly, as a result of the synthesis of the images of the respective colors, a color image is projected onto the screen or the like via the projection lens 1114.

  Here, paying attention to the display images by the liquid crystal panels 1110R, 1110B, and 1110G, the display image by the liquid crystal panel 1110G needs to be horizontally reversed with respect to the display images by the liquid crystal panels 1110R, 1110B.

  Note that since light corresponding to the primary colors R, G, and B is incident on the liquid crystal panels 1110R, 1110B, and 1110G by the dichroic mirror 1108, it is not necessary to provide a color filter.

  In addition to the electronic device described with reference to FIG. 15, a liquid crystal television, a viewfinder type, a monitor direct-view type video tape recorder, a car navigation device, a pager, an electronic notebook, a calculator, a word processor, a workstation, a television. Examples include a telephone, a POS terminal, and a device equipped with a touch panel. Needless to say, the present invention can be applied to these various electronic devices.

  In addition to the liquid crystal device described in the above embodiment, the present invention also includes a reflective liquid crystal device (LCOS) in which elements are formed on a silicon substrate, a plasma display (PDP), a field emission display (FED, SED), It can also be applied to an organic EL display or the like.

  The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification, and an electro-optical device with such a change, In addition, the inspection method and the electronic apparatus including the electro-optical device are also included in the technical scope of the present invention.

It is a top view which shows the whole structure of the liquid crystal device which concerns on this embodiment. It is HH 'sectional drawing of FIG. It is a block diagram which shows the main circuit structures of the liquid crystal device which concerns on this embodiment. It is a circuit diagram which shows the electrical structure of a pixel part. It is a circuit diagram which shows the electric constitution of a pull-down circuit. It is a circuit diagram which shows the electrical structure of a pull-up circuit. It is a circuit diagram which shows the electric constitution of a differential amplifier circuit. It is a block diagram which shows the electrical structure of an image signal supply circuit. It is a conceptual diagram which shows the state of the pixel part to which the signal was supplied previously at the time of a test | inspection. It is a conceptual diagram which shows the state of the electric potential of the pixel part at the time of outputting a 1st electric potential signal and a 2nd electric potential signal. It is a block diagram of an inspection system. It is a timing chart which showed the timing of various signals at the time of inspection. 5 is a flowchart of an inspection method for an electro-optical device according to the embodiment. It is a timing chart of various signals at the time of reading an output signal. It is a top view of the electronic device which concerns on this embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Liquid crystal device, 10 ... TFT array substrate, 101 ... Image signal supply circuit, 100 ... Data line drive circuit, 110 ... Sampling circuit, 111 ... Sampling switch, 91 ...・ Image signal line

Claims (7)

On the board
A plurality of scan lines and a plurality of data lines intersecting each other;
A plurality of pixel portions arranged corresponding to intersections of the plurality of scanning lines and the plurality of data lines;
An inspection circuit that receives an inspection signal held in the plurality of pixel portions, and outputs a signal obtained by amplifying the potential of the input inspection signal to a potential higher or lower than a reference potential as an output signal;
Readout means for simultaneously reading out N output signals output to N (N is a natural number of 2 or more) data lines among the plurality of data lines out of the plurality of output signals. An electro-optical device. The reading means includes N image signal lines that are electrically connected to each of the N data lines and supply image signals that have undergone serial-parallel conversion to N systems. The electro-optical device according to Item 1. The reading means includes a sampling circuit including a plurality of sampling switches for supplying each of the N system image signals to each of the N data lines according to a sampling circuit driving signal, and the sampling circuit among the plurality of sampling switches. A data line driving circuit that sequentially supplies the sampling circuit driving signal for each sampling switch corresponding to N data lines;
The N output signals are sampling switches corresponding to the N data lines that are switched on by a sampling circuit drive signal output from the data line drive circuit when the N output signals are read. The electro-optical device according to claim 2, wherein the data is read for each of the N data lines. The inspection circuit includes a differential amplifier circuit provided corresponding to a set of two data lines among the N data lines,
The differential amplifier circuit reads a first potential signal from the pixel portion via one data line of the two data lines and is electrically connected to another data line of the two data lines. A second potential signal having the reference potential is read from the other pixel portion via the other data line, and a potential higher or lower than the reference potential is applied to each of the one data line and the other data line. The electro-optical device according to any one of claims 1 to 3, wherein the first output signal and the second output signal are output. The differential amplifier circuit compares the potential of the first potential signal with the reference potential, and (i) when the potential of the first potential signal is lower than the reference potential, A low potential signal having a potential lower than the potential; (ii) when the potential of the first potential signal is higher than the reference potential, the high potential signal having a potential higher than the potential of the first potential signal is The electro-optical device according to claim 4, wherein the electro-optical device is output to the one data line as an output signal. An inspection signal held in a plurality of pixel portions arranged corresponding to the intersection of a plurality of scanning lines and a plurality of data lines intersecting each other on the substrate is input, and the potential of the input inspection signal is set as a reference potential. An output step for outputting a signal amplified to a higher or lower potential as an output signal;
A readout step of simultaneously reading out N output signals output to N (N is a natural number of 2 or more) data lines included in the plurality of data lines out of the plurality of output signals. Inspection method for electro-optical device. An electronic apparatus comprising the electro-optical device according to any one of claims 1 to 5.

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